| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_ipp_top.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /********************************************************** |
| 36 | *********************************************************** |
| 37 | |
| 38 | Project : Niu |
| 39 | |
| 40 | File name : niu_ipp_top.v |
| 41 | |
| 42 | Module(s) name : niu_ipp_top |
| 43 | Original: : ipp_top.v main.37, label: IPP_RTL_2.3 |
| 44 | |
| 45 | Parent modules : none |
| 46 | |
| 47 | Child modules : niu_ipp.v, niu_ipp_ffl_arbiter.v. |
| 48 | |
| 49 | Author's name : George Chu |
| 50 | |
| 51 | Date : March 10, 2004 |
| 52 | |
| 53 | Description : Top level of combined 4 IPPs. |
| 54 | Arbitration logic has been implemented for ipp/fflp. |
| 55 | Each xmac/bmac is directly connected to ipp. |
| 56 | All ipp's directly connect to Dmc. |
| 57 | |
| 58 | Synthesis Notes: |
| 59 | |
| 60 | Modification History: |
| 61 | |
| 62 | Date Description |
| 63 | ---- ----------- |
| 64 | |
| 65 | ************************************************************ |
| 66 | ***********************************************************/ |
| 67 | |
| 68 | module niu_ipp_top ( |
| 69 | `ifdef NEPTUNE |
| 70 | `else |
| 71 | tcu_mbist_user_mode, |
| 72 | tcu_scan_en, |
| 73 | tcu_mbist_bisi_en, |
| 74 | tcu_rtx_rxc_ipp0_mbist_start, |
| 75 | tcu_rtx_rxc_ipp1_mbist_start, |
| 76 | rtx_rxc_ipp0_tcu_mbist_fail, |
| 77 | rtx_rxc_ipp1_tcu_mbist_fail, |
| 78 | rtx_rxc_ipp0_tcu_mbist_done, |
| 79 | rtx_rxc_ipp1_tcu_mbist_done, |
| 80 | niu_mb3_prebuf_header_scan_in, |
| 81 | niu_mb3_prebuf_header_scan_out, |
| 82 | niu_mb3_rx_data_fifo_scan_in, |
| 83 | niu_mb3_rx_data_fifo_scan_out, |
| 84 | rtx_rxc_ipp0_mb3_mbist_scan_in, |
| 85 | rtx_rxc_ipp0_mb3_mbist_scan_out, |
| 86 | rtx_rxc_ipp0_mb3_dmo_dout, |
| 87 | niu_mb4_prebuf_header_scan_in, |
| 88 | niu_mb4_prebuf_header_scan_out, |
| 89 | niu_mb4_rx_data_fifo_scan_in, |
| 90 | niu_mb4_rx_data_fifo_scan_out, |
| 91 | rtx_rxc_ipp1_mb3_mbist_scan_in, |
| 92 | rtx_rxc_ipp1_mb3_mbist_scan_out, |
| 93 | rtx_rxc_ipp1_mb3_dmo_dout, |
| 94 | |
| 95 | hdr_sram_rvalue_ipp0, |
| 96 | hdr_sram_rid_ipp0, |
| 97 | hdr_sram_wr_en_ipp0, |
| 98 | hdr_sram_red_clr_ipp0, |
| 99 | sram_hdr_read_data_ipp0, |
| 100 | |
| 101 | hdr_sram_rvalue_ipp1, |
| 102 | hdr_sram_rid_ipp1, |
| 103 | hdr_sram_wr_en_ipp1, |
| 104 | hdr_sram_red_clr_ipp1, |
| 105 | sram_hdr_read_data_ipp1, |
| 106 | |
| 107 | tcu_aclk, |
| 108 | tcu_bclk, |
| 109 | tcu_se_scancollar_in, |
| 110 | tcu_se_scancollar_out, |
| 111 | tcu_array_wr_inhibit, |
| 112 | |
| 113 | iol2clk, |
| 114 | l2clk_2x, |
| 115 | `endif |
| 116 | fflp_ipp_ready, // input from fflp |
| 117 | fflp_ipp_dvalid, |
| 118 | fflp_ipp_sum, |
| 119 | |
| 120 | pio_clients_sel_ipp,// input from cpu |
| 121 | pio_clients_addr, |
| 122 | pio_clients_rd, |
| 123 | pio_clients_wdata, |
| 124 | |
| 125 | reset_l, |
| 126 | clk, |
| 127 | |
| 128 | ipp_fflp_dvalid, // output to fflp |
| 129 | ipp_fflp_port, |
| 130 | ipp_fflp_data, |
| 131 | ipp_fflp_mac_default, |
| 132 | |
| 133 | ipp_pio_ack, // output to cpu |
| 134 | ipp_pio_rdata, |
| 135 | ipp_pio_err, |
| 136 | ipp_pio_intr, |
| 137 | ipp_debug_port, |
| 138 | |
| 139 | `ifdef NEPTUNE |
| 140 | // ipp3 |
| 141 | mac_rxc_req3, // input from bmac |
| 142 | mac_rxc_tag3, |
| 143 | mac_rxc_data3, |
| 144 | mac_rxc_ctrl3, |
| 145 | mac_rxc_stat3, |
| 146 | dmc_ipp_dat_req3, // input from dmc |
| 147 | |
| 148 | rxc_mac_ack3, // output to bmac |
| 149 | ipp_dmc_dat_ack3, // output to dmc |
| 150 | ipp_dmc_data3, |
| 151 | ipp_dmc_ful_pkt3, |
| 152 | ipp_dmc_dat_err3, |
| 153 | // ipp2 |
| 154 | mac_rxc_req2, // input from bmac |
| 155 | mac_rxc_tag2, |
| 156 | mac_rxc_data2, |
| 157 | mac_rxc_ctrl2, |
| 158 | mac_rxc_stat2, |
| 159 | dmc_ipp_dat_req2, // input from dmc |
| 160 | |
| 161 | rxc_mac_ack2, // output to bmac |
| 162 | ipp_dmc_dat_ack2, // output to dmc |
| 163 | ipp_dmc_data2, |
| 164 | ipp_dmc_ful_pkt2, |
| 165 | ipp_dmc_dat_err2, |
| 166 | `endif |
| 167 | |
| 168 | // ipp1 |
| 169 | mac_rxc_ack1, // input from xmac |
| 170 | mac_rxc_tag1, |
| 171 | mac_rxc_data1, |
| 172 | mac_rxc_ctrl1, |
| 173 | mac_rxc_stat1, |
| 174 | dmc_ipp_dat_req1, // input from dmc |
| 175 | |
| 176 | rxc_mac_req1, // output to xmac |
| 177 | ipp_dmc_dat_ack1, // output to dmc |
| 178 | ipp_dmc_data1, |
| 179 | ipp_dmc_ful_pkt1, |
| 180 | ipp_dmc_dat_err1, |
| 181 | // ipp0 |
| 182 | mac_rxc_ack0, // input from xmac |
| 183 | mac_rxc_tag0, |
| 184 | mac_rxc_data0, |
| 185 | mac_rxc_ctrl0, |
| 186 | mac_rxc_stat0, |
| 187 | dmc_ipp_dat_req0, // input from dmc |
| 188 | |
| 189 | rxc_mac_req0, // output to xmac |
| 190 | ipp_dmc_dat_ack0, // output to dmc |
| 191 | ipp_dmc_data0, |
| 192 | ipp_dmc_ful_pkt0, |
| 193 | ipp_dmc_dat_err0 |
| 194 | ); // end of niu_ipp_top pin definition |
| 195 | |
| 196 | `ifdef NEPTUNE |
| 197 | `else |
| 198 | input tcu_mbist_user_mode; |
| 199 | input tcu_scan_en; |
| 200 | input tcu_mbist_bisi_en; |
| 201 | input tcu_rtx_rxc_ipp0_mbist_start; |
| 202 | input tcu_rtx_rxc_ipp1_mbist_start; |
| 203 | output rtx_rxc_ipp0_tcu_mbist_fail; |
| 204 | output rtx_rxc_ipp0_tcu_mbist_done; |
| 205 | output rtx_rxc_ipp1_tcu_mbist_fail; |
| 206 | output rtx_rxc_ipp1_tcu_mbist_done; |
| 207 | input niu_mb3_prebuf_header_scan_in; |
| 208 | output niu_mb3_prebuf_header_scan_out; |
| 209 | input niu_mb3_rx_data_fifo_scan_in; |
| 210 | output niu_mb3_rx_data_fifo_scan_out; |
| 211 | input rtx_rxc_ipp0_mb3_mbist_scan_in; |
| 212 | output rtx_rxc_ipp0_mb3_mbist_scan_out; |
| 213 | output [39:0] rtx_rxc_ipp0_mb3_dmo_dout; |
| 214 | input niu_mb4_prebuf_header_scan_in; |
| 215 | output niu_mb4_prebuf_header_scan_out; |
| 216 | input niu_mb4_rx_data_fifo_scan_in; |
| 217 | output niu_mb4_rx_data_fifo_scan_out; |
| 218 | input rtx_rxc_ipp1_mb3_mbist_scan_in; |
| 219 | output rtx_rxc_ipp1_mb3_mbist_scan_out; |
| 220 | output [39:0] rtx_rxc_ipp1_mb3_dmo_dout; |
| 221 | |
| 222 | input [6:0] hdr_sram_rvalue_ipp0; |
| 223 | input [2:0] hdr_sram_rid_ipp0; |
| 224 | input hdr_sram_wr_en_ipp0; |
| 225 | input hdr_sram_red_clr_ipp0; |
| 226 | output [6:0] sram_hdr_read_data_ipp0; |
| 227 | |
| 228 | input [6:0] hdr_sram_rvalue_ipp1; |
| 229 | input [2:0] hdr_sram_rid_ipp1; |
| 230 | input hdr_sram_wr_en_ipp1; |
| 231 | input hdr_sram_red_clr_ipp1; |
| 232 | output [6:0] sram_hdr_read_data_ipp1; |
| 233 | |
| 234 | input tcu_aclk; |
| 235 | input tcu_bclk; |
| 236 | input tcu_se_scancollar_in; |
| 237 | input tcu_se_scancollar_out; |
| 238 | input tcu_array_wr_inhibit; |
| 239 | |
| 240 | input iol2clk; |
| 241 | input l2clk_2x; |
| 242 | `endif |
| 243 | |
| 244 | // output of fflp |
| 245 | input fflp_ipp_ready; // ready to accept data from ipp |
| 246 | `ifdef NEPTUNE |
| 247 | input [3:0] fflp_ipp_dvalid; // which port's parsed data is valid |
| 248 | `else |
| 249 | input [1:0] fflp_ipp_dvalid; // which port's parsed data is valid |
| 250 | `endif |
| 251 | input [13:0] fflp_ipp_sum; // parsed packet header information |
| 252 | |
| 253 | // output of cpu |
| 254 | input pio_clients_sel_ipp; // select ipp's |
| 255 | input [19:0] pio_clients_addr; |
| 256 | input pio_clients_rd; // rd_wr |
| 257 | input [31:0] pio_clients_wdata; |
| 258 | |
| 259 | // input from global |
| 260 | input reset_l; |
| 261 | input clk; |
| 262 | |
| 263 | // output to ffl |
| 264 | output ipp_fflp_dvalid; // packet header data is valid |
| 265 | output [1:0] ipp_fflp_port; // the data belongs to which mac_port |
| 266 | output [127:0] ipp_fflp_data; // ipp sends a packet's header data |
| 267 | output [11:0] ipp_fflp_mac_default; // default value of mac addr table |
| 268 | |
| 269 | output ipp_pio_ack; // output to cpu |
| 270 | output [63:0] ipp_pio_rdata; |
| 271 | output ipp_pio_err; |
| 272 | output ipp_pio_intr; |
| 273 | output [31:0] ipp_debug_port; |
| 274 | |
| 275 | // input to ipp0 |
| 276 | input mac_rxc_ack0; // xmac sends the ack to ipp |
| 277 | input mac_rxc_tag0; // xmac identifies the last part packet |
| 278 | input [63:0] mac_rxc_data0; // xmac writing the data to ipp |
| 279 | input mac_rxc_ctrl0; // active high for control information |
| 280 | input [22:0] mac_rxc_stat0; // xmac writing the status to ipp |
| 281 | input dmc_ipp_dat_req0; // dmc request data from rxc_data_fifo_0 |
| 282 | |
| 283 | // output of ipp0 |
| 284 | output rxc_mac_req0; // req(as rdy) from ipp to xmac |
| 285 | output ipp_dmc_dat_ack0; // rxc_data_fifo_0 is sending data to dmc |
| 286 | output [129:0] ipp_dmc_data0; // rxc_data_fifo_0's data to dmc |
| 287 | output ipp_dmc_ful_pkt0; // rxc_data_fifo_0 has at least 1 full packet |
| 288 | output ipp_dmc_dat_err0; // rxc_data_fifo_0 data has error |
| 289 | |
| 290 | // input to ipp1 |
| 291 | input mac_rxc_ack1; // xmac sends the ack to ipp |
| 292 | input mac_rxc_tag1; // bmac identifies the last part packet |
| 293 | input [63:0] mac_rxc_data1; // bmac writing the data to ipp |
| 294 | input mac_rxc_ctrl1; // active high for control information |
| 295 | input [22:0] mac_rxc_stat1; // bmac writing the status to ipp |
| 296 | input dmc_ipp_dat_req1; // dmc request data from rxc_data_fifo_1 |
| 297 | |
| 298 | // output of ipp1 |
| 299 | output rxc_mac_req1; // ack from ipp to bmac |
| 300 | output ipp_dmc_dat_ack1; // rxc_data_fifo_1 is sending data to dmc |
| 301 | output [129:0] ipp_dmc_data1; // rxc_data_fifo_1's data to dmc |
| 302 | output ipp_dmc_ful_pkt1; // rxc_data_fifo_1 has at least 1 full packet |
| 303 | output ipp_dmc_dat_err1; // rxc_data_fifo_1 data has error |
| 304 | |
| 305 | `ifdef NEPTUNE |
| 306 | // input to ipp2 |
| 307 | input mac_rxc_req2; // bmac sends the request to ipp |
| 308 | input mac_rxc_tag2; // bmac identifies the last part packet |
| 309 | input [63:0] mac_rxc_data2; // bmac writing the data to ipp |
| 310 | input mac_rxc_ctrl2; // active high for control information |
| 311 | input [22:0] mac_rxc_stat2; // bmac writing the status to ipp |
| 312 | input dmc_ipp_dat_req2; // dmc request data from rxc_data_fifo_2 |
| 313 | |
| 314 | // output of ipp2 |
| 315 | output rxc_mac_ack2; // ack from ipp to bmac |
| 316 | output ipp_dmc_dat_ack2; // rxc_data_fifo_2 is sending data to dmc |
| 317 | output [129:0] ipp_dmc_data2; // rxc_data_fifo_2's data to dmc |
| 318 | output ipp_dmc_ful_pkt2; // rxc_data_fifo_2 has at least 1 full packet |
| 319 | output ipp_dmc_dat_err2; // rxc_data_fifo_2 data has error |
| 320 | |
| 321 | // input to ipp3 |
| 322 | input mac_rxc_req3; // bmac sends the request to ipp |
| 323 | input mac_rxc_tag3; // bmac identifies the last part packet |
| 324 | input [63:0] mac_rxc_data3; // bmac writing the data to ipp |
| 325 | input mac_rxc_ctrl3; // active high for control information |
| 326 | input [22:0] mac_rxc_stat3; // bmac writing the status to ipp |
| 327 | input dmc_ipp_dat_req3; // dmc request data from rxc_data_fifo_3 |
| 328 | |
| 329 | // output of ipp3 |
| 330 | output rxc_mac_ack3; // ack from ipp to bmac |
| 331 | output ipp_dmc_dat_ack3; // rxc_data_fifo_3 is sending data to dmc |
| 332 | output [129:0] ipp_dmc_data3; // rxc_data_fifo_3's data to dmc |
| 333 | output ipp_dmc_ful_pkt3; // rxc_data_fifo_3 has at least 1 full packet |
| 334 | output ipp_dmc_dat_err3; // rxc_data_fifo_3 data has error |
| 335 | `endif |
| 336 | |
| 337 | reg pio_ipp_sel; // select ipp's |
| 338 | reg [19:0] pio_addr; |
| 339 | reg pio_rd; // rd_wr |
| 340 | reg [31:0] pio_wdata; |
| 341 | |
| 342 | /*****************************************************************************/ |
| 343 | // output to ffl |
| 344 | wire ipp_fflp_dvalid; |
| 345 | wire [1:0] ipp_fflp_port; |
| 346 | wire [127:0] ipp_fflp_data; |
| 347 | wire [11:0] ipp_fflp_mac_default; |
| 348 | |
| 349 | // output to cpu |
| 350 | reg ipp_pio_ack; |
| 351 | reg [63:0] ipp_pio_rdata; |
| 352 | reg ipp_pio_err; |
| 353 | reg ipp_pio_intr; |
| 354 | reg [31:0] ipp_debug_port; |
| 355 | |
| 356 | // output of ipp0 |
| 357 | wire rxc_mac_req0; |
| 358 | wire ipp_dmc_dat_ack0; |
| 359 | wire [129:0] ipp_dmc_data0; |
| 360 | wire ipp_dmc_ful_pkt0; |
| 361 | wire ipp_dmc_dat_err0; |
| 362 | |
| 363 | // output of ipp1 |
| 364 | wire rxc_mac_req1; |
| 365 | wire ipp_dmc_dat_ack1; |
| 366 | wire [129:0] ipp_dmc_data1; |
| 367 | wire ipp_dmc_ful_pkt1; |
| 368 | wire ipp_dmc_dat_err1; |
| 369 | |
| 370 | `ifdef NEPTUNE |
| 371 | // output of ipp2 |
| 372 | wire rxc_mac_ack2; |
| 373 | wire ipp_dmc_dat_ack2; |
| 374 | wire [129:0] ipp_dmc_data2; |
| 375 | wire ipp_dmc_ful_pkt2; |
| 376 | wire ipp_dmc_dat_err2; |
| 377 | |
| 378 | // output of ipp3 |
| 379 | wire rxc_mac_ack3; |
| 380 | wire ipp_dmc_dat_ack3; |
| 381 | wire [129:0] ipp_dmc_data3; |
| 382 | wire ipp_dmc_ful_pkt3; |
| 383 | wire ipp_dmc_dat_err3; |
| 384 | `endif |
| 385 | |
| 386 | /*****************************************************************************/ |
| 387 | // output of ipp0 |
| 388 | wire ipp_ack0; |
| 389 | wire [31:0] ipp_rdata0; |
| 390 | wire ipp_pio_err0; |
| 391 | wire ipp_intr0; |
| 392 | wire [31:0] ipp_debug0; |
| 393 | wire debug_out_ena0; |
| 394 | |
| 395 | wire sel_ipp0; |
| 396 | |
| 397 | // output of ipp1 |
| 398 | wire ipp_ack1; |
| 399 | wire [31:0] ipp_rdata1; |
| 400 | wire ipp_pio_err1; |
| 401 | wire ipp_intr1; |
| 402 | wire [31:0] ipp_debug1; |
| 403 | wire debug_out_ena1; |
| 404 | |
| 405 | wire sel_ipp1; |
| 406 | wire /*geo*/ clk1 = clk; |
| 407 | |
| 408 | `ifdef NEPTUNE |
| 409 | // output of ipp2 |
| 410 | wire ipp_ack2; |
| 411 | wire [31:0] ipp_rdata2; |
| 412 | wire ipp_pio_err2; |
| 413 | wire ipp_intr2; |
| 414 | wire [31:0] ipp_debug2; |
| 415 | wire debug_out_ena2; |
| 416 | |
| 417 | wire sel_ipp2; |
| 418 | wire /*geo*/ clk2 = clk; |
| 419 | |
| 420 | // output of ipp3 |
| 421 | wire ipp_ack3; |
| 422 | wire [31:0] ipp_rdata3; |
| 423 | wire ipp_pio_err3; |
| 424 | wire ipp_intr3; |
| 425 | wire [31:0] ipp_debug3; |
| 426 | wire debug_out_ena3; |
| 427 | |
| 428 | wire sel_ipp3; |
| 429 | wire /*geo*/ clk3 = clk; |
| 430 | `endif |
| 431 | |
| 432 | /*****************************************************************************/ |
| 433 | |
| 434 | /*****************************************************************************/ |
| 435 | // for ffl_arbiter |
| 436 | wire ipp_ffl_req0; |
| 437 | wire [127:0] ipp_ffl_data0; |
| 438 | wire [11:0] ipp_ffl_mac_default0; |
| 439 | wire ipp_ffl_dvalid0; |
| 440 | wire ffl_arb_ack0; |
| 441 | |
| 442 | wire ipp_ffl_req1; |
| 443 | wire [127:0] ipp_ffl_data1; |
| 444 | wire [11:0] ipp_ffl_mac_default1; |
| 445 | wire ipp_ffl_dvalid1; |
| 446 | wire ffl_arb_ack1; |
| 447 | |
| 448 | `ifdef NEPTUNE |
| 449 | wire ipp_ffl_req2; |
| 450 | wire [127:0] ipp_ffl_data2; |
| 451 | wire [11:0] ipp_ffl_mac_default2; |
| 452 | wire ipp_ffl_dvalid2; |
| 453 | wire ffl_arb_ack2; |
| 454 | |
| 455 | wire ipp_ffl_req3; |
| 456 | wire [127:0] ipp_ffl_data3; |
| 457 | wire [11:0] ipp_ffl_mac_default3; |
| 458 | wire ipp_ffl_dvalid3; |
| 459 | wire ffl_arb_ack3; |
| 460 | `endif |
| 461 | |
| 462 | wire ipp_ack; |
| 463 | wire [31:0] ipp_rdata_32; |
| 464 | wire [63:0] ipp_rdata; |
| 465 | wire ipp_err; |
| 466 | wire ipp_intr; |
| 467 | wire [31:0] ipp_debug; |
| 468 | |
| 469 | /******************************* local reset *********************************/ |
| 470 | wire reset_ipp; |
| 471 | |
| 472 | niu_ipp_reset_blk ipp_reset_blk (.reset_l(reset_l), .clk(clk), .reset(reset_ipp)); |
| 473 | |
| 474 | /*****************************************************************************/ |
| 475 | |
| 476 | `ifdef NEPTUNE |
| 477 | `else |
| 478 | /******************************* N2 mode memory scan and mbist staff *********/ |
| 479 | wire [9:0] niu_mb3_addr; |
| 480 | wire [7:0] niu_mb3_wdata; |
| 481 | wire niu_mb3_run; |
| 482 | |
| 483 | wire [9:0] niu_mb4_addr; |
| 484 | wire [7:0] niu_mb4_wdata; |
| 485 | wire niu_mb4_run; |
| 486 | |
| 487 | wire [7:0] niu_mb3_prebuf_header_wdata = niu_mb3_wdata; |
| 488 | wire [5:0] niu_mb3_prebuf_header_rd_addr = niu_mb3_addr[5:0]; |
| 489 | wire [5:0] niu_mb3_prebuf_header_wr_addr = niu_mb3_addr[5:0]; |
| 490 | wire niu_mb3_prebuf_header_wr_en; |
| 491 | wire niu_mb3_prebuf_header_rd_en; |
| 492 | wire niu_mb3_prebuf_header_run = niu_mb3_run; |
| 493 | wire niu_mb3_prebuf_header_scan_out; |
| 494 | wire [145:0] niu_mb3_prebuf_header_data_out; |
| 495 | |
| 496 | wire [7:0] niu_mb3_rx_data_fifo_wdata = niu_mb3_wdata; |
| 497 | wire [9:0] niu_mb3_rx_data_fifo_rd_addr = niu_mb3_addr[9:0]; |
| 498 | wire [9:0] niu_mb3_rx_data_fifo_wr_addr = niu_mb3_addr[9:0]; |
| 499 | wire niu_mb3_rx_data_fifo_wr_en; |
| 500 | wire niu_mb3_rx_data_fifo_rd_en; |
| 501 | wire niu_mb3_rx_data_fifo_run = niu_mb3_run; |
| 502 | wire niu_mb3_rx_data_fifo_scan_out; |
| 503 | wire [145:0] niu_mb3_rx_data_fifo_data_out; |
| 504 | |
| 505 | wire rtx_rxc_ipp0_tcu_mbist_fail; |
| 506 | wire rtx_rxc_ipp0_tcu_mbist_done; |
| 507 | wire rtx_rxc_ipp0_mb3_mbist_scan_out; |
| 508 | wire [39:0] rtx_rxc_ipp0_mb3_dmo_dout; |
| 509 | |
| 510 | wire [7:0] niu_mb4_prebuf_header_wdata = niu_mb4_wdata; |
| 511 | wire [5:0] niu_mb4_prebuf_header_rd_addr = niu_mb4_addr[5:0]; |
| 512 | wire [5:0] niu_mb4_prebuf_header_wr_addr = niu_mb4_addr[5:0]; |
| 513 | wire niu_mb4_prebuf_header_wr_en; |
| 514 | wire niu_mb4_prebuf_header_rd_en; |
| 515 | wire niu_mb4_prebuf_header_run = niu_mb4_run; |
| 516 | wire niu_mb4_prebuf_header_scan_in; |
| 517 | wire niu_mb4_prebuf_header_scan_out; |
| 518 | wire [145:0] niu_mb4_prebuf_header_data_out; |
| 519 | |
| 520 | wire [7:0] niu_mb4_rx_data_fifo_wdata = niu_mb4_wdata; |
| 521 | wire [9:0] niu_mb4_rx_data_fifo_rd_addr = niu_mb4_addr[9:0]; |
| 522 | wire [9:0] niu_mb4_rx_data_fifo_wr_addr = niu_mb4_addr[9:0]; |
| 523 | wire niu_mb4_rx_data_fifo_wr_en; |
| 524 | wire niu_mb4_rx_data_fifo_rd_en; |
| 525 | wire niu_mb4_rx_data_fifo_run = niu_mb4_run; |
| 526 | wire niu_mb4_rx_data_fifo_scan_out; |
| 527 | wire [145:0] niu_mb4_rx_data_fifo_data_out; |
| 528 | |
| 529 | wire rtx_rxc_ipp1_tcu_mbist_fail; |
| 530 | wire rtx_rxc_ipp1_tcu_mbist_done; |
| 531 | wire rtx_rxc_ipp1_mb3_mbist_scan_out; |
| 532 | wire [39:0] rtx_rxc_ipp1_mb3_dmo_dout; |
| 533 | |
| 534 | niu_mb3 niu_mb3_ipp0 ( |
| 535 | .rst (reset_ipp), |
| 536 | .niu_mb3_rx_data_fifo_rd_en (niu_mb3_rx_data_fifo_rd_en), |
| 537 | .niu_mb3_rx_data_fifo_wr_en (niu_mb3_rx_data_fifo_wr_en), |
| 538 | .niu_mb3_prebuf_header_rd_en (niu_mb3_prebuf_header_rd_en), |
| 539 | .niu_mb3_prebuf_header_wr_en (niu_mb3_prebuf_header_wr_en), |
| 540 | .niu_mb3_addr (niu_mb3_addr[9:0]), |
| 541 | .niu_mb3_wdata (niu_mb3_wdata), |
| 542 | .niu_mb3_run (niu_mb3_run), |
| 543 | .niu_mb3_rx_data_fifo_data_out (niu_mb3_rx_data_fifo_data_out), |
| 544 | .niu_mb3_prebuf_header_data_out (niu_mb3_prebuf_header_data_out), |
| 545 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en), |
| 546 | .tcu_niu_mbist_start_3 (tcu_rtx_rxc_ipp0_mbist_start), |
| 547 | .niu_tcu_mbist_fail_3 (rtx_rxc_ipp0_tcu_mbist_fail), |
| 548 | .niu_tcu_mbist_done_3 (rtx_rxc_ipp0_tcu_mbist_done), |
| 549 | .l1clk (clk), |
| 550 | .mb3_scan_out (rtx_rxc_ipp0_mb3_mbist_scan_out), |
| 551 | .mb3_dmo_dout (rtx_rxc_ipp0_mb3_dmo_dout), |
| 552 | .mb3_scan_in (rtx_rxc_ipp0_mb3_mbist_scan_in), |
| 553 | .tcu_aclk (tcu_aclk), |
| 554 | .tcu_bclk (tcu_bclk), |
| 555 | .tcu_mbist_user_mode (tcu_mbist_user_mode) |
| 556 | ); |
| 557 | |
| 558 | niu_mb3 niu_mb3_ipp1 ( |
| 559 | .rst (reset_ipp), |
| 560 | .niu_mb3_rx_data_fifo_rd_en (niu_mb4_rx_data_fifo_rd_en), |
| 561 | .niu_mb3_rx_data_fifo_wr_en (niu_mb4_rx_data_fifo_wr_en), |
| 562 | .niu_mb3_prebuf_header_rd_en (niu_mb4_prebuf_header_rd_en), |
| 563 | .niu_mb3_prebuf_header_wr_en (niu_mb4_prebuf_header_wr_en), |
| 564 | .niu_mb3_addr (niu_mb4_addr[9:0]), |
| 565 | .niu_mb3_wdata (niu_mb4_wdata), |
| 566 | .niu_mb3_run (niu_mb4_run), |
| 567 | .niu_mb3_rx_data_fifo_data_out (niu_mb4_rx_data_fifo_data_out), |
| 568 | .niu_mb3_prebuf_header_data_out (niu_mb4_prebuf_header_data_out), |
| 569 | .tcu_mbist_bisi_en (tcu_mbist_bisi_en), |
| 570 | .tcu_niu_mbist_start_3 (tcu_rtx_rxc_ipp1_mbist_start), |
| 571 | .niu_tcu_mbist_fail_3 (rtx_rxc_ipp1_tcu_mbist_fail), |
| 572 | .niu_tcu_mbist_done_3 (rtx_rxc_ipp1_tcu_mbist_done), |
| 573 | .l1clk (clk), |
| 574 | .mb3_scan_out (rtx_rxc_ipp1_mb3_mbist_scan_out), |
| 575 | .mb3_dmo_dout (rtx_rxc_ipp1_mb3_dmo_dout), |
| 576 | .mb3_scan_in (rtx_rxc_ipp1_mb3_mbist_scan_in), |
| 577 | .tcu_aclk (tcu_aclk), |
| 578 | .tcu_bclk (tcu_bclk), |
| 579 | .tcu_mbist_user_mode (tcu_mbist_user_mode) |
| 580 | ); |
| 581 | |
| 582 | /******************************* N2 mode repairable SRAM headers *************/ |
| 583 | wire [6:0] sram_hdr_read_data_ipp0; |
| 584 | wire [6:0] sram_hdr_read_data_ipp1; |
| 585 | `endif |
| 586 | |
| 587 | /******************************* pio access **********************************/ |
| 588 | `ifdef NEPTUNE |
| 589 | assign sel_ipp3 = pio_ipp_sel && (pio_addr[19:14] == `NIU_IPP_PIO_SPACE_IPP3_NEP); |
| 590 | assign sel_ipp2 = pio_ipp_sel && (pio_addr[19:14] == `NIU_IPP_PIO_SPACE_IPP2_NEP); |
| 591 | assign sel_ipp1 = pio_ipp_sel && (pio_addr[19:14] == `NIU_IPP_PIO_SPACE_IPP1_NEP); |
| 592 | assign sel_ipp0 = pio_ipp_sel && (pio_addr[19:14] == `NIU_IPP_PIO_SPACE_IPP0_NEP); |
| 593 | `else |
| 594 | assign sel_ipp1 = pio_ipp_sel && (pio_addr[19:15] == `NIU_IPP_PIO_SPACE_IPP1_N2); |
| 595 | assign sel_ipp0 = pio_ipp_sel && (pio_addr[19:15] == `NIU_IPP_PIO_SPACE_IPP0_N2); |
| 596 | `endif |
| 597 | |
| 598 | assign ipp_ack = `ifdef NEPTUNE sel_ipp3 && ipp_ack3 || sel_ipp2 && ipp_ack2 || `endif |
| 599 | sel_ipp1 && ipp_ack1 || sel_ipp0 && ipp_ack0; |
| 600 | |
| 601 | assign ipp_rdata_32 = `ifdef NEPTUNE {32{sel_ipp3}} & ipp_rdata3[31:0] | |
| 602 | {32{sel_ipp2}} & ipp_rdata2[31:0] | `endif |
| 603 | {32{sel_ipp1}} & ipp_rdata1[31:0] | |
| 604 | {32{sel_ipp0}} & ipp_rdata0[31:0]; |
| 605 | |
| 606 | assign ipp_rdata = {32'h0,ipp_rdata_32[31:0]}; |
| 607 | |
| 608 | assign ipp_err = `ifdef NEPTUNE ipp_pio_err3 || ipp_pio_err2 || `endif |
| 609 | ipp_pio_err1 || ipp_pio_err0; |
| 610 | |
| 611 | assign ipp_intr = `ifdef NEPTUNE ipp_intr3 || ipp_intr2 || `endif |
| 612 | ipp_intr1 || ipp_intr0; |
| 613 | |
| 614 | assign ipp_debug = `ifdef NEPTUNE {32{debug_out_ena3}} & ipp_debug3[31:0] | {32{debug_out_ena2}} & ipp_debug2[31:0] | `endif |
| 615 | {32{debug_out_ena1}} & ipp_debug1[31:0] | {32{debug_out_ena0}} & ipp_debug0[31:0]; |
| 616 | |
| 617 | /******************************* Instantiation *******************************/ |
| 618 | |
| 619 | // ipp_ffl arbiter |
| 620 | niu_ipp_ffl_arbiter ffl_arbiter( |
| 621 | // input signals |
| 622 | .ipp_ffl_req0 (ipp_ffl_req0), |
| 623 | .ipp_fflp_data0 (ipp_ffl_data0[127:0]), |
| 624 | .ipp_fflp_mac_default0 (ipp_ffl_mac_default0[11:0]), |
| 625 | .ipp_fflp_dvalid0 (ipp_ffl_dvalid0), |
| 626 | .ipp_ffl_req1 (ipp_ffl_req1), |
| 627 | .ipp_fflp_data1 (ipp_ffl_data1[127:0]), |
| 628 | .ipp_fflp_mac_default1 (ipp_ffl_mac_default1[11:0]), |
| 629 | .ipp_fflp_dvalid1 (ipp_ffl_dvalid1), |
| 630 | `ifdef NEPTUNE |
| 631 | .ipp_ffl_req2 (ipp_ffl_req2), |
| 632 | .ipp_fflp_data2 (ipp_ffl_data2[127:0]), |
| 633 | .ipp_fflp_mac_default2 (ipp_ffl_mac_default2[11:0]), |
| 634 | .ipp_fflp_dvalid2 (ipp_ffl_dvalid2), |
| 635 | .ipp_ffl_req3 (ipp_ffl_req3), |
| 636 | .ipp_fflp_data3 (ipp_ffl_data3[127:0]), |
| 637 | .ipp_fflp_mac_default3 (ipp_ffl_mac_default3[11:0]), |
| 638 | .ipp_fflp_dvalid3 (ipp_ffl_dvalid3), |
| 639 | `endif |
| 640 | .reset (reset_ipp), |
| 641 | .clk(clk), |
| 642 | // output signals |
| 643 | .ffl_arb_ack0 (ffl_arb_ack0), |
| 644 | .ffl_arb_ack1 (ffl_arb_ack1), |
| 645 | `ifdef NEPTUNE |
| 646 | .ffl_arb_ack2 (ffl_arb_ack2), |
| 647 | .ffl_arb_ack3 (ffl_arb_ack3), |
| 648 | `endif |
| 649 | .ipp_fflp_dvalid (ipp_fflp_dvalid), |
| 650 | .ipp_fflp_data (ipp_fflp_data[127:0]), |
| 651 | .ipp_fflp_port (ipp_fflp_port[1:0]), |
| 652 | .ipp_fflp_mac_default (ipp_fflp_mac_default[11:0]) |
| 653 | ); // end of ffl_arbiter |
| 654 | |
| 655 | // ipp0 module (connected to xmac) |
| 656 | `ifdef NEPTUNE niu_ipp_2ke ipp0( |
| 657 | .ipp_pio_addr (pio_addr[13:0]), |
| 658 | `else niu_ipp_1ke ipp0( |
| 659 | .ipp_pio_addr (pio_addr[14:0]), |
| 660 | .tcu_aclk (tcu_aclk), |
| 661 | .tcu_bclk (tcu_bclk), |
| 662 | .tcu_scan_en (tcu_scan_en), |
| 663 | .tcu_se_scancollar_in (tcu_se_scancollar_in), |
| 664 | .tcu_se_scancollar_out (tcu_se_scancollar_out), |
| 665 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), |
| 666 | |
| 667 | .hdr_sram_rvalue (hdr_sram_rvalue_ipp0[6:0]), |
| 668 | .hdr_sram_rid (hdr_sram_rid_ipp0[2:0]), |
| 669 | .hdr_sram_wr_en (hdr_sram_wr_en_ipp0), |
| 670 | .hdr_sram_red_clr (hdr_sram_red_clr_ipp0), |
| 671 | .sram_hdr_read_data (sram_hdr_read_data_ipp0[6:0]), |
| 672 | |
| 673 | .iol2clk (iol2clk), |
| 674 | .l2clk_2x (l2clk_2x), |
| 675 | |
| 676 | .mbi_prebuf_header_wdata (niu_mb3_prebuf_header_wdata), |
| 677 | .mbi_prebuf_header_rd_addr (niu_mb3_prebuf_header_rd_addr), |
| 678 | .mbi_prebuf_header_wr_addr (niu_mb3_prebuf_header_wr_addr), |
| 679 | .mbi_prebuf_header_wr_en (niu_mb3_prebuf_header_wr_en), |
| 680 | .mbi_prebuf_header_rd_en (niu_mb3_prebuf_header_rd_en), |
| 681 | .mbi_prebuf_header_run (niu_mb3_prebuf_header_run), |
| 682 | .mbi_prebuf_header_scan_in (niu_mb3_prebuf_header_scan_in), |
| 683 | .mbi_prebuf_header_scan_out (niu_mb3_prebuf_header_scan_out), |
| 684 | .mbi_prebuf_header_data_out (niu_mb3_prebuf_header_data_out), |
| 685 | |
| 686 | .mbi_rx_data_fifo_wdata (niu_mb3_rx_data_fifo_wdata), |
| 687 | .mbi_rx_data_fifo_rd_addr (niu_mb3_rx_data_fifo_rd_addr), |
| 688 | .mbi_rx_data_fifo_wr_addr (niu_mb3_rx_data_fifo_wr_addr), |
| 689 | .mbi_rx_data_fifo_wr_en (niu_mb3_rx_data_fifo_wr_en), |
| 690 | .mbi_rx_data_fifo_rd_en (niu_mb3_rx_data_fifo_rd_en), |
| 691 | .mbi_rx_data_fifo_run (niu_mb3_rx_data_fifo_run), |
| 692 | .mbi_rx_data_fifo_scan_in (niu_mb3_rx_data_fifo_scan_in), |
| 693 | .mbi_rx_data_fifo_scan_out (niu_mb3_rx_data_fifo_scan_out), |
| 694 | .mbi_rx_data_fifo_data_out (niu_mb3_rx_data_fifo_data_out), |
| 695 | `endif |
| 696 | // xmac interface |
| 697 | .mac_ipp_req (1'b0), |
| 698 | .xmac_ipp_ack (mac_rxc_ack0), |
| 699 | .mac_ipp_tag (mac_rxc_tag0), |
| 700 | .mac_ipp_data (mac_rxc_data0), |
| 701 | .mac_ipp_ctrl (mac_rxc_ctrl0), |
| 702 | .mac_ipp_stat (mac_rxc_stat0), |
| 703 | .ipp_mac_ack (), |
| 704 | .ipp_xmac_req (rxc_mac_req0), |
| 705 | // ffl interface |
| 706 | .ffl_ipp_dvalid (fflp_ipp_dvalid[0]), |
| 707 | .ffl_ipp_data (fflp_ipp_sum[13:0]), |
| 708 | .ffl_ipp_ready (fflp_ipp_ready), |
| 709 | .ipp_ffl_dvalid (ipp_ffl_dvalid0), |
| 710 | .ipp_ffl_data (ipp_ffl_data0), |
| 711 | .ipp_ffl_mac_default (ipp_ffl_mac_default0[11:0]), |
| 712 | // dmc interface |
| 713 | .dmc_ipp_dat_req (dmc_ipp_dat_req0), |
| 714 | .ipp_dmc_dat_ack (ipp_dmc_dat_ack0), |
| 715 | .ipp_dmc_data (ipp_dmc_data0[129:0]), |
| 716 | .ipp_dmc_ful_pkt (ipp_dmc_ful_pkt0), |
| 717 | .ipp_dmc_dat_err (ipp_dmc_dat_err0), |
| 718 | // ffl_arb interface |
| 719 | .ipp_ffl_req (ipp_ffl_req0), |
| 720 | .ffl_arb_ack (ffl_arb_ack0), |
| 721 | // cpu interface |
| 722 | .ipp_pio_sel (sel_ipp0), |
| 723 | .ipp_pio_rd (pio_rd), |
| 724 | .ipp_pio_wdata (pio_wdata[31:0]), |
| 725 | .ipp_pio_ack (ipp_ack0), |
| 726 | .ipp_pio_rdata (ipp_rdata0[31:0]), |
| 727 | .ipp_pio_err (ipp_pio_err0), |
| 728 | .ipp_pio_intr (ipp_intr0), |
| 729 | .ipp_debug (ipp_debug0[31:0]), |
| 730 | .debug_out_ena (debug_out_ena0), |
| 731 | // global |
| 732 | .xmac_mode (1'b1), |
| 733 | .port_id (2'b00), |
| 734 | .clk (clk), |
| 735 | .reset (reset_ipp) |
| 736 | ); // end of ipp0 |
| 737 | |
| 738 | // ipp1 module (connected to xmac) |
| 739 | `ifdef NEPTUNE niu_ipp_2ke ipp1( |
| 740 | .ipp_pio_addr (pio_addr[13:0]), |
| 741 | `else niu_ipp_1ke ipp1( |
| 742 | .ipp_pio_addr (pio_addr[14:0]), |
| 743 | .tcu_aclk (tcu_aclk), |
| 744 | .tcu_bclk (tcu_bclk), |
| 745 | .tcu_scan_en (tcu_scan_en), |
| 746 | .tcu_se_scancollar_in (tcu_se_scancollar_in), |
| 747 | .tcu_se_scancollar_out (tcu_se_scancollar_out), |
| 748 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), |
| 749 | |
| 750 | .hdr_sram_rvalue (hdr_sram_rvalue_ipp1[6:0]), |
| 751 | .hdr_sram_rid (hdr_sram_rid_ipp1[2:0]), |
| 752 | .hdr_sram_wr_en (hdr_sram_wr_en_ipp1), |
| 753 | .hdr_sram_red_clr (hdr_sram_red_clr_ipp1), |
| 754 | .sram_hdr_read_data (sram_hdr_read_data_ipp1[6:0]), |
| 755 | |
| 756 | .iol2clk (iol2clk), |
| 757 | .l2clk_2x (l2clk_2x), |
| 758 | |
| 759 | .mbi_prebuf_header_wdata (niu_mb4_prebuf_header_wdata), |
| 760 | .mbi_prebuf_header_rd_addr (niu_mb4_prebuf_header_rd_addr), |
| 761 | .mbi_prebuf_header_wr_addr (niu_mb4_prebuf_header_wr_addr), |
| 762 | .mbi_prebuf_header_wr_en (niu_mb4_prebuf_header_wr_en), |
| 763 | .mbi_prebuf_header_rd_en (niu_mb4_prebuf_header_rd_en), |
| 764 | .mbi_prebuf_header_run (niu_mb4_prebuf_header_run), |
| 765 | .mbi_prebuf_header_scan_in (niu_mb4_prebuf_header_scan_in), |
| 766 | .mbi_prebuf_header_scan_out (niu_mb4_prebuf_header_scan_out), |
| 767 | .mbi_prebuf_header_data_out (niu_mb4_prebuf_header_data_out), |
| 768 | |
| 769 | .mbi_rx_data_fifo_wdata (niu_mb4_rx_data_fifo_wdata), |
| 770 | .mbi_rx_data_fifo_rd_addr (niu_mb4_rx_data_fifo_rd_addr), |
| 771 | .mbi_rx_data_fifo_wr_addr (niu_mb4_rx_data_fifo_wr_addr), |
| 772 | .mbi_rx_data_fifo_wr_en (niu_mb4_rx_data_fifo_wr_en), |
| 773 | .mbi_rx_data_fifo_rd_en (niu_mb4_rx_data_fifo_rd_en), |
| 774 | .mbi_rx_data_fifo_run (niu_mb4_rx_data_fifo_run), |
| 775 | .mbi_rx_data_fifo_scan_in (niu_mb4_rx_data_fifo_scan_in), |
| 776 | .mbi_rx_data_fifo_scan_out (niu_mb4_rx_data_fifo_scan_out), |
| 777 | .mbi_rx_data_fifo_data_out (niu_mb4_rx_data_fifo_data_out), |
| 778 | `endif |
| 779 | // xmac interface |
| 780 | .mac_ipp_req (1'b0), |
| 781 | .xmac_ipp_ack (mac_rxc_ack1), |
| 782 | .mac_ipp_tag (mac_rxc_tag1), |
| 783 | .mac_ipp_data (mac_rxc_data1), |
| 784 | .mac_ipp_ctrl (mac_rxc_ctrl1), |
| 785 | .mac_ipp_stat (mac_rxc_stat1), |
| 786 | .ipp_mac_ack (), |
| 787 | .ipp_xmac_req (rxc_mac_req1), |
| 788 | // ffl interface |
| 789 | .ffl_ipp_dvalid (fflp_ipp_dvalid[1]), |
| 790 | .ffl_ipp_data (fflp_ipp_sum[13:0]), |
| 791 | .ffl_ipp_ready (fflp_ipp_ready), |
| 792 | .ipp_ffl_dvalid (ipp_ffl_dvalid1), |
| 793 | .ipp_ffl_data (ipp_ffl_data1), |
| 794 | .ipp_ffl_mac_default (ipp_ffl_mac_default1[11:0]), |
| 795 | // dmc interface |
| 796 | .dmc_ipp_dat_req (dmc_ipp_dat_req1), |
| 797 | .ipp_dmc_dat_ack (ipp_dmc_dat_ack1), |
| 798 | .ipp_dmc_data (ipp_dmc_data1[129:0]), |
| 799 | .ipp_dmc_ful_pkt (ipp_dmc_ful_pkt1), |
| 800 | .ipp_dmc_dat_err (ipp_dmc_dat_err1), |
| 801 | // ffl_arb interface |
| 802 | .ipp_ffl_req (ipp_ffl_req1), |
| 803 | .ffl_arb_ack (ffl_arb_ack1), |
| 804 | // cpu interface |
| 805 | .ipp_pio_sel (sel_ipp1), |
| 806 | .ipp_pio_rd (pio_rd), |
| 807 | .ipp_pio_wdata (pio_wdata[31:0]), |
| 808 | .ipp_pio_ack (ipp_ack1), |
| 809 | .ipp_pio_rdata (ipp_rdata1[31:0]), |
| 810 | .ipp_pio_err (ipp_pio_err1), |
| 811 | .ipp_pio_intr (ipp_intr1), |
| 812 | .ipp_debug (ipp_debug1[31:0]), |
| 813 | .debug_out_ena (debug_out_ena1), |
| 814 | // global |
| 815 | .xmac_mode (1'b1), |
| 816 | .port_id (2'b01), |
| 817 | .clk (clk1), |
| 818 | .reset (reset_ipp) |
| 819 | ); // end of ipp1 |
| 820 | |
| 821 | `ifdef NEPTUNE |
| 822 | // ipp2 module (connected to mac) |
| 823 | niu_ipp_1ke ipp2( |
| 824 | // mac interface |
| 825 | .mac_ipp_req (mac_rxc_req2), |
| 826 | .xmac_ipp_ack (1'b0), |
| 827 | .mac_ipp_tag (mac_rxc_tag2), |
| 828 | .mac_ipp_data (mac_rxc_data2), |
| 829 | .mac_ipp_ctrl (mac_rxc_ctrl2), |
| 830 | .mac_ipp_stat (mac_rxc_stat2), |
| 831 | .ipp_mac_ack (rxc_mac_ack2), |
| 832 | .ipp_xmac_req (), |
| 833 | // ffl interface |
| 834 | .ffl_ipp_dvalid (fflp_ipp_dvalid[2]), |
| 835 | .ffl_ipp_data (fflp_ipp_sum[13:0]), |
| 836 | .ffl_ipp_ready (fflp_ipp_ready), |
| 837 | .ipp_ffl_dvalid (ipp_ffl_dvalid2), |
| 838 | .ipp_ffl_data (ipp_ffl_data2), |
| 839 | .ipp_ffl_mac_default (ipp_ffl_mac_default2[11:0]), |
| 840 | // dmc interface |
| 841 | .dmc_ipp_dat_req (dmc_ipp_dat_req2), |
| 842 | .ipp_dmc_dat_ack (ipp_dmc_dat_ack2), |
| 843 | .ipp_dmc_data (ipp_dmc_data2[129:0]), |
| 844 | .ipp_dmc_ful_pkt (ipp_dmc_ful_pkt2), |
| 845 | .ipp_dmc_dat_err (ipp_dmc_dat_err2), |
| 846 | // ffl_arb interface |
| 847 | .ipp_ffl_req (ipp_ffl_req2), |
| 848 | .ffl_arb_ack (ffl_arb_ack2), |
| 849 | // cpu interface |
| 850 | .ipp_pio_sel (sel_ipp2), |
| 851 | .ipp_pio_addr (pio_addr[13:0]), |
| 852 | .ipp_pio_rd (pio_rd), |
| 853 | .ipp_pio_wdata (pio_wdata[31:0]), |
| 854 | .ipp_pio_ack (ipp_ack2), |
| 855 | .ipp_pio_rdata (ipp_rdata2[31:0]), |
| 856 | .ipp_pio_err (ipp_pio_err2), |
| 857 | .ipp_pio_intr (ipp_intr2), |
| 858 | .ipp_debug (ipp_debug2[31:0]), |
| 859 | .debug_out_ena (debug_out_ena2), |
| 860 | // global |
| 861 | .xmac_mode (1'b0), |
| 862 | .port_id (2'b10), |
| 863 | .clk (clk2), |
| 864 | .reset (reset_ipp) |
| 865 | ); // end of ipp2 |
| 866 | |
| 867 | // ipp3 module (connected to mac) |
| 868 | niu_ipp_1ke ipp3( |
| 869 | // mac interface |
| 870 | .mac_ipp_req (mac_rxc_req3), |
| 871 | .xmac_ipp_ack (1'b0), |
| 872 | .mac_ipp_tag (mac_rxc_tag3), |
| 873 | .mac_ipp_data (mac_rxc_data3), |
| 874 | .mac_ipp_ctrl (mac_rxc_ctrl3), |
| 875 | .mac_ipp_stat (mac_rxc_stat3), |
| 876 | .ipp_mac_ack (rxc_mac_ack3), |
| 877 | .ipp_xmac_req (), |
| 878 | // ffl interface |
| 879 | .ffl_ipp_dvalid (fflp_ipp_dvalid[3]), |
| 880 | .ffl_ipp_data (fflp_ipp_sum[13:0]), |
| 881 | .ffl_ipp_ready (fflp_ipp_ready), |
| 882 | .ipp_ffl_dvalid (ipp_ffl_dvalid3), |
| 883 | .ipp_ffl_data (ipp_ffl_data3), |
| 884 | .ipp_ffl_mac_default (ipp_ffl_mac_default3[11:0]), |
| 885 | // dmc interface |
| 886 | .dmc_ipp_dat_req (dmc_ipp_dat_req3), |
| 887 | .ipp_dmc_dat_ack (ipp_dmc_dat_ack3), |
| 888 | .ipp_dmc_data (ipp_dmc_data3[129:0]), |
| 889 | .ipp_dmc_ful_pkt (ipp_dmc_ful_pkt3), |
| 890 | .ipp_dmc_dat_err (ipp_dmc_dat_err3), |
| 891 | // ffl_arb interface |
| 892 | .ipp_ffl_req (ipp_ffl_req3), |
| 893 | .ffl_arb_ack (ffl_arb_ack3), |
| 894 | // cpu interface |
| 895 | .ipp_pio_sel (sel_ipp3), |
| 896 | .ipp_pio_addr (pio_addr[13:0]), |
| 897 | .ipp_pio_rd (pio_rd), |
| 898 | .ipp_pio_wdata (pio_wdata[31:0]), |
| 899 | .ipp_pio_ack (ipp_ack3), |
| 900 | .ipp_pio_rdata (ipp_rdata3[31:0]), |
| 901 | .ipp_pio_err (ipp_pio_err3), |
| 902 | .ipp_pio_intr (ipp_intr3), |
| 903 | .ipp_debug (ipp_debug3[31:0]), |
| 904 | .debug_out_ena (debug_out_ena3), |
| 905 | // global |
| 906 | .xmac_mode (1'b0), |
| 907 | .port_id (2'b11), |
| 908 | .clk (clk3), |
| 909 | .reset (reset_ipp) |
| 910 | ); // end of ipp3 |
| 911 | `endif |
| 912 | |
| 913 | /****** glue logic ******/ |
| 914 | always @ (posedge clk) |
| 915 | if (reset_ipp) begin |
| 916 | pio_ipp_sel <= 1'h0; |
| 917 | pio_addr <= 20'h0; |
| 918 | pio_rd <= 1'h0; |
| 919 | pio_wdata <= 32'h0; |
| 920 | ipp_pio_ack <= 1'h0; |
| 921 | ipp_pio_rdata <= 64'h0; |
| 922 | ipp_pio_err <= 1'h0; |
| 923 | ipp_pio_intr <= 1'h0; |
| 924 | ipp_debug_port <= 32'h0; |
| 925 | end |
| 926 | else begin |
| 927 | pio_ipp_sel <= pio_clients_sel_ipp; // select ipp's |
| 928 | pio_addr <= pio_clients_addr[19:0]; |
| 929 | pio_rd <= pio_clients_rd; // rd_wr |
| 930 | pio_wdata <= pio_clients_wdata[31:0]; |
| 931 | ipp_pio_ack <= ipp_ack; |
| 932 | ipp_pio_rdata <= ipp_rdata[63:0]; |
| 933 | ipp_pio_err <= ipp_err; |
| 934 | ipp_pio_intr <= ipp_intr; |
| 935 | ipp_debug_port <= ipp_debug[31:0]; |
| 936 | end |
| 937 | |
| 938 | endmodule |