| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_mb7.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | |
| 36 | /////////////////////////////////////////////////////////////////////////////// |
| 37 | // |
| 38 | // |
| 39 | // Released: 2/06/05 |
| 40 | // Authors: carlos.castil@sun.com/shahryar.aryani@sun.com |
| 41 | // Description: Memory BIST Controller for Niagara2 NIU core |
| 42 | // Block Type: Control Block |
| 43 | // Chip Name: |
| 44 | // Unit Name: |
| 45 | // Module: mbist_engine |
| 46 | // Where Instantiated: |
| 47 | // |
| 48 | // |
| 49 | // (c) 2005 Sun Microsystems, Inc. |
| 50 | // Sun Proprietary/Confidential |
| 51 | // Internal use only. |
| 52 | // |
| 53 | // All rights reserved. No part of this design may be reproduced stored |
| 54 | // in a retrieval system, or transmitted, in any form or by any means, |
| 55 | // electronic, mechanical, photocopying, recording, or otherwise, without |
| 56 | // prior written permission of Sun Microsystems, Inc. |
| 57 | // |
| 58 | /////////////////////////////////////////////////////////////////////////////// |
| 59 | |
| 60 | |
| 61 | module niu_mb7 ( |
| 62 | niu_mb7_cntrl_fifo_zcp_rd_en, |
| 63 | niu_mb7_cntrl_fifo_zcp_wr_en, |
| 64 | niu_mb7_addr, |
| 65 | niu_mb7_wdata, |
| 66 | niu_mb7_run, |
| 67 | niu_tcu_mbist_fail_7, |
| 68 | niu_tcu_mbist_done_7, |
| 69 | mb7_scan_out, |
| 70 | mb7_dmo_dout, |
| 71 | l1clk, |
| 72 | rst, |
| 73 | tcu_mbist_user_mode, |
| 74 | mb7_scan_in, |
| 75 | tcu_aclk, |
| 76 | tcu_bclk, |
| 77 | tcu_niu_mbist_start_7, |
| 78 | niu_mb7_cntrl_fifo_zcp_data_out, |
| 79 | tcu_mbist_bisi_en); |
| 80 | wire siclk; |
| 81 | wire soclk; |
| 82 | wire reset; |
| 83 | wire config_reg_scanin; |
| 84 | wire config_reg_scanout; |
| 85 | wire [8:0] config_in; |
| 86 | wire [8:0] config_out; |
| 87 | wire start_transition; |
| 88 | wire reset_engine; |
| 89 | wire mbist_user_loop_mode; |
| 90 | wire mbist_done; |
| 91 | wire run; |
| 92 | wire bisi; |
| 93 | wire user_mode; |
| 94 | wire user_data_mode; |
| 95 | wire user_addr_mode; |
| 96 | wire user_loop_mode; |
| 97 | wire user_cmpsel_hold; |
| 98 | wire ten_n_mode; |
| 99 | wire mbist_user_data_mode; |
| 100 | wire mbist_user_addr_mode; |
| 101 | wire mbist_user_cmpsel_hold; |
| 102 | wire mbist_ten_n_mode; |
| 103 | wire user_data_reg_scanin; |
| 104 | wire user_data_reg_scanout; |
| 105 | wire [7:0] user_data_in; |
| 106 | wire [7:0] user_data_out; |
| 107 | wire user_start_addr_reg_scanin; |
| 108 | wire user_start_addr_reg_scanout; |
| 109 | wire [8:0] user_start_addr_in; |
| 110 | wire [8:0] user_start_addr; |
| 111 | wire user_stop_addr_reg_scanin; |
| 112 | wire user_stop_addr_reg_scanout; |
| 113 | wire [8:0] user_stop_addr_in; |
| 114 | wire [8:0] user_stop_addr; |
| 115 | wire user_incr_addr_reg_scanin; |
| 116 | wire user_incr_addr_reg_scanout; |
| 117 | wire [8:0] user_incr_addr_in; |
| 118 | wire [8:0] user_incr_addr; |
| 119 | wire user_cmpsel_reg_scanin; |
| 120 | wire user_cmpsel_reg_scanout; |
| 121 | wire [1:0] user_cmpsel_in; |
| 122 | wire [1:0] user_cmpsel; |
| 123 | wire user_bisi_wr_reg_scanin; |
| 124 | wire user_bisi_wr_reg_scanout; |
| 125 | wire user_bisi_wr_mode_in; |
| 126 | wire user_bisi_wr_mode; |
| 127 | wire user_bisi_rd_reg_scanin; |
| 128 | wire user_bisi_rd_reg_scanout; |
| 129 | wire user_bisi_rd_mode_in; |
| 130 | wire user_bisi_rd_mode; |
| 131 | wire mbist_user_bisi_wr_mode; |
| 132 | wire mbist_user_bisi_wr_rd_mode; |
| 133 | wire start_transition_reg_scanin; |
| 134 | wire start_transition_reg_scanout; |
| 135 | wire start_transition_piped; |
| 136 | wire run_reg_scanin; |
| 137 | wire run_reg_scanout; |
| 138 | wire run1_reg_scanin; |
| 139 | wire run1_reg_scanout; |
| 140 | wire run1_in; |
| 141 | wire run1_out; |
| 142 | wire run2_reg_scanin; |
| 143 | wire run2_reg_scanout; |
| 144 | wire run2_in; |
| 145 | wire run2_out; |
| 146 | wire run_piped3; |
| 147 | wire msb; |
| 148 | wire control_reg_scanin; |
| 149 | wire control_reg_scanout; |
| 150 | wire [22:0] control_in; |
| 151 | wire [22:0] control_out; |
| 152 | wire bisi_wr_rd; |
| 153 | wire [1:0] comp_sel; |
| 154 | wire [1:0] data_control; |
| 155 | wire address_mix; |
| 156 | wire [3:0] march_element; |
| 157 | wire [8:0] array_address; |
| 158 | wire upaddress_march; |
| 159 | wire [2:0] read_write_control; |
| 160 | wire five_cycle_march; |
| 161 | wire increment_addr; |
| 162 | wire [8:0] start_addr; |
| 163 | wire [8:0] next_array_address; |
| 164 | wire next_upaddr_march; |
| 165 | wire next_downaddr_march; |
| 166 | wire [8:0] stop_addr; |
| 167 | wire [9:0] overflow_addr; |
| 168 | wire [8:0] incr_addr; |
| 169 | wire overflow; |
| 170 | wire [9:0] compare_addr; |
| 171 | wire [8:0] add; |
| 172 | wire [8:0] adj_address; |
| 173 | wire [8:0] mbist_address; |
| 174 | wire increment_march_elem; |
| 175 | wire [1:0] next_cmpsel; |
| 176 | wire [1:0] next_data_control; |
| 177 | wire next_address_mix; |
| 178 | wire [3:0] next_march_element; |
| 179 | wire array_write; |
| 180 | wire one_op_march; |
| 181 | wire array_read; |
| 182 | wire [7:0] mbist_wdata; |
| 183 | wire true_data; |
| 184 | wire [7:0] data_pattern; |
| 185 | wire [7:0] exp_read_data; |
| 186 | wire done_counter_reg_scanin; |
| 187 | wire done_counter_reg_scanout; |
| 188 | wire [2:0] done_counter_in; |
| 189 | wire [2:0] done_counter_out; |
| 190 | wire done_reg_in; |
| 191 | wire done_reg_out; |
| 192 | wire done_reg_scanin; |
| 193 | wire done_reg_scanout; |
| 194 | wire data_pipe_reg1_scanin; |
| 195 | wire data_pipe_reg1_scanout; |
| 196 | wire [7:0] data_pipe_reg1_in; |
| 197 | wire [7:0] data_pipe_out1; |
| 198 | wire data_pipe_reg2_scanin; |
| 199 | wire data_pipe_reg2_scanout; |
| 200 | wire [7:0] data_pipe_reg2_in; |
| 201 | wire [7:0] data_pipe_out2; |
| 202 | wire [7:0] old_piped_data; |
| 203 | wire ren_pipe_reg1_scanin; |
| 204 | wire ren_pipe_reg1_scanout; |
| 205 | wire ren_pipe_reg1_in; |
| 206 | wire ren_pipe_out1; |
| 207 | wire ren_pipe_reg2_scanin; |
| 208 | wire ren_pipe_reg2_scanout; |
| 209 | wire ren_pipe_reg2_in; |
| 210 | wire ren_pipe_out2; |
| 211 | wire old_piped_ren; |
| 212 | wire comp_sel_reg1_scanin; |
| 213 | wire comp_sel_reg1_scanout; |
| 214 | wire [1:0] comp_sel_reg1_in; |
| 215 | wire [1:0] comp_sel_reg1_out1; |
| 216 | wire [1:0] comp_sel_pipe1; |
| 217 | wire fail_out_reg_in; |
| 218 | wire fail; |
| 219 | wire fail_out_reg_out; |
| 220 | wire fail_out_reg_scanin; |
| 221 | wire fail_out_reg_scanout; |
| 222 | wire [39:0] read_data_reg_in; |
| 223 | wire [39:0] read_data_mux2; |
| 224 | wire [39:0] read_data_reg_out; |
| 225 | wire read_data_pipe_reg_scanin; |
| 226 | wire read_data_pipe_reg_scanout; |
| 227 | wire fail_reg_scanin; |
| 228 | wire fail_reg_scanout; |
| 229 | wire fail_reg_in; |
| 230 | wire fail_reg_out; |
| 231 | wire fail_detect; |
| 232 | |
| 233 | |
| 234 | |
| 235 | |
| 236 | |
| 237 | // ///////////////////////////////////////////////////////////////////////////// |
| 238 | // Outputs |
| 239 | // ///////////////////////////////////////////////////////////////////////////// |
| 240 | |
| 241 | output niu_mb7_cntrl_fifo_zcp_rd_en; |
| 242 | output niu_mb7_cntrl_fifo_zcp_wr_en; |
| 243 | |
| 244 | output [8:0] niu_mb7_addr; |
| 245 | output [7:0] niu_mb7_wdata; |
| 246 | |
| 247 | output niu_mb7_run; |
| 248 | |
| 249 | output niu_tcu_mbist_fail_7; |
| 250 | output niu_tcu_mbist_done_7; |
| 251 | |
| 252 | output mb7_scan_out; |
| 253 | |
| 254 | output [39:0] mb7_dmo_dout; |
| 255 | |
| 256 | |
| 257 | // ///////////////////////////////////////////////////////////////////////////// |
| 258 | // Inputs |
| 259 | // ///////////////////////////////////////////////////////////////////////////// |
| 260 | |
| 261 | input l1clk; |
| 262 | input rst; |
| 263 | input tcu_mbist_user_mode; |
| 264 | |
| 265 | input mb7_scan_in; |
| 266 | input tcu_aclk; |
| 267 | input tcu_bclk; |
| 268 | |
| 269 | input tcu_niu_mbist_start_7; |
| 270 | |
| 271 | input [145:0] niu_mb7_cntrl_fifo_zcp_data_out; |
| 272 | |
| 273 | input tcu_mbist_bisi_en; |
| 274 | |
| 275 | |
| 276 | // ///////////////////////////////////////////////////////////////////////////// |
| 277 | // Scan Renames |
| 278 | // ///////////////////////////////////////////////////////////////////////////// |
| 279 | |
| 280 | // assign se = tcu_scan_en; |
| 281 | // assign pce_ov = tcu_pce_ov; |
| 282 | // assign stop = tcu_clk_stop; |
| 283 | |
| 284 | assign siclk = tcu_aclk; |
| 285 | assign soclk = tcu_bclk; |
| 286 | |
| 287 | |
| 288 | // ///////////////////////////////////////////////////////////////////////////// |
| 289 | // Invert reset |
| 290 | // ///////////////////////////////////////////////////////////////////////////// |
| 291 | |
| 292 | assign reset = ~rst; |
| 293 | |
| 294 | |
| 295 | //////////////////////////////////////////////////////////////////////////////// |
| 296 | // Clock header |
| 297 | |
| 298 | // l1clkhdr_ctl_macro clkgen ( |
| 299 | // .l2clk (iol2clk ), |
| 300 | // .l1en (1'b1 ), |
| 301 | // .l1clk (l1clk ) |
| 302 | // ); |
| 303 | //assign siclk = 1'b0; |
| 304 | //assign soclk = 1'b0; |
| 305 | |
| 306 | |
| 307 | // ///////////////////////////////////////////////////////////////////////////// |
| 308 | // |
| 309 | // MBIST Config Register |
| 310 | // |
| 311 | // ///////////////////////////////////////////////////////////////////////////// |
| 312 | // |
| 313 | // A low to high transition on mbist_start will reset and start the engine. |
| 314 | // mbist_start must remain active high for the duration of MBIST. |
| 315 | // If mbist_start deasserts the engine will stop but not reset. |
| 316 | // Once MBIST has completed niu_tcu_mbist_done_7 will assert and the fail status |
| 317 | // signals will be valid. |
| 318 | // To run MBIST again the mbist_start signal must transition low then high. |
| 319 | // |
| 320 | // Loop on Address will disable the address mix function. |
| 321 | // |
| 322 | // ///////////////////////////////////////////////////////////////////////////// |
| 323 | |
| 324 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_9 config_reg ( |
| 325 | .scan_in(config_reg_scanin), |
| 326 | .scan_out(config_reg_scanout), |
| 327 | .din ( config_in[8:0] ), |
| 328 | .dout ( config_out[8:0] ), |
| 329 | .reset(reset), |
| 330 | .l1clk(l1clk), |
| 331 | .siclk(siclk), |
| 332 | .soclk(soclk)); |
| 333 | |
| 334 | assign config_in[0] = tcu_niu_mbist_start_7; |
| 335 | assign config_in[1] = config_out[0]; |
| 336 | assign start_transition = config_out[0] & ~config_out[1]; |
| 337 | assign reset_engine = start_transition | (mbist_user_loop_mode & mbist_done); |
| 338 | assign run = config_out[0] & config_out[1]; // 9/19/05 run to follow start only! |
| 339 | |
| 340 | |
| 341 | assign config_in[2] = start_transition ? tcu_mbist_bisi_en: config_out[2]; |
| 342 | assign bisi = config_out[2]; |
| 343 | |
| 344 | assign config_in[3] = start_transition ? tcu_mbist_user_mode : config_out[3]; |
| 345 | assign user_mode = config_out[3]; |
| 346 | |
| 347 | assign config_in[4] = config_out[4]; |
| 348 | assign user_data_mode = config_out[4]; |
| 349 | |
| 350 | assign config_in[5] = config_out[5]; |
| 351 | assign user_addr_mode = config_out[5]; |
| 352 | |
| 353 | assign config_in[6] = config_out[6]; |
| 354 | assign user_loop_mode = config_out[6]; |
| 355 | |
| 356 | assign config_in[7] = config_out[7]; |
| 357 | assign user_cmpsel_hold = config_out[7]; //cmpsel_hold = 0 : Default, All cominations |
| 358 | // = 1 : |
| 359 | // User-specified cmpsel |
| 360 | |
| 361 | assign config_in[8] = config_out[8]; |
| 362 | assign ten_n_mode = config_out[8]; |
| 363 | |
| 364 | |
| 365 | assign mbist_user_data_mode = user_mode & user_data_mode; |
| 366 | assign mbist_user_addr_mode = user_mode & user_addr_mode; |
| 367 | assign mbist_user_loop_mode = user_mode & user_loop_mode; |
| 368 | assign mbist_user_cmpsel_hold = user_mode & user_cmpsel_hold; |
| 369 | assign mbist_ten_n_mode = user_mode & ten_n_mode; |
| 370 | |
| 371 | |
| 372 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_8 user_data_reg ( |
| 373 | .scan_in(user_data_reg_scanin), |
| 374 | .scan_out(user_data_reg_scanout), |
| 375 | .din ( user_data_in[7:0] ), |
| 376 | .dout ( user_data_out[7:0] ), |
| 377 | .reset(reset), |
| 378 | .l1clk(l1clk), |
| 379 | .siclk(siclk), |
| 380 | .soclk(soclk)); |
| 381 | |
| 382 | |
| 383 | assign user_data_in[7:0] = user_data_out[7:0]; |
| 384 | |
| 385 | |
| 386 | // Defining User start, stop, and increment addresses. |
| 387 | |
| 388 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_9 user_start_addr_reg ( |
| 389 | .scan_in(user_start_addr_reg_scanin), |
| 390 | .scan_out(user_start_addr_reg_scanout), |
| 391 | .din ( user_start_addr_in[8:0] ), |
| 392 | .dout ( user_start_addr[8:0] ), |
| 393 | .reset(reset), |
| 394 | .l1clk(l1clk), |
| 395 | .siclk(siclk), |
| 396 | .soclk(soclk)); |
| 397 | |
| 398 | assign user_start_addr_in[8:0] = user_start_addr[8:0]; |
| 399 | |
| 400 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_9 user_stop_addr_reg ( |
| 401 | .scan_in(user_stop_addr_reg_scanin), |
| 402 | .scan_out(user_stop_addr_reg_scanout), |
| 403 | .din ( user_stop_addr_in[8:0] ), |
| 404 | .dout ( user_stop_addr[8:0] ), |
| 405 | .reset(reset), |
| 406 | .l1clk(l1clk), |
| 407 | .siclk(siclk), |
| 408 | .soclk(soclk)); |
| 409 | |
| 410 | assign user_stop_addr_in[8:0] = user_stop_addr[8:0]; |
| 411 | |
| 412 | |
| 413 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_9 user_incr_addr_reg ( |
| 414 | .scan_in(user_incr_addr_reg_scanin), |
| 415 | .scan_out(user_incr_addr_reg_scanout), |
| 416 | .din ( user_incr_addr_in[8:0] ), |
| 417 | .dout ( user_incr_addr[8:0] ), |
| 418 | .reset(reset), |
| 419 | .l1clk(l1clk), |
| 420 | .siclk(siclk), |
| 421 | .soclk(soclk)); |
| 422 | |
| 423 | assign user_incr_addr_in[8:0] = user_incr_addr[8:0]; |
| 424 | |
| 425 | // Defining User cmpsel. |
| 426 | |
| 427 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_2 user_cmpsel_reg ( |
| 428 | .scan_in(user_cmpsel_reg_scanin), |
| 429 | .scan_out(user_cmpsel_reg_scanout), |
| 430 | .din ( user_cmpsel_in[1:0] ), |
| 431 | .dout ( user_cmpsel[1:0] ), |
| 432 | .reset(reset), |
| 433 | .l1clk(l1clk), |
| 434 | .siclk(siclk), |
| 435 | .soclk(soclk)); |
| 436 | |
| 437 | assign user_cmpsel_in[1:0] = user_cmpsel[1:0]; |
| 438 | |
| 439 | // Defining user_bisi write and read registers |
| 440 | |
| 441 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_1 user_bisi_wr_reg ( |
| 442 | .scan_in(user_bisi_wr_reg_scanin), |
| 443 | .scan_out(user_bisi_wr_reg_scanout), |
| 444 | .din ( user_bisi_wr_mode_in ), |
| 445 | .dout ( user_bisi_wr_mode ), |
| 446 | .reset(reset), |
| 447 | .l1clk(l1clk), |
| 448 | .siclk(siclk), |
| 449 | .soclk(soclk)); |
| 450 | |
| 451 | assign user_bisi_wr_mode_in = user_bisi_wr_mode; |
| 452 | |
| 453 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_1 user_bisi_rd_reg ( |
| 454 | .scan_in(user_bisi_rd_reg_scanin), |
| 455 | .scan_out(user_bisi_rd_reg_scanout), |
| 456 | .din ( user_bisi_rd_mode_in ), |
| 457 | .dout ( user_bisi_rd_mode ), |
| 458 | .reset(reset), |
| 459 | .l1clk(l1clk), |
| 460 | .siclk(siclk), |
| 461 | .soclk(soclk)); |
| 462 | |
| 463 | assign user_bisi_rd_mode_in = user_bisi_rd_mode; |
| 464 | |
| 465 | assign mbist_user_bisi_wr_mode = user_mode & bisi & user_bisi_wr_mode & ~user_bisi_rd_mode; |
| 466 | // assign mbist_user_bisi_rd_mode = user_mode & bisi & user_bisi_rd_mode & ~user_bisi_wr_mode; |
| 467 | |
| 468 | assign mbist_user_bisi_wr_rd_mode = user_mode & bisi & |
| 469 | ((user_bisi_wr_mode & user_bisi_rd_mode) | |
| 470 | (~user_bisi_wr_mode & ~user_bisi_rd_mode)); |
| 471 | |
| 472 | //////////////////////////////////////////////////////////////////////////////// |
| 473 | // Piping start_transition |
| 474 | //////////////////////////////////////////////////////////////////////////////// |
| 475 | |
| 476 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_1 start_transition_reg ( |
| 477 | .scan_in(start_transition_reg_scanin), |
| 478 | .scan_out(start_transition_reg_scanout), |
| 479 | .din ( start_transition ), |
| 480 | .dout ( start_transition_piped ), |
| 481 | .reset(reset), |
| 482 | .l1clk(l1clk), |
| 483 | .siclk(siclk), |
| 484 | .soclk(soclk)); |
| 485 | |
| 486 | |
| 487 | //////////////////////////////////////////////////////////////////////////////// |
| 488 | // Adding 2 extra pipeline stages to run to delay the start of mbist for 3 cycles. |
| 489 | //////////////////////////////////////////////////////////////////////////////// |
| 490 | |
| 491 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_1 run_reg ( |
| 492 | .scan_in(run_reg_scanin), |
| 493 | .scan_out(run_reg_scanout), |
| 494 | .din ( run ), |
| 495 | .dout ( niu_mb7_run ), |
| 496 | .reset(reset), |
| 497 | .l1clk(l1clk), |
| 498 | .siclk(siclk), |
| 499 | .soclk(soclk)); |
| 500 | |
| 501 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_1 run1_reg ( |
| 502 | .scan_in(run1_reg_scanin), |
| 503 | .scan_out(run1_reg_scanout), |
| 504 | .din ( run1_in ), |
| 505 | .dout ( run1_out ), |
| 506 | .reset(reset), |
| 507 | .l1clk(l1clk), |
| 508 | .siclk(siclk), |
| 509 | .soclk(soclk)); |
| 510 | |
| 511 | assign run1_in = reset_engine ? 1'b0: niu_mb7_run; |
| 512 | |
| 513 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_1 run2_reg ( |
| 514 | .scan_in(run2_reg_scanin), |
| 515 | .scan_out(run2_reg_scanout), |
| 516 | .din ( run2_in ), |
| 517 | .dout ( run2_out ), |
| 518 | .reset(reset), |
| 519 | .l1clk(l1clk), |
| 520 | .siclk(siclk), |
| 521 | .soclk(soclk)); |
| 522 | |
| 523 | assign run2_in = reset_engine ? 1'b0: run1_out; |
| 524 | assign run_piped3 = config_out[0] & run2_out & ~msb; |
| 525 | |
| 526 | |
| 527 | // ///////////////////////////////////////////////////////////////////////////// |
| 528 | // |
| 529 | // MBIST Control Register |
| 530 | // |
| 531 | // ///////////////////////////////////////////////////////////////////////////// |
| 532 | // Remove Address mix disable before delivery |
| 533 | // ///////////////////////////////////////////////////////////////////////////// |
| 534 | |
| 535 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_23 control_reg ( |
| 536 | .scan_in(control_reg_scanin), |
| 537 | .scan_out(control_reg_scanout), |
| 538 | .din ( control_in[22:0] ), |
| 539 | .dout ( control_out[22:0] ), |
| 540 | .reset(reset), |
| 541 | .l1clk(l1clk), |
| 542 | .siclk(siclk), |
| 543 | .soclk(soclk)); |
| 544 | |
| 545 | assign msb = control_out[22]; |
| 546 | assign bisi_wr_rd = (bisi & ~user_mode) | mbist_user_bisi_wr_rd_mode ? control_out[21] : 1'b1; |
| 547 | assign comp_sel[1:0] = mbist_user_cmpsel_hold ? user_cmpsel[1:0] : control_out[20:19]; |
| 548 | assign data_control[1:0] = control_out[18:17]; |
| 549 | assign address_mix = (bisi | mbist_user_addr_mode) ? 1'b0: control_out[16]; |
| 550 | assign march_element[3:0] = control_out[15:12]; |
| 551 | |
| 552 | assign array_address[8:0] = upaddress_march ? control_out[11:3] : ~control_out[11:3]; |
| 553 | |
| 554 | assign read_write_control[2:0] = ~five_cycle_march ? {2'b11, control_out[0]} : |
| 555 | control_out[2:0]; |
| 556 | |
| 557 | assign control_in[2:0] = reset_engine ? 3'b000: |
| 558 | ~run_piped3 ? control_out[2:0]: |
| 559 | (five_cycle_march && (read_write_control[2:0] == 3'b100)) ? 3'b000: |
| 560 | (read_write_control[2:0] == 3'b110 ) ? 3'b000: |
| 561 | control_out[2:0] + 3'b001; |
| 562 | |
| 563 | assign increment_addr = (five_cycle_march && (read_write_control[2:0] == 3'b100)) || |
| 564 | (read_write_control[2:0] == 3'b110); |
| 565 | |
| 566 | |
| 567 | assign control_in[11:3] = (start_transition_piped || reset_engine ) ? start_addr[8:0]: |
| 568 | (~run_piped3) || (~increment_addr) ? control_out[11:3]: |
| 569 | next_array_address[8:0]; |
| 570 | |
| 571 | assign next_array_address[8:0] = next_upaddr_march ? start_addr[8:0]: |
| 572 | next_downaddr_march ? ~stop_addr[8:0]: |
| 573 | (overflow_addr[8:0]); // array_addr + incr_addr |
| 574 | |
| 575 | assign start_addr[8:0] = mbist_user_addr_mode ? user_start_addr[8:0] : 9'b000000000; |
| 576 | assign stop_addr[8:0] = mbist_user_addr_mode ? user_stop_addr[8:0] : 9'b111111111; |
| 577 | assign incr_addr[8:0] = mbist_user_addr_mode ? user_incr_addr[8:0] : 9'b000000001; |
| 578 | |
| 579 | assign overflow_addr[9:0] = {1'b0,control_out[11:3]} + {1'b0,incr_addr[8:0]}; |
| 580 | assign overflow = compare_addr[9:0] < overflow_addr[9:0]; |
| 581 | |
| 582 | assign compare_addr[9:0] = upaddress_march ? {1'b0, stop_addr[8:0]} : |
| 583 | {1'b0, ~start_addr[8:0]}; |
| 584 | |
| 585 | assign next_upaddr_march = ( (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || |
| 586 | (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h5) || |
| 587 | (march_element[3:0] == 4'h8) ) && overflow; |
| 588 | |
| 589 | assign next_downaddr_march = ( (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h7) || |
| 590 | (march_element[3:0] == 4'h3) || (march_element[3:0] == 4'h4) ) && |
| 591 | overflow; |
| 592 | |
| 593 | assign add[8:0] = five_cycle_march && ( (read_write_control[2:0] == 3'h1) || |
| 594 | (read_write_control[2:0] == 3'h3)) ? |
| 595 | adj_address[8:0]: array_address[8:0]; |
| 596 | |
| 597 | |
| 598 | assign adj_address[8:0] = address_mix ? { array_address[8:1], ~array_address[0] } : |
| 599 | { array_address[8:3], ~array_address[2], array_address[1:0]}; |
| 600 | |
| 601 | assign mbist_address[8:0] = address_mix ? {add[6:0], add[8:7]} : // Fast row |
| 602 | add[8:0]; // Fast column |
| 603 | |
| 604 | assign increment_march_elem = increment_addr && overflow; |
| 605 | |
| 606 | assign control_in[22:12] = reset_engine ? 11'b0: |
| 607 | ~run_piped3 ? control_out[22:12]: |
| 608 | {msb, bisi_wr_rd, next_cmpsel[1:0], next_data_control[1:0], next_address_mix, next_march_element[3:0]} + |
| 609 | {10'b0, increment_march_elem}; |
| 610 | |
| 611 | assign next_address_mix = ( bisi | mbist_user_addr_mode) ? 1'b1 : address_mix; |
| 612 | |
| 613 | assign next_cmpsel[1:0] = mbist_user_cmpsel_hold || (~bisi_wr_rd) || mbist_user_bisi_wr_mode ? 2'b11: control_out[20:19]; |
| 614 | |
| 615 | assign next_data_control[1:0] = (bisi || (mbist_user_data_mode && (data_control[1:0] == 2'b00))) ? 2'b11: |
| 616 | data_control[1:0]; |
| 617 | |
| 618 | // Incorporated ten_n_mode! |
| 619 | assign next_march_element[3:0] = ( bisi || |
| 620 | (mbist_ten_n_mode && (march_element[3:0] == 4'b0101)) || |
| 621 | ((march_element[3:0] == 4'b1000) && (read_write_control[2:0] == 3'b100)) ) |
| 622 | && overflow ? 4'b1111: march_element[3:0]; |
| 623 | |
| 624 | assign array_write = ~run_piped3 ? 1'b0: |
| 625 | five_cycle_march ? (read_write_control[2:0] == 3'h0) || |
| 626 | (read_write_control[2:0] == 3'h1) || |
| 627 | (read_write_control[2:0] == 3'h4): |
| 628 | (~five_cycle_march & ~one_op_march) ? (read_write_control[0] == 1'b0) : |
| 629 | ( ((march_element[3:0] == 4'h0) & (~bisi || ~bisi_wr_rd || mbist_user_bisi_wr_mode)) || (march_element[3:0] == 4'h7)); |
| 630 | |
| 631 | assign array_read = (~five_cycle_march & ~one_op_march) ? run_piped3 : |
| 632 | (~array_write) && run_piped3; |
| 633 | |
| 634 | // assign mbist_done = msb; |
| 635 | |
| 636 | assign mbist_wdata[7:0] = true_data ? data_pattern[7:0]: ~data_pattern[7:0]; |
| 637 | |
| 638 | assign five_cycle_march = (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h8); |
| 639 | assign one_op_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h5) || |
| 640 | (march_element[3:0] == 4'h7); |
| 641 | |
| 642 | assign upaddress_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || |
| 643 | (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h6) || |
| 644 | (march_element[3:0] == 4'h7); |
| 645 | |
| 646 | |
| 647 | assign true_data = (five_cycle_march && (march_element[3:0] == 4'h6)) ? |
| 648 | ((read_write_control[2:0] == 3'h0) || (read_write_control[2:0] == 3'h2)): |
| 649 | (five_cycle_march && (march_element[3:0] == 4'h8)) ? |
| 650 | ((read_write_control[2:0] == 3'h1) || |
| 651 | (read_write_control[2:0] == 3'h3) || (read_write_control[2:0] == 3'h4)): |
| 652 | one_op_march ? (march_element[3:0] == 4'h7) : |
| 653 | (march_element[3:0] == 4'h1) || (march_element[3:0] == 4'h3); |
| 654 | |
| 655 | |
| 656 | assign data_pattern[7:0] = (bisi & mbist_user_data_mode) ? ~user_data_out[7:0]: |
| 657 | mbist_user_data_mode ? user_data_out[7:0]: |
| 658 | bisi ? 8'hFF: // true_data function will invert to 8'h00 |
| 659 | (data_control[1:0] == 2'h0) ? 8'hAA: |
| 660 | (data_control[1:0] == 2'h1) ? 8'h99: |
| 661 | (data_control[1:0] == 2'h2) ? 8'hCC: |
| 662 | 8'h00; |
| 663 | |
| 664 | // ///////////////////////////////////////////////////////////////////// |
| 665 | // May need pipelining !!! |
| 666 | // ///////////////////////////////////////////////////////////////////// |
| 667 | |
| 668 | assign niu_mb7_cntrl_fifo_zcp_wr_en = array_write; |
| 669 | assign niu_mb7_cntrl_fifo_zcp_rd_en = array_read; |
| 670 | |
| 671 | assign niu_mb7_addr[8:0] = mbist_address[8:0]; |
| 672 | assign niu_mb7_wdata[7:0] = mbist_wdata[7:0]; |
| 673 | |
| 674 | assign exp_read_data[7:0] = (~five_cycle_march & ~one_op_march) ? ~mbist_wdata[7:0] : mbist_wdata[7:0]; |
| 675 | |
| 676 | ///////////////////////////////////////////////////////////////////////// |
| 677 | // Creating the mbist_done signal |
| 678 | ///////////////////////////////////////////////////////////////////////// |
| 679 | // Delaying mbist_done 8 clock signals after msb going high, to provide |
| 680 | // a generic solution for done going high after the last fail has come back! |
| 681 | |
| 682 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_3 done_counter_reg ( |
| 683 | .scan_in(done_counter_reg_scanin), |
| 684 | .scan_out(done_counter_reg_scanout), |
| 685 | .din ( done_counter_in[2:0] ), |
| 686 | .dout ( done_counter_out[2:0] ), |
| 687 | .reset(reset), |
| 688 | .l1clk(l1clk), |
| 689 | .siclk(siclk), |
| 690 | .soclk(soclk)); |
| 691 | |
| 692 | // config_out[1] is AND'ed to force mbist_done low 2 cycles after mbist_start |
| 693 | // goes low. |
| 694 | |
| 695 | assign mbist_done = (&done_counter_out[2:0] == 1'b1) & config_out[1]; |
| 696 | assign done_counter_in[2:0] = reset_engine ? 3'b000: |
| 697 | msb & ~mbist_done & config_out[1] ? done_counter_out[2:0] + 3'b001: |
| 698 | done_counter_out[2:0]; |
| 699 | |
| 700 | |
| 701 | // ///////////////////////////////////////////////////////////////////////////// |
| 702 | // Done Detection |
| 703 | // ///////////////////////////////////////////////////////////////////////////// |
| 704 | |
| 705 | assign done_reg_in = mbist_done; |
| 706 | assign niu_tcu_mbist_done_7 = done_reg_out; |
| 707 | |
| 708 | |
| 709 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_1 done_reg ( |
| 710 | .scan_in(done_reg_scanin), |
| 711 | .scan_out(done_reg_scanout), |
| 712 | .din ( done_reg_in ), |
| 713 | .dout ( done_reg_out ), |
| 714 | .reset(reset), |
| 715 | .l1clk(l1clk), |
| 716 | .siclk(siclk), |
| 717 | .soclk(soclk)); |
| 718 | |
| 719 | |
| 720 | // ///////////////////////////////////////////////////////////////////////////// |
| 721 | // Pipeline for wdata, and Read_en |
| 722 | // ///////////////////////////////////////////////////////////////////////////// |
| 723 | |
| 724 | // ///////////////////////////////////////////////////////////////////////////// |
| 725 | // Pipeline for wdata |
| 726 | // ///////////////////////////////////////////////////////////////////////////// |
| 727 | |
| 728 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_8 data_pipe_reg1 ( |
| 729 | .scan_in(data_pipe_reg1_scanin), |
| 730 | .scan_out(data_pipe_reg1_scanout), |
| 731 | .din ( data_pipe_reg1_in[7:0] ), |
| 732 | .dout ( data_pipe_out1[7:0] ), |
| 733 | .reset(reset), |
| 734 | .l1clk(l1clk), |
| 735 | .siclk(siclk), |
| 736 | .soclk(soclk)); |
| 737 | |
| 738 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_8 data_pipe_reg2 ( |
| 739 | .scan_in(data_pipe_reg2_scanin), |
| 740 | .scan_out(data_pipe_reg2_scanout), |
| 741 | .din ( data_pipe_reg2_in[7:0] ), |
| 742 | .dout ( data_pipe_out2[7:0] ), |
| 743 | .reset(reset), |
| 744 | .l1clk(l1clk), |
| 745 | .siclk(siclk), |
| 746 | .soclk(soclk)); |
| 747 | |
| 748 | //Adding an extra level of pipe since piping the read_data |
| 749 | //msff_ctl_macro data_pipe_reg3 (width=8, library=a1, reset=1)( |
| 750 | // .scan_in(data_pipe_reg3_scanin), |
| 751 | // .scan_out(data_pipe_reg3_scanout), |
| 752 | // .din ( data_pipe_reg3_in[7:0] ), |
| 753 | // .dout ( data_pipe_out3[7:0] )); |
| 754 | |
| 755 | assign data_pipe_reg1_in[7:0] = reset_engine ? 8'h00: exp_read_data[7:0]; |
| 756 | assign data_pipe_reg2_in[7:0] = reset_engine ? 8'h00: data_pipe_out1[7:0]; |
| 757 | //assign data_pipe_reg3_in[7:0] = reset_engine ? 8'h00: data_pipe_out2[7:0]; |
| 758 | //assign old_piped_data[7:0] = data_pipe_out3[7:0]; |
| 759 | assign old_piped_data[7:0] = data_pipe_out2[7:0]; |
| 760 | |
| 761 | // ///////////////////////////////////////////////////////////////////////////// |
| 762 | // Pipeline for Read_en |
| 763 | // ///////////////////////////////////////////////////////////////////////////// |
| 764 | |
| 765 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_1 ren_pipe_reg1 ( |
| 766 | .scan_in(ren_pipe_reg1_scanin), |
| 767 | .scan_out(ren_pipe_reg1_scanout), |
| 768 | .din ( ren_pipe_reg1_in ), |
| 769 | .dout ( ren_pipe_out1 ), |
| 770 | .reset(reset), |
| 771 | .l1clk(l1clk), |
| 772 | .siclk(siclk), |
| 773 | .soclk(soclk)); |
| 774 | |
| 775 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_1 ren_pipe_reg2 ( |
| 776 | .scan_in(ren_pipe_reg2_scanin), |
| 777 | .scan_out(ren_pipe_reg2_scanout), |
| 778 | .din ( ren_pipe_reg2_in ), |
| 779 | .dout ( ren_pipe_out2 ), |
| 780 | .reset(reset), |
| 781 | .l1clk(l1clk), |
| 782 | .siclk(siclk), |
| 783 | .soclk(soclk)); |
| 784 | |
| 785 | //Adding an extra level of pipe since piping the read_data |
| 786 | //msff_ctl_macro ren_pipe_reg3 (width=1, library=a1, reset=1)( |
| 787 | // .scan_in(ren_pipe_reg3_scanin), |
| 788 | // .scan_out(ren_pipe_reg3_scanout), |
| 789 | // .din ( ren_pipe_reg3_in ), |
| 790 | // .dout ( ren_pipe_out3 )); |
| 791 | |
| 792 | assign ren_pipe_reg1_in = reset_engine ? 1'b0: array_read; |
| 793 | assign ren_pipe_reg2_in = reset_engine ? 1'b0: ren_pipe_out1; |
| 794 | //assign ren_pipe_reg3_in = reset_engine ? 1'b0: ren_pipe_out2; |
| 795 | // assign old_piped_ren = ren_pipe_out3; |
| 796 | assign old_piped_ren = ren_pipe_out2; |
| 797 | |
| 798 | // piped sel |
| 799 | // msff_ctl_macro sel_pipe_reg1 (width=1, library=a1, reset=1) ( |
| 800 | // .scan_in(sel_pipe_reg1_scanin), |
| 801 | // .scan_out(sel_pipe_reg1_scanout), |
| 802 | // .din ( sel_pipe_reg1_in ), |
| 803 | // .dout ( sel_pipe_out1 )); |
| 804 | |
| 805 | // msff_ctl_macro sel_pipe_reg2 (width=1, library=a1, reset=1) ( |
| 806 | // .scan_in(sel_pipe_reg2_scanin), |
| 807 | // .scan_out(sel_pipe_reg2_scanout), |
| 808 | // .din ( sel_pipe_reg2_in ), |
| 809 | // .dout ( sel_pipe_out2 )); |
| 810 | |
| 811 | // ///////////////////////////////////////////////////////////////////////////// |
| 812 | // Pipeline for comp sel |
| 813 | // ///////////////////////////////////////////////////////////////////////////// |
| 814 | |
| 815 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_2 comp_sel_reg1 ( |
| 816 | .scan_in(comp_sel_reg1_scanin), |
| 817 | .scan_out(comp_sel_reg1_scanout), |
| 818 | .din ( comp_sel_reg1_in[ 1 : 0 ] ), |
| 819 | .dout ( comp_sel_reg1_out1[ 1 : 0 ] ), |
| 820 | .reset(reset), |
| 821 | .l1clk(l1clk), |
| 822 | .siclk(siclk), |
| 823 | .soclk(soclk)); |
| 824 | |
| 825 | assign comp_sel_reg1_in[ 1 : 0 ] = comp_sel[ 1 : 0 ]; |
| 826 | |
| 827 | assign comp_sel_pipe1[ 1 : 0 ] = comp_sel_reg1_out1[ 1 : 0 ]; |
| 828 | |
| 829 | // ///////////////////////////////////////////////////////////////////////////// |
| 830 | // Fail Detection |
| 831 | // ///////////////////////////////////////////////////////////////////////////// |
| 832 | |
| 833 | assign fail_out_reg_in = fail; |
| 834 | assign niu_tcu_mbist_fail_7 = fail_out_reg_out; |
| 835 | |
| 836 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_1 fail_out_reg ( |
| 837 | .scan_in(fail_out_reg_scanin), |
| 838 | .scan_out(fail_out_reg_scanout), |
| 839 | .din ( fail_out_reg_in ), |
| 840 | .dout ( fail_out_reg_out ), |
| 841 | .reset(reset), |
| 842 | .l1clk(l1clk), |
| 843 | .siclk(siclk), |
| 844 | .soclk(soclk)); |
| 845 | |
| 846 | |
| 847 | // ///////////////////////////////////////////////////////////////////////////// |
| 848 | // Fail Detection |
| 849 | // ///////////////////////////////////////////////////////////////////////////// |
| 850 | |
| 851 | assign read_data_reg_in[ 39 : 0 ] = read_data_mux2[ 39 : 0 ]; |
| 852 | assign mb7_dmo_dout[ 39 : 0 ] = read_data_reg_out[ 39 : 0 ]; |
| 853 | |
| 854 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_40 read_data_pipe_reg ( |
| 855 | .scan_in(read_data_pipe_reg_scanin), |
| 856 | .scan_out(read_data_pipe_reg_scanout), |
| 857 | .din ( read_data_reg_in[ 39 : 0 ] ), |
| 858 | .dout ( read_data_reg_out[ 39 : 0 ] ), |
| 859 | .reset(reset), |
| 860 | .l1clk(l1clk), |
| 861 | .siclk(siclk), |
| 862 | .soclk(soclk)); |
| 863 | |
| 864 | |
| 865 | niu_mb7_msff_ctl_macro__library_a1__reset_1__width_1 fail_reg ( |
| 866 | .scan_in(fail_reg_scanin), |
| 867 | .scan_out(fail_reg_scanout), |
| 868 | .din ( fail_reg_in ), |
| 869 | .dout ( fail_reg_out ), |
| 870 | .reset(reset), |
| 871 | .l1clk(l1clk), |
| 872 | .siclk(siclk), |
| 873 | .soclk(soclk)); |
| 874 | |
| 875 | assign fail_reg_in = reset_engine ? 1'b0 : fail_detect | fail_reg_out; |
| 876 | |
| 877 | assign fail_detect = ({old_piped_data[ 7 : 0 ], |
| 878 | old_piped_data[ 7 : 0 ], |
| 879 | old_piped_data[ 7 : 0 ], |
| 880 | old_piped_data[ 7 : 0 ], |
| 881 | old_piped_data[ 7 : 0 ]}) != mb7_dmo_dout[ 39 : 0 ] && old_piped_ren; |
| 882 | |
| 883 | assign fail = mbist_done ? fail_reg_out : fail_detect; |
| 884 | |
| 885 | // Pipelining the read_data to meet the timing requirement |
| 886 | // Check if need to reset?? |
| 887 | |
| 888 | assign read_data_mux2[ 39 : 0 ] = (comp_sel_pipe1[ 1 : 0 ] == 2'b00) ? niu_mb7_cntrl_fifo_zcp_data_out[ 39 : 0 ] : |
| 889 | (comp_sel_pipe1[ 1 : 0 ] == 2'b01) ? niu_mb7_cntrl_fifo_zcp_data_out[ 79 : 40 ] : |
| 890 | (comp_sel_pipe1[ 1 : 0 ] == 2'b10) ? niu_mb7_cntrl_fifo_zcp_data_out[ 119 : 80 ] : |
| 891 | {data_pipe_out1[ 7 : 0 ], data_pipe_out1[ 7 : 2 ], niu_mb7_cntrl_fifo_zcp_data_out[ 145 : 120 ]} ; |
| 892 | |
| 893 | supply0 vss; // <- port for ground |
| 894 | supply1 vdd; // <- port for power |
| 895 | // ///////////////////////////////////////////////////////////////////////////// |
| 896 | // fixscan start: |
| 897 | assign config_reg_scanin = mb7_scan_in ; |
| 898 | assign user_data_reg_scanin = config_reg_scanout ; |
| 899 | assign user_start_addr_reg_scanin = user_data_reg_scanout ; |
| 900 | assign user_stop_addr_reg_scanin = user_start_addr_reg_scanout; |
| 901 | assign user_incr_addr_reg_scanin = user_stop_addr_reg_scanout; |
| 902 | assign user_cmpsel_reg_scanin = user_incr_addr_reg_scanout; |
| 903 | assign user_bisi_wr_reg_scanin = user_cmpsel_reg_scanout ; |
| 904 | assign user_bisi_rd_reg_scanin = user_bisi_wr_reg_scanout ; |
| 905 | assign start_transition_reg_scanin = user_bisi_rd_reg_scanout ; |
| 906 | assign run_reg_scanin = start_transition_reg_scanout; |
| 907 | assign run1_reg_scanin = run_reg_scanout ; |
| 908 | assign run2_reg_scanin = run1_reg_scanout ; |
| 909 | assign control_reg_scanin = run2_reg_scanout ; |
| 910 | assign done_counter_reg_scanin = control_reg_scanout ; |
| 911 | assign done_reg_scanin = done_counter_reg_scanout ; |
| 912 | assign data_pipe_reg1_scanin = done_reg_scanout ; |
| 913 | assign data_pipe_reg2_scanin = data_pipe_reg1_scanout ; |
| 914 | assign ren_pipe_reg1_scanin = data_pipe_reg2_scanout ; |
| 915 | assign ren_pipe_reg2_scanin = ren_pipe_reg1_scanout ; |
| 916 | assign comp_sel_reg1_scanin = ren_pipe_reg2_scanout ; |
| 917 | assign fail_out_reg_scanin = comp_sel_reg1_scanout ; |
| 918 | assign read_data_pipe_reg_scanin = fail_out_reg_scanout ; |
| 919 | assign fail_reg_scanin = read_data_pipe_reg_scanout; |
| 920 | assign mb7_scan_out = fail_reg_scanout ; |
| 921 | // fixscan end: |
| 922 | endmodule |
| 923 | // ///////////////////////////////////////////////////////////////////////////// |
| 924 | |
| 925 | |
| 926 | |
| 927 | |
| 928 | |
| 929 | |
| 930 | // any PARAMS parms go into naming of macro |
| 931 | |
| 932 | module niu_mb7_msff_ctl_macro__library_a1__reset_1__width_9 ( |
| 933 | din, |
| 934 | reset, |
| 935 | l1clk, |
| 936 | scan_in, |
| 937 | siclk, |
| 938 | soclk, |
| 939 | dout, |
| 940 | scan_out); |
| 941 | wire [8:0] fdin; |
| 942 | wire [8:1] sout; |
| 943 | |
| 944 | input [8:0] din; |
| 945 | input reset; |
| 946 | input l1clk; |
| 947 | input scan_in; |
| 948 | |
| 949 | |
| 950 | input siclk; |
| 951 | input soclk; |
| 952 | |
| 953 | output [8:0] dout; |
| 954 | output scan_out; |
| 955 | assign fdin[8:0] = din[8:0] & {9 {reset}}; |
| 956 | |
| 957 | |
| 958 | |
| 959 | |
| 960 | |
| 961 | |
| 962 | |
| 963 | |
| 964 | |
| 965 | |
| 966 | |
| 967 | |
| 968 | |
| 969 | |
| 970 | |
| 971 | |
| 972 | |
| 973 | cl_a1_msff_syrst_4x d0_0 ( |
| 974 | .l1clk(l1clk), |
| 975 | .siclk(siclk), |
| 976 | .soclk(soclk), |
| 977 | .d(fdin[0]), |
| 978 | .si(sout[1]), |
| 979 | .so(scan_out), |
| 980 | .reset(reset), |
| 981 | .q(dout[0]) |
| 982 | ); |
| 983 | cl_a1_msff_syrst_4x d0_1 ( |
| 984 | .l1clk(l1clk), |
| 985 | .siclk(siclk), |
| 986 | .soclk(soclk), |
| 987 | .d(fdin[1]), |
| 988 | .si(sout[2]), |
| 989 | .so(sout[1]), |
| 990 | .reset(reset), |
| 991 | .q(dout[1]) |
| 992 | ); |
| 993 | cl_a1_msff_syrst_4x d0_2 ( |
| 994 | .l1clk(l1clk), |
| 995 | .siclk(siclk), |
| 996 | .soclk(soclk), |
| 997 | .d(fdin[2]), |
| 998 | .si(sout[3]), |
| 999 | .so(sout[2]), |
| 1000 | .reset(reset), |
| 1001 | .q(dout[2]) |
| 1002 | ); |
| 1003 | cl_a1_msff_syrst_4x d0_3 ( |
| 1004 | .l1clk(l1clk), |
| 1005 | .siclk(siclk), |
| 1006 | .soclk(soclk), |
| 1007 | .d(fdin[3]), |
| 1008 | .si(sout[4]), |
| 1009 | .so(sout[3]), |
| 1010 | .reset(reset), |
| 1011 | .q(dout[3]) |
| 1012 | ); |
| 1013 | cl_a1_msff_syrst_4x d0_4 ( |
| 1014 | .l1clk(l1clk), |
| 1015 | .siclk(siclk), |
| 1016 | .soclk(soclk), |
| 1017 | .d(fdin[4]), |
| 1018 | .si(sout[5]), |
| 1019 | .so(sout[4]), |
| 1020 | .reset(reset), |
| 1021 | .q(dout[4]) |
| 1022 | ); |
| 1023 | cl_a1_msff_syrst_4x d0_5 ( |
| 1024 | .l1clk(l1clk), |
| 1025 | .siclk(siclk), |
| 1026 | .soclk(soclk), |
| 1027 | .d(fdin[5]), |
| 1028 | .si(sout[6]), |
| 1029 | .so(sout[5]), |
| 1030 | .reset(reset), |
| 1031 | .q(dout[5]) |
| 1032 | ); |
| 1033 | cl_a1_msff_syrst_4x d0_6 ( |
| 1034 | .l1clk(l1clk), |
| 1035 | .siclk(siclk), |
| 1036 | .soclk(soclk), |
| 1037 | .d(fdin[6]), |
| 1038 | .si(sout[7]), |
| 1039 | .so(sout[6]), |
| 1040 | .reset(reset), |
| 1041 | .q(dout[6]) |
| 1042 | ); |
| 1043 | cl_a1_msff_syrst_4x d0_7 ( |
| 1044 | .l1clk(l1clk), |
| 1045 | .siclk(siclk), |
| 1046 | .soclk(soclk), |
| 1047 | .d(fdin[7]), |
| 1048 | .si(sout[8]), |
| 1049 | .so(sout[7]), |
| 1050 | .reset(reset), |
| 1051 | .q(dout[7]) |
| 1052 | ); |
| 1053 | cl_a1_msff_syrst_4x d0_8 ( |
| 1054 | .l1clk(l1clk), |
| 1055 | .siclk(siclk), |
| 1056 | .soclk(soclk), |
| 1057 | .d(fdin[8]), |
| 1058 | .si(scan_in), |
| 1059 | .so(sout[8]), |
| 1060 | .reset(reset), |
| 1061 | .q(dout[8]) |
| 1062 | ); |
| 1063 | |
| 1064 | |
| 1065 | |
| 1066 | |
| 1067 | endmodule |
| 1068 | |
| 1069 | |
| 1070 | |
| 1071 | |
| 1072 | |
| 1073 | |
| 1074 | |
| 1075 | |
| 1076 | |
| 1077 | |
| 1078 | |
| 1079 | |
| 1080 | |
| 1081 | // any PARAMS parms go into naming of macro |
| 1082 | |
| 1083 | module niu_mb7_msff_ctl_macro__library_a1__reset_1__width_8 ( |
| 1084 | din, |
| 1085 | reset, |
| 1086 | l1clk, |
| 1087 | scan_in, |
| 1088 | siclk, |
| 1089 | soclk, |
| 1090 | dout, |
| 1091 | scan_out); |
| 1092 | wire [7:0] fdin; |
| 1093 | wire [7:1] sout; |
| 1094 | |
| 1095 | input [7:0] din; |
| 1096 | input reset; |
| 1097 | input l1clk; |
| 1098 | input scan_in; |
| 1099 | |
| 1100 | |
| 1101 | input siclk; |
| 1102 | input soclk; |
| 1103 | |
| 1104 | output [7:0] dout; |
| 1105 | output scan_out; |
| 1106 | assign fdin[7:0] = din[7:0] & {8 {reset}}; |
| 1107 | |
| 1108 | |
| 1109 | |
| 1110 | |
| 1111 | |
| 1112 | |
| 1113 | |
| 1114 | |
| 1115 | |
| 1116 | |
| 1117 | |
| 1118 | |
| 1119 | |
| 1120 | |
| 1121 | |
| 1122 | |
| 1123 | |
| 1124 | cl_a1_msff_syrst_4x d0_0 ( |
| 1125 | .l1clk(l1clk), |
| 1126 | .siclk(siclk), |
| 1127 | .soclk(soclk), |
| 1128 | .d(fdin[0]), |
| 1129 | .si(sout[1]), |
| 1130 | .so(scan_out), |
| 1131 | .reset(reset), |
| 1132 | .q(dout[0]) |
| 1133 | ); |
| 1134 | cl_a1_msff_syrst_4x d0_1 ( |
| 1135 | .l1clk(l1clk), |
| 1136 | .siclk(siclk), |
| 1137 | .soclk(soclk), |
| 1138 | .d(fdin[1]), |
| 1139 | .si(sout[2]), |
| 1140 | .so(sout[1]), |
| 1141 | .reset(reset), |
| 1142 | .q(dout[1]) |
| 1143 | ); |
| 1144 | cl_a1_msff_syrst_4x d0_2 ( |
| 1145 | .l1clk(l1clk), |
| 1146 | .siclk(siclk), |
| 1147 | .soclk(soclk), |
| 1148 | .d(fdin[2]), |
| 1149 | .si(sout[3]), |
| 1150 | .so(sout[2]), |
| 1151 | .reset(reset), |
| 1152 | .q(dout[2]) |
| 1153 | ); |
| 1154 | cl_a1_msff_syrst_4x d0_3 ( |
| 1155 | .l1clk(l1clk), |
| 1156 | .siclk(siclk), |
| 1157 | .soclk(soclk), |
| 1158 | .d(fdin[3]), |
| 1159 | .si(sout[4]), |
| 1160 | .so(sout[3]), |
| 1161 | .reset(reset), |
| 1162 | .q(dout[3]) |
| 1163 | ); |
| 1164 | cl_a1_msff_syrst_4x d0_4 ( |
| 1165 | .l1clk(l1clk), |
| 1166 | .siclk(siclk), |
| 1167 | .soclk(soclk), |
| 1168 | .d(fdin[4]), |
| 1169 | .si(sout[5]), |
| 1170 | .so(sout[4]), |
| 1171 | .reset(reset), |
| 1172 | .q(dout[4]) |
| 1173 | ); |
| 1174 | cl_a1_msff_syrst_4x d0_5 ( |
| 1175 | .l1clk(l1clk), |
| 1176 | .siclk(siclk), |
| 1177 | .soclk(soclk), |
| 1178 | .d(fdin[5]), |
| 1179 | .si(sout[6]), |
| 1180 | .so(sout[5]), |
| 1181 | .reset(reset), |
| 1182 | .q(dout[5]) |
| 1183 | ); |
| 1184 | cl_a1_msff_syrst_4x d0_6 ( |
| 1185 | .l1clk(l1clk), |
| 1186 | .siclk(siclk), |
| 1187 | .soclk(soclk), |
| 1188 | .d(fdin[6]), |
| 1189 | .si(sout[7]), |
| 1190 | .so(sout[6]), |
| 1191 | .reset(reset), |
| 1192 | .q(dout[6]) |
| 1193 | ); |
| 1194 | cl_a1_msff_syrst_4x d0_7 ( |
| 1195 | .l1clk(l1clk), |
| 1196 | .siclk(siclk), |
| 1197 | .soclk(soclk), |
| 1198 | .d(fdin[7]), |
| 1199 | .si(scan_in), |
| 1200 | .so(sout[7]), |
| 1201 | .reset(reset), |
| 1202 | .q(dout[7]) |
| 1203 | ); |
| 1204 | |
| 1205 | |
| 1206 | |
| 1207 | |
| 1208 | endmodule |
| 1209 | |
| 1210 | |
| 1211 | |
| 1212 | |
| 1213 | |
| 1214 | |
| 1215 | |
| 1216 | |
| 1217 | |
| 1218 | |
| 1219 | |
| 1220 | |
| 1221 | |
| 1222 | // any PARAMS parms go into naming of macro |
| 1223 | |
| 1224 | module niu_mb7_msff_ctl_macro__library_a1__reset_1__width_2 ( |
| 1225 | din, |
| 1226 | reset, |
| 1227 | l1clk, |
| 1228 | scan_in, |
| 1229 | siclk, |
| 1230 | soclk, |
| 1231 | dout, |
| 1232 | scan_out); |
| 1233 | wire [1:0] fdin; |
| 1234 | wire [1:1] sout; |
| 1235 | |
| 1236 | input [1:0] din; |
| 1237 | input reset; |
| 1238 | input l1clk; |
| 1239 | input scan_in; |
| 1240 | |
| 1241 | |
| 1242 | input siclk; |
| 1243 | input soclk; |
| 1244 | |
| 1245 | output [1:0] dout; |
| 1246 | output scan_out; |
| 1247 | assign fdin[1:0] = din[1:0] & {2 {reset}}; |
| 1248 | |
| 1249 | |
| 1250 | |
| 1251 | |
| 1252 | |
| 1253 | |
| 1254 | |
| 1255 | |
| 1256 | |
| 1257 | |
| 1258 | |
| 1259 | |
| 1260 | |
| 1261 | |
| 1262 | |
| 1263 | |
| 1264 | |
| 1265 | cl_a1_msff_syrst_4x d0_0 ( |
| 1266 | .l1clk(l1clk), |
| 1267 | .siclk(siclk), |
| 1268 | .soclk(soclk), |
| 1269 | .d(fdin[0]), |
| 1270 | .si(sout[1]), |
| 1271 | .so(scan_out), |
| 1272 | .reset(reset), |
| 1273 | .q(dout[0]) |
| 1274 | ); |
| 1275 | cl_a1_msff_syrst_4x d0_1 ( |
| 1276 | .l1clk(l1clk), |
| 1277 | .siclk(siclk), |
| 1278 | .soclk(soclk), |
| 1279 | .d(fdin[1]), |
| 1280 | .si(scan_in), |
| 1281 | .so(sout[1]), |
| 1282 | .reset(reset), |
| 1283 | .q(dout[1]) |
| 1284 | ); |
| 1285 | |
| 1286 | |
| 1287 | |
| 1288 | |
| 1289 | endmodule |
| 1290 | |
| 1291 | |
| 1292 | |
| 1293 | |
| 1294 | |
| 1295 | |
| 1296 | |
| 1297 | |
| 1298 | |
| 1299 | |
| 1300 | |
| 1301 | |
| 1302 | |
| 1303 | // any PARAMS parms go into naming of macro |
| 1304 | |
| 1305 | module niu_mb7_msff_ctl_macro__library_a1__reset_1__width_1 ( |
| 1306 | din, |
| 1307 | reset, |
| 1308 | l1clk, |
| 1309 | scan_in, |
| 1310 | siclk, |
| 1311 | soclk, |
| 1312 | dout, |
| 1313 | scan_out); |
| 1314 | wire [0:0] fdin; |
| 1315 | |
| 1316 | input [0:0] din; |
| 1317 | input reset; |
| 1318 | input l1clk; |
| 1319 | input scan_in; |
| 1320 | |
| 1321 | |
| 1322 | input siclk; |
| 1323 | input soclk; |
| 1324 | |
| 1325 | output [0:0] dout; |
| 1326 | output scan_out; |
| 1327 | assign fdin[0:0] = din[0:0] & {1 {reset}}; |
| 1328 | |
| 1329 | |
| 1330 | |
| 1331 | |
| 1332 | |
| 1333 | |
| 1334 | |
| 1335 | |
| 1336 | |
| 1337 | |
| 1338 | |
| 1339 | |
| 1340 | |
| 1341 | |
| 1342 | |
| 1343 | |
| 1344 | |
| 1345 | cl_a1_msff_syrst_4x d0_0 ( |
| 1346 | .l1clk(l1clk), |
| 1347 | .siclk(siclk), |
| 1348 | .soclk(soclk), |
| 1349 | .d(fdin[0]), |
| 1350 | .si(scan_in), |
| 1351 | .so(scan_out), |
| 1352 | .reset(reset), |
| 1353 | .q(dout[0]) |
| 1354 | ); |
| 1355 | |
| 1356 | |
| 1357 | |
| 1358 | |
| 1359 | endmodule |
| 1360 | |
| 1361 | |
| 1362 | |
| 1363 | |
| 1364 | |
| 1365 | |
| 1366 | |
| 1367 | |
| 1368 | |
| 1369 | |
| 1370 | |
| 1371 | |
| 1372 | |
| 1373 | // any PARAMS parms go into naming of macro |
| 1374 | |
| 1375 | module niu_mb7_msff_ctl_macro__library_a1__reset_1__width_23 ( |
| 1376 | din, |
| 1377 | reset, |
| 1378 | l1clk, |
| 1379 | scan_in, |
| 1380 | siclk, |
| 1381 | soclk, |
| 1382 | dout, |
| 1383 | scan_out); |
| 1384 | wire [22:0] fdin; |
| 1385 | wire [22:1] sout; |
| 1386 | |
| 1387 | input [22:0] din; |
| 1388 | input reset; |
| 1389 | input l1clk; |
| 1390 | input scan_in; |
| 1391 | |
| 1392 | |
| 1393 | input siclk; |
| 1394 | input soclk; |
| 1395 | |
| 1396 | output [22:0] dout; |
| 1397 | output scan_out; |
| 1398 | assign fdin[22:0] = din[22:0] & {23 {reset}}; |
| 1399 | |
| 1400 | |
| 1401 | |
| 1402 | |
| 1403 | |
| 1404 | |
| 1405 | |
| 1406 | |
| 1407 | |
| 1408 | |
| 1409 | |
| 1410 | |
| 1411 | |
| 1412 | |
| 1413 | |
| 1414 | |
| 1415 | |
| 1416 | cl_a1_msff_syrst_4x d0_0 ( |
| 1417 | .l1clk(l1clk), |
| 1418 | .siclk(siclk), |
| 1419 | .soclk(soclk), |
| 1420 | .d(fdin[0]), |
| 1421 | .si(sout[1]), |
| 1422 | .so(scan_out), |
| 1423 | .reset(reset), |
| 1424 | .q(dout[0]) |
| 1425 | ); |
| 1426 | cl_a1_msff_syrst_4x d0_1 ( |
| 1427 | .l1clk(l1clk), |
| 1428 | .siclk(siclk), |
| 1429 | .soclk(soclk), |
| 1430 | .d(fdin[1]), |
| 1431 | .si(sout[2]), |
| 1432 | .so(sout[1]), |
| 1433 | .reset(reset), |
| 1434 | .q(dout[1]) |
| 1435 | ); |
| 1436 | cl_a1_msff_syrst_4x d0_2 ( |
| 1437 | .l1clk(l1clk), |
| 1438 | .siclk(siclk), |
| 1439 | .soclk(soclk), |
| 1440 | .d(fdin[2]), |
| 1441 | .si(sout[3]), |
| 1442 | .so(sout[2]), |
| 1443 | .reset(reset), |
| 1444 | .q(dout[2]) |
| 1445 | ); |
| 1446 | cl_a1_msff_syrst_4x d0_3 ( |
| 1447 | .l1clk(l1clk), |
| 1448 | .siclk(siclk), |
| 1449 | .soclk(soclk), |
| 1450 | .d(fdin[3]), |
| 1451 | .si(sout[4]), |
| 1452 | .so(sout[3]), |
| 1453 | .reset(reset), |
| 1454 | .q(dout[3]) |
| 1455 | ); |
| 1456 | cl_a1_msff_syrst_4x d0_4 ( |
| 1457 | .l1clk(l1clk), |
| 1458 | .siclk(siclk), |
| 1459 | .soclk(soclk), |
| 1460 | .d(fdin[4]), |
| 1461 | .si(sout[5]), |
| 1462 | .so(sout[4]), |
| 1463 | .reset(reset), |
| 1464 | .q(dout[4]) |
| 1465 | ); |
| 1466 | cl_a1_msff_syrst_4x d0_5 ( |
| 1467 | .l1clk(l1clk), |
| 1468 | .siclk(siclk), |
| 1469 | .soclk(soclk), |
| 1470 | .d(fdin[5]), |
| 1471 | .si(sout[6]), |
| 1472 | .so(sout[5]), |
| 1473 | .reset(reset), |
| 1474 | .q(dout[5]) |
| 1475 | ); |
| 1476 | cl_a1_msff_syrst_4x d0_6 ( |
| 1477 | .l1clk(l1clk), |
| 1478 | .siclk(siclk), |
| 1479 | .soclk(soclk), |
| 1480 | .d(fdin[6]), |
| 1481 | .si(sout[7]), |
| 1482 | .so(sout[6]), |
| 1483 | .reset(reset), |
| 1484 | .q(dout[6]) |
| 1485 | ); |
| 1486 | cl_a1_msff_syrst_4x d0_7 ( |
| 1487 | .l1clk(l1clk), |
| 1488 | .siclk(siclk), |
| 1489 | .soclk(soclk), |
| 1490 | .d(fdin[7]), |
| 1491 | .si(sout[8]), |
| 1492 | .so(sout[7]), |
| 1493 | .reset(reset), |
| 1494 | .q(dout[7]) |
| 1495 | ); |
| 1496 | cl_a1_msff_syrst_4x d0_8 ( |
| 1497 | .l1clk(l1clk), |
| 1498 | .siclk(siclk), |
| 1499 | .soclk(soclk), |
| 1500 | .d(fdin[8]), |
| 1501 | .si(sout[9]), |
| 1502 | .so(sout[8]), |
| 1503 | .reset(reset), |
| 1504 | .q(dout[8]) |
| 1505 | ); |
| 1506 | cl_a1_msff_syrst_4x d0_9 ( |
| 1507 | .l1clk(l1clk), |
| 1508 | .siclk(siclk), |
| 1509 | .soclk(soclk), |
| 1510 | .d(fdin[9]), |
| 1511 | .si(sout[10]), |
| 1512 | .so(sout[9]), |
| 1513 | .reset(reset), |
| 1514 | .q(dout[9]) |
| 1515 | ); |
| 1516 | cl_a1_msff_syrst_4x d0_10 ( |
| 1517 | .l1clk(l1clk), |
| 1518 | .siclk(siclk), |
| 1519 | .soclk(soclk), |
| 1520 | .d(fdin[10]), |
| 1521 | .si(sout[11]), |
| 1522 | .so(sout[10]), |
| 1523 | .reset(reset), |
| 1524 | .q(dout[10]) |
| 1525 | ); |
| 1526 | cl_a1_msff_syrst_4x d0_11 ( |
| 1527 | .l1clk(l1clk), |
| 1528 | .siclk(siclk), |
| 1529 | .soclk(soclk), |
| 1530 | .d(fdin[11]), |
| 1531 | .si(sout[12]), |
| 1532 | .so(sout[11]), |
| 1533 | .reset(reset), |
| 1534 | .q(dout[11]) |
| 1535 | ); |
| 1536 | cl_a1_msff_syrst_4x d0_12 ( |
| 1537 | .l1clk(l1clk), |
| 1538 | .siclk(siclk), |
| 1539 | .soclk(soclk), |
| 1540 | .d(fdin[12]), |
| 1541 | .si(sout[13]), |
| 1542 | .so(sout[12]), |
| 1543 | .reset(reset), |
| 1544 | .q(dout[12]) |
| 1545 | ); |
| 1546 | cl_a1_msff_syrst_4x d0_13 ( |
| 1547 | .l1clk(l1clk), |
| 1548 | .siclk(siclk), |
| 1549 | .soclk(soclk), |
| 1550 | .d(fdin[13]), |
| 1551 | .si(sout[14]), |
| 1552 | .so(sout[13]), |
| 1553 | .reset(reset), |
| 1554 | .q(dout[13]) |
| 1555 | ); |
| 1556 | cl_a1_msff_syrst_4x d0_14 ( |
| 1557 | .l1clk(l1clk), |
| 1558 | .siclk(siclk), |
| 1559 | .soclk(soclk), |
| 1560 | .d(fdin[14]), |
| 1561 | .si(sout[15]), |
| 1562 | .so(sout[14]), |
| 1563 | .reset(reset), |
| 1564 | .q(dout[14]) |
| 1565 | ); |
| 1566 | cl_a1_msff_syrst_4x d0_15 ( |
| 1567 | .l1clk(l1clk), |
| 1568 | .siclk(siclk), |
| 1569 | .soclk(soclk), |
| 1570 | .d(fdin[15]), |
| 1571 | .si(sout[16]), |
| 1572 | .so(sout[15]), |
| 1573 | .reset(reset), |
| 1574 | .q(dout[15]) |
| 1575 | ); |
| 1576 | cl_a1_msff_syrst_4x d0_16 ( |
| 1577 | .l1clk(l1clk), |
| 1578 | .siclk(siclk), |
| 1579 | .soclk(soclk), |
| 1580 | .d(fdin[16]), |
| 1581 | .si(sout[17]), |
| 1582 | .so(sout[16]), |
| 1583 | .reset(reset), |
| 1584 | .q(dout[16]) |
| 1585 | ); |
| 1586 | cl_a1_msff_syrst_4x d0_17 ( |
| 1587 | .l1clk(l1clk), |
| 1588 | .siclk(siclk), |
| 1589 | .soclk(soclk), |
| 1590 | .d(fdin[17]), |
| 1591 | .si(sout[18]), |
| 1592 | .so(sout[17]), |
| 1593 | .reset(reset), |
| 1594 | .q(dout[17]) |
| 1595 | ); |
| 1596 | cl_a1_msff_syrst_4x d0_18 ( |
| 1597 | .l1clk(l1clk), |
| 1598 | .siclk(siclk), |
| 1599 | .soclk(soclk), |
| 1600 | .d(fdin[18]), |
| 1601 | .si(sout[19]), |
| 1602 | .so(sout[18]), |
| 1603 | .reset(reset), |
| 1604 | .q(dout[18]) |
| 1605 | ); |
| 1606 | cl_a1_msff_syrst_4x d0_19 ( |
| 1607 | .l1clk(l1clk), |
| 1608 | .siclk(siclk), |
| 1609 | .soclk(soclk), |
| 1610 | .d(fdin[19]), |
| 1611 | .si(sout[20]), |
| 1612 | .so(sout[19]), |
| 1613 | .reset(reset), |
| 1614 | .q(dout[19]) |
| 1615 | ); |
| 1616 | cl_a1_msff_syrst_4x d0_20 ( |
| 1617 | .l1clk(l1clk), |
| 1618 | .siclk(siclk), |
| 1619 | .soclk(soclk), |
| 1620 | .d(fdin[20]), |
| 1621 | .si(sout[21]), |
| 1622 | .so(sout[20]), |
| 1623 | .reset(reset), |
| 1624 | .q(dout[20]) |
| 1625 | ); |
| 1626 | cl_a1_msff_syrst_4x d0_21 ( |
| 1627 | .l1clk(l1clk), |
| 1628 | .siclk(siclk), |
| 1629 | .soclk(soclk), |
| 1630 | .d(fdin[21]), |
| 1631 | .si(sout[22]), |
| 1632 | .so(sout[21]), |
| 1633 | .reset(reset), |
| 1634 | .q(dout[21]) |
| 1635 | ); |
| 1636 | cl_a1_msff_syrst_4x d0_22 ( |
| 1637 | .l1clk(l1clk), |
| 1638 | .siclk(siclk), |
| 1639 | .soclk(soclk), |
| 1640 | .d(fdin[22]), |
| 1641 | .si(scan_in), |
| 1642 | .so(sout[22]), |
| 1643 | .reset(reset), |
| 1644 | .q(dout[22]) |
| 1645 | ); |
| 1646 | |
| 1647 | |
| 1648 | |
| 1649 | |
| 1650 | endmodule |
| 1651 | |
| 1652 | |
| 1653 | |
| 1654 | |
| 1655 | |
| 1656 | |
| 1657 | |
| 1658 | |
| 1659 | |
| 1660 | |
| 1661 | |
| 1662 | |
| 1663 | |
| 1664 | // any PARAMS parms go into naming of macro |
| 1665 | |
| 1666 | module niu_mb7_msff_ctl_macro__library_a1__reset_1__width_3 ( |
| 1667 | din, |
| 1668 | reset, |
| 1669 | l1clk, |
| 1670 | scan_in, |
| 1671 | siclk, |
| 1672 | soclk, |
| 1673 | dout, |
| 1674 | scan_out); |
| 1675 | wire [2:0] fdin; |
| 1676 | wire [2:1] sout; |
| 1677 | |
| 1678 | input [2:0] din; |
| 1679 | input reset; |
| 1680 | input l1clk; |
| 1681 | input scan_in; |
| 1682 | |
| 1683 | |
| 1684 | input siclk; |
| 1685 | input soclk; |
| 1686 | |
| 1687 | output [2:0] dout; |
| 1688 | output scan_out; |
| 1689 | assign fdin[2:0] = din[2:0] & {3 {reset}}; |
| 1690 | |
| 1691 | |
| 1692 | |
| 1693 | |
| 1694 | |
| 1695 | |
| 1696 | |
| 1697 | |
| 1698 | |
| 1699 | |
| 1700 | |
| 1701 | |
| 1702 | |
| 1703 | |
| 1704 | |
| 1705 | |
| 1706 | |
| 1707 | cl_a1_msff_syrst_4x d0_0 ( |
| 1708 | .l1clk(l1clk), |
| 1709 | .siclk(siclk), |
| 1710 | .soclk(soclk), |
| 1711 | .d(fdin[0]), |
| 1712 | .si(sout[1]), |
| 1713 | .so(scan_out), |
| 1714 | .reset(reset), |
| 1715 | .q(dout[0]) |
| 1716 | ); |
| 1717 | cl_a1_msff_syrst_4x d0_1 ( |
| 1718 | .l1clk(l1clk), |
| 1719 | .siclk(siclk), |
| 1720 | .soclk(soclk), |
| 1721 | .d(fdin[1]), |
| 1722 | .si(sout[2]), |
| 1723 | .so(sout[1]), |
| 1724 | .reset(reset), |
| 1725 | .q(dout[1]) |
| 1726 | ); |
| 1727 | cl_a1_msff_syrst_4x d0_2 ( |
| 1728 | .l1clk(l1clk), |
| 1729 | .siclk(siclk), |
| 1730 | .soclk(soclk), |
| 1731 | .d(fdin[2]), |
| 1732 | .si(scan_in), |
| 1733 | .so(sout[2]), |
| 1734 | .reset(reset), |
| 1735 | .q(dout[2]) |
| 1736 | ); |
| 1737 | |
| 1738 | |
| 1739 | |
| 1740 | |
| 1741 | endmodule |
| 1742 | |
| 1743 | |
| 1744 | |
| 1745 | |
| 1746 | |
| 1747 | |
| 1748 | |
| 1749 | |
| 1750 | |
| 1751 | |
| 1752 | |
| 1753 | |
| 1754 | |
| 1755 | // any PARAMS parms go into naming of macro |
| 1756 | |
| 1757 | module niu_mb7_msff_ctl_macro__library_a1__reset_1__width_40 ( |
| 1758 | din, |
| 1759 | reset, |
| 1760 | l1clk, |
| 1761 | scan_in, |
| 1762 | siclk, |
| 1763 | soclk, |
| 1764 | dout, |
| 1765 | scan_out); |
| 1766 | wire [39:0] fdin; |
| 1767 | wire [39:1] sout; |
| 1768 | |
| 1769 | input [39:0] din; |
| 1770 | input reset; |
| 1771 | input l1clk; |
| 1772 | input scan_in; |
| 1773 | |
| 1774 | |
| 1775 | input siclk; |
| 1776 | input soclk; |
| 1777 | |
| 1778 | output [39:0] dout; |
| 1779 | output scan_out; |
| 1780 | assign fdin[39:0] = din[39:0] & {40 {reset}}; |
| 1781 | |
| 1782 | |
| 1783 | |
| 1784 | |
| 1785 | |
| 1786 | |
| 1787 | |
| 1788 | |
| 1789 | |
| 1790 | |
| 1791 | |
| 1792 | |
| 1793 | |
| 1794 | |
| 1795 | |
| 1796 | |
| 1797 | |
| 1798 | cl_a1_msff_syrst_4x d0_0 ( |
| 1799 | .l1clk(l1clk), |
| 1800 | .siclk(siclk), |
| 1801 | .soclk(soclk), |
| 1802 | .d(fdin[0]), |
| 1803 | .si(sout[1]), |
| 1804 | .so(scan_out), |
| 1805 | .reset(reset), |
| 1806 | .q(dout[0]) |
| 1807 | ); |
| 1808 | cl_a1_msff_syrst_4x d0_1 ( |
| 1809 | .l1clk(l1clk), |
| 1810 | .siclk(siclk), |
| 1811 | .soclk(soclk), |
| 1812 | .d(fdin[1]), |
| 1813 | .si(sout[2]), |
| 1814 | .so(sout[1]), |
| 1815 | .reset(reset), |
| 1816 | .q(dout[1]) |
| 1817 | ); |
| 1818 | cl_a1_msff_syrst_4x d0_2 ( |
| 1819 | .l1clk(l1clk), |
| 1820 | .siclk(siclk), |
| 1821 | .soclk(soclk), |
| 1822 | .d(fdin[2]), |
| 1823 | .si(sout[3]), |
| 1824 | .so(sout[2]), |
| 1825 | .reset(reset), |
| 1826 | .q(dout[2]) |
| 1827 | ); |
| 1828 | cl_a1_msff_syrst_4x d0_3 ( |
| 1829 | .l1clk(l1clk), |
| 1830 | .siclk(siclk), |
| 1831 | .soclk(soclk), |
| 1832 | .d(fdin[3]), |
| 1833 | .si(sout[4]), |
| 1834 | .so(sout[3]), |
| 1835 | .reset(reset), |
| 1836 | .q(dout[3]) |
| 1837 | ); |
| 1838 | cl_a1_msff_syrst_4x d0_4 ( |
| 1839 | .l1clk(l1clk), |
| 1840 | .siclk(siclk), |
| 1841 | .soclk(soclk), |
| 1842 | .d(fdin[4]), |
| 1843 | .si(sout[5]), |
| 1844 | .so(sout[4]), |
| 1845 | .reset(reset), |
| 1846 | .q(dout[4]) |
| 1847 | ); |
| 1848 | cl_a1_msff_syrst_4x d0_5 ( |
| 1849 | .l1clk(l1clk), |
| 1850 | .siclk(siclk), |
| 1851 | .soclk(soclk), |
| 1852 | .d(fdin[5]), |
| 1853 | .si(sout[6]), |
| 1854 | .so(sout[5]), |
| 1855 | .reset(reset), |
| 1856 | .q(dout[5]) |
| 1857 | ); |
| 1858 | cl_a1_msff_syrst_4x d0_6 ( |
| 1859 | .l1clk(l1clk), |
| 1860 | .siclk(siclk), |
| 1861 | .soclk(soclk), |
| 1862 | .d(fdin[6]), |
| 1863 | .si(sout[7]), |
| 1864 | .so(sout[6]), |
| 1865 | .reset(reset), |
| 1866 | .q(dout[6]) |
| 1867 | ); |
| 1868 | cl_a1_msff_syrst_4x d0_7 ( |
| 1869 | .l1clk(l1clk), |
| 1870 | .siclk(siclk), |
| 1871 | .soclk(soclk), |
| 1872 | .d(fdin[7]), |
| 1873 | .si(sout[8]), |
| 1874 | .so(sout[7]), |
| 1875 | .reset(reset), |
| 1876 | .q(dout[7]) |
| 1877 | ); |
| 1878 | cl_a1_msff_syrst_4x d0_8 ( |
| 1879 | .l1clk(l1clk), |
| 1880 | .siclk(siclk), |
| 1881 | .soclk(soclk), |
| 1882 | .d(fdin[8]), |
| 1883 | .si(sout[9]), |
| 1884 | .so(sout[8]), |
| 1885 | .reset(reset), |
| 1886 | .q(dout[8]) |
| 1887 | ); |
| 1888 | cl_a1_msff_syrst_4x d0_9 ( |
| 1889 | .l1clk(l1clk), |
| 1890 | .siclk(siclk), |
| 1891 | .soclk(soclk), |
| 1892 | .d(fdin[9]), |
| 1893 | .si(sout[10]), |
| 1894 | .so(sout[9]), |
| 1895 | .reset(reset), |
| 1896 | .q(dout[9]) |
| 1897 | ); |
| 1898 | cl_a1_msff_syrst_4x d0_10 ( |
| 1899 | .l1clk(l1clk), |
| 1900 | .siclk(siclk), |
| 1901 | .soclk(soclk), |
| 1902 | .d(fdin[10]), |
| 1903 | .si(sout[11]), |
| 1904 | .so(sout[10]), |
| 1905 | .reset(reset), |
| 1906 | .q(dout[10]) |
| 1907 | ); |
| 1908 | cl_a1_msff_syrst_4x d0_11 ( |
| 1909 | .l1clk(l1clk), |
| 1910 | .siclk(siclk), |
| 1911 | .soclk(soclk), |
| 1912 | .d(fdin[11]), |
| 1913 | .si(sout[12]), |
| 1914 | .so(sout[11]), |
| 1915 | .reset(reset), |
| 1916 | .q(dout[11]) |
| 1917 | ); |
| 1918 | cl_a1_msff_syrst_4x d0_12 ( |
| 1919 | .l1clk(l1clk), |
| 1920 | .siclk(siclk), |
| 1921 | .soclk(soclk), |
| 1922 | .d(fdin[12]), |
| 1923 | .si(sout[13]), |
| 1924 | .so(sout[12]), |
| 1925 | .reset(reset), |
| 1926 | .q(dout[12]) |
| 1927 | ); |
| 1928 | cl_a1_msff_syrst_4x d0_13 ( |
| 1929 | .l1clk(l1clk), |
| 1930 | .siclk(siclk), |
| 1931 | .soclk(soclk), |
| 1932 | .d(fdin[13]), |
| 1933 | .si(sout[14]), |
| 1934 | .so(sout[13]), |
| 1935 | .reset(reset), |
| 1936 | .q(dout[13]) |
| 1937 | ); |
| 1938 | cl_a1_msff_syrst_4x d0_14 ( |
| 1939 | .l1clk(l1clk), |
| 1940 | .siclk(siclk), |
| 1941 | .soclk(soclk), |
| 1942 | .d(fdin[14]), |
| 1943 | .si(sout[15]), |
| 1944 | .so(sout[14]), |
| 1945 | .reset(reset), |
| 1946 | .q(dout[14]) |
| 1947 | ); |
| 1948 | cl_a1_msff_syrst_4x d0_15 ( |
| 1949 | .l1clk(l1clk), |
| 1950 | .siclk(siclk), |
| 1951 | .soclk(soclk), |
| 1952 | .d(fdin[15]), |
| 1953 | .si(sout[16]), |
| 1954 | .so(sout[15]), |
| 1955 | .reset(reset), |
| 1956 | .q(dout[15]) |
| 1957 | ); |
| 1958 | cl_a1_msff_syrst_4x d0_16 ( |
| 1959 | .l1clk(l1clk), |
| 1960 | .siclk(siclk), |
| 1961 | .soclk(soclk), |
| 1962 | .d(fdin[16]), |
| 1963 | .si(sout[17]), |
| 1964 | .so(sout[16]), |
| 1965 | .reset(reset), |
| 1966 | .q(dout[16]) |
| 1967 | ); |
| 1968 | cl_a1_msff_syrst_4x d0_17 ( |
| 1969 | .l1clk(l1clk), |
| 1970 | .siclk(siclk), |
| 1971 | .soclk(soclk), |
| 1972 | .d(fdin[17]), |
| 1973 | .si(sout[18]), |
| 1974 | .so(sout[17]), |
| 1975 | .reset(reset), |
| 1976 | .q(dout[17]) |
| 1977 | ); |
| 1978 | cl_a1_msff_syrst_4x d0_18 ( |
| 1979 | .l1clk(l1clk), |
| 1980 | .siclk(siclk), |
| 1981 | .soclk(soclk), |
| 1982 | .d(fdin[18]), |
| 1983 | .si(sout[19]), |
| 1984 | .so(sout[18]), |
| 1985 | .reset(reset), |
| 1986 | .q(dout[18]) |
| 1987 | ); |
| 1988 | cl_a1_msff_syrst_4x d0_19 ( |
| 1989 | .l1clk(l1clk), |
| 1990 | .siclk(siclk), |
| 1991 | .soclk(soclk), |
| 1992 | .d(fdin[19]), |
| 1993 | .si(sout[20]), |
| 1994 | .so(sout[19]), |
| 1995 | .reset(reset), |
| 1996 | .q(dout[19]) |
| 1997 | ); |
| 1998 | cl_a1_msff_syrst_4x d0_20 ( |
| 1999 | .l1clk(l1clk), |
| 2000 | .siclk(siclk), |
| 2001 | .soclk(soclk), |
| 2002 | .d(fdin[20]), |
| 2003 | .si(sout[21]), |
| 2004 | .so(sout[20]), |
| 2005 | .reset(reset), |
| 2006 | .q(dout[20]) |
| 2007 | ); |
| 2008 | cl_a1_msff_syrst_4x d0_21 ( |
| 2009 | .l1clk(l1clk), |
| 2010 | .siclk(siclk), |
| 2011 | .soclk(soclk), |
| 2012 | .d(fdin[21]), |
| 2013 | .si(sout[22]), |
| 2014 | .so(sout[21]), |
| 2015 | .reset(reset), |
| 2016 | .q(dout[21]) |
| 2017 | ); |
| 2018 | cl_a1_msff_syrst_4x d0_22 ( |
| 2019 | .l1clk(l1clk), |
| 2020 | .siclk(siclk), |
| 2021 | .soclk(soclk), |
| 2022 | .d(fdin[22]), |
| 2023 | .si(sout[23]), |
| 2024 | .so(sout[22]), |
| 2025 | .reset(reset), |
| 2026 | .q(dout[22]) |
| 2027 | ); |
| 2028 | cl_a1_msff_syrst_4x d0_23 ( |
| 2029 | .l1clk(l1clk), |
| 2030 | .siclk(siclk), |
| 2031 | .soclk(soclk), |
| 2032 | .d(fdin[23]), |
| 2033 | .si(sout[24]), |
| 2034 | .so(sout[23]), |
| 2035 | .reset(reset), |
| 2036 | .q(dout[23]) |
| 2037 | ); |
| 2038 | cl_a1_msff_syrst_4x d0_24 ( |
| 2039 | .l1clk(l1clk), |
| 2040 | .siclk(siclk), |
| 2041 | .soclk(soclk), |
| 2042 | .d(fdin[24]), |
| 2043 | .si(sout[25]), |
| 2044 | .so(sout[24]), |
| 2045 | .reset(reset), |
| 2046 | .q(dout[24]) |
| 2047 | ); |
| 2048 | cl_a1_msff_syrst_4x d0_25 ( |
| 2049 | .l1clk(l1clk), |
| 2050 | .siclk(siclk), |
| 2051 | .soclk(soclk), |
| 2052 | .d(fdin[25]), |
| 2053 | .si(sout[26]), |
| 2054 | .so(sout[25]), |
| 2055 | .reset(reset), |
| 2056 | .q(dout[25]) |
| 2057 | ); |
| 2058 | cl_a1_msff_syrst_4x d0_26 ( |
| 2059 | .l1clk(l1clk), |
| 2060 | .siclk(siclk), |
| 2061 | .soclk(soclk), |
| 2062 | .d(fdin[26]), |
| 2063 | .si(sout[27]), |
| 2064 | .so(sout[26]), |
| 2065 | .reset(reset), |
| 2066 | .q(dout[26]) |
| 2067 | ); |
| 2068 | cl_a1_msff_syrst_4x d0_27 ( |
| 2069 | .l1clk(l1clk), |
| 2070 | .siclk(siclk), |
| 2071 | .soclk(soclk), |
| 2072 | .d(fdin[27]), |
| 2073 | .si(sout[28]), |
| 2074 | .so(sout[27]), |
| 2075 | .reset(reset), |
| 2076 | .q(dout[27]) |
| 2077 | ); |
| 2078 | cl_a1_msff_syrst_4x d0_28 ( |
| 2079 | .l1clk(l1clk), |
| 2080 | .siclk(siclk), |
| 2081 | .soclk(soclk), |
| 2082 | .d(fdin[28]), |
| 2083 | .si(sout[29]), |
| 2084 | .so(sout[28]), |
| 2085 | .reset(reset), |
| 2086 | .q(dout[28]) |
| 2087 | ); |
| 2088 | cl_a1_msff_syrst_4x d0_29 ( |
| 2089 | .l1clk(l1clk), |
| 2090 | .siclk(siclk), |
| 2091 | .soclk(soclk), |
| 2092 | .d(fdin[29]), |
| 2093 | .si(sout[30]), |
| 2094 | .so(sout[29]), |
| 2095 | .reset(reset), |
| 2096 | .q(dout[29]) |
| 2097 | ); |
| 2098 | cl_a1_msff_syrst_4x d0_30 ( |
| 2099 | .l1clk(l1clk), |
| 2100 | .siclk(siclk), |
| 2101 | .soclk(soclk), |
| 2102 | .d(fdin[30]), |
| 2103 | .si(sout[31]), |
| 2104 | .so(sout[30]), |
| 2105 | .reset(reset), |
| 2106 | .q(dout[30]) |
| 2107 | ); |
| 2108 | cl_a1_msff_syrst_4x d0_31 ( |
| 2109 | .l1clk(l1clk), |
| 2110 | .siclk(siclk), |
| 2111 | .soclk(soclk), |
| 2112 | .d(fdin[31]), |
| 2113 | .si(sout[32]), |
| 2114 | .so(sout[31]), |
| 2115 | .reset(reset), |
| 2116 | .q(dout[31]) |
| 2117 | ); |
| 2118 | cl_a1_msff_syrst_4x d0_32 ( |
| 2119 | .l1clk(l1clk), |
| 2120 | .siclk(siclk), |
| 2121 | .soclk(soclk), |
| 2122 | .d(fdin[32]), |
| 2123 | .si(sout[33]), |
| 2124 | .so(sout[32]), |
| 2125 | .reset(reset), |
| 2126 | .q(dout[32]) |
| 2127 | ); |
| 2128 | cl_a1_msff_syrst_4x d0_33 ( |
| 2129 | .l1clk(l1clk), |
| 2130 | .siclk(siclk), |
| 2131 | .soclk(soclk), |
| 2132 | .d(fdin[33]), |
| 2133 | .si(sout[34]), |
| 2134 | .so(sout[33]), |
| 2135 | .reset(reset), |
| 2136 | .q(dout[33]) |
| 2137 | ); |
| 2138 | cl_a1_msff_syrst_4x d0_34 ( |
| 2139 | .l1clk(l1clk), |
| 2140 | .siclk(siclk), |
| 2141 | .soclk(soclk), |
| 2142 | .d(fdin[34]), |
| 2143 | .si(sout[35]), |
| 2144 | .so(sout[34]), |
| 2145 | .reset(reset), |
| 2146 | .q(dout[34]) |
| 2147 | ); |
| 2148 | cl_a1_msff_syrst_4x d0_35 ( |
| 2149 | .l1clk(l1clk), |
| 2150 | .siclk(siclk), |
| 2151 | .soclk(soclk), |
| 2152 | .d(fdin[35]), |
| 2153 | .si(sout[36]), |
| 2154 | .so(sout[35]), |
| 2155 | .reset(reset), |
| 2156 | .q(dout[35]) |
| 2157 | ); |
| 2158 | cl_a1_msff_syrst_4x d0_36 ( |
| 2159 | .l1clk(l1clk), |
| 2160 | .siclk(siclk), |
| 2161 | .soclk(soclk), |
| 2162 | .d(fdin[36]), |
| 2163 | .si(sout[37]), |
| 2164 | .so(sout[36]), |
| 2165 | .reset(reset), |
| 2166 | .q(dout[36]) |
| 2167 | ); |
| 2168 | cl_a1_msff_syrst_4x d0_37 ( |
| 2169 | .l1clk(l1clk), |
| 2170 | .siclk(siclk), |
| 2171 | .soclk(soclk), |
| 2172 | .d(fdin[37]), |
| 2173 | .si(sout[38]), |
| 2174 | .so(sout[37]), |
| 2175 | .reset(reset), |
| 2176 | .q(dout[37]) |
| 2177 | ); |
| 2178 | cl_a1_msff_syrst_4x d0_38 ( |
| 2179 | .l1clk(l1clk), |
| 2180 | .siclk(siclk), |
| 2181 | .soclk(soclk), |
| 2182 | .d(fdin[38]), |
| 2183 | .si(sout[39]), |
| 2184 | .so(sout[38]), |
| 2185 | .reset(reset), |
| 2186 | .q(dout[38]) |
| 2187 | ); |
| 2188 | cl_a1_msff_syrst_4x d0_39 ( |
| 2189 | .l1clk(l1clk), |
| 2190 | .siclk(siclk), |
| 2191 | .soclk(soclk), |
| 2192 | .d(fdin[39]), |
| 2193 | .si(scan_in), |
| 2194 | .so(sout[39]), |
| 2195 | .reset(reset), |
| 2196 | .q(dout[39]) |
| 2197 | ); |
| 2198 | |
| 2199 | |
| 2200 | |
| 2201 | |
| 2202 | endmodule |
| 2203 | |
| 2204 | |
| 2205 | |
| 2206 | |
| 2207 | |
| 2208 | |
| 2209 | |
| 2210 | |