| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_pio_scheduler64.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /*%W% %G%*/ |
| 36 | |
| 37 | /*************************************************************** |
| 38 | * |
| 39 | * File Name : niu_pio_scheduler64.v |
| 40 | * Author Name : John Lo |
| 41 | * Description : This file is copy from Vega ibtp scheduler64.v. |
| 42 | * It includes three major part of |
| 43 | * fuctions: |
| 44 | * 1. req_mux which is composed from req_mux.c code. |
| 45 | * 2. daisy_chain which is a priority |
| 46 | * daisy chain nor gates. |
| 47 | * It is composed from daisy_chain.c code. |
| 48 | * 3. encoder which is composed from encoder.c code. |
| 49 | * Parent Module: niu_pio_ic |
| 50 | * Child Module: |
| 51 | * Interface Mod: |
| 52 | * Date Created : 6/17/02 |
| 53 | * |
| 54 | * Copyright (c) 2008, Sun Microsystems, Inc. |
| 55 | * Sun Proprietary and Confidential |
| 56 | * |
| 57 | * Modification : |
| 58 | * |
| 59 | * Synthesis Notes: There is a multicycle path of 2 |
| 60 | * from gnt[63:0] to result_qpn[5:0]. |
| 61 | * |
| 62 | * |
| 63 | **************************************************************/ |
| 64 | |
| 65 | module niu_pio_scheduler64 ( |
| 66 | clk, |
| 67 | reset, |
| 68 | intr_req_group, |
| 69 | intr_rel_group, |
| 70 | activate_ig_sm, |
| 71 | activate_ig_sm_rel, |
| 72 | activate_ig_sm_rel_latched, |
| 73 | latch_req_mux_out, |
| 74 | latch_result_group, |
| 75 | latch_nx_pri_group, |
| 76 | // output |
| 77 | group |
| 78 | ); |
| 79 | |
| 80 | input clk; |
| 81 | input reset; |
| 82 | input [63:0] intr_req_group; |
| 83 | input [63:0] intr_rel_group; |
| 84 | input latch_req_mux_out; |
| 85 | input activate_ig_sm; |
| 86 | input activate_ig_sm_rel; |
| 87 | input activate_ig_sm_rel_latched; |
| 88 | input latch_result_group; |
| 89 | input latch_nx_pri_group; |
| 90 | // output |
| 91 | output [5:0] group; |
| 92 | |
| 93 | reg [63:0] del_intr_rel_group; |
| 94 | |
| 95 | wire [63:0] intr_req_group; |
| 96 | wire [63:0] mux_input; |
| 97 | wire [63:0] req_mux_dout; |
| 98 | wire [63:0] req_mux_dout_reg; |
| 99 | wire [63:0] gnt; |
| 100 | // wire [63:0] gnt_reg; |
| 101 | wire [5:0] gnt_num; |
| 102 | wire [5:0] group; |
| 103 | wire [5:0] result_group; |
| 104 | wire [5:0] pri_group_1; |
| 105 | wire [5:0] pri_group_2; |
| 106 | wire [5:0] nx_pri_group; |
| 107 | |
| 108 | always @ (posedge clk) |
| 109 | begin |
| 110 | if (reset) |
| 111 | del_intr_rel_group <= 64'b0 ; |
| 112 | else |
| 113 | begin |
| 114 | if (activate_ig_sm_rel) |
| 115 | del_intr_rel_group <= intr_rel_group ; |
| 116 | else |
| 117 | del_intr_rel_group <= del_intr_rel_group; |
| 118 | end |
| 119 | end |
| 120 | |
| 121 | assign mux_input[63:0] = ((activate_ig_sm)?intr_req_group:((activate_ig_sm_rel_latched)?del_intr_rel_group:64'b0)) ; |
| 122 | |
| 123 | reg [63:0] mux_input_del ; |
| 124 | reg latch_req_mux_out_del ; |
| 125 | reg latch_result_group_del ; |
| 126 | reg latch_nx_pri_group_del ; |
| 127 | |
| 128 | always @ (posedge clk) |
| 129 | begin |
| 130 | if (reset) |
| 131 | begin |
| 132 | mux_input_del <= 64'b0 ; |
| 133 | latch_req_mux_out_del <= 1'b0 ; |
| 134 | latch_result_group_del <= 1'b0 ; |
| 135 | latch_nx_pri_group_del <= 1'b0 ; |
| 136 | end |
| 137 | else |
| 138 | begin |
| 139 | mux_input_del <= mux_input ; |
| 140 | latch_req_mux_out_del <= latch_req_mux_out ; |
| 141 | latch_result_group_del <= latch_result_group ; |
| 142 | latch_nx_pri_group_del <= latch_nx_pri_group ; |
| 143 | end |
| 144 | end |
| 145 | |
| 146 | niu_req_mux req_mux(.req_mux_din(mux_input_del), |
| 147 | .sel_1(pri_group_1), |
| 148 | .sel_2(pri_group_2), |
| 149 | .req_mux_dout(req_mux_dout)); |
| 150 | |
| 151 | dffre #(64) req_mux_dout_reg_dffre( |
| 152 | .clk(clk), |
| 153 | .reset(reset), |
| 154 | .en(latch_req_mux_out_del), |
| 155 | .d(req_mux_dout), |
| 156 | .q(req_mux_dout_reg)); |
| 157 | |
| 158 | niu_daisy_chain daisy_chain(.req_mux_dout(req_mux_dout_reg), |
| 159 | .gnt(gnt)); |
| 160 | |
| 161 | niu_gnt_encoder gnt_encoder(.gnt(gnt),.gnt_num(gnt_num)); |
| 162 | |
| 163 | |
| 164 | assign result_group = gnt_num + pri_group_1; |
| 165 | |
| 166 | dffre #(6) group_dffre (.clk(clk),.reset(reset), |
| 167 | .en(latch_result_group_del), |
| 168 | .d(result_group), |
| 169 | .q(group)); |
| 170 | |
| 171 | assign nx_pri_group = group + 1; |
| 172 | |
| 173 | dffre #(6) pri_group_dffre_1(.clk(clk),.reset(reset), |
| 174 | .en(latch_nx_pri_group_del), |
| 175 | .d(nx_pri_group), |
| 176 | .q(pri_group_1)); |
| 177 | |
| 178 | dffre #(6) pri_group_dffre_2 (.clk(clk),.reset(reset), |
| 179 | .en(latch_nx_pri_group_del), |
| 180 | .d(nx_pri_group), |
| 181 | .q(pri_group_2)); |
| 182 | |
| 183 | endmodule // niu_pio_scheduler64 |