| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_rdmc_buf_manager.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /************************************************************************* |
| 36 | * |
| 37 | * File Name : niu_rdmc_buf_manager.v |
| 38 | * Author Name : Jeanne Cai |
| 39 | * Description : |
| 40 | * Date Created : 07/18/2004 |
| 41 | * |
| 42 | * Copyright (c) 2001, Sun Microsystems, Inc. |
| 43 | * Sun Proprietary and Confidential |
| 44 | * |
| 45 | * |
| 46 | *************************************************************************/ |
| 47 | `include "niu_rdmc.h" |
| 48 | module niu_rdmc_buf_manager ( |
| 49 | clk, |
| 50 | reset, |
| 51 | wred_enable, |
| 52 | random_num, |
| 53 | dma_chnl_grp_id, |
| 54 | dma_data_offset, |
| 55 | full_header, |
| 56 | dma_en, |
| 57 | dma_reset, |
| 58 | page_valid0, |
| 59 | addr_mask0, |
| 60 | comp_value0, |
| 61 | relo_value0, |
| 62 | page_valid1, |
| 63 | addr_mask1, |
| 64 | comp_value1, |
| 65 | relo_value1, |
| 66 | dma_fatal_err, |
| 67 | rx_log_page_hdl_reg, |
| 68 | rdc_red_param_reg, |
| 69 | rbr_cfig_a_reg, |
| 70 | rbr_cfig_b_reg, |
| 71 | rbr_kick_reg, |
| 72 | rbr_cfig_a_reg_wenu, |
| 73 | rbr_cfig_a_reg_wenl, |
| 74 | rbr_kick_reg_wen, |
| 75 | muxed_pkt_len, |
| 76 | muxed_rdc_num_r, |
| 77 | muxed_drop_pkt_r, |
| 78 | muxed_s_event_r, |
| 79 | sel_buf_en, //it is stage0_en_r, in stage1 |
| 80 | pkt_req_cnt_e_done_mod, |
| 81 | pkt_buf_done, |
| 82 | is_hdr_wr_data, |
| 83 | is_jmb1_wr_data, |
| 84 | fetch_desp_req_sm, |
| 85 | fetch_desp_pre_done, |
| 86 | fetch_desp_done, |
| 87 | fetch_desp_resp_vld, |
| 88 | rdmc_resp_data_valid, |
| 89 | cache_start_addr, |
| 90 | cache_end_addr, |
| 91 | cache_buf_rd_gnt, |
| 92 | cache_buf_rd_data, |
| 93 | cache_parity_err, |
| 94 | rcr_curr_qlen, |
| 95 | shadw_curr_space_cnt, |
| 96 | |
| 97 | chnl_sel_buf_en_r, |
| 98 | desp_init_valid, |
| 99 | fetch_desp_trig, |
| 100 | fetch_desp_addr, |
| 101 | fetch_desp_num, |
| 102 | cache_read_req, |
| 103 | cache_rd_ptr, |
| 104 | cache_wr_ptr, |
| 105 | drop_pkt, |
| 106 | pkt_buf_gnt, |
| 107 | pkt_buf_size, |
| 108 | pkt_buf_addr, |
| 109 | orig_buf_addr, |
| 110 | pref_buf_used_num, |
| 111 | pkt_trans_len, |
| 112 | desp_curr_addr, |
| 113 | desp_curr_cnt, |
| 114 | desp_addr_not_valid, |
| 115 | buf_addr_not_valid, |
| 116 | rbr_addr_overflow, |
| 117 | desp_curr_cnt_overflow, |
| 118 | rbr_empty, |
| 119 | wred_drop_pkt, |
| 120 | rcr_drop_pkt, |
| 121 | rbr_drop_pkt, |
| 122 | chnl_sel_buf_en, |
| 123 | chnl_cache_parity_err |
| 124 | |
| 125 | ); |
| 126 | |
| 127 | input clk; |
| 128 | input reset; |
| 129 | input wred_enable; |
| 130 | input[15:0] random_num; |
| 131 | input[4:0] dma_chnl_grp_id; |
| 132 | input[1:0] dma_data_offset; |
| 133 | input full_header; |
| 134 | input dma_reset; |
| 135 | input dma_en; |
| 136 | input page_valid0; |
| 137 | input[31:0] addr_mask0; |
| 138 | input[31:0] comp_value0; |
| 139 | input[31:0] relo_value0; |
| 140 | input page_valid1; |
| 141 | input[31:0] addr_mask1; |
| 142 | input[31:0] comp_value1; |
| 143 | input[31:0] relo_value1; |
| 144 | input dma_fatal_err; |
| 145 | input[19:0] rx_log_page_hdl_reg; |
| 146 | input[31:0] rdc_red_param_reg; |
| 147 | input[53:0] rbr_cfig_a_reg; |
| 148 | input[10:0] rbr_cfig_b_reg; |
| 149 | input[15:0] rbr_kick_reg; |
| 150 | input rbr_cfig_a_reg_wenu; |
| 151 | input rbr_cfig_a_reg_wenl; |
| 152 | input rbr_kick_reg_wen; |
| 153 | input[13:0] muxed_pkt_len; |
| 154 | input[4:0] muxed_rdc_num_r; |
| 155 | input muxed_drop_pkt_r; |
| 156 | input muxed_s_event_r; |
| 157 | input sel_buf_en; |
| 158 | input pkt_req_cnt_e_done_mod; |
| 159 | input pkt_buf_done; |
| 160 | input is_hdr_wr_data; |
| 161 | input is_jmb1_wr_data; |
| 162 | input fetch_desp_req_sm; |
| 163 | input fetch_desp_pre_done; |
| 164 | input fetch_desp_done; |
| 165 | input fetch_desp_resp_vld; |
| 166 | input rdmc_resp_data_valid; |
| 167 | input[7:0] cache_start_addr; |
| 168 | input[7:0] cache_end_addr; |
| 169 | input cache_buf_rd_gnt; |
| 170 | input[131:0] cache_buf_rd_data; |
| 171 | input cache_parity_err; |
| 172 | input[15:0] rcr_curr_qlen; |
| 173 | input[7:0] shadw_curr_space_cnt; |
| 174 | |
| 175 | output chnl_sel_buf_en_r; |
| 176 | output desp_init_valid; |
| 177 | output fetch_desp_trig; |
| 178 | output[63:0] fetch_desp_addr; |
| 179 | output[4:0] fetch_desp_num; |
| 180 | output cache_read_req; |
| 181 | output[7:0] cache_rd_ptr; |
| 182 | output[7:0] cache_wr_ptr; |
| 183 | output drop_pkt; |
| 184 | output pkt_buf_gnt; |
| 185 | output[1:0] pkt_buf_size; |
| 186 | output[63:0] pkt_buf_addr; |
| 187 | output[35:0] orig_buf_addr; |
| 188 | output[1:0] pref_buf_used_num; |
| 189 | output[13:0] pkt_trans_len; |
| 190 | output[15:0] desp_curr_addr; |
| 191 | output[16:0] desp_curr_cnt; |
| 192 | output desp_addr_not_valid; |
| 193 | output buf_addr_not_valid; |
| 194 | output rbr_addr_overflow; |
| 195 | output desp_curr_cnt_overflow; |
| 196 | output rbr_empty; |
| 197 | output wred_drop_pkt; |
| 198 | output rcr_drop_pkt; |
| 199 | output rbr_drop_pkt; |
| 200 | output chnl_sel_buf_en; |
| 201 | output chnl_cache_parity_err; |
| 202 | |
| 203 | |
| 204 | reg rbr_cfig_a_reg_wenu_dly2; |
| 205 | reg rbr_cfig_a_reg_wenu_dly; |
| 206 | reg rbr_cfig_a_reg_wenl_dly2; |
| 207 | reg rbr_cfig_a_reg_wenl_dly; |
| 208 | |
| 209 | reg rbr_kick_reg_wen_dly; |
| 210 | reg[16:0] rbr_end_addr_r; |
| 211 | |
| 212 | |
| 213 | always @ (posedge clk) |
| 214 | if (reset) |
| 215 | rbr_cfig_a_reg_wenu_dly <= 1'b0; |
| 216 | else if (dma_reset) |
| 217 | rbr_cfig_a_reg_wenu_dly <= 1'b0; |
| 218 | else |
| 219 | rbr_cfig_a_reg_wenu_dly <= rbr_cfig_a_reg_wenu; |
| 220 | |
| 221 | always @ (posedge clk) |
| 222 | if (reset) |
| 223 | rbr_cfig_a_reg_wenu_dly2 <= 1'b0; |
| 224 | else if (dma_reset) |
| 225 | rbr_cfig_a_reg_wenu_dly2 <= 1'b0; |
| 226 | else |
| 227 | rbr_cfig_a_reg_wenu_dly2 <= rbr_cfig_a_reg_wenu_dly; |
| 228 | |
| 229 | always @ (posedge clk) |
| 230 | if (reset) |
| 231 | rbr_cfig_a_reg_wenl_dly <= 1'b0; |
| 232 | else if (dma_reset) |
| 233 | rbr_cfig_a_reg_wenl_dly <= 1'b0; |
| 234 | else |
| 235 | rbr_cfig_a_reg_wenl_dly <= rbr_cfig_a_reg_wenl; |
| 236 | |
| 237 | always @ (posedge clk) |
| 238 | if (reset) |
| 239 | rbr_cfig_a_reg_wenl_dly2 <= 1'b0; |
| 240 | else if (dma_reset) |
| 241 | rbr_cfig_a_reg_wenl_dly2 <= 1'b0; |
| 242 | else |
| 243 | rbr_cfig_a_reg_wenl_dly2 <= rbr_cfig_a_reg_wenl_dly; |
| 244 | |
| 245 | |
| 246 | always @ (posedge clk) |
| 247 | if (reset) |
| 248 | rbr_kick_reg_wen_dly <= 1'b0; |
| 249 | else if (dma_reset) |
| 250 | rbr_kick_reg_wen_dly <= 1'b0; |
| 251 | else |
| 252 | rbr_kick_reg_wen_dly <= rbr_kick_reg_wen; |
| 253 | |
| 254 | /**********************************************/ |
| 255 | //PIO programmed parameters |
| 256 | /**********************************************/ |
| 257 | wire[19:0] page_handle = rx_log_page_hdl_reg[19:0]; |
| 258 | wire[3:0] wred_window = rdc_red_param_reg[3:0]; |
| 259 | wire[11:0] wred_thresh = rdc_red_param_reg[15:4]; |
| 260 | wire[3:0] wred_window_syn = rdc_red_param_reg[19:16]; |
| 261 | wire[11:0] wred_thresh_syn = rdc_red_param_reg[31:20]; |
| 262 | |
| 263 | wire[15:0] rbr_max_len = rbr_cfig_a_reg[53:38]; |
| 264 | wire[25:0] rbr_base_addr = rbr_cfig_a_reg[37:12]; |
| 265 | wire[15:0] rbr_start_addr = {rbr_cfig_a_reg[11:0], 4'b0}; //4 bytes aligned |
| 266 | wire[15:0] rbr_end_addr = rbr_end_addr_r[15:0]; |
| 267 | wire rbr_addr_overflow = rbr_end_addr_r[16] & dma_en; |
| 268 | |
| 269 | wire[1:0] cache_buf_size_sel = rbr_cfig_b_reg[10:9]; //{00:4k, 01:8k, 10:16k,11:32k} |
| 270 | wire size2_config_valid = rbr_cfig_b_reg[8]; |
| 271 | wire[1:0] size2_buf_size_sel = rbr_cfig_b_reg[7:6]; //{00:2k, 01:4k, 10:8k,11:16k} |
| 272 | wire size1_config_valid = rbr_cfig_b_reg[5]; |
| 273 | wire[1:0] size1_buf_size_sel = rbr_cfig_b_reg[4:3]; //{00:1k, 01:2k, 10:4k,11:8k} |
| 274 | wire size0_config_valid = rbr_cfig_b_reg[2]; |
| 275 | wire[1:0] size0_buf_size_sel = rbr_cfig_b_reg[1:0]; //{00:256, 01:512, 10:1k,11:2k} |
| 276 | |
| 277 | |
| 278 | /************************/ |
| 279 | //descriptor manager |
| 280 | /************************/ |
| 281 | reg cal_addr_en; |
| 282 | reg[4:0] addr_cnt; // at most, fetch 16 addresses |
| 283 | reg[15:0] desp_curr_addr_tmp; |
| 284 | reg[15:0] desp_curr_addr; // always on 4 bytes boundry |
| 285 | reg[16:0] desp_curr_cnt; // bit[16] is overflow bit |
| 286 | reg inc_desp_curr_cnt; |
| 287 | reg desp_curr_cnt_overflow_r; |
| 288 | reg[15:0] desp_addr_avail_num; |
| 289 | |
| 290 | reg[7:0] cache_space_cnt; //support 255 lines, for most cases, it is 8 lines |
| 291 | reg[7:0] cache_buf_cnt; |
| 292 | reg inc_cache_buf_cnt; |
| 293 | reg cache_buf_empty; |
| 294 | reg cache_buf_full; |
| 295 | |
| 296 | reg[4:0] fetch_desp_num; |
| 297 | |
| 298 | wire[15:0] rbr_end_addr_sub = rbr_max_len[15:0] - 16'd1; |
| 299 | |
| 300 | always @ (posedge clk) |
| 301 | if (reset) |
| 302 | rbr_end_addr_r <= 17'b0; |
| 303 | else if (dma_reset) |
| 304 | rbr_end_addr_r <= 17'b0; |
| 305 | else if (rbr_cfig_a_reg_wenu_dly & (|rbr_max_len)) |
| 306 | rbr_end_addr_r <= {1'b0, rbr_end_addr_sub[15:0]}; |
| 307 | else if (rbr_cfig_a_reg_wenl_dly2 | rbr_cfig_a_reg_wenu_dly2) |
| 308 | rbr_end_addr_r <= {1'b0, rbr_start_addr[15:0]} + rbr_end_addr_r; |
| 309 | else |
| 310 | rbr_end_addr_r <= rbr_end_addr_r; |
| 311 | |
| 312 | always @ (posedge clk) |
| 313 | if (reset) |
| 314 | addr_cnt <= 5'b0; |
| 315 | else if (dma_reset) |
| 316 | addr_cnt <= 5'b0; |
| 317 | else if (cal_addr_en) |
| 318 | addr_cnt <= fetch_desp_num; |
| 319 | else if (addr_cnt != 5'b0) |
| 320 | addr_cnt <= addr_cnt - 5'd1; |
| 321 | else |
| 322 | addr_cnt <= addr_cnt; |
| 323 | |
| 324 | always @ (posedge clk) |
| 325 | if (reset) |
| 326 | desp_curr_addr_tmp <= 16'b0; |
| 327 | else if (dma_reset) |
| 328 | desp_curr_addr_tmp <= 16'b0; |
| 329 | else if ((addr_cnt != 5'b0) & (desp_curr_addr_tmp == rbr_end_addr)) |
| 330 | desp_curr_addr_tmp <= rbr_start_addr; |
| 331 | else if (addr_cnt != 5'b0) |
| 332 | desp_curr_addr_tmp <= desp_curr_addr_tmp + 16'd1; |
| 333 | else if (cal_addr_en) |
| 334 | desp_curr_addr_tmp <= desp_curr_addr; |
| 335 | else |
| 336 | desp_curr_addr_tmp <= desp_curr_addr_tmp; |
| 337 | |
| 338 | always @ (posedge clk) |
| 339 | if (reset) |
| 340 | desp_curr_addr <= 16'b0; |
| 341 | else if (rbr_cfig_a_reg_wenl_dly) |
| 342 | desp_curr_addr <= rbr_start_addr; |
| 343 | else if (fetch_desp_done) |
| 344 | desp_curr_addr <= desp_curr_addr_tmp; |
| 345 | else |
| 346 | desp_curr_addr <= desp_curr_addr; |
| 347 | |
| 348 | always @ (posedge clk) |
| 349 | if (reset) |
| 350 | desp_addr_avail_num <= 16'b0; |
| 351 | else if (dma_reset) |
| 352 | desp_addr_avail_num <= 16'b0; |
| 353 | else if (rbr_cfig_a_reg_wenu_dly) |
| 354 | desp_addr_avail_num <= rbr_max_len[15:0]; |
| 355 | else if (fetch_desp_pre_done) |
| 356 | desp_addr_avail_num <= rbr_end_addr[15:0] - desp_curr_addr_tmp[15:0]; |
| 357 | else if (fetch_desp_done) |
| 358 | desp_addr_avail_num <= desp_addr_avail_num + 16'd1; |
| 359 | else |
| 360 | desp_addr_avail_num <= desp_addr_avail_num; |
| 361 | |
| 362 | |
| 363 | always @ (posedge clk) |
| 364 | if (reset) |
| 365 | inc_desp_curr_cnt <= 1'b0; |
| 366 | else if (dma_reset) |
| 367 | inc_desp_curr_cnt <= 1'b0; |
| 368 | else if (rbr_kick_reg_wen & !fetch_desp_pre_done | rbr_kick_reg_wen_dly & !inc_desp_curr_cnt) |
| 369 | inc_desp_curr_cnt <= 1'b1; |
| 370 | else |
| 371 | inc_desp_curr_cnt <= 1'b0; |
| 372 | |
| 373 | always @ (posedge clk) |
| 374 | if (reset) |
| 375 | desp_curr_cnt <= 17'b0; //pio read only |
| 376 | else if (dma_reset) |
| 377 | desp_curr_cnt <= 17'b0; |
| 378 | else if (desp_curr_cnt[16] | desp_curr_cnt_overflow_r) |
| 379 | desp_curr_cnt <= desp_curr_cnt; |
| 380 | else if (inc_desp_curr_cnt) |
| 381 | desp_curr_cnt <= desp_curr_cnt + {1'b0, rbr_kick_reg[15:0]}; // bit[16] is overflow bit |
| 382 | else if (fetch_desp_done) |
| 383 | desp_curr_cnt <= desp_curr_cnt - {12'b0, fetch_desp_num[4:0]}; |
| 384 | else |
| 385 | desp_curr_cnt <= desp_curr_cnt; |
| 386 | |
| 387 | |
| 388 | wire desp_curr_cnt_overflow = (desp_curr_cnt > {1'b0, rbr_max_len}) & dma_en; |
| 389 | |
| 390 | always @ (posedge clk) |
| 391 | if (reset) |
| 392 | desp_curr_cnt_overflow_r <= 1'b0; |
| 393 | else if (dma_reset) |
| 394 | desp_curr_cnt_overflow_r <= 1'b0; |
| 395 | else if (desp_curr_cnt_overflow) |
| 396 | desp_curr_cnt_overflow_r <= 1'b1; |
| 397 | else |
| 398 | desp_curr_cnt_overflow_r <= desp_curr_cnt_overflow_r; |
| 399 | |
| 400 | /*****************************/ |
| 401 | //request descriptor |
| 402 | /*****************************/ |
| 403 | reg[31:0] desp_relo_addr_r; |
| 404 | wire rbr_empty = (|cache_space_cnt[7:2]) & !(|desp_curr_cnt[15:0]) & dma_en; |
| 405 | wire fetch_desp_trig = (cache_space_cnt[7:0] > 8'd4) & (|desp_curr_cnt[15:0]); |
| 406 | wire[4:0] desp_cnt_avail_num = (|desp_curr_cnt[15:4]) ? 5'b10000 : desp_curr_cnt[4:0]; |
| 407 | wire[4:0] desp_addr_avail_num1 = (|desp_addr_avail_num[15:4]) ? 5'b10000 : desp_addr_avail_num[4:0]; |
| 408 | wire[4:0] fetch_desp_min_num = (desp_addr_avail_num1[4:0] > desp_cnt_avail_num[4:0]) ? desp_cnt_avail_num[4:0] : |
| 409 | desp_addr_avail_num1[4:0]; |
| 410 | |
| 411 | wire[43:0] desp_full_addr = {rbr_base_addr[25:0], desp_curr_addr[15:0], 2'b0}; |
| 412 | |
| 413 | wire desp_addr_valid0 = ((desp_full_addr[43:12] & addr_mask0) == (comp_value0 & addr_mask0)) & page_valid0; |
| 414 | wire desp_addr_valid1 = ((desp_full_addr[43:12] & addr_mask1) == (comp_value1 & addr_mask1)) & page_valid1; |
| 415 | |
| 416 | wire[31:0] desp_relo_addr0 = (desp_full_addr[43:12] & ~addr_mask0) | (relo_value0 & addr_mask0); |
| 417 | wire[31:0] desp_relo_addr1 = (desp_full_addr[43:12] & ~addr_mask1) | (relo_value1 & addr_mask1); |
| 418 | |
| 419 | wire[31:0] desp_relo_addr = desp_addr_valid0 ? desp_relo_addr0 : desp_relo_addr1; |
| 420 | wire[63:0] fetch_desp_addr = {page_handle[19:0], desp_relo_addr_r[31:0], desp_full_addr[11:0]}; |
| 421 | |
| 422 | wire desp_addr_not_valid = !(desp_addr_valid0 | desp_addr_valid1) & dma_en; |
| 423 | wire desp_init_valid = (desp_addr_valid0 | desp_addr_valid1) & dma_en; |
| 424 | |
| 425 | |
| 426 | always @ (posedge clk) |
| 427 | if (reset) |
| 428 | cal_addr_en <= 1'b0; |
| 429 | else |
| 430 | cal_addr_en <= fetch_desp_req_sm; |
| 431 | |
| 432 | always @ (posedge clk) |
| 433 | if (reset) |
| 434 | desp_relo_addr_r <= 32'b0; |
| 435 | else if (fetch_desp_req_sm) |
| 436 | desp_relo_addr_r <= desp_relo_addr; |
| 437 | else |
| 438 | desp_relo_addr_r <= desp_relo_addr_r; |
| 439 | |
| 440 | always @ (posedge clk) |
| 441 | if (reset) |
| 442 | fetch_desp_num <= 5'b0; |
| 443 | else if (fetch_desp_req_sm) |
| 444 | fetch_desp_num <= fetch_desp_min_num; |
| 445 | else |
| 446 | fetch_desp_num <= fetch_desp_num; |
| 447 | |
| 448 | |
| 449 | /******************************/ |
| 450 | //buffer size decode |
| 451 | /******************************/ |
| 452 | reg[7:0] cache_buf_size_dec; |
| 453 | reg[7:0] size2_buf_size_dec; |
| 454 | reg[7:0] size1_buf_size_dec; |
| 455 | reg[7:0] size0_buf_size_dec; |
| 456 | reg[7:0] size2_buf_num_dec; |
| 457 | reg[7:0] size1_buf_num_dec; |
| 458 | reg[7:0] size0_buf_num_dec; |
| 459 | reg[7:0] cache_buf_size_pre; |
| 460 | reg[9:0] cache_buf_size1_pre; //one cache - data_offset |
| 461 | reg[10:0] cache_buf_size2_pre; //for two cache buf size - 1 data_offset |
| 462 | reg[10:0] cache_buf_size3_pre; //for three cache buf size - 2 data_offset |
| 463 | reg[7:0] size2_buf_size_pre; |
| 464 | reg[7:0] size1_buf_size_pre; |
| 465 | reg[7:0] size0_buf_size_pre; |
| 466 | reg[7:0] start_size2_buf_num; |
| 467 | reg[7:0] start_size1_buf_num; |
| 468 | reg[7:0] start_size0_buf_num; |
| 469 | |
| 470 | |
| 471 | wire[7:0] byte_offset = (dma_data_offset[1:0] == 2'b01) ? 8'd64 : |
| 472 | (dma_data_offset[1:0] == 2'b10) ? 8'd128 : 8'd0; |
| 473 | |
| 474 | |
| 475 | always @(cache_buf_size_sel) |
| 476 | case(cache_buf_size_sel) //synopsys parallel_case full_case |
| 477 | 2'd0: cache_buf_size_dec = 8'h10; //4k |
| 478 | 2'd1: cache_buf_size_dec = 8'h20; //8k |
| 479 | 2'd2: cache_buf_size_dec = 8'h40; //16k |
| 480 | 2'd3: cache_buf_size_dec = 8'h80; //32k |
| 481 | default: cache_buf_size_dec = 8'h10; |
| 482 | endcase |
| 483 | |
| 484 | always @(size2_buf_size_sel) |
| 485 | case(size2_buf_size_sel) //synopsys parallel_case full_case |
| 486 | 2'd0: size2_buf_size_dec = 8'h08; //2k |
| 487 | 2'd1: size2_buf_size_dec = 8'h10; //4k |
| 488 | 2'd2: size2_buf_size_dec = 8'h20; //8k |
| 489 | 2'd3: size2_buf_size_dec = 8'h40; //16k |
| 490 | default: size2_buf_size_dec = 8'h08; |
| 491 | endcase |
| 492 | |
| 493 | always @(size1_buf_size_sel) |
| 494 | case(size1_buf_size_sel) //synopsys parallel_case full_case |
| 495 | 2'd0: size1_buf_size_dec = 8'h04; //1k |
| 496 | 2'd1: size1_buf_size_dec = 8'h08; //2k |
| 497 | 2'd2: size1_buf_size_dec = 8'h10; //4k |
| 498 | 2'd3: size1_buf_size_dec = 8'h20; //8k |
| 499 | default: size1_buf_size_dec = 8'h04; |
| 500 | endcase |
| 501 | |
| 502 | always @(size0_buf_size_sel) |
| 503 | case(size0_buf_size_sel) //synopsys parallel_case full_case |
| 504 | 2'd0: size0_buf_size_dec = 8'h01; //256 |
| 505 | 2'd1: size0_buf_size_dec = 8'h02; //512 |
| 506 | 2'd2: size0_buf_size_dec = 8'h04; //1k |
| 507 | 2'd3: size0_buf_size_dec = 8'h08; //2k |
| 508 | default: size0_buf_size_dec = 8'h01; |
| 509 | endcase |
| 510 | |
| 511 | |
| 512 | always @(cache_buf_size_sel or size2_buf_size_sel) |
| 513 | case(cache_buf_size_sel) //synopsys parallel_case full_case |
| 514 | 2'b00: begin |
| 515 | case(size2_buf_size_sel) //synopsys parallel_case full_case |
| 516 | 2'b00: size2_buf_num_dec = 8'd2; |
| 517 | 2'b01: size2_buf_num_dec = 8'd1; |
| 518 | 2'b10: size2_buf_num_dec = 8'd0; |
| 519 | 2'b11: size2_buf_num_dec = 8'd0; |
| 520 | default:size2_buf_num_dec = 8'd0; |
| 521 | endcase |
| 522 | end |
| 523 | 2'b01: begin |
| 524 | case(size2_buf_size_sel) //synopsys parallel_case full_case |
| 525 | 2'b00: size2_buf_num_dec = 8'd4; |
| 526 | 2'b01: size2_buf_num_dec = 8'd2; |
| 527 | 2'b10: size2_buf_num_dec = 8'd1; |
| 528 | 2'b11: size2_buf_num_dec = 8'd0; |
| 529 | default:size2_buf_num_dec = 8'd0; |
| 530 | endcase |
| 531 | end |
| 532 | 2'b10: begin |
| 533 | case(size2_buf_size_sel) //synopsys parallel_case full_case |
| 534 | 2'b00: size2_buf_num_dec = 8'd8; |
| 535 | 2'b01: size2_buf_num_dec = 8'd4; |
| 536 | 2'b10: size2_buf_num_dec = 8'd2; |
| 537 | 2'b11: size2_buf_num_dec = 8'd1; |
| 538 | default:size2_buf_num_dec = 8'd1; |
| 539 | endcase |
| 540 | end |
| 541 | 2'b11: begin |
| 542 | case(size2_buf_size_sel) //synopsys parallel_case full_case |
| 543 | 2'b00: size2_buf_num_dec = 8'd16; |
| 544 | 2'b01: size2_buf_num_dec = 8'd8; |
| 545 | 2'b10: size2_buf_num_dec = 8'd4; |
| 546 | 2'b11: size2_buf_num_dec = 8'd2; |
| 547 | default:size2_buf_num_dec = 8'd2; |
| 548 | endcase |
| 549 | end |
| 550 | default: size2_buf_num_dec = 8'd0; |
| 551 | endcase |
| 552 | |
| 553 | always @(cache_buf_size_sel or size1_buf_size_sel) |
| 554 | case(cache_buf_size_sel) //synopsys parallel_case full_case |
| 555 | 2'b00: begin |
| 556 | case(size1_buf_size_sel) //synopsys parallel_case full_case |
| 557 | 2'b00: size1_buf_num_dec = 8'd4; |
| 558 | 2'b01: size1_buf_num_dec = 8'd2; |
| 559 | 2'b10: size1_buf_num_dec = 8'd1; |
| 560 | 2'b11: size1_buf_num_dec = 8'd0; |
| 561 | default:size1_buf_num_dec = 8'd0; |
| 562 | endcase |
| 563 | end |
| 564 | 2'b01: begin |
| 565 | case(size1_buf_size_sel) //synopsys parallel_case full_case |
| 566 | 2'b00: size1_buf_num_dec = 8'd8; |
| 567 | 2'b01: size1_buf_num_dec = 8'd4; |
| 568 | 2'b10: size1_buf_num_dec = 8'd2; |
| 569 | 2'b11: size1_buf_num_dec = 8'd1; |
| 570 | default:size1_buf_num_dec = 8'd1; |
| 571 | endcase |
| 572 | end |
| 573 | 2'b10: begin |
| 574 | case(size1_buf_size_sel) //synopsys parallel_case full_case |
| 575 | 2'b00: size1_buf_num_dec = 8'd16; |
| 576 | 2'b01: size1_buf_num_dec = 8'd8; |
| 577 | 2'b10: size1_buf_num_dec = 8'd4; |
| 578 | 2'b11: size1_buf_num_dec = 8'd2; |
| 579 | default:size1_buf_num_dec = 8'd2; |
| 580 | endcase |
| 581 | end |
| 582 | 2'b11: begin |
| 583 | case(size1_buf_size_sel) //synopsys parallel_case full_case |
| 584 | 2'b00: size1_buf_num_dec = 8'd32; |
| 585 | 2'b01: size1_buf_num_dec = 8'd16; |
| 586 | 2'b10: size1_buf_num_dec = 8'd8; |
| 587 | 2'b11: size1_buf_num_dec = 8'd4; |
| 588 | default:size1_buf_num_dec = 8'd4; |
| 589 | endcase |
| 590 | end |
| 591 | default: size1_buf_num_dec = 8'd0; |
| 592 | endcase |
| 593 | |
| 594 | always @(cache_buf_size_sel or size0_buf_size_sel) |
| 595 | case(cache_buf_size_sel) //synopsys parallel_case full_case |
| 596 | 2'b00: begin |
| 597 | case(size0_buf_size_sel) //synopsys parallel_case full_case |
| 598 | 2'b00: size0_buf_num_dec = 8'd16; |
| 599 | 2'b01: size0_buf_num_dec = 8'd8; |
| 600 | 2'b10: size0_buf_num_dec = 8'd4; |
| 601 | 2'b11: size0_buf_num_dec = 8'd2; |
| 602 | default:size0_buf_num_dec = 8'd2; |
| 603 | endcase |
| 604 | end |
| 605 | 2'b01: begin |
| 606 | case(size0_buf_size_sel) //synopsys parallel_case full_case |
| 607 | 2'b00: size0_buf_num_dec = 8'd32; |
| 608 | 2'b01: size0_buf_num_dec = 8'd16; |
| 609 | 2'b10: size0_buf_num_dec = 8'd8; |
| 610 | 2'b11: size0_buf_num_dec = 8'd4; |
| 611 | default:size0_buf_num_dec = 8'd4; |
| 612 | endcase |
| 613 | end |
| 614 | 2'b10: begin |
| 615 | case(size0_buf_size_sel) //synopsys parallel_case full_case |
| 616 | 2'b00: size0_buf_num_dec = 8'd64; |
| 617 | 2'b01: size0_buf_num_dec = 8'd32; |
| 618 | 2'b10: size0_buf_num_dec = 8'd16; |
| 619 | 2'b11: size0_buf_num_dec = 8'd8; |
| 620 | default:size0_buf_num_dec = 8'd8; |
| 621 | endcase |
| 622 | end |
| 623 | 2'b11: begin |
| 624 | case(size0_buf_size_sel) //synopsys parallel_case full_case |
| 625 | 2'b00: size0_buf_num_dec = 8'd128; |
| 626 | 2'b01: size0_buf_num_dec = 8'd64; |
| 627 | 2'b10: size0_buf_num_dec = 8'd32; |
| 628 | 2'b11: size0_buf_num_dec = 8'd16; |
| 629 | default:size0_buf_num_dec = 8'd16; |
| 630 | endcase |
| 631 | end |
| 632 | default: size0_buf_num_dec = 8'd0; |
| 633 | endcase |
| 634 | |
| 635 | |
| 636 | always @ (posedge clk) |
| 637 | if (reset) |
| 638 | cache_buf_size_pre <= 8'b0; |
| 639 | else |
| 640 | cache_buf_size_pre <= cache_buf_size_dec; |
| 641 | |
| 642 | wire[15:0] cache_buf_size = {cache_buf_size_pre[7:0], 8'b0}; |
| 643 | wire[9:0] cache_buf_size1_in = {cache_buf_size_dec[7:0], 2'b0} - {8'b0, byte_offset[7:6]}; |
| 644 | |
| 645 | always @ (posedge clk) |
| 646 | if (reset) |
| 647 | cache_buf_size1_pre <= 10'b0; |
| 648 | else |
| 649 | cache_buf_size1_pre <= cache_buf_size1_in; |
| 650 | |
| 651 | //wire[15:0] cache_buf_size1 = {cache_buf_size1_pre[9:0], 6'b0}; |
| 652 | wire[13:0] cache_buf_size1 = {cache_buf_size1_pre[7:0], 6'b0}; |
| 653 | wire[10:0] cache_buf_size2_in = {cache_buf_size_pre[7:0], 3'b0} - {9'b0, byte_offset[7:6]}; |
| 654 | |
| 655 | always @ (posedge clk) |
| 656 | if (reset) |
| 657 | cache_buf_size2_pre <= 11'b0; |
| 658 | else |
| 659 | cache_buf_size2_pre <= cache_buf_size2_in; |
| 660 | |
| 661 | |
| 662 | //wire[16:0] cache_buf_size2 = {cache_buf_size2_pre[10:0], 6'b0}; |
| 663 | wire[15:0] cache_buf_size2 = {cache_buf_size2_pre[9:0], 6'b0}; |
| 664 | wire[10:0] cache_buf_size3_in = cache_buf_size2_pre[10:0] + {1'b0, cache_buf_size1_pre[9:0]}; |
| 665 | |
| 666 | always @ (posedge clk) |
| 667 | if (reset) |
| 668 | cache_buf_size3_pre <= 11'b0; |
| 669 | else |
| 670 | cache_buf_size3_pre <= cache_buf_size3_in; |
| 671 | |
| 672 | wire[16:0] cache_buf_size3 = {cache_buf_size3_pre[10:0], 6'b0}; |
| 673 | |
| 674 | |
| 675 | always @ (posedge clk) |
| 676 | if (reset) |
| 677 | size2_buf_size_pre <= 8'b0; |
| 678 | else |
| 679 | size2_buf_size_pre <= size2_buf_size_dec; |
| 680 | |
| 681 | wire[15:0] size2_buf_size = {size2_buf_size_pre[7:0], 8'b0}; |
| 682 | |
| 683 | always @ (posedge clk) |
| 684 | if (reset) |
| 685 | size1_buf_size_pre <= 8'b0; |
| 686 | else |
| 687 | size1_buf_size_pre <= size1_buf_size_dec; |
| 688 | |
| 689 | wire[15:0] size1_buf_size = {size1_buf_size_pre[7:0], 8'b0}; |
| 690 | |
| 691 | always @ (posedge clk) |
| 692 | if (reset) |
| 693 | size0_buf_size_pre <= 8'b0; |
| 694 | else |
| 695 | size0_buf_size_pre <= size0_buf_size_dec; |
| 696 | |
| 697 | wire[15:0] size0_buf_size = {size0_buf_size_pre[7:0], 8'b0}; |
| 698 | |
| 699 | |
| 700 | always @ (posedge clk) |
| 701 | if (reset) |
| 702 | start_size2_buf_num <= 8'b0; |
| 703 | else |
| 704 | start_size2_buf_num <= size2_buf_num_dec; |
| 705 | |
| 706 | |
| 707 | always @ (posedge clk) |
| 708 | if (reset) |
| 709 | start_size1_buf_num <= 8'b0; |
| 710 | else |
| 711 | start_size1_buf_num <= size1_buf_num_dec; |
| 712 | |
| 713 | always @ (posedge clk) |
| 714 | if (reset) |
| 715 | start_size0_buf_num <= 8'b0; |
| 716 | else |
| 717 | start_size0_buf_num <= size0_buf_num_dec; |
| 718 | |
| 719 | |
| 720 | /*********************************/ |
| 721 | // cache memory manager |
| 722 | /*********************************/ |
| 723 | reg cache_buf_rd_gnt_dly1; |
| 724 | reg cache_buf_rd_gnt_dly2; |
| 725 | reg cache_buf_rd_gnt_dly3; |
| 726 | |
| 727 | reg[7:0] cache_wr_ptr; |
| 728 | reg[7:0] cache_rd_ptr; |
| 729 | reg[2:0] cache_rd_cnt; //at most read 4 addresses |
| 730 | |
| 731 | wire cache_buf_wr_gnt = fetch_desp_resp_vld & rdmc_resp_data_valid; |
| 732 | wire last_rd_ptr = (cache_space_cnt == `CACHE_LEN_SUB1); |
| 733 | wire last_wr_ptr = (cache_space_cnt == 8'd1); |
| 734 | |
| 735 | wire last_wr_addr = (cache_wr_ptr == cache_end_addr); |
| 736 | wire last_rd_addr = (cache_rd_ptr == cache_end_addr); |
| 737 | |
| 738 | always @ (posedge clk) |
| 739 | if (reset) |
| 740 | cache_wr_ptr <= cache_start_addr; |
| 741 | else if (dma_reset) |
| 742 | cache_wr_ptr <= cache_start_addr; |
| 743 | else if (cache_buf_wr_gnt & last_wr_addr) |
| 744 | cache_wr_ptr <= cache_start_addr; |
| 745 | else if (cache_buf_wr_gnt) |
| 746 | cache_wr_ptr <= cache_wr_ptr + 8'd1; |
| 747 | else |
| 748 | cache_wr_ptr <= cache_wr_ptr; |
| 749 | |
| 750 | always @ (posedge clk) |
| 751 | if (reset) |
| 752 | cache_rd_ptr <= cache_start_addr; |
| 753 | else if (dma_reset) |
| 754 | cache_rd_ptr <= cache_start_addr; |
| 755 | else if (cache_buf_rd_gnt_dly3 & last_rd_addr) |
| 756 | cache_rd_ptr <= cache_start_addr; |
| 757 | else if (cache_buf_rd_gnt_dly3) |
| 758 | cache_rd_ptr <= cache_rd_ptr + 8'd1; |
| 759 | else |
| 760 | cache_rd_ptr <= cache_rd_ptr; |
| 761 | |
| 762 | always @ (posedge clk) |
| 763 | if (reset) |
| 764 | cache_buf_empty <= 1'b1; |
| 765 | else if (dma_reset) |
| 766 | cache_buf_empty <= 1'b1; |
| 767 | else if (cache_buf_wr_gnt) |
| 768 | cache_buf_empty <= 1'b0; |
| 769 | else if (cache_buf_rd_gnt_dly3 & last_rd_ptr) |
| 770 | cache_buf_empty <= 1'b1; |
| 771 | else |
| 772 | cache_buf_empty <= cache_buf_empty; |
| 773 | |
| 774 | |
| 775 | always @ (posedge clk) |
| 776 | if (reset) |
| 777 | cache_buf_full <= 1'b0; |
| 778 | else if (dma_reset) |
| 779 | cache_buf_full <= 1'b0; |
| 780 | else if (cache_buf_rd_gnt_dly3) |
| 781 | cache_buf_full <= 1'b0; |
| 782 | else if (cache_buf_wr_gnt & last_wr_ptr) |
| 783 | cache_buf_full <= 1'b1; |
| 784 | else |
| 785 | cache_buf_full <= cache_buf_full; |
| 786 | |
| 787 | always @ (posedge clk) |
| 788 | if (reset) |
| 789 | cache_space_cnt <= `CACHE_LEN; |
| 790 | else if (dma_reset) |
| 791 | cache_space_cnt <= `CACHE_LEN; |
| 792 | else if (cache_buf_wr_gnt & cache_buf_rd_gnt_dly3) |
| 793 | cache_space_cnt <= cache_space_cnt; |
| 794 | else if (cache_buf_wr_gnt) |
| 795 | cache_space_cnt <= cache_space_cnt - 8'd1; |
| 796 | else if (cache_buf_rd_gnt_dly3) |
| 797 | cache_space_cnt <= cache_space_cnt + 8'd1; |
| 798 | else |
| 799 | cache_space_cnt <= cache_space_cnt; |
| 800 | |
| 801 | |
| 802 | wire[3:0] cache_rd_valid_bits = cache_buf_rd_data[131:128]; |
| 803 | |
| 804 | always @ (posedge clk) |
| 805 | if (reset) |
| 806 | cache_buf_rd_gnt_dly1 <= 1'b0; |
| 807 | else if (dma_reset) |
| 808 | cache_buf_rd_gnt_dly1 <= 1'b0; |
| 809 | else |
| 810 | cache_buf_rd_gnt_dly1 <= cache_buf_rd_gnt; |
| 811 | |
| 812 | always @ (posedge clk) |
| 813 | if (reset) |
| 814 | begin |
| 815 | cache_buf_rd_gnt_dly2 <= 1'b0; |
| 816 | cache_buf_rd_gnt_dly3 <= 1'b0; |
| 817 | end |
| 818 | else |
| 819 | begin |
| 820 | cache_buf_rd_gnt_dly2 <= cache_buf_rd_gnt_dly1; |
| 821 | cache_buf_rd_gnt_dly3 <= cache_buf_rd_gnt_dly2; |
| 822 | end |
| 823 | |
| 824 | always @ (cache_rd_valid_bits) |
| 825 | begin |
| 826 | |
| 827 | case (cache_rd_valid_bits) //synopsys parallel_case full_case |
| 828 | |
| 829 | 4'b0001, 4'b0010, 4'b0100, 4'b1000: |
| 830 | cache_rd_cnt = 3'b001; |
| 831 | 4'b0011, 4'b0110, 4'b1100: |
| 832 | cache_rd_cnt = 3'b010; |
| 833 | 4'b0111, 4'b1110: |
| 834 | cache_rd_cnt = 3'b011; |
| 835 | 4'b1111: |
| 836 | cache_rd_cnt = 3'b100; |
| 837 | default: |
| 838 | cache_rd_cnt = 3'b000; |
| 839 | endcase |
| 840 | end |
| 841 | |
| 842 | always @ (posedge clk) |
| 843 | if (reset) |
| 844 | inc_cache_buf_cnt <= 1'b0; |
| 845 | else if (dma_reset) |
| 846 | inc_cache_buf_cnt <= 1'b0; |
| 847 | else if (fetch_desp_pre_done & cache_buf_rd_gnt_dly3) |
| 848 | inc_cache_buf_cnt <= 1'b1; |
| 849 | else |
| 850 | inc_cache_buf_cnt <= 1'b0; |
| 851 | |
| 852 | always @ (posedge clk) |
| 853 | if (reset) |
| 854 | cache_buf_cnt <= 8'b0; |
| 855 | else if (dma_reset) |
| 856 | cache_buf_cnt <= 8'b0; |
| 857 | else if (fetch_desp_pre_done & !cache_buf_rd_gnt_dly3 | inc_cache_buf_cnt) |
| 858 | cache_buf_cnt <= cache_buf_cnt + {3'b0, fetch_desp_num[4:0]}; |
| 859 | else if (cache_buf_rd_gnt_dly3) |
| 860 | cache_buf_cnt <= cache_buf_cnt - {5'b0, cache_rd_cnt}; |
| 861 | else |
| 862 | cache_buf_cnt <= cache_buf_cnt; |
| 863 | |
| 864 | |
| 865 | /************************/ |
| 866 | //Discard pkt |
| 867 | /************************/ |
| 868 | reg chnl_sel_buf_en; |
| 869 | reg sel_buf_en_r; //same as chnl_sel_buf_en |
| 870 | reg drop_pkt; |
| 871 | reg wred_drop_pkt; |
| 872 | |
| 873 | wire buf_addr_not_valid; |
| 874 | wire rbr_drop_pkt; |
| 875 | wire rcr_drop_pkt; |
| 876 | wire shadow_not_empty = (|shadw_curr_space_cnt); |
| 877 | wire shadow_not_e_empty = (|shadw_curr_space_cnt[7:2]) | (&shadw_curr_space_cnt[1:0]); |
| 878 | |
| 879 | wire is_drop_pkt_tmp = wred_drop_pkt | rcr_drop_pkt | muxed_drop_pkt_r | dma_fatal_err | !dma_en; |
| 880 | wire sel_buf_enabled_tmp = chnl_sel_buf_en & !is_drop_pkt_tmp; |
| 881 | |
| 882 | wire is_drop_pkt = is_drop_pkt_tmp | rbr_drop_pkt; |
| 883 | wire sel_buf_enabled = chnl_sel_buf_en & !is_drop_pkt; |
| 884 | |
| 885 | always @ (posedge clk) |
| 886 | if (reset) |
| 887 | chnl_sel_buf_en <= 1'b0; |
| 888 | else if (dma_reset) |
| 889 | chnl_sel_buf_en <= 1'b0; |
| 890 | else |
| 891 | chnl_sel_buf_en <= sel_buf_en & (muxed_rdc_num_r == dma_chnl_grp_id); |
| 892 | |
| 893 | always @ (posedge clk) |
| 894 | if (reset) |
| 895 | sel_buf_en_r <= 1'b0; |
| 896 | else if (dma_reset) |
| 897 | sel_buf_en_r <= 1'b0; |
| 898 | else |
| 899 | sel_buf_en_r <= sel_buf_en & (muxed_rdc_num_r == dma_chnl_grp_id); |
| 900 | |
| 901 | always @ (posedge clk) |
| 902 | if (reset) |
| 903 | drop_pkt <= 1'b0; |
| 904 | else if (dma_reset) |
| 905 | drop_pkt <= 1'b0; |
| 906 | else if (chnl_sel_buf_en) |
| 907 | drop_pkt <= (is_drop_pkt | buf_addr_not_valid); |
| 908 | else |
| 909 | drop_pkt <= 1'b0; |
| 910 | |
| 911 | /*********************************/ |
| 912 | // prefetch buffer manager |
| 913 | /*********************************/ |
| 914 | reg[3:0] use_pref_buf; //pkt use pref buf, in stage2 |
| 915 | reg[3:0] unload_pref_buf; //size load pref buf, not in stage2 |
| 916 | reg is_last_pref_buf; |
| 917 | reg d_pref_buf_valid; |
| 918 | reg t_pref_buf_valid; |
| 919 | |
| 920 | reg[127:0] pref_buf_addr_reg; |
| 921 | reg pref_buf0_valid; |
| 922 | reg pref_buf1_valid; |
| 923 | reg pref_buf2_valid; |
| 924 | reg pref_buf3_valid; |
| 925 | reg cache_read_req; |
| 926 | |
| 927 | reg size0_buf_req; |
| 928 | reg size1_buf_req; |
| 929 | reg size2_buf_req; |
| 930 | |
| 931 | reg[31:0] pref_buf_addr0; |
| 932 | reg[31:0] pref_buf_addr1; |
| 933 | reg[31:0] pref_buf_addr2; |
| 934 | reg[31:0] pref_buf_addr3; |
| 935 | |
| 936 | |
| 937 | wire get_pkt_pref_buf; |
| 938 | wire pkt_pref_buf_in_use; |
| 939 | |
| 940 | wire chnl_cache_parity_err = cache_buf_rd_gnt_dly3 & cache_parity_err; |
| 941 | wire load_pref_buf = cache_buf_rd_gnt_dly3 & !cache_parity_err; |
| 942 | |
| 943 | wire[31:0] pref_buf_addr_tmp0 = cache_buf_rd_data[31:0]; |
| 944 | wire[31:0] pref_buf_addr_tmp1 = cache_buf_rd_data[63:32]; |
| 945 | wire[31:0] pref_buf_addr_tmp2 = cache_buf_rd_data[95:64]; |
| 946 | wire[31:0] pref_buf_addr_tmp3 = cache_buf_rd_data[127:96]; |
| 947 | |
| 948 | always @(cache_buf_size_sel or |
| 949 | pref_buf_addr_tmp0 or pref_buf_addr_tmp1 or |
| 950 | pref_buf_addr_tmp2 or pref_buf_addr_tmp3) |
| 951 | |
| 952 | case(cache_buf_size_sel) //synopsys parallel_case full_case |
| 953 | 2'b00: begin |
| 954 | pref_buf_addr0 = pref_buf_addr_tmp0[31:0]; |
| 955 | pref_buf_addr1 = pref_buf_addr_tmp1[31:0]; |
| 956 | pref_buf_addr2 = pref_buf_addr_tmp2[31:0]; |
| 957 | pref_buf_addr3 = pref_buf_addr_tmp3[31:0]; |
| 958 | end |
| 959 | 2'b01: begin |
| 960 | pref_buf_addr0 = {pref_buf_addr_tmp0[31:1], 1'b0}; |
| 961 | pref_buf_addr1 = {pref_buf_addr_tmp1[31:1], 1'b0}; |
| 962 | pref_buf_addr2 = {pref_buf_addr_tmp2[31:1], 1'b0}; |
| 963 | pref_buf_addr3 = {pref_buf_addr_tmp3[31:1], 1'b0}; |
| 964 | end |
| 965 | 2'b10: begin |
| 966 | pref_buf_addr0 = {pref_buf_addr_tmp0[31:2], 2'b0}; |
| 967 | pref_buf_addr1 = {pref_buf_addr_tmp1[31:2], 2'b0}; |
| 968 | pref_buf_addr2 = {pref_buf_addr_tmp2[31:2], 2'b0}; |
| 969 | pref_buf_addr3 = {pref_buf_addr_tmp3[31:2], 2'b0}; |
| 970 | end |
| 971 | 2'b11: begin |
| 972 | pref_buf_addr0 = {pref_buf_addr_tmp0[31:3], 3'b0}; |
| 973 | pref_buf_addr1 = {pref_buf_addr_tmp1[31:3], 3'b0}; |
| 974 | pref_buf_addr2 = {pref_buf_addr_tmp2[31:3], 3'b0}; |
| 975 | pref_buf_addr3 = {pref_buf_addr_tmp3[31:3], 3'b0}; |
| 976 | end |
| 977 | default: begin |
| 978 | pref_buf_addr0 = pref_buf_addr_tmp0[31:0]; |
| 979 | pref_buf_addr1 = pref_buf_addr_tmp1[31:0]; |
| 980 | pref_buf_addr2 = pref_buf_addr_tmp2[31:0]; |
| 981 | pref_buf_addr3 = pref_buf_addr_tmp3[31:0]; |
| 982 | end |
| 983 | endcase |
| 984 | |
| 985 | |
| 986 | always @ (posedge clk) |
| 987 | if (reset) |
| 988 | pref_buf_addr_reg <= 128'b0; |
| 989 | else if (load_pref_buf) |
| 990 | pref_buf_addr_reg <= {pref_buf_addr3, pref_buf_addr2, pref_buf_addr1, pref_buf_addr0}; |
| 991 | else |
| 992 | pref_buf_addr_reg <= pref_buf_addr_reg; |
| 993 | |
| 994 | always @ (posedge clk) |
| 995 | if (reset) |
| 996 | pref_buf0_valid <= 1'b0; |
| 997 | else if (dma_reset) |
| 998 | pref_buf0_valid <= 1'b0; |
| 999 | else if (unload_pref_buf[0] | get_pkt_pref_buf & use_pref_buf[0]) |
| 1000 | pref_buf0_valid <= 1'b0; |
| 1001 | else if (load_pref_buf) |
| 1002 | pref_buf0_valid <= cache_rd_valid_bits[0]; |
| 1003 | else |
| 1004 | pref_buf0_valid <= pref_buf0_valid; |
| 1005 | |
| 1006 | always @ (posedge clk) |
| 1007 | if (reset) |
| 1008 | pref_buf1_valid <= 1'b0; |
| 1009 | else if (dma_reset) |
| 1010 | pref_buf1_valid <= 1'b0; |
| 1011 | else if (unload_pref_buf[1] | get_pkt_pref_buf & use_pref_buf[1]) |
| 1012 | pref_buf1_valid <= 1'b0; |
| 1013 | else if (load_pref_buf) |
| 1014 | pref_buf1_valid <= cache_rd_valid_bits[1]; |
| 1015 | else |
| 1016 | pref_buf1_valid <= pref_buf1_valid; |
| 1017 | |
| 1018 | always @ (posedge clk) |
| 1019 | if (reset) |
| 1020 | pref_buf2_valid <= 1'b0; |
| 1021 | else if (dma_reset) |
| 1022 | pref_buf2_valid <= 1'b0; |
| 1023 | else if (unload_pref_buf[2] | get_pkt_pref_buf & use_pref_buf[2]) |
| 1024 | pref_buf2_valid <= 1'b0; |
| 1025 | else if (load_pref_buf) |
| 1026 | pref_buf2_valid <= cache_rd_valid_bits[2]; |
| 1027 | else |
| 1028 | pref_buf2_valid <= pref_buf2_valid; |
| 1029 | |
| 1030 | always @ (posedge clk) |
| 1031 | if (reset) |
| 1032 | pref_buf3_valid <= 1'b0; |
| 1033 | else if (dma_reset) |
| 1034 | pref_buf3_valid <= 1'b0; |
| 1035 | else if (unload_pref_buf[3] | get_pkt_pref_buf & use_pref_buf[3]) |
| 1036 | pref_buf3_valid <= 1'b0; |
| 1037 | else if (load_pref_buf) |
| 1038 | pref_buf3_valid <= cache_rd_valid_bits[3]; |
| 1039 | else |
| 1040 | pref_buf3_valid <= pref_buf3_valid; |
| 1041 | |
| 1042 | |
| 1043 | wire[3:0] pref_buf_valid_bits = {pref_buf3_valid, pref_buf2_valid, pref_buf1_valid, pref_buf0_valid}; |
| 1044 | wire pref_buf_valid = |pref_buf_valid_bits; |
| 1045 | |
| 1046 | wire[31:0] muxed_pref_buf_addr = pref_buf0_valid ? pref_buf_addr_reg[31:0] : |
| 1047 | pref_buf1_valid ? pref_buf_addr_reg[63:32] : |
| 1048 | pref_buf2_valid ? pref_buf_addr_reg[95:64] : |
| 1049 | pref_buf_addr_reg[127:96]; |
| 1050 | |
| 1051 | wire size_buf_req = size0_buf_req | size1_buf_req | size2_buf_req; |
| 1052 | |
| 1053 | always @ (pref_buf_valid_bits) |
| 1054 | begin |
| 1055 | |
| 1056 | case (pref_buf_valid_bits) //synopsys parallel_case full_case |
| 1057 | |
| 1058 | 4'b0001, 4'b0010, 4'b0100, 4'b1000: |
| 1059 | begin |
| 1060 | is_last_pref_buf = 1'b1; |
| 1061 | d_pref_buf_valid = 1'b0; |
| 1062 | t_pref_buf_valid = 1'b0; |
| 1063 | end |
| 1064 | 4'b0011, 4'b0110, 4'b1100: |
| 1065 | begin |
| 1066 | is_last_pref_buf = 1'b0; |
| 1067 | d_pref_buf_valid = 1'b1; |
| 1068 | t_pref_buf_valid = 1'b0; |
| 1069 | end |
| 1070 | 4'b0111, 4'b1110: |
| 1071 | begin |
| 1072 | is_last_pref_buf = 1'b0; |
| 1073 | d_pref_buf_valid = 1'b1; |
| 1074 | t_pref_buf_valid = 1'b1; |
| 1075 | end |
| 1076 | 4'b1111: |
| 1077 | begin |
| 1078 | is_last_pref_buf = 1'b0; |
| 1079 | d_pref_buf_valid = 1'b1; |
| 1080 | t_pref_buf_valid = 1'b1; |
| 1081 | end |
| 1082 | default: |
| 1083 | begin |
| 1084 | is_last_pref_buf = 1'b0; |
| 1085 | d_pref_buf_valid = 1'b0; |
| 1086 | t_pref_buf_valid = 1'b0; |
| 1087 | end |
| 1088 | endcase |
| 1089 | end |
| 1090 | |
| 1091 | |
| 1092 | always @ (pref_buf_valid_bits or size_buf_req or pkt_pref_buf_in_use) |
| 1093 | begin |
| 1094 | if (size_buf_req & !pkt_pref_buf_in_use) |
| 1095 | begin |
| 1096 | if (pref_buf_valid_bits[0]) |
| 1097 | unload_pref_buf = 4'b0001; |
| 1098 | else if (pref_buf_valid_bits[1]) |
| 1099 | unload_pref_buf = 4'b0010; |
| 1100 | else if (pref_buf_valid_bits[2]) |
| 1101 | unload_pref_buf = 4'b0100; |
| 1102 | else if (pref_buf_valid_bits[3]) |
| 1103 | unload_pref_buf = 4'b1000; |
| 1104 | else |
| 1105 | unload_pref_buf = 4'b0000; |
| 1106 | end |
| 1107 | else |
| 1108 | unload_pref_buf = 4'b0000; |
| 1109 | end |
| 1110 | |
| 1111 | wire cache_buf_rd_gnt_p = cache_buf_rd_gnt | cache_buf_rd_gnt_dly1 | |
| 1112 | cache_buf_rd_gnt_dly2 | cache_buf_rd_gnt_dly3; |
| 1113 | |
| 1114 | always @ (posedge clk) |
| 1115 | if (reset) |
| 1116 | cache_read_req <= 1'b0; |
| 1117 | else if (dma_reset) |
| 1118 | cache_read_req <= 1'b0; |
| 1119 | else if (cache_buf_rd_gnt_p) |
| 1120 | cache_read_req <= 1'b0; |
| 1121 | else if (!cache_buf_empty & (is_last_pref_buf & (|unload_pref_buf) | !pref_buf_valid)) |
| 1122 | cache_read_req <= 1'b1; |
| 1123 | else |
| 1124 | cache_read_req <= cache_read_req; |
| 1125 | |
| 1126 | |
| 1127 | /*********************************/ |
| 1128 | // size buffer manager |
| 1129 | /*********************************/ |
| 1130 | reg[2:0] load_size_buf; |
| 1131 | reg size0_buf_valid; |
| 1132 | reg size1_buf_valid; |
| 1133 | reg size2_buf_valid; |
| 1134 | reg[7:0] curr_size0_buf_num; |
| 1135 | reg[7:0] curr_size1_buf_num; |
| 1136 | reg[7:0] curr_size2_buf_num; |
| 1137 | reg[35:0] curr_size0_buf_addr_pre; |
| 1138 | reg[35:0] curr_size1_buf_addr_pre; |
| 1139 | reg[35:0] curr_size2_buf_addr_pre; |
| 1140 | |
| 1141 | wire use_size0_buf; |
| 1142 | wire use_size1_buf; |
| 1143 | wire use_size2_buf; |
| 1144 | |
| 1145 | wire is_last_size0_buf = sel_buf_enabled & use_size0_buf & (curr_size0_buf_num == 8'h01); |
| 1146 | wire is_last_size1_buf = sel_buf_enabled & use_size1_buf & (curr_size1_buf_num == 8'h01); |
| 1147 | wire is_last_size2_buf = sel_buf_enabled & use_size2_buf & (curr_size2_buf_num == 8'h01); |
| 1148 | |
| 1149 | always @ (posedge clk) |
| 1150 | if (reset) |
| 1151 | size0_buf_valid <= 1'b0; |
| 1152 | else if (dma_reset) |
| 1153 | size0_buf_valid <= 1'b0; |
| 1154 | else if (is_last_size0_buf) |
| 1155 | size0_buf_valid <= 1'b0; |
| 1156 | else if (load_size_buf[0]) |
| 1157 | size0_buf_valid <= 1'b1; |
| 1158 | else |
| 1159 | size0_buf_valid <= size0_buf_valid; |
| 1160 | |
| 1161 | always @ (posedge clk) |
| 1162 | if (reset) |
| 1163 | size1_buf_valid <= 1'b0; |
| 1164 | else if (dma_reset) |
| 1165 | size1_buf_valid <= 1'b0; |
| 1166 | else if (is_last_size1_buf) |
| 1167 | size1_buf_valid <= 1'b0; |
| 1168 | else if (load_size_buf[1]) |
| 1169 | size1_buf_valid <= 1'b1; |
| 1170 | else |
| 1171 | size1_buf_valid <= size1_buf_valid; |
| 1172 | |
| 1173 | always @ (posedge clk) |
| 1174 | if (reset) |
| 1175 | size2_buf_valid <= 1'b0; |
| 1176 | else if (dma_reset) |
| 1177 | size2_buf_valid <= 1'b0; |
| 1178 | else if (is_last_size2_buf) |
| 1179 | size2_buf_valid <= 1'b0; |
| 1180 | else if (load_size_buf[2]) |
| 1181 | size2_buf_valid <= 1'b1; |
| 1182 | else |
| 1183 | size2_buf_valid <= size2_buf_valid; |
| 1184 | |
| 1185 | |
| 1186 | always @ (posedge clk) |
| 1187 | if (reset) |
| 1188 | curr_size0_buf_num <= 8'b0; |
| 1189 | else if (dma_reset) |
| 1190 | curr_size0_buf_num <= 8'b0; |
| 1191 | else if (sel_buf_enabled & use_size0_buf) |
| 1192 | curr_size0_buf_num <= curr_size0_buf_num - 8'h01; |
| 1193 | else if (load_size_buf[0]) |
| 1194 | curr_size0_buf_num <= start_size0_buf_num; |
| 1195 | else |
| 1196 | curr_size0_buf_num <= curr_size0_buf_num; |
| 1197 | |
| 1198 | |
| 1199 | always @ (posedge clk) |
| 1200 | if (reset) |
| 1201 | curr_size1_buf_num <= 8'b0; |
| 1202 | else if (dma_reset) |
| 1203 | curr_size1_buf_num <= 8'b0; |
| 1204 | else if (sel_buf_enabled & use_size1_buf) |
| 1205 | curr_size1_buf_num <= curr_size1_buf_num - 8'h01; |
| 1206 | else if (load_size_buf[1]) |
| 1207 | curr_size1_buf_num <= start_size1_buf_num; |
| 1208 | else |
| 1209 | curr_size1_buf_num <= curr_size1_buf_num; |
| 1210 | |
| 1211 | |
| 1212 | always @ (posedge clk) |
| 1213 | if (reset) |
| 1214 | curr_size2_buf_num <= 8'b0; |
| 1215 | else if (dma_reset) |
| 1216 | curr_size2_buf_num <= 8'b0; |
| 1217 | else if (sel_buf_enabled & use_size2_buf) |
| 1218 | curr_size2_buf_num <= curr_size2_buf_num - 8'h01; |
| 1219 | else if (load_size_buf[2]) |
| 1220 | curr_size2_buf_num <= start_size2_buf_num; |
| 1221 | else |
| 1222 | curr_size2_buf_num <= curr_size2_buf_num; |
| 1223 | |
| 1224 | |
| 1225 | wire[43:0] curr_size0_buf_addr = {curr_size0_buf_addr_pre[35:0], 8'b0}; |
| 1226 | wire[43:0] curr_size1_buf_addr = {curr_size1_buf_addr_pre[35:0], 8'b0}; |
| 1227 | wire[43:0] curr_size2_buf_addr = {curr_size2_buf_addr_pre[35:0], 8'b0}; |
| 1228 | |
| 1229 | wire[7:0] next_size0_buf_addr_tmp = curr_size0_buf_addr_pre[7:0] + size0_buf_size[15:8]; |
| 1230 | wire[35:0] next_size0_buf_addr = {curr_size0_buf_addr_pre[35:8], next_size0_buf_addr_tmp[7:0]}; |
| 1231 | |
| 1232 | wire[7:0] next_size1_buf_addr_tmp = curr_size1_buf_addr_pre[7:0] + size1_buf_size[15:8]; |
| 1233 | wire[35:0] next_size1_buf_addr = {curr_size1_buf_addr_pre[35:8], next_size1_buf_addr_tmp[7:0]}; |
| 1234 | |
| 1235 | wire[7:0] next_size2_buf_addr_tmp = curr_size2_buf_addr_pre[7:0] + size2_buf_size[15:8]; |
| 1236 | wire[35:0] next_size2_buf_addr = {curr_size2_buf_addr_pre[35:8], next_size2_buf_addr_tmp[7:0]}; |
| 1237 | |
| 1238 | |
| 1239 | always @ (posedge clk) |
| 1240 | if (reset) |
| 1241 | curr_size0_buf_addr_pre <= 36'b0; |
| 1242 | else if (sel_buf_enabled & use_size0_buf) |
| 1243 | curr_size0_buf_addr_pre <= next_size0_buf_addr; |
| 1244 | else if (load_size_buf[0]) |
| 1245 | curr_size0_buf_addr_pre <= {muxed_pref_buf_addr, 4'b0}; |
| 1246 | else |
| 1247 | curr_size0_buf_addr_pre <= curr_size0_buf_addr_pre; |
| 1248 | |
| 1249 | always @ (posedge clk) |
| 1250 | if (reset) |
| 1251 | curr_size1_buf_addr_pre <= 36'b0; |
| 1252 | else if (sel_buf_enabled & use_size1_buf) |
| 1253 | curr_size1_buf_addr_pre <= next_size1_buf_addr; |
| 1254 | else if (load_size_buf[1]) |
| 1255 | curr_size1_buf_addr_pre <= {muxed_pref_buf_addr, 4'b0}; |
| 1256 | else |
| 1257 | curr_size1_buf_addr_pre <= curr_size1_buf_addr_pre; |
| 1258 | |
| 1259 | always @ (posedge clk) |
| 1260 | if (reset) |
| 1261 | curr_size2_buf_addr_pre <= 36'b0; |
| 1262 | else if (sel_buf_enabled & use_size2_buf) |
| 1263 | curr_size2_buf_addr_pre <= next_size2_buf_addr; |
| 1264 | else if (load_size_buf[2]) |
| 1265 | curr_size2_buf_addr_pre <= {muxed_pref_buf_addr, 4'b0}; |
| 1266 | else |
| 1267 | curr_size2_buf_addr_pre <= curr_size2_buf_addr_pre; |
| 1268 | |
| 1269 | /**************************************/ |
| 1270 | //req for loading new size buffer |
| 1271 | /**************************************/ |
| 1272 | always @ (posedge clk) |
| 1273 | if (reset) |
| 1274 | size0_buf_req <= 1'b0; |
| 1275 | else if (dma_reset) |
| 1276 | size0_buf_req <= 1'b0; |
| 1277 | else if (load_size_buf[0]) |
| 1278 | size0_buf_req <= 1'b0; |
| 1279 | else if ((is_last_size0_buf | !size0_buf_valid) & size0_config_valid) |
| 1280 | size0_buf_req <= 1'b1; |
| 1281 | else |
| 1282 | size0_buf_req <= size0_buf_req; |
| 1283 | |
| 1284 | always @ (posedge clk) |
| 1285 | if (reset) |
| 1286 | size1_buf_req <= 1'b0; |
| 1287 | else if (dma_reset) |
| 1288 | size1_buf_req <= 1'b0; |
| 1289 | else if (load_size_buf[1]) |
| 1290 | size1_buf_req <= 1'b0; |
| 1291 | else if ((is_last_size1_buf | !size1_buf_valid) & size1_config_valid) |
| 1292 | size1_buf_req <= 1'b1; |
| 1293 | else |
| 1294 | size1_buf_req <= size1_buf_req; |
| 1295 | |
| 1296 | always @ (posedge clk) |
| 1297 | if (reset) |
| 1298 | size2_buf_req <= 1'b0; |
| 1299 | else if (dma_reset) |
| 1300 | size2_buf_req <= 1'b0; |
| 1301 | else if (load_size_buf[2]) |
| 1302 | size2_buf_req <= 1'b0; |
| 1303 | else if ((is_last_size2_buf | !size2_buf_valid) & size2_config_valid) |
| 1304 | size2_buf_req <= 1'b1; |
| 1305 | else |
| 1306 | size2_buf_req <= size2_buf_req; |
| 1307 | |
| 1308 | |
| 1309 | always @ (size0_buf_req or size1_buf_req or |
| 1310 | size2_buf_req or pref_buf_valid or pkt_pref_buf_in_use) |
| 1311 | begin |
| 1312 | if (pref_buf_valid & !pkt_pref_buf_in_use) |
| 1313 | begin |
| 1314 | if (size2_buf_req) |
| 1315 | load_size_buf = 3'b100; |
| 1316 | else if (size1_buf_req) |
| 1317 | load_size_buf = 3'b010; |
| 1318 | else if (size0_buf_req) |
| 1319 | load_size_buf = 3'b001; |
| 1320 | else |
| 1321 | load_size_buf = 3'b000; |
| 1322 | end |
| 1323 | else load_size_buf = 3'b000; |
| 1324 | end |
| 1325 | |
| 1326 | |
| 1327 | /***********************************************************/ |
| 1328 | //select proper buffer for incoming pkt |
| 1329 | /***********************************************************/ |
| 1330 | reg chnl_sel_buf_en_r; |
| 1331 | reg[7:0] pkt_hdr_byte_r; |
| 1332 | reg[13:0] muxed_pkt_len_r; |
| 1333 | reg[14:0] full_len_r; |
| 1334 | reg[13:0] pkt_len_leftover; |
| 1335 | reg[13:0] pkt_trans_len; |
| 1336 | |
| 1337 | reg sel_size0_buf_r; |
| 1338 | reg sel_size1_buf_r; |
| 1339 | reg sel_size2_buf_r; |
| 1340 | reg sel_1pref_buf_r; |
| 1341 | reg sel_2pref_buf_r; |
| 1342 | reg sel_3pref_buf_r; |
| 1343 | reg sel_size_buf_r; |
| 1344 | reg sel_size_buf_r1; |
| 1345 | reg use_1pref_buf_r; |
| 1346 | reg use_2pref_buf_r; |
| 1347 | reg use_3pref_buf_r; |
| 1348 | |
| 1349 | reg pkt_buf_gnt; |
| 1350 | reg[43:0] buf_new_addr_r; |
| 1351 | reg[35:0] buf_addr_r; |
| 1352 | reg[1:0] pkt_buf_size; |
| 1353 | reg[1:0] pref_buf_used_num_r; |
| 1354 | reg jmb_pkt_in_process; |
| 1355 | |
| 1356 | wire[7:0] pkt_hdr_byte = full_header ? (byte_offset + 8'd18) : (byte_offset + 8'd2); |
| 1357 | wire[7:0] pkt_hdr_byte1 = full_header ? 8'd18 : 8'd2; |
| 1358 | |
| 1359 | wire[14:0] full_len1 = {1'b0, muxed_pkt_len[13:0]}; |
| 1360 | wire[14:0] full_len2 = {7'b0, pkt_hdr_byte_r[7:0]}; |
| 1361 | wire[14:0] full_len = full_len1 + full_len2; //include offset |
| 1362 | |
| 1363 | wire[13:0] real_len = muxed_pkt_len_r[13:0] + {6'b0, pkt_hdr_byte1[7:0]}; //not include offset |
| 1364 | wire pkt_len_overflow= full_len_r[14]; |
| 1365 | |
| 1366 | wire sel_size0_buf = (size0_buf_size[13:0] >= full_len_r[13:0]); |
| 1367 | wire sel_size1_buf = (size1_buf_size[13:0] >= full_len_r[13:0]); |
| 1368 | wire sel_size2_buf = (size2_buf_size[14:0] >= {1'b0, full_len_r[13:0]}); |
| 1369 | wire sel_1pref_buf = (cache_buf_size[15:0] >= {2'b0, full_len_r[13:0]}); |
| 1370 | wire sel_2pref_buf = (cache_buf_size2[15:0]>= {2'b0, full_len_r[13:0]}); |
| 1371 | wire sel_3pref_buf = (cache_buf_size3[16:0]>= {3'b0, full_len_r[13:0]}); |
| 1372 | |
| 1373 | wire[35:0] orig_buf_addr = buf_addr_r[35:0]; |
| 1374 | |
| 1375 | wire get_next_buf; |
| 1376 | wire get_last_buf; |
| 1377 | |
| 1378 | always @ (posedge clk) |
| 1379 | if (reset) |
| 1380 | pkt_hdr_byte_r <= 8'b0; |
| 1381 | else |
| 1382 | pkt_hdr_byte_r <= pkt_hdr_byte; |
| 1383 | |
| 1384 | always @ (posedge clk) |
| 1385 | if (reset) |
| 1386 | muxed_pkt_len_r <= 14'b0; |
| 1387 | else |
| 1388 | muxed_pkt_len_r <= muxed_pkt_len[13:0]; |
| 1389 | |
| 1390 | |
| 1391 | always @ (posedge clk) |
| 1392 | if (reset) |
| 1393 | full_len_r <= 15'b0; |
| 1394 | else |
| 1395 | full_len_r <= full_len; |
| 1396 | |
| 1397 | |
| 1398 | always @ (posedge clk) |
| 1399 | if (reset) |
| 1400 | pkt_len_leftover <= 14'b0; |
| 1401 | else if (sel_buf_en_r) |
| 1402 | pkt_len_leftover <= full_len_r[13:0] - cache_buf_size[13:0]; |
| 1403 | else if (get_next_buf) |
| 1404 | pkt_len_leftover <= pkt_len_leftover - cache_buf_size1[13:0]; |
| 1405 | else |
| 1406 | pkt_len_leftover <= pkt_len_leftover; |
| 1407 | |
| 1408 | |
| 1409 | always @ (posedge clk) |
| 1410 | if (reset) |
| 1411 | sel_size0_buf_r <= 1'b0; |
| 1412 | else |
| 1413 | sel_size0_buf_r <= sel_size0_buf; |
| 1414 | |
| 1415 | always @ (posedge clk) |
| 1416 | if (reset) |
| 1417 | sel_size1_buf_r <= 1'b0; |
| 1418 | else |
| 1419 | sel_size1_buf_r <= sel_size1_buf; |
| 1420 | |
| 1421 | always @ (posedge clk) |
| 1422 | if (reset) |
| 1423 | sel_size2_buf_r <= 1'b0; |
| 1424 | else |
| 1425 | sel_size2_buf_r <= sel_size2_buf; |
| 1426 | |
| 1427 | |
| 1428 | always @ (posedge clk) |
| 1429 | if (reset) |
| 1430 | begin |
| 1431 | sel_size_buf_r <= 1'b0; |
| 1432 | sel_size_buf_r1 <= 1'b0; |
| 1433 | end |
| 1434 | else |
| 1435 | begin |
| 1436 | sel_size_buf_r <= (sel_size0_buf | sel_size1_buf | sel_size2_buf); |
| 1437 | sel_size_buf_r1 <= sel_size_buf_r; |
| 1438 | end |
| 1439 | |
| 1440 | always @ (posedge clk) |
| 1441 | if (reset) |
| 1442 | sel_1pref_buf_r <= 1'b0; |
| 1443 | else |
| 1444 | sel_1pref_buf_r <= sel_1pref_buf; |
| 1445 | |
| 1446 | always @ (posedge clk) |
| 1447 | if (reset) |
| 1448 | sel_2pref_buf_r <= 1'b0; |
| 1449 | else |
| 1450 | sel_2pref_buf_r <= sel_2pref_buf & !sel_1pref_buf; |
| 1451 | |
| 1452 | always @ (posedge clk) |
| 1453 | if (reset) |
| 1454 | sel_3pref_buf_r <= 1'b0; |
| 1455 | else |
| 1456 | sel_3pref_buf_r <= sel_3pref_buf & !(sel_1pref_buf | sel_2pref_buf); |
| 1457 | |
| 1458 | assign use_size0_buf = sel_size0_buf_r & size0_buf_valid; |
| 1459 | wire use_size1_buf_tmp = sel_size1_buf_r & size1_buf_valid; |
| 1460 | wire use_size2_buf_tmp = sel_size2_buf_r & size2_buf_valid; |
| 1461 | assign use_size1_buf = !use_size0_buf & use_size1_buf_tmp; |
| 1462 | assign use_size2_buf = !(use_size0_buf | use_size1_buf_tmp) & use_size2_buf_tmp; |
| 1463 | |
| 1464 | wire use_1pref_buf = !sel_size_buf_r & sel_1pref_buf_r & pref_buf_valid; |
| 1465 | wire use_2pref_buf = !sel_size_buf_r & sel_2pref_buf_r & (d_pref_buf_valid | pref_buf_valid & !cache_buf_empty); |
| 1466 | wire use_3pref_buf = !sel_size_buf_r & sel_3pref_buf_r & (pref_buf_valid & (|cache_buf_cnt[7:1]) | |
| 1467 | d_pref_buf_valid & !cache_buf_empty | |
| 1468 | t_pref_buf_valid); |
| 1469 | |
| 1470 | wire is_use_pref_buf = (use_1pref_buf | use_2pref_buf | use_3pref_buf) & !pkt_len_overflow; |
| 1471 | wire is_use_size_buf = (use_size0_buf | use_size1_buf | use_size2_buf) & !pkt_len_overflow; |
| 1472 | |
| 1473 | wire buf_gnt = (is_use_pref_buf | is_use_size_buf); |
| 1474 | |
| 1475 | wire[1:0] buf_size_in = use_size0_buf ? 2'b00 : |
| 1476 | use_size1_buf ? 2'b01 : |
| 1477 | use_size2_buf ? 2'b10 : |
| 1478 | 2'b11; |
| 1479 | |
| 1480 | always @ (posedge clk) |
| 1481 | if (reset) |
| 1482 | pkt_buf_gnt <= 1'b0; |
| 1483 | else if (dma_reset) |
| 1484 | pkt_buf_gnt <= 1'b0; |
| 1485 | else if (sel_buf_enabled_tmp & !buf_addr_not_valid) |
| 1486 | pkt_buf_gnt <= buf_gnt; |
| 1487 | else if (pkt_buf_done) |
| 1488 | pkt_buf_gnt <= 1'b0; |
| 1489 | else |
| 1490 | pkt_buf_gnt <= pkt_buf_gnt; |
| 1491 | |
| 1492 | always @ (posedge clk) |
| 1493 | if (reset) |
| 1494 | pkt_buf_size <= 2'b0; |
| 1495 | else if (sel_buf_en_r) |
| 1496 | pkt_buf_size <= buf_size_in; |
| 1497 | else |
| 1498 | pkt_buf_size <= pkt_buf_size; |
| 1499 | |
| 1500 | |
| 1501 | assign rbr_drop_pkt = !buf_gnt; |
| 1502 | assign rcr_drop_pkt = !((sel_size_buf_r | sel_1pref_buf_r) & shadow_not_empty | shadow_not_e_empty); |
| 1503 | |
| 1504 | |
| 1505 | /*******************************/ |
| 1506 | //Calculate pkt transfer len |
| 1507 | /*******************************/ |
| 1508 | wire chnl_pkt_cnt_done = pkt_req_cnt_e_done_mod & (muxed_rdc_num_r == dma_chnl_grp_id); |
| 1509 | |
| 1510 | wire jmb_pkt_mode = !(sel_size_buf_r | use_1pref_buf); |
| 1511 | wire[1:0] pref_buf_used_num = (sel_size_buf_r1 | use_1pref_buf_r) ? 2'b01 : |
| 1512 | use_2pref_buf_r ? 2'b10 : |
| 1513 | use_3pref_buf_r ? 2'b11 : 2'b00; |
| 1514 | |
| 1515 | assign get_next_buf = chnl_pkt_cnt_done & is_hdr_wr_data & (&pref_buf_used_num_r); |
| 1516 | assign get_last_buf = chnl_pkt_cnt_done & (is_hdr_wr_data & (pref_buf_used_num_r == 2'b10) | |
| 1517 | is_jmb1_wr_data & (pref_buf_used_num_r == 2'b11)); |
| 1518 | |
| 1519 | wire[13:0] pkt_len_tmp = (jmb_pkt_mode & sel_buf_en_r) ? cache_buf_size1[13:0]: |
| 1520 | sel_buf_en_r ? real_len[13:0] : |
| 1521 | get_next_buf ? cache_buf_size1[13:0] : pkt_len_leftover; |
| 1522 | |
| 1523 | |
| 1524 | always @ (posedge clk) |
| 1525 | if (reset) |
| 1526 | begin |
| 1527 | use_1pref_buf_r <= 1'b0; |
| 1528 | use_2pref_buf_r <= 1'b0; |
| 1529 | use_3pref_buf_r <= 1'b0; |
| 1530 | end |
| 1531 | else if (sel_buf_en_r) |
| 1532 | begin |
| 1533 | use_1pref_buf_r <= use_1pref_buf; |
| 1534 | use_2pref_buf_r <= use_2pref_buf; |
| 1535 | use_3pref_buf_r <= use_3pref_buf; |
| 1536 | end |
| 1537 | |
| 1538 | always @ (posedge clk) |
| 1539 | if (reset) |
| 1540 | chnl_sel_buf_en_r <= 1'b0; |
| 1541 | else if (dma_reset) |
| 1542 | chnl_sel_buf_en_r <= 1'b0; |
| 1543 | else |
| 1544 | chnl_sel_buf_en_r <= sel_buf_enabled; |
| 1545 | |
| 1546 | always @ (posedge clk) |
| 1547 | if (reset) |
| 1548 | pref_buf_used_num_r <= 2'b0; |
| 1549 | else if (chnl_sel_buf_en_r) |
| 1550 | pref_buf_used_num_r <= pref_buf_used_num; |
| 1551 | else |
| 1552 | pref_buf_used_num_r <= pref_buf_used_num_r; |
| 1553 | |
| 1554 | always @ (posedge clk) |
| 1555 | if (reset) |
| 1556 | pkt_trans_len <= 14'b0; |
| 1557 | else if (sel_buf_en_r | get_next_buf | get_last_buf) |
| 1558 | pkt_trans_len <= pkt_len_tmp; |
| 1559 | else |
| 1560 | pkt_trans_len <= pkt_trans_len; |
| 1561 | |
| 1562 | /*******************************/ |
| 1563 | //Calculate pkt transfer addr |
| 1564 | /*******************************/ |
| 1565 | assign get_pkt_pref_buf = sel_buf_enabled_tmp & is_use_pref_buf | get_next_buf | get_last_buf; |
| 1566 | assign pkt_pref_buf_in_use = chnl_sel_buf_en | jmb_pkt_in_process; |
| 1567 | |
| 1568 | wire[43:0] buf_addr_tmp1= {44{use_size0_buf}} & curr_size0_buf_addr | |
| 1569 | {44{use_size1_buf}} & curr_size1_buf_addr | |
| 1570 | {44{use_size2_buf}} & curr_size2_buf_addr ; |
| 1571 | |
| 1572 | wire[43:0] buf_addr_tmp2= is_use_size_buf & sel_buf_en_r ? buf_addr_tmp1 : {muxed_pref_buf_addr, 12'b0}; |
| 1573 | |
| 1574 | |
| 1575 | wire[43:0] buf_addr = (dma_data_offset[1:0] == 2'b01) ? {buf_addr_tmp2[43:8], 8'b0100_0000} : |
| 1576 | (dma_data_offset[1:0] == 2'b10) ? {buf_addr_tmp2[43:8], 8'b1000_0000} : |
| 1577 | buf_addr_tmp2[43:0]; |
| 1578 | |
| 1579 | |
| 1580 | wire buf_addr_valid0 = ((buf_addr[43:12] & addr_mask0) == (comp_value0 & addr_mask0)) & page_valid0; |
| 1581 | wire buf_addr_valid1 = ((buf_addr[43:12] & addr_mask1) == (comp_value1 & addr_mask1)) & page_valid1; |
| 1582 | |
| 1583 | assign buf_addr_not_valid = !(buf_addr_valid0 | buf_addr_valid1) & buf_gnt & chnl_sel_buf_en & dma_en; |
| 1584 | |
| 1585 | |
| 1586 | wire[31:0] buf_relo_addr0 = (buf_addr[43:12] & ~addr_mask0) | (relo_value0 & addr_mask0); |
| 1587 | wire[31:0] buf_relo_addr1 = (buf_addr[43:12] & ~addr_mask1) | (relo_value1 & addr_mask1); |
| 1588 | wire[31:0] buf_relo_addr = buf_addr_valid0 ? buf_relo_addr0 : buf_relo_addr1; |
| 1589 | wire[43:0] buf_new_addr = {buf_relo_addr, buf_addr[11:0]}; |
| 1590 | wire[63:0] pkt_buf_addr = {page_handle[19:0], buf_new_addr_r[43:0]}; |
| 1591 | |
| 1592 | always @ (pref_buf_valid_bits) |
| 1593 | begin |
| 1594 | if (pref_buf_valid_bits[0]) |
| 1595 | use_pref_buf = 4'b0001; |
| 1596 | else if (pref_buf_valid_bits[1]) |
| 1597 | use_pref_buf = 4'b0010; |
| 1598 | else if (pref_buf_valid_bits[2]) |
| 1599 | use_pref_buf = 4'b0100; |
| 1600 | else if (pref_buf_valid_bits[3]) |
| 1601 | use_pref_buf = 4'b1000; |
| 1602 | else |
| 1603 | use_pref_buf = 4'b0000; |
| 1604 | end |
| 1605 | |
| 1606 | |
| 1607 | always @ (posedge clk) |
| 1608 | if (reset) |
| 1609 | jmb_pkt_in_process <= 1'b0; |
| 1610 | else if (dma_reset) |
| 1611 | jmb_pkt_in_process <= 1'b0; |
| 1612 | else if (sel_buf_enabled_tmp & (use_2pref_buf | use_3pref_buf)) |
| 1613 | jmb_pkt_in_process <= 1'b1; |
| 1614 | else if (get_last_buf) |
| 1615 | jmb_pkt_in_process <= 1'b0; |
| 1616 | else |
| 1617 | jmb_pkt_in_process <= jmb_pkt_in_process; |
| 1618 | |
| 1619 | |
| 1620 | always @ (posedge clk) |
| 1621 | if (reset) |
| 1622 | buf_new_addr_r <= 44'b0; |
| 1623 | else if (sel_buf_en_r | get_next_buf | get_last_buf) |
| 1624 | buf_new_addr_r <= buf_new_addr; |
| 1625 | else |
| 1626 | buf_new_addr_r <= buf_new_addr_r; |
| 1627 | |
| 1628 | always @ (posedge clk) |
| 1629 | if (reset) |
| 1630 | buf_addr_r <= 36'b0; |
| 1631 | else if (sel_buf_en_r | get_next_buf | get_last_buf) |
| 1632 | buf_addr_r <= buf_addr[43:8]; |
| 1633 | else |
| 1634 | buf_addr_r <= buf_addr_r; |
| 1635 | |
| 1636 | |
| 1637 | /*************************/ |
| 1638 | //Weighted RED |
| 1639 | /*************************/ |
| 1640 | reg[15:0] wred_v2_tmp; |
| 1641 | reg[16:0] wred_v1; |
| 1642 | reg[15:0] wred_v2; |
| 1643 | |
| 1644 | wire[11:0] muxed_wred_thresh = muxed_s_event_r ? wred_thresh_syn : wred_thresh; |
| 1645 | wire[3:0] muxed_wred_window = muxed_s_event_r ? wred_window_syn : wred_window; |
| 1646 | |
| 1647 | wire[16:0] wred_v1_tmp = {1'b0, rcr_curr_qlen[15:0]} - {5'b0, muxed_wred_thresh[11:0]}; |
| 1648 | //wire[15:0] wred_v2_msb = wred_v2_tmp[31:16]; |
| 1649 | //wire wred_v3_tmp = (wred_v2[15:0] < wred_v1[15:0]) & !wred_v1[16]; //drop pkt when cross (THRSH + WIN); |
| 1650 | wire wred_v3_tmp = ((wred_v2[15:0] < wred_v1[15:0]) | (wred_v2[15:0] == wred_v1[15:0])) & !wred_v1[16]; //drop pkt when hit threshold |
| 1651 | |
| 1652 | always @ (muxed_wred_window or random_num) |
| 1653 | begin |
| 1654 | |
| 1655 | case (muxed_wred_window) //synopsys parallel_case full_case |
| 1656 | |
| 1657 | /* |
| 1658 | 4'd0: wred_v2_tmp = {16'b0, random_num}; |
| 1659 | 4'd1: wred_v2_tmp = {15'b0, random_num, 1'b0}; |
| 1660 | 4'd2: wred_v2_tmp = {14'b0, random_num, 2'b0}; |
| 1661 | 4'd3: wred_v2_tmp = {13'b0, random_num, 3'b0}; |
| 1662 | 4'd4: wred_v2_tmp = {12'b0, random_num, 4'b0}; |
| 1663 | 4'd5: wred_v2_tmp = {11'b0, random_num, 5'b0}; |
| 1664 | 4'd6: wred_v2_tmp = {10'b0, random_num, 6'b0}; |
| 1665 | 4'd7: wred_v2_tmp = {9'b0, random_num, 7'b0}; |
| 1666 | 4'd8: wred_v2_tmp = {8'b0, random_num, 8'b0}; |
| 1667 | 4'd9: wred_v2_tmp = {7'b0, random_num, 9'b0}; |
| 1668 | 4'd10: wred_v2_tmp = {6'b0, random_num, 10'b0}; |
| 1669 | 4'd11: wred_v2_tmp = {5'b0, random_num, 11'b0}; |
| 1670 | 4'd12: wred_v2_tmp = {4'b0, random_num, 12'b0}; |
| 1671 | 4'd13: wred_v2_tmp = {3'b0, random_num, 13'b0}; |
| 1672 | 4'd14: wred_v2_tmp = {2'b0, random_num, 14'b0}; |
| 1673 | 4'd15: wred_v2_tmp = {1'b0, random_num, 15'b0}; |
| 1674 | */ |
| 1675 | |
| 1676 | 4'd0: wred_v2_tmp = 16'b0; |
| 1677 | 4'd1: wred_v2_tmp = {15'b0, random_num[15]}; |
| 1678 | 4'd2: wred_v2_tmp = {14'b0, random_num[15:14]}; |
| 1679 | 4'd3: wred_v2_tmp = {13'b0, random_num[15:13]}; |
| 1680 | 4'd4: wred_v2_tmp = {12'b0, random_num[15:12]}; |
| 1681 | 4'd5: wred_v2_tmp = {11'b0, random_num[15:11]}; |
| 1682 | 4'd6: wred_v2_tmp = {10'b0, random_num[15:10]}; |
| 1683 | 4'd7: wred_v2_tmp = {9'b0, random_num[15:9]}; |
| 1684 | 4'd8: wred_v2_tmp = {8'b0, random_num[15:8]}; |
| 1685 | 4'd9: wred_v2_tmp = {7'b0, random_num[15:7]}; |
| 1686 | 4'd10: wred_v2_tmp = {6'b0, random_num[15:6]}; |
| 1687 | 4'd11: wred_v2_tmp = {5'b0, random_num[15:5]}; |
| 1688 | 4'd12: wred_v2_tmp = {4'b0, random_num[15:4]}; |
| 1689 | 4'd13: wred_v2_tmp = {3'b0, random_num[15:3]}; |
| 1690 | 4'd14: wred_v2_tmp = {2'b0, random_num[15:2]}; |
| 1691 | 4'd15: wred_v2_tmp = {1'b0, random_num[15:1]}; |
| 1692 | |
| 1693 | |
| 1694 | endcase |
| 1695 | end |
| 1696 | |
| 1697 | |
| 1698 | always @ (posedge clk) |
| 1699 | if (reset) |
| 1700 | begin |
| 1701 | wred_v1 <= 17'b0; |
| 1702 | wred_v2 <= 16'b0; |
| 1703 | end |
| 1704 | else |
| 1705 | begin |
| 1706 | wred_v1 <= wred_v1_tmp[16:0]; |
| 1707 | wred_v2 <= wred_v2_tmp[15:0]; |
| 1708 | end |
| 1709 | |
| 1710 | |
| 1711 | always @ (posedge clk) |
| 1712 | if (reset) |
| 1713 | wred_drop_pkt <= 1'b0; |
| 1714 | else if (dma_reset) |
| 1715 | wred_drop_pkt <= 1'b0; |
| 1716 | else if (!wred_enable) |
| 1717 | wred_drop_pkt <= 1'b0; |
| 1718 | else if (sel_buf_en) |
| 1719 | wred_drop_pkt <= wred_v3_tmp; |
| 1720 | else |
| 1721 | wred_drop_pkt <= 1'b0; |
| 1722 | |
| 1723 | |
| 1724 | |
| 1725 | endmodule |
| 1726 | |
| 1727 | |