| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_smx_pio.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | |
| 36 | module niu_smx_pio( |
| 37 | /*AUTOARG*/ |
| 38 | // Outputs |
| 39 | reg_timer_cfg, reg_ras_cfg, smx_pio_intr, smx_pio_status, |
| 40 | smx_debug_port, pio_xtb_err_inject_cfg, pio_resp_err_inject_cfg, |
| 41 | // Inputs |
| 42 | clk, reset_l, pio_data, pio_smx_clear_intr, pio_smx_ctrl, |
| 43 | pio_smx_debug_vector, tohdl_set_intr, tohdl_intr_status, |
| 44 | niu_sii_hdr_vld, niu_sii_reqbypass, niu_sii_datareq, sii_niu_oqdq, |
| 45 | sii_niu_bqdq, wreq_cmdff_rd, rdreq_cmdff_rd, wreq_dataff_rd, |
| 46 | wreq_cmdff_wr, rdreq_cmdff_wr, wreq_dataff_wr, sio_niu_hdr_vld, |
| 47 | sio_niu_datareq, niu_sio_dq, resp_cmdff_wr, resp_dataff_wr, |
| 48 | resp_cmdff_rd, resp_dataff_rd, meta_dmc_resp_ready, |
| 49 | meta_dmc_ack_ready, dmc_meta0_req, meta_dmc1_req_accept, |
| 50 | dmc_meta1_req, meta_dmc0_req_accept, meta_dmc0_data_req, |
| 51 | dmc_meta0_data_valid, sii_cs, arb_cs, rdreq_cmd_cs, wreq_cmd_cs, |
| 52 | wreq_dv_cs, dreq_cs, proc_cs, cmdl_cs, dv_cs |
| 53 | ); |
| 54 | |
| 55 | |
| 56 | input clk; |
| 57 | input reset_l; |
| 58 | |
| 59 | output [31:0] reg_timer_cfg; |
| 60 | output [1:0] reg_ras_cfg; |
| 61 | |
| 62 | // pio blk if |
| 63 | // input pio_ld; |
| 64 | input [31:0] pio_data; |
| 65 | output smx_pio_intr; // level signal; |
| 66 | // once high stays high until clear by pio |
| 67 | output[31:0] smx_pio_status; // status info related to intr |
| 68 | input pio_smx_clear_intr; // a pulse |
| 69 | // read_only status |
| 70 | |
| 71 | input [31:0] pio_smx_ctrl; // debug select; extra bits |
| 72 | // reserved within smx in case |
| 73 | // needed for sth else |
| 74 | input [31:0] pio_smx_debug_vector; // training vector |
| 75 | output [31:0] smx_debug_port; |
| 76 | |
| 77 | // timout_hdlr i/f |
| 78 | input tohdl_set_intr; |
| 79 | input [5:0] tohdl_intr_status; |
| 80 | |
| 81 | |
| 82 | // xtb i/f (error inject) |
| 83 | output [2:0] pio_xtb_err_inject_cfg; // [0] - one pkt |
| 84 | // [1] - alt pkt |
| 85 | // [2] - all pkt |
| 86 | |
| 87 | // resp_dv i/f (err inject) |
| 88 | output [2:0] pio_resp_err_inject_cfg; // [0] - one pkt |
| 89 | // [1] - alt pkt |
| 90 | // [2] - all pkt |
| 91 | |
| 92 | |
| 93 | // debug port |
| 94 | input niu_sii_hdr_vld; |
| 95 | input niu_sii_reqbypass; |
| 96 | input niu_sii_datareq; |
| 97 | input sii_niu_oqdq; |
| 98 | input sii_niu_bqdq; |
| 99 | input wreq_cmdff_rd; |
| 100 | input rdreq_cmdff_rd; |
| 101 | input wreq_dataff_rd; |
| 102 | input wreq_cmdff_wr; |
| 103 | input rdreq_cmdff_wr; |
| 104 | input wreq_dataff_wr; |
| 105 | input sio_niu_hdr_vld; |
| 106 | input sio_niu_datareq; |
| 107 | input niu_sio_dq; |
| 108 | input resp_cmdff_wr; |
| 109 | input resp_dataff_wr; |
| 110 | input resp_cmdff_rd; |
| 111 | input resp_dataff_rd; |
| 112 | input meta_dmc_resp_ready; |
| 113 | input meta_dmc_ack_ready; |
| 114 | input dmc_meta0_req; |
| 115 | input meta_dmc1_req_accept; |
| 116 | input dmc_meta1_req; |
| 117 | input meta_dmc0_req_accept; |
| 118 | input meta_dmc0_data_req; |
| 119 | input dmc_meta0_data_valid; |
| 120 | |
| 121 | |
| 122 | input [1:0] sii_cs; |
| 123 | input [1:0] arb_cs; |
| 124 | input [2:0] rdreq_cmd_cs; |
| 125 | input [2:0] wreq_cmd_cs; |
| 126 | input [1:0] wreq_dv_cs; |
| 127 | input [2:0] dreq_cs; |
| 128 | input [1:0] proc_cs; |
| 129 | input [2:0] cmdl_cs; |
| 130 | input [2:0] dv_cs; |
| 131 | |
| 132 | |
| 133 | |
| 134 | // place holder ???? |
| 135 | // don't have anything to intr for now |
| 136 | // wire smx_pio_intr= 1'b0; |
| 137 | // wire [31:0] smx_pio_status= 32'h0; |
| 138 | |
| 139 | |
| 140 | // timer config related |
| 141 | reg [31:0] reg_smx_cfg; |
| 142 | wire [31:0] reg_timer_cfg= reg_smx_cfg; |
| 143 | wire [1:0] reg_ras_cfg= reg_smx_cfg[31:30]; |
| 144 | |
| 145 | |
| 146 | // debug port related |
| 147 | reg [31:0] pio_smx_debug_vector_r; |
| 148 | reg [2:0] debug_sel; |
| 149 | reg [31:0] smx_debug_port, smx_debug_port_n; |
| 150 | reg [31:0] int_debug_port; |
| 151 | |
| 152 | // intr related |
| 153 | reg smx_pio_intr; |
| 154 | reg [5:0] pio_status_tohdl; |
| 155 | reg [25:0] int_status; |
| 156 | wire [31:0] smx_pio_status= {int_status, pio_status_tohdl}; |
| 157 | |
| 158 | // error inject related |
| 159 | reg [2:0] pio_xtb_err_inject_cfg; |
| 160 | reg [2:0] pio_resp_err_inject_cfg; |
| 161 | |
| 162 | always @(posedge clk) begin |
| 163 | if(!reset_l) |
| 164 | smx_pio_intr<= `SMX_PD 1'b0; |
| 165 | else |
| 166 | if(tohdl_set_intr) smx_pio_intr<= `SMX_PD 1'b1; |
| 167 | else if (pio_smx_clear_intr) smx_pio_intr<= `SMX_PD 1'b0; |
| 168 | end |
| 169 | |
| 170 | always @(posedge clk) begin |
| 171 | if(!reset_l) |
| 172 | pio_status_tohdl<= `SMX_PD 6'h0; |
| 173 | else |
| 174 | if(tohdl_set_intr) pio_status_tohdl<= `SMX_PD tohdl_intr_status; |
| 175 | else if (pio_smx_clear_intr) pio_status_tohdl<= `SMX_PD 6'h0; |
| 176 | end |
| 177 | |
| 178 | always @(posedge clk) begin |
| 179 | if(!reset_l) |
| 180 | int_status<= `SMX_PD 26'h0; |
| 181 | else |
| 182 | int_status<= `SMX_PD {3'h0, |
| 183 | sii_cs, arb_cs, |
| 184 | rdreq_cmd_cs, wreq_cmd_cs, |
| 185 | wreq_dv_cs, dreq_cs, |
| 186 | proc_cs, cmdl_cs, dv_cs}; |
| 187 | end |
| 188 | |
| 189 | |
| 190 | |
| 191 | always @(posedge clk) begin |
| 192 | if(!reset_l) |
| 193 | reg_smx_cfg<= `SMX_PD {32'hFFFFFFFF}; // cc 051905 to default enable |
| 194 | else // disable ras for now ???? |
| 195 | // if(pio_ld) // enable when verif env chg to support ??? |
| 196 | reg_smx_cfg<= `SMX_PD pio_data[31:0]; |
| 197 | end |
| 198 | |
| 199 | always @(posedge clk) begin |
| 200 | smx_debug_port<= `SMX_PD smx_debug_port_n; |
| 201 | pio_smx_debug_vector_r<= `SMX_PD pio_smx_debug_vector; |
| 202 | debug_sel<= `SMX_PD pio_smx_ctrl[2:0]; |
| 203 | end |
| 204 | |
| 205 | always @(posedge clk) begin |
| 206 | if(reset_l) begin |
| 207 | pio_xtb_err_inject_cfg<= `SMX_PD 3'h0; |
| 208 | pio_resp_err_inject_cfg<= `SMX_PD 3'h0; |
| 209 | end |
| 210 | else begin |
| 211 | pio_xtb_err_inject_cfg<= `SMX_PD pio_smx_ctrl[6:4]; |
| 212 | pio_resp_err_inject_cfg<= `SMX_PD pio_smx_ctrl[10:8]; |
| 213 | end |
| 214 | end |
| 215 | |
| 216 | always @(posedge clk) begin |
| 217 | int_debug_port<= `SMX_PD { 6'h0, |
| 218 | niu_sii_hdr_vld, |
| 219 | niu_sii_reqbypass, |
| 220 | niu_sii_datareq, |
| 221 | sii_niu_oqdq, |
| 222 | sii_niu_bqdq, |
| 223 | wreq_cmdff_rd, |
| 224 | rdreq_cmdff_rd, |
| 225 | wreq_dataff_rd, |
| 226 | wreq_cmdff_wr, |
| 227 | rdreq_cmdff_wr, |
| 228 | wreq_dataff_wr, |
| 229 | sio_niu_hdr_vld, |
| 230 | sio_niu_datareq, |
| 231 | niu_sio_dq, |
| 232 | resp_cmdff_wr, |
| 233 | resp_dataff_wr, |
| 234 | resp_cmdff_rd, |
| 235 | resp_dataff_rd, |
| 236 | meta_dmc_resp_ready, |
| 237 | meta_dmc_ack_ready, |
| 238 | dmc_meta0_req, |
| 239 | meta_dmc1_req_accept, |
| 240 | dmc_meta1_req, |
| 241 | meta_dmc0_req_accept, |
| 242 | meta_dmc0_data_req, |
| 243 | dmc_meta0_data_valid}; |
| 244 | |
| 245 | end |
| 246 | |
| 247 | |
| 248 | /*AUTO_CONSTANT (`META_ARB__TRAINING_SET `MEGA_ARB__TRAINING_LOAD)*/ |
| 249 | |
| 250 | always @ (/*AUTOSENSE*/ debug_sel or int_debug_port or pio_smx_debug_vector_r |
| 251 | or smx_debug_port) begin |
| 252 | case(debug_sel) |
| 253 | `SMX_TRAINING_SET: smx_debug_port_n= ~smx_debug_port; |
| 254 | `SMX_TRAINING_LOAD: smx_debug_port_n= pio_smx_debug_vector_r; |
| 255 | default: smx_debug_port_n= int_debug_port; |
| 256 | endcase |
| 257 | end |
| 258 | |
| 259 | endmodule |
| 260 | |
| 261 | |
| 262 | |
| 263 | |
| 264 | |
| 265 | |
| 266 | |