| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_smx_sm_req_siireq.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | |
| 36 | |
| 37 | module niu_smx_sm_req_siireq( |
| 38 | /*AUTOARG*/ |
| 39 | // Outputs |
| 40 | niu_sii_hdr_vld, niu_sii_reqbypass, niu_sii_datareq, niu_sii_data, |
| 41 | niu_sii_parity, nxt_xmit, wreq_dataff_rd, sii_cs, siireq_idle, |
| 42 | tid_xmited_set, tid_xmited_set_addr, |
| 43 | // Inputs |
| 44 | clk, reset_l, xmitflag, rwflag, hdr_data, bypass, |
| 45 | wreq_dataff_rdata, wreq_dataff_empty |
| 46 | ); |
| 47 | |
| 48 | input clk; |
| 49 | input reset_l; |
| 50 | |
| 51 | // sii interface |
| 52 | output niu_sii_hdr_vld; |
| 53 | output niu_sii_reqbypass; |
| 54 | output niu_sii_datareq; |
| 55 | output [127:0] niu_sii_data; |
| 56 | output [7:0] niu_sii_parity; |
| 57 | |
| 58 | |
| 59 | // arb interface |
| 60 | input xmitflag; |
| 61 | input rwflag; // 0= rd, 1= wr |
| 62 | input [128:0] hdr_data; // [128] valid bit |
| 63 | input bypass; |
| 64 | output nxt_xmit; // arb to update xmit flag |
| 65 | |
| 66 | |
| 67 | // dataff if |
| 68 | output wreq_dataff_rd; |
| 69 | input [127:0] wreq_dataff_rdata; |
| 70 | input wreq_dataff_empty; // not use for now??? |
| 71 | |
| 72 | output [1:0] sii_cs; |
| 73 | |
| 74 | // stall_hdlr if |
| 75 | output siireq_idle; |
| 76 | |
| 77 | // status file interface |
| 78 | output tid_xmited_set; // rst by sii_req |
| 79 | output [5:0] tid_xmited_set_addr; |
| 80 | |
| 81 | parameter sii_s0= 2'h0, |
| 82 | sii_s1= 2'h1; |
| 83 | |
| 84 | reg inc_wcnt_n, rst_wcnt_n; |
| 85 | reg [2:0] wcnt; |
| 86 | reg nxt_xmit_n; |
| 87 | wire nxt_xmit= nxt_xmit_n; |
| 88 | wire wcnt_done_n= (wcnt==`SMX_DATA_CYCLES); |
| 89 | |
| 90 | reg niu_sii_hdr_vld_n, niu_sii_hdr_vld ; |
| 91 | reg niu_sii_datareq_n, niu_sii_datareq; |
| 92 | reg ld_hdr_n; |
| 93 | reg ld_data_n; |
| 94 | reg wreq_dataff_rd_n; |
| 95 | reg [1:0] sii_ns, sii_cs; |
| 96 | |
| 97 | wire siireq_idle= (sii_cs==sii_s0) && !xmitflag; |
| 98 | |
| 99 | wire tag_is_valid_n= hdr_data[128]; // added 121405 - end |
| 100 | reg tid_xmited_set; |
| 101 | wire [5:0] tid_xmited_set_addr= hdr_data[79:74]; |
| 102 | |
| 103 | always @(/*AUTOSENSE*/`SMX_REQARB_WR or rwflag or sii_cs |
| 104 | or tag_is_valid_n or wcnt_done_n or xmitflag) begin |
| 105 | tid_xmited_set= 1'b0; |
| 106 | niu_sii_hdr_vld_n= 1'b0; |
| 107 | niu_sii_datareq_n= 1'b0; |
| 108 | nxt_xmit_n= 1'b0; |
| 109 | ld_hdr_n= 1'b0; |
| 110 | ld_data_n= 1'b0; |
| 111 | wreq_dataff_rd_n= 1'b0; |
| 112 | inc_wcnt_n= 1'b0; |
| 113 | rst_wcnt_n= 1'b0; |
| 114 | sii_ns= sii_cs; |
| 115 | case(sii_cs) |
| 116 | sii_s0: begin |
| 117 | if(xmitflag) begin |
| 118 | niu_sii_hdr_vld_n= tag_is_valid_n; // changed 121405 |
| 119 | niu_sii_datareq_n= (rwflag==`SMX_REQARB_WR); |
| 120 | ld_hdr_n= 1'b1; |
| 121 | sii_ns= (rwflag==`SMX_REQARB_WR)? sii_s1 : sii_s0; |
| 122 | nxt_xmit_n= 1'b1; |
| 123 | rst_wcnt_n= 1'b1; |
| 124 | tid_xmited_set= tag_is_valid_n; // set xmited flag; use by timer |
| 125 | end |
| 126 | end |
| 127 | sii_s1: begin // wr data xfer |
| 128 | ld_data_n= 1'b1; |
| 129 | wreq_dataff_rd_n= 1'b1; |
| 130 | inc_wcnt_n= 1'b1; |
| 131 | sii_ns= (wcnt_done_n)? sii_s0 : sii_s1; |
| 132 | end |
| 133 | endcase |
| 134 | end |
| 135 | |
| 136 | reg niu_sii_reqbypass; |
| 137 | reg [127:0] niu_sii_data; |
| 138 | |
| 139 | wire [7:0] niu_hdr_parity_n= 8'h0; |
| 140 | |
| 141 | // little endian -> big endian |
| 142 | wire [127:0] niu_sii_data_n= { wreq_dataff_rdata[`SMX_LE_B0], |
| 143 | wreq_dataff_rdata[`SMX_LE_B1], |
| 144 | wreq_dataff_rdata[`SMX_LE_B2], |
| 145 | wreq_dataff_rdata[`SMX_LE_B3], |
| 146 | wreq_dataff_rdata[`SMX_LE_B4], |
| 147 | wreq_dataff_rdata[`SMX_LE_B5], |
| 148 | wreq_dataff_rdata[`SMX_LE_B6], |
| 149 | wreq_dataff_rdata[`SMX_LE_B7], |
| 150 | wreq_dataff_rdata[`SMX_LE_B8], |
| 151 | wreq_dataff_rdata[`SMX_LE_B9], |
| 152 | wreq_dataff_rdata[`SMX_LE_B10], |
| 153 | wreq_dataff_rdata[`SMX_LE_B11], |
| 154 | wreq_dataff_rdata[`SMX_LE_B12], |
| 155 | wreq_dataff_rdata[`SMX_LE_B13], |
| 156 | wreq_dataff_rdata[`SMX_LE_B14], |
| 157 | wreq_dataff_rdata[`SMX_LE_B15] |
| 158 | }; |
| 159 | /* |
| 160 | wire [15:0] e0_niu_sii_data_n={ |
| 161 | niu_sii_data_n[30], niu_sii_data_n[28], |
| 162 | niu_sii_data_n[26], niu_sii_data_n[24], |
| 163 | niu_sii_data_n[22], niu_sii_data_n[20], |
| 164 | niu_sii_data_n[18], niu_sii_data_n[16], |
| 165 | niu_sii_data_n[14], niu_sii_data_n[12], |
| 166 | niu_sii_data_n[10], niu_sii_data_n[8], |
| 167 | niu_sii_data_n[6], niu_sii_data_n[4], |
| 168 | niu_sii_data_n[2], niu_sii_data_n[0] |
| 169 | }; |
| 170 | wire [15:0] e1_niu_sii_data_n={ |
| 171 | niu_sii_data_n[62], niu_sii_data_n[60], |
| 172 | niu_sii_data_n[58], niu_sii_data_n[56], |
| 173 | niu_sii_data_n[54], niu_sii_data_n[52], |
| 174 | niu_sii_data_n[50], niu_sii_data_n[48], |
| 175 | niu_sii_data_n[46], niu_sii_data_n[44], |
| 176 | niu_sii_data_n[42], niu_sii_data_n[40], |
| 177 | niu_sii_data_n[38], niu_sii_data_n[36], |
| 178 | niu_sii_data_n[34], niu_sii_data_n[32] |
| 179 | }; |
| 180 | wire [15:0] e2_niu_sii_data_n={ |
| 181 | niu_sii_data_n[94], niu_sii_data_n[92], |
| 182 | niu_sii_data_n[90], niu_sii_data_n[88], |
| 183 | niu_sii_data_n[86], niu_sii_data_n[84], |
| 184 | niu_sii_data_n[82], niu_sii_data_n[80], |
| 185 | niu_sii_data_n[78], niu_sii_data_n[76], |
| 186 | niu_sii_data_n[74], niu_sii_data_n[72], |
| 187 | niu_sii_data_n[70], niu_sii_data_n[68], |
| 188 | niu_sii_data_n[66], niu_sii_data_n[64] |
| 189 | }; |
| 190 | wire [15:0] e3_niu_sii_data_n={ |
| 191 | niu_sii_data_n[126], niu_sii_data_n[124], |
| 192 | niu_sii_data_n[122], niu_sii_data_n[120], |
| 193 | niu_sii_data_n[118], niu_sii_data_n[116], |
| 194 | niu_sii_data_n[114], niu_sii_data_n[112], |
| 195 | niu_sii_data_n[110], niu_sii_data_n[108], |
| 196 | niu_sii_data_n[106], niu_sii_data_n[104], |
| 197 | niu_sii_data_n[102], niu_sii_data_n[100], |
| 198 | niu_sii_data_n[98], niu_sii_data_n[96] |
| 199 | }; |
| 200 | |
| 201 | wire [15:0] o0_niu_sii_data_n={ |
| 202 | niu_sii_data_n[31], niu_sii_data_n[29], |
| 203 | niu_sii_data_n[27], niu_sii_data_n[25], |
| 204 | niu_sii_data_n[23], niu_sii_data_n[21], |
| 205 | niu_sii_data_n[19], niu_sii_data_n[17], |
| 206 | niu_sii_data_n[15], niu_sii_data_n[13], |
| 207 | niu_sii_data_n[11], niu_sii_data_n[9], |
| 208 | niu_sii_data_n[7], niu_sii_data_n[5], |
| 209 | niu_sii_data_n[3], niu_sii_data_n[1] |
| 210 | }; |
| 211 | wire [15:0] o1_niu_sii_data_n={ |
| 212 | niu_sii_data_n[63], niu_sii_data_n[61], |
| 213 | niu_sii_data_n[59], niu_sii_data_n[57], |
| 214 | niu_sii_data_n[55], niu_sii_data_n[53], |
| 215 | niu_sii_data_n[51], niu_sii_data_n[49], |
| 216 | niu_sii_data_n[47], niu_sii_data_n[45], |
| 217 | niu_sii_data_n[43], niu_sii_data_n[41], |
| 218 | niu_sii_data_n[39], niu_sii_data_n[37], |
| 219 | niu_sii_data_n[35], niu_sii_data_n[33] |
| 220 | }; |
| 221 | wire [15:0] o2_niu_sii_data_n={ |
| 222 | niu_sii_data_n[95], niu_sii_data_n[93], |
| 223 | niu_sii_data_n[91], niu_sii_data_n[89], |
| 224 | niu_sii_data_n[87], niu_sii_data_n[85], |
| 225 | niu_sii_data_n[83], niu_sii_data_n[81], |
| 226 | niu_sii_data_n[79], niu_sii_data_n[77], |
| 227 | niu_sii_data_n[75], niu_sii_data_n[73], |
| 228 | niu_sii_data_n[71], niu_sii_data_n[69], |
| 229 | niu_sii_data_n[67], niu_sii_data_n[65] |
| 230 | }; |
| 231 | wire [15:0] o3_niu_sii_data_n={ |
| 232 | niu_sii_data_n[127], niu_sii_data_n[125], |
| 233 | niu_sii_data_n[123], niu_sii_data_n[121], |
| 234 | niu_sii_data_n[119], niu_sii_data_n[117], |
| 235 | niu_sii_data_n[115], niu_sii_data_n[113], |
| 236 | niu_sii_data_n[111], niu_sii_data_n[109], |
| 237 | niu_sii_data_n[107], niu_sii_data_n[105], |
| 238 | niu_sii_data_n[103], niu_sii_data_n[101], |
| 239 | niu_sii_data_n[99], niu_sii_data_n[97] |
| 240 | }; |
| 241 | */ |
| 242 | |
| 243 | /* |
| 244 | assign niu_sii_parity_n[0]= ~(^e0_niu_sii_data_n); |
| 245 | assign niu_sii_parity_n[2]= ~(^e1_niu_sii_data_n); |
| 246 | assign niu_sii_parity_n[4]= ~(^e2_niu_sii_data_n); |
| 247 | assign niu_sii_parity_n[6]= ~(^e3_niu_sii_data_n); |
| 248 | |
| 249 | assign niu_sii_parity_n[1]= ~(^o0_niu_sii_data_n); |
| 250 | assign niu_sii_parity_n[3]= ~(^o1_niu_sii_data_n); |
| 251 | assign niu_sii_parity_n[5]= ~(^o2_niu_sii_data_n); |
| 252 | assign niu_sii_parity_n[7]= ~(^o3_niu_sii_data_n); |
| 253 | */ |
| 254 | |
| 255 | reg [7:0] niu_sii_parity; |
| 256 | wire [7:0] niu_sii_parity_n; |
| 257 | |
| 258 | niu_smx_gen_siudp gen_siudp( // gen parity per N2 ras |
| 259 | .data (niu_sii_data_n [127:0]), |
| 260 | .parity (niu_sii_parity_n [7:0]) |
| 261 | ); |
| 262 | |
| 263 | |
| 264 | wire cmd_parity_n= ~(^hdr_data[`SMX_SICMD_POS_CMD]); |
| 265 | |
| 266 | wire [39:0] pa_hdr_data= hdr_data[`SMX_SICMD_POS_PA]; |
| 267 | wire [19:0] e_pa_hdr_data={ |
| 268 | pa_hdr_data[38], pa_hdr_data[36], |
| 269 | pa_hdr_data[34], pa_hdr_data[32], |
| 270 | pa_hdr_data[30], pa_hdr_data[28], |
| 271 | pa_hdr_data[26], pa_hdr_data[24], |
| 272 | pa_hdr_data[22], pa_hdr_data[20], |
| 273 | pa_hdr_data[18], pa_hdr_data[16], |
| 274 | pa_hdr_data[14], pa_hdr_data[12], |
| 275 | pa_hdr_data[10], pa_hdr_data[8], |
| 276 | pa_hdr_data[6], pa_hdr_data[4], |
| 277 | pa_hdr_data[2], pa_hdr_data[0] |
| 278 | }; |
| 279 | wire [19:0] o_pa_hdr_data={ |
| 280 | pa_hdr_data[39], pa_hdr_data[37], |
| 281 | pa_hdr_data[35], pa_hdr_data[33], |
| 282 | pa_hdr_data[31], pa_hdr_data[29], |
| 283 | pa_hdr_data[27], pa_hdr_data[25], |
| 284 | pa_hdr_data[23], pa_hdr_data[21], |
| 285 | pa_hdr_data[19], pa_hdr_data[17], |
| 286 | pa_hdr_data[15], pa_hdr_data[13], |
| 287 | pa_hdr_data[11], pa_hdr_data[9], |
| 288 | pa_hdr_data[7], pa_hdr_data[5], |
| 289 | pa_hdr_data[3], pa_hdr_data[1] |
| 290 | }; |
| 291 | wire [1:0] pa_parity_n= {~(^o_pa_hdr_data), ~(^e_pa_hdr_data)}; |
| 292 | |
| 293 | wire [5:0] tid_ecc_n; |
| 294 | |
| 295 | niu_smx_ecc16_genpar ecc_genpar( |
| 296 | .data (hdr_data[`SMX_SICMD_POS_ID]), |
| 297 | .chkbit (5'h0), |
| 298 | .parity (tid_ecc_n[5:0]), |
| 299 | .cor_parity_5 () // nc |
| 300 | ); |
| 301 | |
| 302 | wire [127:0] niu_hdr_data_n= { hdr_data[`SMX_SICMD_POS_CMD], |
| 303 | hdr_data[`SMX_SICMD_POS_RSV0], |
| 304 | pa_parity_n, |
| 305 | hdr_data[`SMX_SICMD_POS_ERR], |
| 306 | hdr_data[`SMX_SICMD_POS_ID], |
| 307 | hdr_data[`SMX_SICMD_POS_RSV1], |
| 308 | cmd_parity_n, |
| 309 | tid_ecc_n, |
| 310 | hdr_data[`SMX_SICMD_POS_RSV2], |
| 311 | hdr_data[`SMX_SICMD_POS_PA] |
| 312 | }; |
| 313 | |
| 314 | always @(posedge clk) begin |
| 315 | if(!reset_l) begin |
| 316 | sii_cs<= `SMX_PD sii_s0; |
| 317 | niu_sii_hdr_vld<= `SMX_PD 1'b0; |
| 318 | niu_sii_datareq<= `SMX_PD 1'b0; |
| 319 | niu_sii_reqbypass<= `SMX_PD 1'b0; |
| 320 | niu_sii_data<= `SMX_PD 128'h0; |
| 321 | niu_sii_parity<= `SMX_PD 8'h0; |
| 322 | end |
| 323 | else begin |
| 324 | sii_cs<= `SMX_PD sii_ns; |
| 325 | niu_sii_hdr_vld<= `SMX_PD niu_sii_hdr_vld_n; |
| 326 | niu_sii_datareq<= `SMX_PD niu_sii_datareq_n; |
| 327 | if(ld_hdr_n) |
| 328 | niu_sii_reqbypass<= `SMX_PD bypass; |
| 329 | else |
| 330 | niu_sii_reqbypass<= `SMX_PD 1'b0; |
| 331 | if(ld_hdr_n) begin |
| 332 | niu_sii_data<= `SMX_PD niu_hdr_data_n; |
| 333 | niu_sii_parity<= `SMX_PD niu_hdr_parity_n; |
| 334 | end |
| 335 | else if (ld_data_n) begin |
| 336 | niu_sii_data<= `SMX_PD niu_sii_data_n; |
| 337 | niu_sii_parity<= `SMX_PD niu_sii_parity_n; |
| 338 | end |
| 339 | end |
| 340 | end |
| 341 | |
| 342 | always @(posedge clk) begin |
| 343 | if(!reset_l) |
| 344 | wcnt<= `SMX_PD 3'h1; |
| 345 | else begin |
| 346 | if(rst_wcnt_n) wcnt<= `SMX_PD 3'h1; // start with 1 |
| 347 | else if(inc_wcnt_n) wcnt<= `SMX_PD wcnt + 1'b1; |
| 348 | end |
| 349 | end |
| 350 | |
| 351 | wire wreq_dataff_rd= wreq_dataff_rd_n; |
| 352 | endmodule |
| 353 | |
| 354 | |
| 355 | |
| 356 | |