| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_smx_stall_hdlr.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | |
| 36 | module niu_smx_stall_hdlr( |
| 37 | /*AUTOARG*/ |
| 38 | // Outputs |
| 39 | niu_dbg1_stall_ack, stall_enable, |
| 40 | // Inputs |
| 41 | clk, reset_l, dbg1_niu_stall, dbg1_niu_resume, |
| 42 | tid_valid_rdata_bus, wreq_cmdreq_idle, rdreq_cmdreq_idle, |
| 43 | wreq_cmdff_empty, rdreq_cmdff_empty, siireq_idle, |
| 44 | smx_nc_err |
| 45 | ); |
| 46 | |
| 47 | input clk; |
| 48 | input reset_l; |
| 49 | |
| 50 | input dbg1_niu_stall; |
| 51 | input dbg1_niu_resume; |
| 52 | output niu_dbg1_stall_ack; |
| 53 | |
| 54 | |
| 55 | // status if |
| 56 | input [63:0] tid_valid_rdata_bus; |
| 57 | output stall_enable; |
| 58 | |
| 59 | input wreq_cmdreq_idle; |
| 60 | input rdreq_cmdreq_idle; |
| 61 | input wreq_cmdff_empty; |
| 62 | input rdreq_cmdff_empty; |
| 63 | input siireq_idle; |
| 64 | |
| 65 | input smx_nc_err; //non-recoverable error |
| 66 | |
| 67 | |
| 68 | parameter stall_s0= 2'h0, |
| 69 | stall_s1= 2'h1, |
| 70 | stall_s2= 2'h2; |
| 71 | |
| 72 | reg niu_dbg1_stall_ack, niu_dbg1_stall_ack_n; |
| 73 | reg stall; |
| 74 | reg set_stall_n, rst_stall_n; |
| 75 | reg [1:0] stall_cs, stall_ns; |
| 76 | reg tid_done; |
| 77 | reg dbg1_niu_stall_r; |
| 78 | reg dbg1_niu_resume_r; |
| 79 | |
| 80 | wire stall_enable= stall | smx_nc_err; |
| 81 | |
| 82 | wire all_done_n= tid_done && wreq_cmdreq_idle && rdreq_cmdreq_idle && |
| 83 | wreq_cmdff_empty && rdreq_cmdff_empty && siireq_idle; |
| 84 | |
| 85 | always @(posedge clk) begin |
| 86 | if(!reset_l) begin |
| 87 | dbg1_niu_stall_r<= `SMX_PD 1'b0; |
| 88 | dbg1_niu_resume_r<= `SMX_PD 1'b0; |
| 89 | tid_done<= `SMX_PD 1'b0; |
| 90 | end |
| 91 | else begin |
| 92 | dbg1_niu_stall_r<= `SMX_PD dbg1_niu_stall; |
| 93 | dbg1_niu_resume_r<= `SMX_PD dbg1_niu_resume; |
| 94 | tid_done<= `SMX_PD ~(|tid_valid_rdata_bus); |
| 95 | end |
| 96 | end |
| 97 | |
| 98 | always @(posedge clk) begin |
| 99 | if(!reset_l) begin |
| 100 | niu_dbg1_stall_ack<= `SMX_PD 1'b0; |
| 101 | stall<= `SMX_PD 1'b0; |
| 102 | stall_cs<= `SMX_PD 2'h0; |
| 103 | end |
| 104 | else begin |
| 105 | niu_dbg1_stall_ack<= `SMX_PD niu_dbg1_stall_ack_n; |
| 106 | if(set_stall_n) stall<= `SMX_PD 1'b1; |
| 107 | else if(rst_stall_n) stall<= `SMX_PD 1'b0; |
| 108 | stall_cs<= `SMX_PD stall_ns; |
| 109 | end |
| 110 | end |
| 111 | |
| 112 | always @ (/*AUTOSENSE*/all_done_n or dbg1_niu_resume_r |
| 113 | or dbg1_niu_stall_r or stall_cs) begin |
| 114 | niu_dbg1_stall_ack_n= 1'b0; |
| 115 | set_stall_n= 1'b0; |
| 116 | rst_stall_n= 1'b0; |
| 117 | stall_ns= stall_cs; |
| 118 | case(stall_cs) |
| 119 | stall_s0: begin // idle; wait dbg1 stall |
| 120 | if(dbg1_niu_stall_r) begin |
| 121 | set_stall_n= 1'b1; |
| 122 | stall_ns= stall_s1; |
| 123 | end |
| 124 | end |
| 125 | stall_s1: begin // wait all done |
| 126 | if(all_done_n) begin |
| 127 | niu_dbg1_stall_ack_n= 1'b1; |
| 128 | stall_ns= stall_s2; |
| 129 | end |
| 130 | end |
| 131 | stall_s2: begin // wait resume |
| 132 | if(dbg1_niu_resume_r) begin |
| 133 | rst_stall_n= 1'b1; |
| 134 | stall_ns= stall_s0; |
| 135 | end |
| 136 | end |
| 137 | endcase |
| 138 | end |
| 139 | |
| 140 | endmodule |
| 141 | |