| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_smx_status.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | |
| 36 | module niu_smx_status( |
| 37 | /*AUTOARG*/ |
| 38 | // Outputs |
| 39 | tid_valid_rdata, tid_valid_rdata_bus, tid_newarr_rdata, |
| 40 | tid_newarr_rdata_bus, resp_rcv_rdata, resp_rcv_rdata_bus, |
| 41 | timeout_rdata, timeout_rdata_bus, tid_xmited_rdata_bus, |
| 42 | tid_dirty_rdata_bus, |
| 43 | // Inputs |
| 44 | clk, reset_l, tid_valid_rst0, tid_valid_rst1, tid_valid_rst_addr0, |
| 45 | tid_valid_rst_addr1, tid_valid_set, tid_valid_set_addr, |
| 46 | tid_valid_rd, tid_valid_raddr, tid_newarr_rst, |
| 47 | tid_newarr_rst_addr, tid_newarr_set, tid_newarr_set_addr, |
| 48 | tid_newarr_rd, tid_newarr_raddr, resp_rcv_rst, resp_rcv_rst_addr, |
| 49 | resp_rcv_set, resp_rcv_set_addr, resp_rcv_rd, resp_rcv_raddr, |
| 50 | timeout_set, timeout_rst, timeout_set_addr, timeout_rst_addr, |
| 51 | timeout_rd, timeout_raddr, tid_xmited_set, tid_xmited_set_addr |
| 52 | ); |
| 53 | |
| 54 | input clk; |
| 55 | input reset_l; |
| 56 | input tid_valid_rst0; // rst by resp_cmdproc |
| 57 | input tid_valid_rst1; // rst by timer |
| 58 | input [5:0] tid_valid_rst_addr0; |
| 59 | input [5:0] tid_valid_rst_addr1; |
| 60 | input tid_valid_set; // set by req_cmd |
| 61 | input [5:0] tid_valid_set_addr; |
| 62 | |
| 63 | input tid_valid_rd; // rd by resp_cmdproc |
| 64 | input [5:0] tid_valid_raddr; |
| 65 | output tid_valid_rdata; |
| 66 | output [63:0] tid_valid_rdata_bus; // rd by timer |
| 67 | |
| 68 | input tid_newarr_rst; // rst by timer |
| 69 | input [5:0] tid_newarr_rst_addr; |
| 70 | input tid_newarr_set; // set by req_cmd |
| 71 | input [5:0] tid_newarr_set_addr; |
| 72 | |
| 73 | input tid_newarr_rd; // rd by timer |
| 74 | input [5:0] tid_newarr_raddr; |
| 75 | output tid_newarr_rdata; |
| 76 | output [63:0] tid_newarr_rdata_bus; // rd by timer |
| 77 | |
| 78 | input resp_rcv_rst; // rst by timer |
| 79 | input [5:0] resp_rcv_rst_addr; |
| 80 | input resp_rcv_set; // set by resp_cmdproc |
| 81 | input [5:0] resp_rcv_set_addr; |
| 82 | |
| 83 | input resp_rcv_rd; // rd by timer |
| 84 | input [5:0] resp_rcv_raddr; |
| 85 | output resp_rcv_rdata; |
| 86 | output [63:0] resp_rcv_rdata_bus; // (rd by timer) |
| 87 | |
| 88 | input timeout_set; // set by timer |
| 89 | input timeout_rst; // rst by tohdlr |
| 90 | input [5:0] timeout_set_addr; |
| 91 | input [5:0] timeout_rst_addr; |
| 92 | input timeout_rd; // rd by tohdlr |
| 93 | input [5:0] timeout_raddr; |
| 94 | output timeout_rdata; |
| 95 | output [63:0] timeout_rdata_bus; // rd by tohdlr |
| 96 | |
| 97 | input tid_xmited_set; // rst by sii_req |
| 98 | input [5:0] tid_xmited_set_addr; |
| 99 | output [63:0] tid_xmited_rdata_bus; // rd by timer |
| 100 | |
| 101 | output [63:0] tid_dirty_rdata_bus; |
| 102 | |
| 103 | /* |
| 104 | niu_smx_arb_2c #(6) arb_tid_valid( |
| 105 | .req_a (tid_valid_rst0), |
| 106 | .req_b (tid_valid_rst1), |
| 107 | .muxin_a (tid_valid_rst_addr0 [5:0]), |
| 108 | .muxin_b (tid_valid_rst_addr1 [5:0]), |
| 109 | .ack_a (tid_valid_rst0_ack), |
| 110 | .ack_b (tid_valid_rst1_ack), |
| 111 | .selout (tid_valid_rst_addr [5:0]) |
| 112 | ); |
| 113 | */ |
| 114 | |
| 115 | |
| 116 | // 1 - valid |
| 117 | // 0 - non-valid |
| 118 | niu_smx_regflag tid_valid_flag( |
| 119 | .clk (clk), |
| 120 | .reset_l (reset_l), |
| 121 | .set (tid_valid_set), |
| 122 | .rst0 (tid_valid_rst0), |
| 123 | .rst1 (tid_valid_rst1), |
| 124 | .set_addr (tid_valid_set_addr [5:0]), |
| 125 | .rst_addr0 (tid_valid_rst_addr0 [5:0]), |
| 126 | .rst_addr1 (tid_valid_rst_addr1 [5:0]), |
| 127 | .rst_first (1'b1), |
| 128 | .rd (tid_valid_rd), |
| 129 | .raddr (tid_valid_raddr [5:0]), |
| 130 | .rdata (tid_valid_rdata), |
| 131 | .rdata_bus (tid_valid_rdata_bus [63:0]) |
| 132 | ); |
| 133 | |
| 134 | wire tid_dirty_rdata; |
| 135 | wire tid_dirty_set= tid_valid_rst1 | // set this same time as valid rst by timer |
| 136 | (tid_dirty_rdata & 1'b0); // avoid vlint since tid_dirty_rdata not use |
| 137 | wire [5:0] tid_dirty_set_addr= tid_valid_rst_addr1; |
| 138 | wire tid_dirty_rst0= tid_valid_set; // reset dirty same time as valid entry set; |
| 139 | wire [5:0] tid_dirty_rst_addr0= tid_valid_set_addr; |
| 140 | |
| 141 | niu_smx_regflag tid_dirty_flag( |
| 142 | .clk (clk), |
| 143 | .reset_l (reset_l), |
| 144 | .set (tid_dirty_set), |
| 145 | .rst0 (tid_dirty_rst0), |
| 146 | .rst1 (1'b0), |
| 147 | .set_addr (tid_dirty_set_addr [5:0]), |
| 148 | .rst_addr0 (tid_dirty_rst_addr0 [5:0]), |
| 149 | .rst_addr1 (tid_dirty_rst_addr0 [5:0]), |
| 150 | .rst_first (1'b1), |
| 151 | .rd (1'b0), |
| 152 | .raddr (6'h0), |
| 153 | .rdata (tid_dirty_rdata), |
| 154 | .rdata_bus (tid_dirty_rdata_bus [63:0]) |
| 155 | ); |
| 156 | |
| 157 | |
| 158 | |
| 159 | /* |
| 160 | niu_smx_arb_2c #(6) arb_resp_rcv( |
| 161 | .req_a (resp_rcv_rst0), |
| 162 | .req_b (resp_rcv_rst1), |
| 163 | .muxin_a (resp_rcv_rst_addr0 [5:0]), |
| 164 | .muxin_b (resp_rcv_rst_addr1 [5:0]), |
| 165 | .ack_a (resp_rcv_rst0_ack), |
| 166 | .ack_b (resp_rcv_rst1_ack), |
| 167 | .selout (resp_rcv_rst_addr [5:0]) |
| 168 | ); |
| 169 | */ |
| 170 | |
| 171 | niu_smx_regflag resp_rcv_flag( |
| 172 | .clk (clk), |
| 173 | .reset_l (reset_l), |
| 174 | .set (resp_rcv_set), |
| 175 | .rst0 (resp_rcv_rst), |
| 176 | .rst1 (1'b0), |
| 177 | .set_addr (resp_rcv_set_addr [5:0]), |
| 178 | .rst_addr0 (resp_rcv_rst_addr [5:0]), |
| 179 | .rst_addr1 (resp_rcv_rst_addr [5:0]), |
| 180 | .rst_first (1'b0), |
| 181 | .rd (resp_rcv_rd), |
| 182 | .raddr (resp_rcv_raddr [5:0]), |
| 183 | .rdata (resp_rcv_rdata), |
| 184 | .rdata_bus (resp_rcv_rdata_bus [63:0]) |
| 185 | ); |
| 186 | |
| 187 | niu_smx_regflag timeout_flag( |
| 188 | .clk (clk), |
| 189 | .reset_l (reset_l), |
| 190 | .set (timeout_set), |
| 191 | .rst0 (timeout_rst), |
| 192 | .rst1 (1'b0), |
| 193 | .set_addr (timeout_set_addr [5:0]), |
| 194 | .rst_addr0 (timeout_rst_addr [5:0]), |
| 195 | .rst_addr1 (timeout_rst_addr [5:0]), |
| 196 | .rst_first (1'b0), |
| 197 | .rd (timeout_rd), |
| 198 | .raddr (timeout_raddr [5:0]), |
| 199 | .rdata (timeout_rdata ), |
| 200 | .rdata_bus (timeout_rdata_bus [63:0]) |
| 201 | ); |
| 202 | |
| 203 | niu_smx_regflag tid_newarr_flag( |
| 204 | .clk (clk), |
| 205 | .reset_l (reset_l), |
| 206 | .set (tid_newarr_set), |
| 207 | .rst0 (tid_newarr_rst), |
| 208 | .rst1 (1'b0), |
| 209 | .set_addr (tid_newarr_set_addr [5:0]), |
| 210 | .rst_addr0 (tid_newarr_rst_addr [5:0]), |
| 211 | .rst_addr1 (tid_newarr_rst_addr [5:0]), |
| 212 | .rst_first (1'b0), |
| 213 | .rd (tid_newarr_rd), |
| 214 | .raddr (tid_newarr_raddr [5:0]), |
| 215 | .rdata (tid_newarr_rdata ), |
| 216 | .rdata_bus (tid_newarr_rdata_bus [63:0]) |
| 217 | ); |
| 218 | |
| 219 | wire tid_xmited_rdata; // not use; put this to avoid vlint null port |
| 220 | // rst xmited bit at beginning of a transaction request |
| 221 | wire tid_xmited_rst= tid_valid_set | (tid_xmited_rdata & (1'b0)); |
| 222 | wire [5:0] tid_xmited_rst_addr= tid_valid_set_addr; |
| 223 | |
| 224 | niu_smx_regflag tid_xmited_flag( |
| 225 | .clk (clk), |
| 226 | .reset_l (reset_l), |
| 227 | .set (tid_xmited_set), |
| 228 | .rst0 (tid_xmited_rst), |
| 229 | .rst1 (1'b0), |
| 230 | .set_addr (tid_xmited_set_addr [5:0]), |
| 231 | .rst_addr0 (tid_xmited_rst_addr [5:0]), |
| 232 | .rst_addr1 (tid_xmited_rst_addr [5:0]), |
| 233 | .rst_first (1'b0), |
| 234 | .rd (1'b0), |
| 235 | .raddr (6'h0), |
| 236 | .rdata (tid_xmited_rdata), |
| 237 | .rdata_bus (tid_xmited_rdata_bus [63:0]) |
| 238 | ); |
| 239 | |
| 240 | |
| 241 | |
| 242 | |
| 243 | endmodule |
| 244 | |
| 245 | |