| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_tdmc_cacheread.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | |
| 36 | |
| 37 | `include "txc_defines.h" |
| 38 | `include "niu_dmc_reg_defines.h" |
| 39 | |
| 40 | module niu_tdmc_cacheread (/*AUTOARG*/ |
| 41 | // Outputs |
| 42 | DMA_TxCacheRead, DMA_TxCacheReadPtr, DMA0_CacheReadGnt, |
| 43 | DMA1_CacheReadGnt, DMA2_CacheReadGnt, DMA3_CacheReadGnt, |
| 44 | DMA4_CacheReadGnt, DMA5_CacheReadGnt, DMA6_CacheReadGnt, |
| 45 | DMA7_CacheReadGnt, DMA8_CacheReadGnt, DMA9_CacheReadGnt, |
| 46 | DMA10_CacheReadGnt, DMA11_CacheReadGnt, DMA12_CacheReadGnt, |
| 47 | DMA13_CacheReadGnt, DMA14_CacheReadGnt, DMA15_CacheReadGnt, |
| 48 | DMA16_CacheReadGnt, DMA17_CacheReadGnt, DMA18_CacheReadGnt, |
| 49 | DMA19_CacheReadGnt, DMA20_CacheReadGnt, DMA21_CacheReadGnt, |
| 50 | DMA22_CacheReadGnt, DMA23_CacheReadGnt, |
| 51 | // Inputs |
| 52 | DMA0_CacheReadPtr, DMA0_CacheReadReq, DMA1_CacheReadPtr, |
| 53 | DMA1_CacheReadReq, DMA2_CacheReadPtr, DMA2_CacheReadReq, |
| 54 | DMA3_CacheReadPtr, DMA3_CacheReadReq, DMA4_CacheReadPtr, |
| 55 | DMA4_CacheReadReq, DMA5_CacheReadPtr, DMA5_CacheReadReq, |
| 56 | DMA6_CacheReadPtr, DMA6_CacheReadReq, DMA7_CacheReadPtr, |
| 57 | DMA7_CacheReadReq, DMA8_CacheReadPtr, DMA8_CacheReadReq, |
| 58 | DMA9_CacheReadPtr, DMA9_CacheReadReq, DMA10_CacheReadPtr, |
| 59 | DMA10_CacheReadReq, DMA11_CacheReadPtr, DMA11_CacheReadReq, |
| 60 | DMA12_CacheReadPtr, DMA12_CacheReadReq, DMA13_CacheReadPtr, |
| 61 | DMA13_CacheReadReq, DMA14_CacheReadPtr, DMA14_CacheReadReq, |
| 62 | DMA15_CacheReadPtr, DMA15_CacheReadReq, DMA16_CacheReadPtr, |
| 63 | DMA16_CacheReadReq, DMA17_CacheReadPtr, DMA17_CacheReadReq, |
| 64 | DMA18_CacheReadPtr, DMA18_CacheReadReq, DMA19_CacheReadPtr, |
| 65 | DMA19_CacheReadReq, DMA20_CacheReadPtr, DMA20_CacheReadReq, |
| 66 | DMA21_CacheReadPtr, DMA21_CacheReadReq, DMA22_CacheReadPtr, |
| 67 | DMA22_CacheReadReq, DMA23_CacheReadPtr, DMA23_CacheReadReq, |
| 68 | SysClk, Reset_L |
| 69 | ); |
| 70 | |
| 71 | output DMA_TxCacheRead; |
| 72 | output [7:0] DMA_TxCacheReadPtr; |
| 73 | |
| 74 | output DMA0_CacheReadGnt; |
| 75 | output DMA1_CacheReadGnt; |
| 76 | output DMA2_CacheReadGnt; |
| 77 | output DMA3_CacheReadGnt; |
| 78 | output DMA4_CacheReadGnt; |
| 79 | output DMA5_CacheReadGnt; |
| 80 | output DMA6_CacheReadGnt; |
| 81 | output DMA7_CacheReadGnt; |
| 82 | output DMA8_CacheReadGnt; |
| 83 | output DMA9_CacheReadGnt; |
| 84 | output DMA10_CacheReadGnt; |
| 85 | output DMA11_CacheReadGnt; |
| 86 | output DMA12_CacheReadGnt; |
| 87 | output DMA13_CacheReadGnt; |
| 88 | output DMA14_CacheReadGnt; |
| 89 | output DMA15_CacheReadGnt; |
| 90 | output DMA16_CacheReadGnt; |
| 91 | output DMA17_CacheReadGnt; |
| 92 | output DMA18_CacheReadGnt; |
| 93 | output DMA19_CacheReadGnt; |
| 94 | output DMA20_CacheReadGnt; |
| 95 | output DMA21_CacheReadGnt; |
| 96 | output DMA22_CacheReadGnt; |
| 97 | output DMA23_CacheReadGnt; |
| 98 | |
| 99 | |
| 100 | |
| 101 | |
| 102 | input [3:0] DMA0_CacheReadPtr; |
| 103 | input DMA0_CacheReadReq; |
| 104 | input [3:0] DMA1_CacheReadPtr; |
| 105 | input DMA1_CacheReadReq; |
| 106 | input [3:0] DMA2_CacheReadPtr; |
| 107 | input DMA2_CacheReadReq; |
| 108 | input [3:0] DMA3_CacheReadPtr; |
| 109 | input DMA3_CacheReadReq; |
| 110 | input [3:0] DMA4_CacheReadPtr; |
| 111 | input DMA4_CacheReadReq; |
| 112 | input [3:0] DMA5_CacheReadPtr; |
| 113 | input DMA5_CacheReadReq; |
| 114 | input [3:0] DMA6_CacheReadPtr; |
| 115 | input DMA6_CacheReadReq; |
| 116 | input [3:0] DMA7_CacheReadPtr; |
| 117 | input DMA7_CacheReadReq; |
| 118 | input [3:0] DMA8_CacheReadPtr; |
| 119 | input DMA8_CacheReadReq; |
| 120 | input [3:0] DMA9_CacheReadPtr; |
| 121 | input DMA9_CacheReadReq; |
| 122 | input [3:0] DMA10_CacheReadPtr; |
| 123 | input DMA10_CacheReadReq; |
| 124 | input [3:0] DMA11_CacheReadPtr; |
| 125 | input DMA11_CacheReadReq; |
| 126 | input [3:0] DMA12_CacheReadPtr; |
| 127 | input DMA12_CacheReadReq; |
| 128 | input [3:0] DMA13_CacheReadPtr; |
| 129 | input DMA13_CacheReadReq; |
| 130 | input [3:0] DMA14_CacheReadPtr; |
| 131 | input DMA14_CacheReadReq; |
| 132 | input [3:0] DMA15_CacheReadPtr; |
| 133 | input DMA15_CacheReadReq; |
| 134 | input [3:0] DMA16_CacheReadPtr; |
| 135 | input DMA16_CacheReadReq; |
| 136 | input [3:0] DMA17_CacheReadPtr; |
| 137 | input DMA17_CacheReadReq; |
| 138 | input [3:0] DMA18_CacheReadPtr; |
| 139 | input DMA18_CacheReadReq; |
| 140 | input [3:0] DMA19_CacheReadPtr; |
| 141 | input DMA19_CacheReadReq; |
| 142 | input [3:0] DMA20_CacheReadPtr; |
| 143 | input DMA20_CacheReadReq; |
| 144 | input [3:0] DMA21_CacheReadPtr; |
| 145 | input DMA21_CacheReadReq; |
| 146 | input [3:0] DMA22_CacheReadPtr; |
| 147 | input DMA22_CacheReadReq; |
| 148 | input [3:0] DMA23_CacheReadPtr; |
| 149 | input DMA23_CacheReadReq; |
| 150 | |
| 151 | |
| 152 | |
| 153 | input SysClk; |
| 154 | input Reset_L; |
| 155 | |
| 156 | |
| 157 | reg DMA_TxCacheRead; |
| 158 | reg [7:0] DMA_TxCacheReadPtr; |
| 159 | |
| 160 | wire [31:0] DMA_CacheReadReq; |
| 161 | wire [31:0] DMA_CacheReadGnt; |
| 162 | wire [4:0] DMA_NoToPop; |
| 163 | wire DMA_ArbForPop; |
| 164 | wire DMA0_CacheReadGnt; |
| 165 | wire DMA1_CacheReadGnt; |
| 166 | wire DMA2_CacheReadGnt; |
| 167 | wire DMA3_CacheReadGnt; |
| 168 | wire DMA4_CacheReadGnt; |
| 169 | wire DMA5_CacheReadGnt; |
| 170 | wire DMA6_CacheReadGnt; |
| 171 | wire DMA7_CacheReadGnt; |
| 172 | wire DMA8_CacheReadGnt; |
| 173 | wire DMA9_CacheReadGnt; |
| 174 | wire DMA10_CacheReadGnt; |
| 175 | wire DMA11_CacheReadGnt; |
| 176 | wire DMA12_CacheReadGnt; |
| 177 | wire DMA13_CacheReadGnt; |
| 178 | wire DMA14_CacheReadGnt; |
| 179 | wire DMA15_CacheReadGnt; |
| 180 | wire DMA16_CacheReadGnt; |
| 181 | wire DMA17_CacheReadGnt; |
| 182 | wire DMA18_CacheReadGnt; |
| 183 | wire DMA19_CacheReadGnt; |
| 184 | wire DMA20_CacheReadGnt; |
| 185 | wire DMA21_CacheReadGnt; |
| 186 | wire DMA22_CacheReadGnt; |
| 187 | wire DMA23_CacheReadGnt; |
| 188 | |
| 189 | |
| 190 | // Arbitration for Cache reads and poping data into TxC ? To be added here |
| 191 | assign DMA_ArbForPop = | DMA_CacheReadReq; |
| 192 | |
| 193 | assign DMA_CacheReadReq ={ 8'h0, |
| 194 | /* -----\/----- EXCLUDED -----\/----- |
| 195 | DMA31_CacheReadReq, DMA30_CacheReadReq, DMA29_CacheReadReq, DMA28_CacheReadReq, |
| 196 | DMA27_CacheReadReq, DMA26_CacheReadReq, DMA25_CacheReadReq, DMA24_CacheReadReq, |
| 197 | -----/\----- EXCLUDED -----/\----- */ |
| 198 | DMA23_CacheReadReq, DMA22_CacheReadReq, DMA21_CacheReadReq, DMA20_CacheReadReq, |
| 199 | DMA19_CacheReadReq, DMA18_CacheReadReq, DMA17_CacheReadReq, DMA16_CacheReadReq, |
| 200 | DMA15_CacheReadReq, DMA14_CacheReadReq, DMA13_CacheReadReq, DMA12_CacheReadReq, |
| 201 | DMA11_CacheReadReq, DMA10_CacheReadReq, DMA9_CacheReadReq, DMA8_CacheReadReq, |
| 202 | DMA7_CacheReadReq, DMA6_CacheReadReq, DMA5_CacheReadReq, DMA4_CacheReadReq, |
| 203 | DMA3_CacheReadReq, DMA2_CacheReadReq, DMA1_CacheReadReq, DMA0_CacheReadReq }; |
| 204 | |
| 205 | assign { DMA23_CacheReadGnt, DMA22_CacheReadGnt, DMA21_CacheReadGnt, DMA20_CacheReadGnt, |
| 206 | DMA19_CacheReadGnt, DMA18_CacheReadGnt, DMA17_CacheReadGnt, DMA16_CacheReadGnt, |
| 207 | DMA15_CacheReadGnt, DMA14_CacheReadGnt, DMA13_CacheReadGnt, DMA12_CacheReadGnt, |
| 208 | DMA11_CacheReadGnt, DMA10_CacheReadGnt, DMA9_CacheReadGnt, DMA8_CacheReadGnt, |
| 209 | DMA7_CacheReadGnt, DMA6_CacheReadGnt, DMA5_CacheReadGnt, DMA4_CacheReadGnt, |
| 210 | DMA3_CacheReadGnt, DMA2_CacheReadGnt, DMA1_CacheReadGnt, DMA0_CacheReadGnt } = DMA_CacheReadGnt[23:0]; |
| 211 | |
| 212 | |
| 213 | niu_dmc_dmaarb dma_pop_arb ( .SysClk(SysClk), |
| 214 | .Reset_L(Reset_L), |
| 215 | .Choose_DMAs(DMA_ArbForPop), |
| 216 | .DMA_Reqs(DMA_CacheReadReq), |
| 217 | .ArbDone(), |
| 218 | .DMANum(DMA_NoToPop), |
| 219 | .DMAsGranted(DMA_CacheReadGnt) |
| 220 | ); |
| 221 | |
| 222 | |
| 223 | |
| 224 | always@(/*AUTOJUNK*/DMA0_CacheReadPtr or DMA10_CacheReadPtr |
| 225 | or DMA11_CacheReadPtr or DMA12_CacheReadPtr |
| 226 | or DMA13_CacheReadPtr or DMA14_CacheReadPtr |
| 227 | or DMA15_CacheReadPtr or DMA16_CacheReadPtr |
| 228 | or DMA17_CacheReadPtr or DMA18_CacheReadPtr |
| 229 | or DMA19_CacheReadPtr or DMA1_CacheReadPtr |
| 230 | or DMA20_CacheReadPtr or DMA21_CacheReadPtr |
| 231 | or DMA22_CacheReadPtr or DMA23_CacheReadPtr |
| 232 | or DMA2_CacheReadPtr or DMA3_CacheReadPtr |
| 233 | or DMA4_CacheReadPtr or DMA5_CacheReadPtr |
| 234 | or DMA6_CacheReadPtr or DMA7_CacheReadPtr |
| 235 | or DMA8_CacheReadPtr or DMA9_CacheReadPtr or DMA_NoToPop |
| 236 | ) begin |
| 237 | case(DMA_NoToPop) // Synopsys full_case parallel_case |
| 238 | // REORDER |
| 239 | `DMA_CHANNEL_ZERO: DMA_TxCacheReadPtr = {5'h0,DMA0_CacheReadPtr[2:0] } + `DMA0_Cache_OFFSET; |
| 240 | `DMA_CHANNEL_ONE: DMA_TxCacheReadPtr = {5'h0,DMA1_CacheReadPtr[2:0] } + `DMA1_Cache_OFFSET; |
| 241 | `DMA_CHANNEL_TWO: DMA_TxCacheReadPtr = {5'h0,DMA2_CacheReadPtr[2:0] } + `DMA2_Cache_OFFSET; |
| 242 | `DMA_CHANNEL_THREE: DMA_TxCacheReadPtr = {5'h0,DMA3_CacheReadPtr[2:0] } + `DMA3_Cache_OFFSET; |
| 243 | `DMA_CHANNEL_FOUR: DMA_TxCacheReadPtr = {5'h0,DMA4_CacheReadPtr[2:0] }+ `DMA4_Cache_OFFSET; |
| 244 | `DMA_CHANNEL_FIVE: DMA_TxCacheReadPtr = {5'h0,DMA5_CacheReadPtr[2:0] }+ `DMA5_Cache_OFFSET; |
| 245 | `DMA_CHANNEL_SIX: DMA_TxCacheReadPtr = {5'h0,DMA6_CacheReadPtr[2:0] }+ `DMA6_Cache_OFFSET; |
| 246 | `DMA_CHANNEL_SEVEN: DMA_TxCacheReadPtr = {5'h0,DMA7_CacheReadPtr[2:0] } + `DMA7_Cache_OFFSET; |
| 247 | `DMA_CHANNEL_EIGHT: DMA_TxCacheReadPtr = {5'h0,DMA8_CacheReadPtr[2:0] } + `DMA8_Cache_OFFSET; |
| 248 | `DMA_CHANNEL_NINE: DMA_TxCacheReadPtr = {5'h0,DMA9_CacheReadPtr[2:0] }+ `DMA9_Cache_OFFSET; |
| 249 | `DMA_CHANNEL_TEN: DMA_TxCacheReadPtr = {5'h0,DMA10_CacheReadPtr[2:0] }+ `DMA10_Cache_OFFSET; |
| 250 | `DMA_CHANNEL_ELEVEN: DMA_TxCacheReadPtr = {5'h0,DMA11_CacheReadPtr[2:0] }+ `DMA11_Cache_OFFSET; |
| 251 | `DMA_CHANNEL_TWELVE: DMA_TxCacheReadPtr = {5'h0,DMA12_CacheReadPtr[2:0] }+ `DMA12_Cache_OFFSET; |
| 252 | `DMA_CHANNEL_THIRTEEN: DMA_TxCacheReadPtr = {5'h0,DMA13_CacheReadPtr[2:0] }+ `DMA13_Cache_OFFSET; |
| 253 | `DMA_CHANNEL_FOURTEEN: DMA_TxCacheReadPtr = {5'h0,DMA14_CacheReadPtr[2:0] }+ `DMA14_Cache_OFFSET; |
| 254 | `DMA_CHANNEL_FIFTEEN: DMA_TxCacheReadPtr = {5'h0,DMA15_CacheReadPtr[2:0] }+ `DMA15_Cache_OFFSET; |
| 255 | `DMA_CHANNEL_SIXTEEN: DMA_TxCacheReadPtr = {5'h0,DMA16_CacheReadPtr[2:0] }+ `DMA16_Cache_OFFSET; |
| 256 | `DMA_CHANNEL_SEVENTEEN: DMA_TxCacheReadPtr = {5'h0,DMA17_CacheReadPtr[2:0] } + `DMA17_Cache_OFFSET; |
| 257 | `DMA_CHANNEL_EIGHTEEN: DMA_TxCacheReadPtr = {5'h0,DMA18_CacheReadPtr[2:0] }+ `DMA18_Cache_OFFSET; |
| 258 | `DMA_CHANNEL_NINETEEN: DMA_TxCacheReadPtr = {5'h0,DMA19_CacheReadPtr[2:0] }+ `DMA19_Cache_OFFSET; |
| 259 | `DMA_CHANNEL_TWENTY: DMA_TxCacheReadPtr = {5'h0,DMA20_CacheReadPtr[2:0] }+ `DMA20_Cache_OFFSET; |
| 260 | `DMA_CHANNEL_TWENTYONE: DMA_TxCacheReadPtr = {5'h0,DMA21_CacheReadPtr[2:0] }+ `DMA21_Cache_OFFSET; |
| 261 | `DMA_CHANNEL_TWENTYTWO: DMA_TxCacheReadPtr = {5'h0,DMA22_CacheReadPtr[2:0] }+ `DMA22_Cache_OFFSET; |
| 262 | `DMA_CHANNEL_TWENTYTHREE: DMA_TxCacheReadPtr = {5'h0,DMA23_CacheReadPtr[2:0] }+ `DMA23_Cache_OFFSET; |
| 263 | default: DMA_TxCacheReadPtr = 8'h0; |
| 264 | endcase // case(DMA_NoToPop) |
| 265 | end // always@ ( DMA_NoToPop or DMA0_CacheReadPtr or DMA1_CacheReadPtr ) |
| 266 | |
| 267 | always@(/*AUTOJUNK*/DMA0_CacheReadGnt or DMA10_CacheReadGnt |
| 268 | or DMA11_CacheReadGnt or DMA12_CacheReadGnt |
| 269 | or DMA13_CacheReadGnt or DMA14_CacheReadGnt |
| 270 | or DMA15_CacheReadGnt or DMA16_CacheReadGnt |
| 271 | or DMA17_CacheReadGnt or DMA18_CacheReadGnt |
| 272 | or DMA19_CacheReadGnt or DMA1_CacheReadGnt |
| 273 | or DMA20_CacheReadGnt or DMA21_CacheReadGnt |
| 274 | or DMA22_CacheReadGnt or DMA23_CacheReadGnt |
| 275 | or DMA2_CacheReadGnt or DMA3_CacheReadGnt |
| 276 | or DMA4_CacheReadGnt or DMA5_CacheReadGnt |
| 277 | or DMA6_CacheReadGnt or DMA7_CacheReadGnt |
| 278 | or DMA8_CacheReadGnt or DMA9_CacheReadGnt or DMA_NoToPop |
| 279 | ) begin |
| 280 | case(DMA_NoToPop) // synopsys full_case parallel_case |
| 281 | `DMA_CHANNEL_ZERO: DMA_TxCacheRead = DMA0_CacheReadGnt; |
| 282 | `DMA_CHANNEL_ONE: DMA_TxCacheRead = DMA1_CacheReadGnt; |
| 283 | `DMA_CHANNEL_TWO: DMA_TxCacheRead = DMA2_CacheReadGnt; |
| 284 | `DMA_CHANNEL_THREE: DMA_TxCacheRead = DMA3_CacheReadGnt; |
| 285 | `DMA_CHANNEL_FOUR: DMA_TxCacheRead = DMA4_CacheReadGnt; |
| 286 | `DMA_CHANNEL_FIVE: DMA_TxCacheRead = DMA5_CacheReadGnt; |
| 287 | `DMA_CHANNEL_SIX: DMA_TxCacheRead = DMA6_CacheReadGnt; |
| 288 | `DMA_CHANNEL_SEVEN: DMA_TxCacheRead = DMA7_CacheReadGnt; |
| 289 | `DMA_CHANNEL_EIGHT: DMA_TxCacheRead = DMA8_CacheReadGnt; |
| 290 | `DMA_CHANNEL_NINE: DMA_TxCacheRead = DMA9_CacheReadGnt; |
| 291 | `DMA_CHANNEL_TEN: DMA_TxCacheRead = DMA10_CacheReadGnt; |
| 292 | `DMA_CHANNEL_ELEVEN: DMA_TxCacheRead = DMA11_CacheReadGnt; |
| 293 | `DMA_CHANNEL_TWELVE: DMA_TxCacheRead = DMA12_CacheReadGnt; |
| 294 | `DMA_CHANNEL_THIRTEEN: DMA_TxCacheRead = DMA13_CacheReadGnt; |
| 295 | `DMA_CHANNEL_FOURTEEN: DMA_TxCacheRead = DMA14_CacheReadGnt; |
| 296 | `DMA_CHANNEL_FIFTEEN: DMA_TxCacheRead = DMA15_CacheReadGnt; |
| 297 | `DMA_CHANNEL_SIXTEEN: DMA_TxCacheRead = DMA16_CacheReadGnt; |
| 298 | `DMA_CHANNEL_SEVENTEEN: DMA_TxCacheRead = DMA17_CacheReadGnt; |
| 299 | `DMA_CHANNEL_EIGHTEEN: DMA_TxCacheRead = DMA18_CacheReadGnt; |
| 300 | `DMA_CHANNEL_NINETEEN: DMA_TxCacheRead = DMA19_CacheReadGnt; |
| 301 | `DMA_CHANNEL_TWENTY: DMA_TxCacheRead = DMA20_CacheReadGnt; |
| 302 | `DMA_CHANNEL_TWENTYONE: DMA_TxCacheRead = DMA21_CacheReadGnt; |
| 303 | `DMA_CHANNEL_TWENTYTWO: DMA_TxCacheRead = DMA22_CacheReadGnt; |
| 304 | `DMA_CHANNEL_TWENTYTHREE: DMA_TxCacheRead = DMA23_CacheReadGnt; |
| 305 | default: DMA_TxCacheRead = 1'b0; |
| 306 | endcase // case(DMA_NoToPop) |
| 307 | end // always@ (... |
| 308 | |
| 309 | |
| 310 | endmodule |