| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_tdmc_mbox.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /********************************************************************* |
| 36 | * |
| 37 | * NIU TDMC MailBox Processing Block |
| 38 | * |
| 39 | * Orignal Author(s): Arvind Srinivasan |
| 40 | * Modifier(s): |
| 41 | * Project(s): Neptune |
| 42 | * |
| 43 | * Copyright (c) 2004 Sun Microsystems, Inc. |
| 44 | * |
| 45 | * All Rights Reserved. |
| 46 | * |
| 47 | * This verilog model is the confidential and proprietary property of |
| 48 | * Sun Microsystems, Inc., and the possession or use of this model |
| 49 | * requires a written license from Sun Microsystems, Inc. |
| 50 | * |
| 51 | **********************************************************************/ |
| 52 | |
| 53 | module niu_tdmc_mbox (/*AUTOJUNK*/ |
| 54 | // Outputs |
| 55 | tdmc_arb0_data, tdmc_arb0_data_valid, tdmc_arb0_req, |
| 56 | tdmc_arb0_req_address, tdmc_arb0_req_byteenable, |
| 57 | tdmc_arb0_req_cmd, tdmc_arb0_req_dma_num, tdmc_arb0_req_length, |
| 58 | tdmc_arb0_req_port_num, tdmc_arb0_status, |
| 59 | tdmc_arb0_transfer_complete, tdmc_arb0_req_func_num, |
| 60 | dmc_meta_ack_accept, mbox_ack_dma_err_received, mbox_err_received, |
| 61 | set_mbox_part_error_dma,mbox_debug_state, clear_cfg_dma0_mb, set_cfg_dma0_mmk, |
| 62 | clear_cfg_dma1_mb, set_cfg_dma1_mmk, clear_cfg_dma2_mb, |
| 63 | set_cfg_dma2_mmk, clear_cfg_dma3_mb, set_cfg_dma3_mmk, |
| 64 | clear_cfg_dma4_mb, set_cfg_dma4_mmk, clear_cfg_dma5_mb, |
| 65 | set_cfg_dma5_mmk, clear_cfg_dma6_mb, set_cfg_dma6_mmk, |
| 66 | clear_cfg_dma7_mb, set_cfg_dma7_mmk, clear_cfg_dma8_mb, |
| 67 | set_cfg_dma8_mmk, clear_cfg_dma9_mb, set_cfg_dma9_mmk, |
| 68 | clear_cfg_dma10_mb, set_cfg_dma10_mmk, clear_cfg_dma11_mb, |
| 69 | set_cfg_dma11_mmk, clear_cfg_dma12_mb, set_cfg_dma12_mmk, |
| 70 | clear_cfg_dma13_mb, set_cfg_dma13_mmk, clear_cfg_dma14_mb, |
| 71 | set_cfg_dma14_mmk, clear_cfg_dma15_mb, set_cfg_dma15_mmk, |
| 72 | `ifdef NEPTUNE |
| 73 | |
| 74 | clear_cfg_dma16_mb, set_cfg_dma16_mmk, clear_cfg_dma17_mb, |
| 75 | set_cfg_dma17_mmk, clear_cfg_dma18_mb, set_cfg_dma18_mmk, |
| 76 | clear_cfg_dma19_mb, set_cfg_dma19_mmk, clear_cfg_dma20_mb, |
| 77 | set_cfg_dma20_mmk, clear_cfg_dma21_mb, set_cfg_dma21_mmk, |
| 78 | clear_cfg_dma22_mb, set_cfg_dma22_mmk, clear_cfg_dma23_mb, |
| 79 | set_cfg_dma23_mmk, |
| 80 | `else |
| 81 | `endif // !ifdef CHANNELS_16 |
| 82 | |
| 83 | set_cfg_dma0_mk, |
| 84 | set_cfg_dma1_mk, set_cfg_dma2_mk, set_cfg_dma3_mk, |
| 85 | set_cfg_dma4_mk, set_cfg_dma5_mk, set_cfg_dma6_mk, |
| 86 | set_cfg_dma7_mk, set_cfg_dma8_mk, set_cfg_dma9_mk, |
| 87 | set_cfg_dma10_mk, set_cfg_dma11_mk, set_cfg_dma12_mk, |
| 88 | set_cfg_dma13_mk, set_cfg_dma14_mk, set_cfg_dma15_mk, |
| 89 | `ifdef NEPTUNE |
| 90 | set_cfg_dma16_mk, set_cfg_dma17_mk, set_cfg_dma18_mk, |
| 91 | set_cfg_dma19_mk, set_cfg_dma20_mk, set_cfg_dma21_mk, |
| 92 | set_cfg_dma22_mk, set_cfg_dma23_mk, |
| 93 | `else |
| 94 | `endif // !ifdef CHANNELS_16 |
| 95 | |
| 96 | // Inputs |
| 97 | SysClk, Reset_L, arb0_tdmc_data_req, arb0_tdmc_req_accept, |
| 98 | meta_dmc_ack_ready, meta_dmc_ack_cmd, meta_dmc_ack_dma_num, |
| 99 | meta_dmc_ack_client, meta_dmc_ack_complete, |
| 100 | meta_dmc_ack_cmd_status, txc_dmc_dma0_mark_bit, tx_cfg_dma0_mk, |
| 101 | tx_cfg_dma0_mmk, tx_cfg_dma0_enable_mb, tx_cs_dma0, |
| 102 | tx_dma0_pre_st, tx_rng_head_dma0, tx_rng_tail_dma0, |
| 103 | tx_dma0_rng_err_logh, tx_dma0_rng_err_logl, |
| 104 | dmc_txc_dma0_page_handle, tx_dma_cfg_dma0_mbaddr, page0_mask_dma0, |
| 105 | page0_value_dma0, page0_reloc_dma0, page0_valid_dma0, |
| 106 | page1_mask_dma0, page1_value_dma0, page1_reloc_dma0, |
| 107 | page1_valid_dma0, txc_dmc_dma1_mark_bit, tx_cfg_dma1_mk, |
| 108 | tx_cfg_dma1_mmk, tx_cfg_dma1_enable_mb, tx_cs_dma1, |
| 109 | tx_dma1_pre_st, tx_rng_head_dma1, tx_rng_tail_dma1, |
| 110 | tx_dma1_rng_err_logh, tx_dma1_rng_err_logl, |
| 111 | dmc_txc_dma1_page_handle, tx_dma_cfg_dma1_mbaddr, page0_mask_dma1, |
| 112 | page0_value_dma1, page0_reloc_dma1, page0_valid_dma1, |
| 113 | page1_mask_dma1, page1_value_dma1, page1_reloc_dma1, |
| 114 | page1_valid_dma1, txc_dmc_dma2_mark_bit, tx_cfg_dma2_mk, |
| 115 | tx_cfg_dma2_mmk, tx_cfg_dma2_enable_mb, tx_cs_dma2, |
| 116 | tx_dma2_pre_st, tx_rng_head_dma2, tx_rng_tail_dma2, |
| 117 | tx_dma2_rng_err_logh, tx_dma2_rng_err_logl, |
| 118 | dmc_txc_dma2_page_handle, tx_dma_cfg_dma2_mbaddr, page0_mask_dma2, |
| 119 | page0_value_dma2, page0_reloc_dma2, page0_valid_dma2, |
| 120 | page1_mask_dma2, page1_value_dma2, page1_reloc_dma2, |
| 121 | page1_valid_dma2, txc_dmc_dma3_mark_bit, tx_cfg_dma3_mk, |
| 122 | tx_cfg_dma3_mmk, tx_cfg_dma3_enable_mb, tx_cs_dma3, |
| 123 | tx_dma3_pre_st, tx_rng_head_dma3, tx_rng_tail_dma3, |
| 124 | tx_dma3_rng_err_logh, tx_dma3_rng_err_logl, |
| 125 | dmc_txc_dma3_page_handle, tx_dma_cfg_dma3_mbaddr, page0_mask_dma3, |
| 126 | page0_value_dma3, page0_reloc_dma3, page0_valid_dma3, |
| 127 | page1_mask_dma3, page1_value_dma3, page1_reloc_dma3, |
| 128 | page1_valid_dma3, txc_dmc_dma4_mark_bit, tx_cfg_dma4_mk, |
| 129 | tx_cfg_dma4_mmk, tx_cfg_dma4_enable_mb, tx_cs_dma4, |
| 130 | tx_dma4_pre_st, tx_rng_head_dma4, tx_rng_tail_dma4, |
| 131 | tx_dma4_rng_err_logh, tx_dma4_rng_err_logl, |
| 132 | dmc_txc_dma4_page_handle, tx_dma_cfg_dma4_mbaddr, page0_mask_dma4, |
| 133 | page0_value_dma4, page0_reloc_dma4, page0_valid_dma4, |
| 134 | page1_mask_dma4, page1_value_dma4, page1_reloc_dma4, |
| 135 | page1_valid_dma4, txc_dmc_dma5_mark_bit, tx_cfg_dma5_mk, |
| 136 | tx_cfg_dma5_mmk, tx_cfg_dma5_enable_mb, tx_cs_dma5, |
| 137 | tx_dma5_pre_st, tx_rng_head_dma5, tx_rng_tail_dma5, |
| 138 | tx_dma5_rng_err_logh, tx_dma5_rng_err_logl, |
| 139 | dmc_txc_dma5_page_handle, tx_dma_cfg_dma5_mbaddr, page0_mask_dma5, |
| 140 | page0_value_dma5, page0_reloc_dma5, page0_valid_dma5, |
| 141 | page1_mask_dma5, page1_value_dma5, page1_reloc_dma5, |
| 142 | page1_valid_dma5, txc_dmc_dma6_mark_bit, tx_cfg_dma6_mk, |
| 143 | tx_cfg_dma6_mmk, tx_cfg_dma6_enable_mb, tx_cs_dma6, |
| 144 | tx_dma6_pre_st, tx_rng_head_dma6, tx_rng_tail_dma6, |
| 145 | tx_dma6_rng_err_logh, tx_dma6_rng_err_logl, |
| 146 | dmc_txc_dma6_page_handle, tx_dma_cfg_dma6_mbaddr, page0_mask_dma6, |
| 147 | page0_value_dma6, page0_reloc_dma6, page0_valid_dma6, |
| 148 | page1_mask_dma6, page1_value_dma6, page1_reloc_dma6, |
| 149 | page1_valid_dma6, txc_dmc_dma7_mark_bit, tx_cfg_dma7_mk, |
| 150 | tx_cfg_dma7_mmk, tx_cfg_dma7_enable_mb, tx_cs_dma7, |
| 151 | tx_dma7_pre_st, tx_rng_head_dma7, tx_rng_tail_dma7, |
| 152 | tx_dma7_rng_err_logh, tx_dma7_rng_err_logl, |
| 153 | dmc_txc_dma7_page_handle, tx_dma_cfg_dma7_mbaddr, page0_mask_dma7, |
| 154 | page0_value_dma7, page0_reloc_dma7, page0_valid_dma7, |
| 155 | page1_mask_dma7, page1_value_dma7, page1_reloc_dma7, |
| 156 | page1_valid_dma7, txc_dmc_dma8_mark_bit, tx_cfg_dma8_mk, |
| 157 | tx_cfg_dma8_mmk, tx_cfg_dma8_enable_mb, tx_cs_dma8, |
| 158 | tx_dma8_pre_st, tx_rng_head_dma8, tx_rng_tail_dma8, |
| 159 | tx_dma8_rng_err_logh, tx_dma8_rng_err_logl, |
| 160 | dmc_txc_dma8_page_handle, tx_dma_cfg_dma8_mbaddr, page0_mask_dma8, |
| 161 | page0_value_dma8, page0_reloc_dma8, page0_valid_dma8, |
| 162 | page1_mask_dma8, page1_value_dma8, page1_reloc_dma8, |
| 163 | page1_valid_dma8, txc_dmc_dma9_mark_bit, tx_cfg_dma9_mk, |
| 164 | tx_cfg_dma9_mmk, tx_cfg_dma9_enable_mb, tx_cs_dma9, |
| 165 | tx_dma9_pre_st, tx_rng_head_dma9, tx_rng_tail_dma9, |
| 166 | tx_dma9_rng_err_logh, tx_dma9_rng_err_logl, |
| 167 | dmc_txc_dma9_page_handle, tx_dma_cfg_dma9_mbaddr, page0_mask_dma9, |
| 168 | page0_value_dma9, page0_reloc_dma9, page0_valid_dma9, |
| 169 | page1_mask_dma9, page1_value_dma9, page1_reloc_dma9, |
| 170 | page1_valid_dma9, txc_dmc_dma10_mark_bit, tx_cfg_dma10_mk, |
| 171 | tx_cfg_dma10_mmk, tx_cfg_dma10_enable_mb, tx_cs_dma10, |
| 172 | tx_dma10_pre_st, tx_rng_head_dma10, tx_rng_tail_dma10, |
| 173 | tx_dma10_rng_err_logh, tx_dma10_rng_err_logl, |
| 174 | dmc_txc_dma10_page_handle, tx_dma_cfg_dma10_mbaddr, |
| 175 | page0_mask_dma10, page0_value_dma10, page0_reloc_dma10, |
| 176 | page0_valid_dma10, page1_mask_dma10, page1_value_dma10, |
| 177 | page1_reloc_dma10, page1_valid_dma10, txc_dmc_dma11_mark_bit, |
| 178 | tx_cfg_dma11_mk, tx_cfg_dma11_mmk, tx_cfg_dma11_enable_mb, |
| 179 | tx_cs_dma11, tx_dma11_pre_st, tx_rng_head_dma11, |
| 180 | tx_rng_tail_dma11, tx_dma11_rng_err_logh, tx_dma11_rng_err_logl, |
| 181 | dmc_txc_dma11_page_handle, tx_dma_cfg_dma11_mbaddr, |
| 182 | page0_mask_dma11, page0_value_dma11, page0_reloc_dma11, |
| 183 | page0_valid_dma11, page1_mask_dma11, page1_value_dma11, |
| 184 | page1_reloc_dma11, page1_valid_dma11, txc_dmc_dma12_mark_bit, |
| 185 | tx_cfg_dma12_mk, tx_cfg_dma12_mmk, tx_cfg_dma12_enable_mb, |
| 186 | tx_cs_dma12, tx_dma12_pre_st, tx_rng_head_dma12, |
| 187 | tx_rng_tail_dma12, tx_dma12_rng_err_logh, tx_dma12_rng_err_logl, |
| 188 | dmc_txc_dma12_page_handle, tx_dma_cfg_dma12_mbaddr, |
| 189 | page0_mask_dma12, page0_value_dma12, page0_reloc_dma12, |
| 190 | page0_valid_dma12, page1_mask_dma12, page1_value_dma12, |
| 191 | page1_reloc_dma12, page1_valid_dma12, txc_dmc_dma13_mark_bit, |
| 192 | tx_cfg_dma13_mk, tx_cfg_dma13_mmk, tx_cfg_dma13_enable_mb, |
| 193 | tx_cs_dma13, tx_dma13_pre_st, tx_rng_head_dma13, |
| 194 | tx_rng_tail_dma13, tx_dma13_rng_err_logh, tx_dma13_rng_err_logl, |
| 195 | dmc_txc_dma13_page_handle, tx_dma_cfg_dma13_mbaddr, |
| 196 | page0_mask_dma13, page0_value_dma13, page0_reloc_dma13, |
| 197 | page0_valid_dma13, page1_mask_dma13, page1_value_dma13, |
| 198 | page1_reloc_dma13, page1_valid_dma13, txc_dmc_dma14_mark_bit, |
| 199 | tx_cfg_dma14_mk, tx_cfg_dma14_mmk, tx_cfg_dma14_enable_mb, |
| 200 | tx_cs_dma14, tx_dma14_pre_st, tx_rng_head_dma14, |
| 201 | tx_rng_tail_dma14, tx_dma14_rng_err_logh, tx_dma14_rng_err_logl, |
| 202 | dmc_txc_dma14_page_handle, tx_dma_cfg_dma14_mbaddr, |
| 203 | page0_mask_dma14, page0_value_dma14, page0_reloc_dma14, |
| 204 | page0_valid_dma14, page1_mask_dma14, page1_value_dma14, |
| 205 | page1_reloc_dma14, page1_valid_dma14, txc_dmc_dma15_mark_bit, |
| 206 | tx_cfg_dma15_mk, tx_cfg_dma15_mmk, tx_cfg_dma15_enable_mb, |
| 207 | tx_cs_dma15, tx_dma15_pre_st, tx_rng_head_dma15, |
| 208 | tx_rng_tail_dma15, tx_dma15_rng_err_logh, tx_dma15_rng_err_logl, |
| 209 | dmc_txc_dma15_page_handle, tx_dma_cfg_dma15_mbaddr, |
| 210 | page0_mask_dma15, page0_value_dma15, page0_reloc_dma15, |
| 211 | page0_valid_dma15, page1_mask_dma15, page1_value_dma15, |
| 212 | page1_reloc_dma15, page1_valid_dma15, |
| 213 | `ifdef NEPTUNE |
| 214 | |
| 215 | |
| 216 | txc_dmc_dma16_mark_bit, |
| 217 | tx_cfg_dma16_mk, tx_cfg_dma16_mmk, tx_cfg_dma16_enable_mb, |
| 218 | tx_cs_dma16, tx_dma16_pre_st, tx_rng_head_dma16, |
| 219 | tx_rng_tail_dma16, tx_dma16_rng_err_logh, tx_dma16_rng_err_logl, |
| 220 | dmc_txc_dma16_page_handle, tx_dma_cfg_dma16_mbaddr, |
| 221 | page0_mask_dma16, page0_value_dma16, page0_reloc_dma16, |
| 222 | page0_valid_dma16, page1_mask_dma16, page1_value_dma16, |
| 223 | page1_reloc_dma16, page1_valid_dma16, txc_dmc_dma17_mark_bit, |
| 224 | tx_cfg_dma17_mk, tx_cfg_dma17_mmk, tx_cfg_dma17_enable_mb, |
| 225 | tx_cs_dma17, tx_dma17_pre_st, tx_rng_head_dma17, |
| 226 | tx_rng_tail_dma17, tx_dma17_rng_err_logh, tx_dma17_rng_err_logl, |
| 227 | dmc_txc_dma17_page_handle, tx_dma_cfg_dma17_mbaddr, |
| 228 | page0_mask_dma17, page0_value_dma17, page0_reloc_dma17, |
| 229 | page0_valid_dma17, page1_mask_dma17, page1_value_dma17, |
| 230 | page1_reloc_dma17, page1_valid_dma17, txc_dmc_dma18_mark_bit, |
| 231 | tx_cfg_dma18_mk, tx_cfg_dma18_mmk, tx_cfg_dma18_enable_mb, |
| 232 | tx_cs_dma18, tx_dma18_pre_st, tx_rng_head_dma18, |
| 233 | tx_rng_tail_dma18, tx_dma18_rng_err_logh, tx_dma18_rng_err_logl, |
| 234 | dmc_txc_dma18_page_handle, tx_dma_cfg_dma18_mbaddr, |
| 235 | page0_mask_dma18, page0_value_dma18, page0_reloc_dma18, |
| 236 | page0_valid_dma18, page1_mask_dma18, page1_value_dma18, |
| 237 | page1_reloc_dma18, page1_valid_dma18, txc_dmc_dma19_mark_bit, |
| 238 | tx_cfg_dma19_mk, tx_cfg_dma19_mmk, tx_cfg_dma19_enable_mb, |
| 239 | tx_cs_dma19, tx_dma19_pre_st, tx_rng_head_dma19, |
| 240 | tx_rng_tail_dma19, tx_dma19_rng_err_logh, tx_dma19_rng_err_logl, |
| 241 | dmc_txc_dma19_page_handle, tx_dma_cfg_dma19_mbaddr, |
| 242 | page0_mask_dma19, page0_value_dma19, page0_reloc_dma19, |
| 243 | page0_valid_dma19, page1_mask_dma19, page1_value_dma19, |
| 244 | page1_reloc_dma19, page1_valid_dma19, txc_dmc_dma20_mark_bit, |
| 245 | tx_cfg_dma20_mk, tx_cfg_dma20_mmk, tx_cfg_dma20_enable_mb, |
| 246 | tx_cs_dma20, tx_dma20_pre_st, tx_rng_head_dma20, |
| 247 | tx_rng_tail_dma20, tx_dma20_rng_err_logh, tx_dma20_rng_err_logl, |
| 248 | dmc_txc_dma20_page_handle, tx_dma_cfg_dma20_mbaddr, |
| 249 | page0_mask_dma20, page0_value_dma20, page0_reloc_dma20, |
| 250 | page0_valid_dma20, page1_mask_dma20, page1_value_dma20, |
| 251 | page1_reloc_dma20, page1_valid_dma20, txc_dmc_dma21_mark_bit, |
| 252 | tx_cfg_dma21_mk, tx_cfg_dma21_mmk, tx_cfg_dma21_enable_mb, |
| 253 | tx_cs_dma21, tx_dma21_pre_st, tx_rng_head_dma21, |
| 254 | tx_rng_tail_dma21, tx_dma21_rng_err_logh, tx_dma21_rng_err_logl, |
| 255 | dmc_txc_dma21_page_handle, tx_dma_cfg_dma21_mbaddr, |
| 256 | page0_mask_dma21, page0_value_dma21, page0_reloc_dma21, |
| 257 | page0_valid_dma21, page1_mask_dma21, page1_value_dma21, |
| 258 | page1_reloc_dma21, page1_valid_dma21, txc_dmc_dma22_mark_bit, |
| 259 | tx_cfg_dma22_mk, tx_cfg_dma22_mmk, tx_cfg_dma22_enable_mb, |
| 260 | tx_cs_dma22, tx_dma22_pre_st, tx_rng_head_dma22, |
| 261 | tx_rng_tail_dma22, tx_dma22_rng_err_logh, tx_dma22_rng_err_logl, |
| 262 | dmc_txc_dma22_page_handle, tx_dma_cfg_dma22_mbaddr, |
| 263 | page0_mask_dma22, page0_value_dma22, page0_reloc_dma22, |
| 264 | page0_valid_dma22, page1_mask_dma22, page1_value_dma22, |
| 265 | page1_reloc_dma22, page1_valid_dma22, txc_dmc_dma23_mark_bit, |
| 266 | tx_cfg_dma23_mk, tx_cfg_dma23_mmk, tx_cfg_dma23_enable_mb, |
| 267 | tx_cs_dma23, tx_dma23_pre_st, tx_rng_head_dma23, |
| 268 | tx_rng_tail_dma23, tx_dma23_rng_err_logh, tx_dma23_rng_err_logl, |
| 269 | dmc_txc_dma23_page_handle, tx_dma_cfg_dma23_mbaddr, |
| 270 | page0_mask_dma23, page0_value_dma23, page0_reloc_dma23, |
| 271 | page0_valid_dma23, page1_mask_dma23, page1_value_dma23, |
| 272 | page1_reloc_dma23, page1_valid_dma23, |
| 273 | `else |
| 274 | `endif // !ifdef CHANNELS_16 |
| 275 | |
| 276 | dmc_txc_dma0_func_num, |
| 277 | dmc_txc_dma1_func_num, dmc_txc_dma2_func_num, |
| 278 | dmc_txc_dma3_func_num, dmc_txc_dma4_func_num, |
| 279 | dmc_txc_dma5_func_num, dmc_txc_dma6_func_num, |
| 280 | dmc_txc_dma7_func_num, dmc_txc_dma8_func_num, |
| 281 | dmc_txc_dma9_func_num, dmc_txc_dma10_func_num, |
| 282 | dmc_txc_dma11_func_num, dmc_txc_dma12_func_num, |
| 283 | dmc_txc_dma13_func_num, dmc_txc_dma14_func_num, |
| 284 | `ifdef NEPTUNE |
| 285 | dmc_txc_dma15_func_num, |
| 286 | dmc_txc_dma16_func_num, |
| 287 | dmc_txc_dma17_func_num, dmc_txc_dma18_func_num, |
| 288 | dmc_txc_dma19_func_num, dmc_txc_dma20_func_num, |
| 289 | dmc_txc_dma21_func_num, dmc_txc_dma22_func_num, |
| 290 | dmc_txc_dma23_func_num |
| 291 | `else // !ifdef NEPTUNE |
| 292 | dmc_txc_dma15_func_num |
| 293 | `endif // !ifdef CHANNELS_16 |
| 294 | |
| 295 | ); |
| 296 | |
| 297 | input SysClk; |
| 298 | input Reset_L; |
| 299 | |
| 300 | // Meta Signals |
| 301 | output [127:0] tdmc_arb0_data; // Transfer Data |
| 302 | output tdmc_arb0_data_valid; // Transfer Data Ack |
| 303 | output tdmc_arb0_req; // Req Command Request |
| 304 | output [63:0] tdmc_arb0_req_address; // Memory Address |
| 305 | output [15:0] tdmc_arb0_req_byteenable; // First/Last BE |
| 306 | output [7:0] tdmc_arb0_req_cmd; // Command Request |
| 307 | output [4:0] tdmc_arb0_req_dma_num; // Channel Number |
| 308 | output [13:0] tdmc_arb0_req_length; // Packet Length |
| 309 | output [1:0] tdmc_arb0_req_port_num; // Port Number |
| 310 | output [3:0] tdmc_arb0_status; // Transfer Data Status |
| 311 | output tdmc_arb0_transfer_complete; // Transfer Data Complete |
| 312 | output [1:0] tdmc_arb0_req_func_num; // FUNCTION Number |
| 313 | |
| 314 | input arb0_tdmc_data_req; // Memory line request |
| 315 | input arb0_tdmc_req_accept; // Response to REQ |
| 316 | |
| 317 | // Write Ack Signals |
| 318 | input meta_dmc_ack_ready ; |
| 319 | input [7:0] meta_dmc_ack_cmd ; |
| 320 | input [4:0] meta_dmc_ack_dma_num ; |
| 321 | input meta_dmc_ack_client ; |
| 322 | input meta_dmc_ack_complete ; |
| 323 | input [3:0] meta_dmc_ack_cmd_status; |
| 324 | |
| 325 | output dmc_meta_ack_accept; |
| 326 | |
| 327 | // ERROR related signals |
| 328 | output [`NO_OF_DMAS - 1:0] mbox_ack_dma_err_received; |
| 329 | output mbox_err_received; |
| 330 | output [`NO_OF_DMAS - 1:0] set_mbox_part_error_dma; |
| 331 | |
| 332 | |
| 333 | |
| 334 | |
| 335 | // DMA_0 |
| 336 | input txc_dmc_dma0_mark_bit; |
| 337 | input tx_cfg_dma0_mk; |
| 338 | input tx_cfg_dma0_mmk; |
| 339 | input tx_cfg_dma0_enable_mb; |
| 340 | input [63:0] tx_cs_dma0; |
| 341 | input [63:0] tx_dma0_pre_st; |
| 342 | input [`PTR_WIDTH:0] tx_rng_head_dma0; |
| 343 | input [`PTR_WIDTH:0] tx_rng_tail_dma0; |
| 344 | input [63:0] tx_dma0_rng_err_logh; |
| 345 | input [63:0] tx_dma0_rng_err_logl; |
| 346 | input [19:0] dmc_txc_dma0_page_handle; |
| 347 | input [37:0] tx_dma_cfg_dma0_mbaddr; |
| 348 | |
| 349 | input [31:0] page0_mask_dma0; |
| 350 | input [31:0] page0_value_dma0; |
| 351 | input [31:0] page0_reloc_dma0; |
| 352 | input page0_valid_dma0; |
| 353 | input [31:0] page1_mask_dma0; |
| 354 | input [31:0] page1_value_dma0; |
| 355 | input [31:0] page1_reloc_dma0; |
| 356 | input page1_valid_dma0; |
| 357 | |
| 358 | output clear_cfg_dma0_mb; |
| 359 | output set_cfg_dma0_mmk; |
| 360 | |
| 361 | // DMA_1 |
| 362 | input txc_dmc_dma1_mark_bit; |
| 363 | input tx_cfg_dma1_mk; |
| 364 | input tx_cfg_dma1_mmk; |
| 365 | input tx_cfg_dma1_enable_mb; |
| 366 | input [63:0] tx_cs_dma1; |
| 367 | input [63:0] tx_dma1_pre_st; |
| 368 | input [`PTR_WIDTH:0] tx_rng_head_dma1; |
| 369 | input [`PTR_WIDTH:0] tx_rng_tail_dma1; |
| 370 | input [63:0] tx_dma1_rng_err_logh; |
| 371 | input [63:0] tx_dma1_rng_err_logl; |
| 372 | input [19:0] dmc_txc_dma1_page_handle; |
| 373 | input [37:0] tx_dma_cfg_dma1_mbaddr; |
| 374 | |
| 375 | input [31:0] page0_mask_dma1; |
| 376 | input [31:0] page0_value_dma1; |
| 377 | input [31:0] page0_reloc_dma1; |
| 378 | input page0_valid_dma1; |
| 379 | input [31:0] page1_mask_dma1; |
| 380 | input [31:0] page1_value_dma1; |
| 381 | input [31:0] page1_reloc_dma1; |
| 382 | input page1_valid_dma1; |
| 383 | |
| 384 | output clear_cfg_dma1_mb; |
| 385 | output set_cfg_dma1_mmk; |
| 386 | |
| 387 | // DMA_2 |
| 388 | input txc_dmc_dma2_mark_bit; |
| 389 | input tx_cfg_dma2_mk; |
| 390 | input tx_cfg_dma2_mmk; |
| 391 | input tx_cfg_dma2_enable_mb; |
| 392 | input [63:0] tx_cs_dma2; |
| 393 | input [63:0] tx_dma2_pre_st; |
| 394 | input [`PTR_WIDTH:0] tx_rng_head_dma2; |
| 395 | input [`PTR_WIDTH:0] tx_rng_tail_dma2; |
| 396 | input [63:0] tx_dma2_rng_err_logh; |
| 397 | input [63:0] tx_dma2_rng_err_logl; |
| 398 | input [19:0] dmc_txc_dma2_page_handle; |
| 399 | input [37:0] tx_dma_cfg_dma2_mbaddr; |
| 400 | |
| 401 | input [31:0] page0_mask_dma2; |
| 402 | input [31:0] page0_value_dma2; |
| 403 | input [31:0] page0_reloc_dma2; |
| 404 | input page0_valid_dma2; |
| 405 | input [31:0] page1_mask_dma2; |
| 406 | input [31:0] page1_value_dma2; |
| 407 | input [31:0] page1_reloc_dma2; |
| 408 | input page1_valid_dma2; |
| 409 | |
| 410 | output clear_cfg_dma2_mb; |
| 411 | output set_cfg_dma2_mmk; |
| 412 | |
| 413 | // DMA_3 |
| 414 | input txc_dmc_dma3_mark_bit; |
| 415 | input tx_cfg_dma3_mk; |
| 416 | input tx_cfg_dma3_mmk; |
| 417 | input tx_cfg_dma3_enable_mb; |
| 418 | input [63:0] tx_cs_dma3; |
| 419 | input [63:0] tx_dma3_pre_st; |
| 420 | input [`PTR_WIDTH:0] tx_rng_head_dma3; |
| 421 | input [`PTR_WIDTH:0] tx_rng_tail_dma3; |
| 422 | input [63:0] tx_dma3_rng_err_logh; |
| 423 | input [63:0] tx_dma3_rng_err_logl; |
| 424 | input [19:0] dmc_txc_dma3_page_handle; |
| 425 | input [37:0] tx_dma_cfg_dma3_mbaddr; |
| 426 | |
| 427 | input [31:0] page0_mask_dma3; |
| 428 | input [31:0] page0_value_dma3; |
| 429 | input [31:0] page0_reloc_dma3; |
| 430 | input page0_valid_dma3; |
| 431 | input [31:0] page1_mask_dma3; |
| 432 | input [31:0] page1_value_dma3; |
| 433 | input [31:0] page1_reloc_dma3; |
| 434 | input page1_valid_dma3; |
| 435 | |
| 436 | output clear_cfg_dma3_mb; |
| 437 | output set_cfg_dma3_mmk; |
| 438 | |
| 439 | // DMA_4 |
| 440 | input txc_dmc_dma4_mark_bit; |
| 441 | input tx_cfg_dma4_mk; |
| 442 | input tx_cfg_dma4_mmk; |
| 443 | input tx_cfg_dma4_enable_mb; |
| 444 | input [63:0] tx_cs_dma4; |
| 445 | input [63:0] tx_dma4_pre_st; |
| 446 | input [`PTR_WIDTH:0] tx_rng_head_dma4; |
| 447 | input [`PTR_WIDTH:0] tx_rng_tail_dma4; |
| 448 | input [63:0] tx_dma4_rng_err_logh; |
| 449 | input [63:0] tx_dma4_rng_err_logl; |
| 450 | input [19:0] dmc_txc_dma4_page_handle; |
| 451 | input [37:0] tx_dma_cfg_dma4_mbaddr; |
| 452 | |
| 453 | input [31:0] page0_mask_dma4; |
| 454 | input [31:0] page0_value_dma4; |
| 455 | input [31:0] page0_reloc_dma4; |
| 456 | input page0_valid_dma4; |
| 457 | input [31:0] page1_mask_dma4; |
| 458 | input [31:0] page1_value_dma4; |
| 459 | input [31:0] page1_reloc_dma4; |
| 460 | input page1_valid_dma4; |
| 461 | |
| 462 | output clear_cfg_dma4_mb; |
| 463 | output set_cfg_dma4_mmk; |
| 464 | |
| 465 | // DMA_5 |
| 466 | input txc_dmc_dma5_mark_bit; |
| 467 | input tx_cfg_dma5_mk; |
| 468 | input tx_cfg_dma5_mmk; |
| 469 | input tx_cfg_dma5_enable_mb; |
| 470 | input [63:0] tx_cs_dma5; |
| 471 | input [63:0] tx_dma5_pre_st; |
| 472 | input [`PTR_WIDTH:0] tx_rng_head_dma5; |
| 473 | input [`PTR_WIDTH:0] tx_rng_tail_dma5; |
| 474 | input [63:0] tx_dma5_rng_err_logh; |
| 475 | input [63:0] tx_dma5_rng_err_logl; |
| 476 | input [19:0] dmc_txc_dma5_page_handle; |
| 477 | input [37:0] tx_dma_cfg_dma5_mbaddr; |
| 478 | |
| 479 | input [31:0] page0_mask_dma5; |
| 480 | input [31:0] page0_value_dma5; |
| 481 | input [31:0] page0_reloc_dma5; |
| 482 | input page0_valid_dma5; |
| 483 | input [31:0] page1_mask_dma5; |
| 484 | input [31:0] page1_value_dma5; |
| 485 | input [31:0] page1_reloc_dma5; |
| 486 | input page1_valid_dma5; |
| 487 | |
| 488 | output clear_cfg_dma5_mb; |
| 489 | output set_cfg_dma5_mmk; |
| 490 | |
| 491 | // DMA_6 |
| 492 | input txc_dmc_dma6_mark_bit; |
| 493 | input tx_cfg_dma6_mk; |
| 494 | input tx_cfg_dma6_mmk; |
| 495 | input tx_cfg_dma6_enable_mb; |
| 496 | input [63:0] tx_cs_dma6; |
| 497 | input [63:0] tx_dma6_pre_st; |
| 498 | input [`PTR_WIDTH:0] tx_rng_head_dma6; |
| 499 | input [`PTR_WIDTH:0] tx_rng_tail_dma6; |
| 500 | input [63:0] tx_dma6_rng_err_logh; |
| 501 | input [63:0] tx_dma6_rng_err_logl; |
| 502 | input [19:0] dmc_txc_dma6_page_handle; |
| 503 | input [37:0] tx_dma_cfg_dma6_mbaddr; |
| 504 | |
| 505 | input [31:0] page0_mask_dma6; |
| 506 | input [31:0] page0_value_dma6; |
| 507 | input [31:0] page0_reloc_dma6; |
| 508 | input page0_valid_dma6; |
| 509 | input [31:0] page1_mask_dma6; |
| 510 | input [31:0] page1_value_dma6; |
| 511 | input [31:0] page1_reloc_dma6; |
| 512 | input page1_valid_dma6; |
| 513 | |
| 514 | output clear_cfg_dma6_mb; |
| 515 | output set_cfg_dma6_mmk; |
| 516 | |
| 517 | // DMA_7 |
| 518 | input txc_dmc_dma7_mark_bit; |
| 519 | input tx_cfg_dma7_mk; |
| 520 | input tx_cfg_dma7_mmk; |
| 521 | input tx_cfg_dma7_enable_mb; |
| 522 | input [63:0] tx_cs_dma7; |
| 523 | input [63:0] tx_dma7_pre_st; |
| 524 | input [`PTR_WIDTH:0] tx_rng_head_dma7; |
| 525 | input [`PTR_WIDTH:0] tx_rng_tail_dma7; |
| 526 | input [63:0] tx_dma7_rng_err_logh; |
| 527 | input [63:0] tx_dma7_rng_err_logl; |
| 528 | input [19:0] dmc_txc_dma7_page_handle; |
| 529 | input [37:0] tx_dma_cfg_dma7_mbaddr; |
| 530 | |
| 531 | input [31:0] page0_mask_dma7; |
| 532 | input [31:0] page0_value_dma7; |
| 533 | input [31:0] page0_reloc_dma7; |
| 534 | input page0_valid_dma7; |
| 535 | input [31:0] page1_mask_dma7; |
| 536 | input [31:0] page1_value_dma7; |
| 537 | input [31:0] page1_reloc_dma7; |
| 538 | input page1_valid_dma7; |
| 539 | |
| 540 | output clear_cfg_dma7_mb; |
| 541 | output set_cfg_dma7_mmk; |
| 542 | |
| 543 | // DMA_8 |
| 544 | input txc_dmc_dma8_mark_bit; |
| 545 | input tx_cfg_dma8_mk; |
| 546 | input tx_cfg_dma8_mmk; |
| 547 | input tx_cfg_dma8_enable_mb; |
| 548 | input [63:0] tx_cs_dma8; |
| 549 | input [63:0] tx_dma8_pre_st; |
| 550 | input [`PTR_WIDTH:0] tx_rng_head_dma8; |
| 551 | input [`PTR_WIDTH:0] tx_rng_tail_dma8; |
| 552 | input [63:0] tx_dma8_rng_err_logh; |
| 553 | input [63:0] tx_dma8_rng_err_logl; |
| 554 | input [19:0] dmc_txc_dma8_page_handle; |
| 555 | input [37:0] tx_dma_cfg_dma8_mbaddr; |
| 556 | |
| 557 | input [31:0] page0_mask_dma8; |
| 558 | input [31:0] page0_value_dma8; |
| 559 | input [31:0] page0_reloc_dma8; |
| 560 | input page0_valid_dma8; |
| 561 | input [31:0] page1_mask_dma8; |
| 562 | input [31:0] page1_value_dma8; |
| 563 | input [31:0] page1_reloc_dma8; |
| 564 | input page1_valid_dma8; |
| 565 | |
| 566 | output clear_cfg_dma8_mb; |
| 567 | output set_cfg_dma8_mmk; |
| 568 | |
| 569 | // DMA_9 |
| 570 | input txc_dmc_dma9_mark_bit; |
| 571 | input tx_cfg_dma9_mk; |
| 572 | input tx_cfg_dma9_mmk; |
| 573 | input tx_cfg_dma9_enable_mb; |
| 574 | input [63:0] tx_cs_dma9; |
| 575 | input [63:0] tx_dma9_pre_st; |
| 576 | input [`PTR_WIDTH:0] tx_rng_head_dma9; |
| 577 | input [`PTR_WIDTH:0] tx_rng_tail_dma9; |
| 578 | input [63:0] tx_dma9_rng_err_logh; |
| 579 | input [63:0] tx_dma9_rng_err_logl; |
| 580 | input [19:0] dmc_txc_dma9_page_handle; |
| 581 | input [37:0] tx_dma_cfg_dma9_mbaddr; |
| 582 | |
| 583 | input [31:0] page0_mask_dma9; |
| 584 | input [31:0] page0_value_dma9; |
| 585 | input [31:0] page0_reloc_dma9; |
| 586 | input page0_valid_dma9; |
| 587 | input [31:0] page1_mask_dma9; |
| 588 | input [31:0] page1_value_dma9; |
| 589 | input [31:0] page1_reloc_dma9; |
| 590 | input page1_valid_dma9; |
| 591 | |
| 592 | output clear_cfg_dma9_mb; |
| 593 | output set_cfg_dma9_mmk; |
| 594 | |
| 595 | // DMA_10 |
| 596 | input txc_dmc_dma10_mark_bit; |
| 597 | input tx_cfg_dma10_mk; |
| 598 | input tx_cfg_dma10_mmk; |
| 599 | input tx_cfg_dma10_enable_mb; |
| 600 | input [63:0] tx_cs_dma10; |
| 601 | input [63:0] tx_dma10_pre_st; |
| 602 | input [`PTR_WIDTH:0] tx_rng_head_dma10; |
| 603 | input [`PTR_WIDTH:0] tx_rng_tail_dma10; |
| 604 | input [63:0] tx_dma10_rng_err_logh; |
| 605 | input [63:0] tx_dma10_rng_err_logl; |
| 606 | input [19:0] dmc_txc_dma10_page_handle; |
| 607 | input [37:0] tx_dma_cfg_dma10_mbaddr; |
| 608 | |
| 609 | input [31:0] page0_mask_dma10; |
| 610 | input [31:0] page0_value_dma10; |
| 611 | input [31:0] page0_reloc_dma10; |
| 612 | input page0_valid_dma10; |
| 613 | input [31:0] page1_mask_dma10; |
| 614 | input [31:0] page1_value_dma10; |
| 615 | input [31:0] page1_reloc_dma10; |
| 616 | input page1_valid_dma10; |
| 617 | |
| 618 | output clear_cfg_dma10_mb; |
| 619 | output set_cfg_dma10_mmk; |
| 620 | |
| 621 | // DMA_11 |
| 622 | input txc_dmc_dma11_mark_bit; |
| 623 | input tx_cfg_dma11_mk; |
| 624 | input tx_cfg_dma11_mmk; |
| 625 | input tx_cfg_dma11_enable_mb; |
| 626 | input [63:0] tx_cs_dma11; |
| 627 | input [63:0] tx_dma11_pre_st; |
| 628 | input [`PTR_WIDTH:0] tx_rng_head_dma11; |
| 629 | input [`PTR_WIDTH:0] tx_rng_tail_dma11; |
| 630 | input [63:0] tx_dma11_rng_err_logh; |
| 631 | input [63:0] tx_dma11_rng_err_logl; |
| 632 | input [19:0] dmc_txc_dma11_page_handle; |
| 633 | input [37:0] tx_dma_cfg_dma11_mbaddr; |
| 634 | |
| 635 | input [31:0] page0_mask_dma11; |
| 636 | input [31:0] page0_value_dma11; |
| 637 | input [31:0] page0_reloc_dma11; |
| 638 | input page0_valid_dma11; |
| 639 | input [31:0] page1_mask_dma11; |
| 640 | input [31:0] page1_value_dma11; |
| 641 | input [31:0] page1_reloc_dma11; |
| 642 | input page1_valid_dma11; |
| 643 | |
| 644 | output clear_cfg_dma11_mb; |
| 645 | output set_cfg_dma11_mmk; |
| 646 | |
| 647 | // DMA_12 |
| 648 | input txc_dmc_dma12_mark_bit; |
| 649 | input tx_cfg_dma12_mk; |
| 650 | input tx_cfg_dma12_mmk; |
| 651 | input tx_cfg_dma12_enable_mb; |
| 652 | input [63:0] tx_cs_dma12; |
| 653 | input [63:0] tx_dma12_pre_st; |
| 654 | input [`PTR_WIDTH:0] tx_rng_head_dma12; |
| 655 | input [`PTR_WIDTH:0] tx_rng_tail_dma12; |
| 656 | input [63:0] tx_dma12_rng_err_logh; |
| 657 | input [63:0] tx_dma12_rng_err_logl; |
| 658 | input [19:0] dmc_txc_dma12_page_handle; |
| 659 | input [37:0] tx_dma_cfg_dma12_mbaddr; |
| 660 | |
| 661 | input [31:0] page0_mask_dma12; |
| 662 | input [31:0] page0_value_dma12; |
| 663 | input [31:0] page0_reloc_dma12; |
| 664 | input page0_valid_dma12; |
| 665 | input [31:0] page1_mask_dma12; |
| 666 | input [31:0] page1_value_dma12; |
| 667 | input [31:0] page1_reloc_dma12; |
| 668 | input page1_valid_dma12; |
| 669 | |
| 670 | output clear_cfg_dma12_mb; |
| 671 | output set_cfg_dma12_mmk; |
| 672 | |
| 673 | // DMA_13 |
| 674 | input txc_dmc_dma13_mark_bit; |
| 675 | input tx_cfg_dma13_mk; |
| 676 | input tx_cfg_dma13_mmk; |
| 677 | input tx_cfg_dma13_enable_mb; |
| 678 | input [63:0] tx_cs_dma13; |
| 679 | input [63:0] tx_dma13_pre_st; |
| 680 | input [`PTR_WIDTH:0] tx_rng_head_dma13; |
| 681 | input [`PTR_WIDTH:0] tx_rng_tail_dma13; |
| 682 | input [63:0] tx_dma13_rng_err_logh; |
| 683 | input [63:0] tx_dma13_rng_err_logl; |
| 684 | input [19:0] dmc_txc_dma13_page_handle; |
| 685 | input [37:0] tx_dma_cfg_dma13_mbaddr; |
| 686 | |
| 687 | input [31:0] page0_mask_dma13; |
| 688 | input [31:0] page0_value_dma13; |
| 689 | input [31:0] page0_reloc_dma13; |
| 690 | input page0_valid_dma13; |
| 691 | input [31:0] page1_mask_dma13; |
| 692 | input [31:0] page1_value_dma13; |
| 693 | input [31:0] page1_reloc_dma13; |
| 694 | input page1_valid_dma13; |
| 695 | |
| 696 | output clear_cfg_dma13_mb; |
| 697 | output set_cfg_dma13_mmk; |
| 698 | |
| 699 | // DMA_14 |
| 700 | input txc_dmc_dma14_mark_bit; |
| 701 | input tx_cfg_dma14_mk; |
| 702 | input tx_cfg_dma14_mmk; |
| 703 | input tx_cfg_dma14_enable_mb; |
| 704 | input [63:0] tx_cs_dma14; |
| 705 | input [63:0] tx_dma14_pre_st; |
| 706 | input [`PTR_WIDTH:0] tx_rng_head_dma14; |
| 707 | input [`PTR_WIDTH:0] tx_rng_tail_dma14; |
| 708 | input [63:0] tx_dma14_rng_err_logh; |
| 709 | input [63:0] tx_dma14_rng_err_logl; |
| 710 | input [19:0] dmc_txc_dma14_page_handle; |
| 711 | input [37:0] tx_dma_cfg_dma14_mbaddr; |
| 712 | |
| 713 | input [31:0] page0_mask_dma14; |
| 714 | input [31:0] page0_value_dma14; |
| 715 | input [31:0] page0_reloc_dma14; |
| 716 | input page0_valid_dma14; |
| 717 | input [31:0] page1_mask_dma14; |
| 718 | input [31:0] page1_value_dma14; |
| 719 | input [31:0] page1_reloc_dma14; |
| 720 | input page1_valid_dma14; |
| 721 | |
| 722 | output clear_cfg_dma14_mb; |
| 723 | output set_cfg_dma14_mmk; |
| 724 | |
| 725 | // DMA_15 |
| 726 | input txc_dmc_dma15_mark_bit; |
| 727 | input tx_cfg_dma15_mk; |
| 728 | input tx_cfg_dma15_mmk; |
| 729 | input tx_cfg_dma15_enable_mb; |
| 730 | input [63:0] tx_cs_dma15; |
| 731 | input [63:0] tx_dma15_pre_st; |
| 732 | input [`PTR_WIDTH:0] tx_rng_head_dma15; |
| 733 | input [`PTR_WIDTH:0] tx_rng_tail_dma15; |
| 734 | input [63:0] tx_dma15_rng_err_logh; |
| 735 | input [63:0] tx_dma15_rng_err_logl; |
| 736 | input [19:0] dmc_txc_dma15_page_handle; |
| 737 | input [37:0] tx_dma_cfg_dma15_mbaddr; |
| 738 | |
| 739 | input [31:0] page0_mask_dma15; |
| 740 | input [31:0] page0_value_dma15; |
| 741 | input [31:0] page0_reloc_dma15; |
| 742 | input page0_valid_dma15; |
| 743 | input [31:0] page1_mask_dma15; |
| 744 | input [31:0] page1_value_dma15; |
| 745 | input [31:0] page1_reloc_dma15; |
| 746 | input page1_valid_dma15; |
| 747 | |
| 748 | output clear_cfg_dma15_mb; |
| 749 | output set_cfg_dma15_mmk; |
| 750 | `ifdef NEPTUNE |
| 751 | // DMA_16 |
| 752 | input txc_dmc_dma16_mark_bit; |
| 753 | input tx_cfg_dma16_mk; |
| 754 | input tx_cfg_dma16_mmk; |
| 755 | input tx_cfg_dma16_enable_mb; |
| 756 | input [63:0] tx_cs_dma16; |
| 757 | input [63:0] tx_dma16_pre_st; |
| 758 | input [`PTR_WIDTH:0] tx_rng_head_dma16; |
| 759 | input [`PTR_WIDTH:0] tx_rng_tail_dma16; |
| 760 | input [63:0] tx_dma16_rng_err_logh; |
| 761 | input [63:0] tx_dma16_rng_err_logl; |
| 762 | input [19:0] dmc_txc_dma16_page_handle; |
| 763 | input [37:0] tx_dma_cfg_dma16_mbaddr; |
| 764 | |
| 765 | input [31:0] page0_mask_dma16; |
| 766 | input [31:0] page0_value_dma16; |
| 767 | input [31:0] page0_reloc_dma16; |
| 768 | input page0_valid_dma16; |
| 769 | input [31:0] page1_mask_dma16; |
| 770 | input [31:0] page1_value_dma16; |
| 771 | input [31:0] page1_reloc_dma16; |
| 772 | input page1_valid_dma16; |
| 773 | |
| 774 | output clear_cfg_dma16_mb; |
| 775 | output set_cfg_dma16_mmk; |
| 776 | |
| 777 | // DMA_17 |
| 778 | input txc_dmc_dma17_mark_bit; |
| 779 | input tx_cfg_dma17_mk; |
| 780 | input tx_cfg_dma17_mmk; |
| 781 | input tx_cfg_dma17_enable_mb; |
| 782 | input [63:0] tx_cs_dma17; |
| 783 | input [63:0] tx_dma17_pre_st; |
| 784 | input [`PTR_WIDTH:0] tx_rng_head_dma17; |
| 785 | input [`PTR_WIDTH:0] tx_rng_tail_dma17; |
| 786 | input [63:0] tx_dma17_rng_err_logh; |
| 787 | input [63:0] tx_dma17_rng_err_logl; |
| 788 | input [19:0] dmc_txc_dma17_page_handle; |
| 789 | input [37:0] tx_dma_cfg_dma17_mbaddr; |
| 790 | |
| 791 | input [31:0] page0_mask_dma17; |
| 792 | input [31:0] page0_value_dma17; |
| 793 | input [31:0] page0_reloc_dma17; |
| 794 | input page0_valid_dma17; |
| 795 | input [31:0] page1_mask_dma17; |
| 796 | input [31:0] page1_value_dma17; |
| 797 | input [31:0] page1_reloc_dma17; |
| 798 | input page1_valid_dma17; |
| 799 | |
| 800 | output clear_cfg_dma17_mb; |
| 801 | output set_cfg_dma17_mmk; |
| 802 | |
| 803 | // DMA_18 |
| 804 | input txc_dmc_dma18_mark_bit; |
| 805 | input tx_cfg_dma18_mk; |
| 806 | input tx_cfg_dma18_mmk; |
| 807 | input tx_cfg_dma18_enable_mb; |
| 808 | input [63:0] tx_cs_dma18; |
| 809 | input [63:0] tx_dma18_pre_st; |
| 810 | input [`PTR_WIDTH:0] tx_rng_head_dma18; |
| 811 | input [`PTR_WIDTH:0] tx_rng_tail_dma18; |
| 812 | input [63:0] tx_dma18_rng_err_logh; |
| 813 | input [63:0] tx_dma18_rng_err_logl; |
| 814 | input [19:0] dmc_txc_dma18_page_handle; |
| 815 | input [37:0] tx_dma_cfg_dma18_mbaddr; |
| 816 | |
| 817 | input [31:0] page0_mask_dma18; |
| 818 | input [31:0] page0_value_dma18; |
| 819 | input [31:0] page0_reloc_dma18; |
| 820 | input page0_valid_dma18; |
| 821 | input [31:0] page1_mask_dma18; |
| 822 | input [31:0] page1_value_dma18; |
| 823 | input [31:0] page1_reloc_dma18; |
| 824 | input page1_valid_dma18; |
| 825 | |
| 826 | output clear_cfg_dma18_mb; |
| 827 | output set_cfg_dma18_mmk; |
| 828 | |
| 829 | // DMA_19 |
| 830 | input txc_dmc_dma19_mark_bit; |
| 831 | input tx_cfg_dma19_mk; |
| 832 | input tx_cfg_dma19_mmk; |
| 833 | input tx_cfg_dma19_enable_mb; |
| 834 | input [63:0] tx_cs_dma19; |
| 835 | input [63:0] tx_dma19_pre_st; |
| 836 | input [`PTR_WIDTH:0] tx_rng_head_dma19; |
| 837 | input [`PTR_WIDTH:0] tx_rng_tail_dma19; |
| 838 | input [63:0] tx_dma19_rng_err_logh; |
| 839 | input [63:0] tx_dma19_rng_err_logl; |
| 840 | input [19:0] dmc_txc_dma19_page_handle; |
| 841 | input [37:0] tx_dma_cfg_dma19_mbaddr; |
| 842 | |
| 843 | input [31:0] page0_mask_dma19; |
| 844 | input [31:0] page0_value_dma19; |
| 845 | input [31:0] page0_reloc_dma19; |
| 846 | input page0_valid_dma19; |
| 847 | input [31:0] page1_mask_dma19; |
| 848 | input [31:0] page1_value_dma19; |
| 849 | input [31:0] page1_reloc_dma19; |
| 850 | input page1_valid_dma19; |
| 851 | |
| 852 | output clear_cfg_dma19_mb; |
| 853 | output set_cfg_dma19_mmk; |
| 854 | |
| 855 | // DMA_20 |
| 856 | input txc_dmc_dma20_mark_bit; |
| 857 | input tx_cfg_dma20_mk; |
| 858 | input tx_cfg_dma20_mmk; |
| 859 | input tx_cfg_dma20_enable_mb; |
| 860 | input [63:0] tx_cs_dma20; |
| 861 | input [63:0] tx_dma20_pre_st; |
| 862 | input [`PTR_WIDTH:0] tx_rng_head_dma20; |
| 863 | input [`PTR_WIDTH:0] tx_rng_tail_dma20; |
| 864 | input [63:0] tx_dma20_rng_err_logh; |
| 865 | input [63:0] tx_dma20_rng_err_logl; |
| 866 | input [19:0] dmc_txc_dma20_page_handle; |
| 867 | input [37:0] tx_dma_cfg_dma20_mbaddr; |
| 868 | |
| 869 | input [31:0] page0_mask_dma20; |
| 870 | input [31:0] page0_value_dma20; |
| 871 | input [31:0] page0_reloc_dma20; |
| 872 | input page0_valid_dma20; |
| 873 | input [31:0] page1_mask_dma20; |
| 874 | input [31:0] page1_value_dma20; |
| 875 | input [31:0] page1_reloc_dma20; |
| 876 | input page1_valid_dma20; |
| 877 | |
| 878 | output clear_cfg_dma20_mb; |
| 879 | output set_cfg_dma20_mmk; |
| 880 | |
| 881 | // DMA_21 |
| 882 | input txc_dmc_dma21_mark_bit; |
| 883 | input tx_cfg_dma21_mk; |
| 884 | input tx_cfg_dma21_mmk; |
| 885 | input tx_cfg_dma21_enable_mb; |
| 886 | input [63:0] tx_cs_dma21; |
| 887 | input [63:0] tx_dma21_pre_st; |
| 888 | input [`PTR_WIDTH:0] tx_rng_head_dma21; |
| 889 | input [`PTR_WIDTH:0] tx_rng_tail_dma21; |
| 890 | input [63:0] tx_dma21_rng_err_logh; |
| 891 | input [63:0] tx_dma21_rng_err_logl; |
| 892 | input [19:0] dmc_txc_dma21_page_handle; |
| 893 | input [37:0] tx_dma_cfg_dma21_mbaddr; |
| 894 | |
| 895 | input [31:0] page0_mask_dma21; |
| 896 | input [31:0] page0_value_dma21; |
| 897 | input [31:0] page0_reloc_dma21; |
| 898 | input page0_valid_dma21; |
| 899 | input [31:0] page1_mask_dma21; |
| 900 | input [31:0] page1_value_dma21; |
| 901 | input [31:0] page1_reloc_dma21; |
| 902 | input page1_valid_dma21; |
| 903 | |
| 904 | output clear_cfg_dma21_mb; |
| 905 | output set_cfg_dma21_mmk; |
| 906 | |
| 907 | // DMA_22 |
| 908 | input txc_dmc_dma22_mark_bit; |
| 909 | input tx_cfg_dma22_mk; |
| 910 | input tx_cfg_dma22_mmk; |
| 911 | input tx_cfg_dma22_enable_mb; |
| 912 | input [63:0] tx_cs_dma22; |
| 913 | input [63:0] tx_dma22_pre_st; |
| 914 | input [`PTR_WIDTH:0] tx_rng_head_dma22; |
| 915 | input [`PTR_WIDTH:0] tx_rng_tail_dma22; |
| 916 | input [63:0] tx_dma22_rng_err_logh; |
| 917 | input [63:0] tx_dma22_rng_err_logl; |
| 918 | input [19:0] dmc_txc_dma22_page_handle; |
| 919 | input [37:0] tx_dma_cfg_dma22_mbaddr; |
| 920 | |
| 921 | input [31:0] page0_mask_dma22; |
| 922 | input [31:0] page0_value_dma22; |
| 923 | input [31:0] page0_reloc_dma22; |
| 924 | input page0_valid_dma22; |
| 925 | input [31:0] page1_mask_dma22; |
| 926 | input [31:0] page1_value_dma22; |
| 927 | input [31:0] page1_reloc_dma22; |
| 928 | input page1_valid_dma22; |
| 929 | |
| 930 | output clear_cfg_dma22_mb; |
| 931 | output set_cfg_dma22_mmk; |
| 932 | |
| 933 | // DMA_23 |
| 934 | input txc_dmc_dma23_mark_bit; |
| 935 | input tx_cfg_dma23_mk; |
| 936 | input tx_cfg_dma23_mmk; |
| 937 | input tx_cfg_dma23_enable_mb; |
| 938 | input [63:0] tx_cs_dma23; |
| 939 | input [63:0] tx_dma23_pre_st; |
| 940 | input [`PTR_WIDTH:0] tx_rng_head_dma23; |
| 941 | input [`PTR_WIDTH:0] tx_rng_tail_dma23; |
| 942 | input [63:0] tx_dma23_rng_err_logh; |
| 943 | input [63:0] tx_dma23_rng_err_logl; |
| 944 | input [19:0] dmc_txc_dma23_page_handle; |
| 945 | input [37:0] tx_dma_cfg_dma23_mbaddr; |
| 946 | |
| 947 | input [31:0] page0_mask_dma23; |
| 948 | input [31:0] page0_value_dma23; |
| 949 | input [31:0] page0_reloc_dma23; |
| 950 | input page0_valid_dma23; |
| 951 | input [31:0] page1_mask_dma23; |
| 952 | input [31:0] page1_value_dma23; |
| 953 | input [31:0] page1_reloc_dma23; |
| 954 | input page1_valid_dma23; |
| 955 | |
| 956 | output clear_cfg_dma23_mb; |
| 957 | output set_cfg_dma23_mmk; |
| 958 | |
| 959 | `else |
| 960 | `endif |
| 961 | |
| 962 | output [11:0] mbox_debug_state; // to debug port |
| 963 | |
| 964 | // function number for requests |
| 965 | input [1:0] dmc_txc_dma0_func_num; |
| 966 | input [1:0] dmc_txc_dma1_func_num; |
| 967 | input [1:0] dmc_txc_dma2_func_num; |
| 968 | input [1:0] dmc_txc_dma3_func_num; |
| 969 | input [1:0] dmc_txc_dma4_func_num; |
| 970 | input [1:0] dmc_txc_dma5_func_num; |
| 971 | input [1:0] dmc_txc_dma6_func_num; |
| 972 | input [1:0] dmc_txc_dma7_func_num; |
| 973 | input [1:0] dmc_txc_dma8_func_num; |
| 974 | input [1:0] dmc_txc_dma9_func_num; |
| 975 | input [1:0] dmc_txc_dma10_func_num; |
| 976 | input [1:0] dmc_txc_dma11_func_num; |
| 977 | input [1:0] dmc_txc_dma12_func_num; |
| 978 | input [1:0] dmc_txc_dma13_func_num; |
| 979 | input [1:0] dmc_txc_dma14_func_num; |
| 980 | input [1:0] dmc_txc_dma15_func_num; |
| 981 | `ifdef NEPTUNE |
| 982 | |
| 983 | input [1:0] dmc_txc_dma16_func_num; |
| 984 | input [1:0] dmc_txc_dma17_func_num; |
| 985 | input [1:0] dmc_txc_dma18_func_num; |
| 986 | input [1:0] dmc_txc_dma19_func_num; |
| 987 | input [1:0] dmc_txc_dma20_func_num; |
| 988 | input [1:0] dmc_txc_dma21_func_num; |
| 989 | input [1:0] dmc_txc_dma22_func_num; |
| 990 | input [1:0] dmc_txc_dma23_func_num; |
| 991 | |
| 992 | `else |
| 993 | `endif |
| 994 | output set_cfg_dma0_mk; |
| 995 | output set_cfg_dma1_mk; |
| 996 | output set_cfg_dma2_mk; |
| 997 | output set_cfg_dma3_mk; |
| 998 | output set_cfg_dma4_mk; |
| 999 | output set_cfg_dma5_mk; |
| 1000 | output set_cfg_dma6_mk; |
| 1001 | output set_cfg_dma7_mk; |
| 1002 | output set_cfg_dma8_mk; |
| 1003 | output set_cfg_dma9_mk; |
| 1004 | output set_cfg_dma10_mk; |
| 1005 | output set_cfg_dma11_mk; |
| 1006 | output set_cfg_dma12_mk; |
| 1007 | output set_cfg_dma13_mk; |
| 1008 | output set_cfg_dma14_mk; |
| 1009 | output set_cfg_dma15_mk; |
| 1010 | `ifdef NEPTUNE |
| 1011 | output set_cfg_dma16_mk; |
| 1012 | output set_cfg_dma17_mk; |
| 1013 | output set_cfg_dma18_mk; |
| 1014 | output set_cfg_dma19_mk; |
| 1015 | output set_cfg_dma20_mk; |
| 1016 | output set_cfg_dma21_mk; |
| 1017 | output set_cfg_dma22_mk; |
| 1018 | output set_cfg_dma23_mk; |
| 1019 | |
| 1020 | `else |
| 1021 | `endif |
| 1022 | // Wires -- |
| 1023 | wire [`NO_OF_DMAS - 1:0] set_mbox_part_error_dma; |
| 1024 | wire [`NO_OF_DMAS - 1:0] mbox_ack_dma_err_received; |
| 1025 | wire mbox_err_received; |
| 1026 | // DMA_0 |
| 1027 | wire mbox_ack_dma0_received; |
| 1028 | wire send_mbox_dma0; |
| 1029 | wire done_mbox_dma0; |
| 1030 | wire mbox_dma0_scheduled; |
| 1031 | wire [127:0] mbox_dma0_data; |
| 1032 | wire mbox_dma0_data_valid; |
| 1033 | wire mbox_dma0_data_done; |
| 1034 | wire clear_cfg_dma0_mb; |
| 1035 | wire set_cfg_dma0_mmk; |
| 1036 | |
| 1037 | |
| 1038 | // DMA_1 |
| 1039 | wire mbox_ack_dma1_received; |
| 1040 | wire send_mbox_dma1; |
| 1041 | wire done_mbox_dma1; |
| 1042 | wire mbox_dma1_scheduled; |
| 1043 | wire [127:0] mbox_dma1_data; |
| 1044 | wire mbox_dma1_data_valid; |
| 1045 | wire mbox_dma1_data_done; |
| 1046 | wire clear_cfg_dma1_mb; |
| 1047 | wire set_cfg_dma1_mmk; |
| 1048 | |
| 1049 | |
| 1050 | // DMA_2 |
| 1051 | wire mbox_ack_dma2_received; |
| 1052 | wire send_mbox_dma2; |
| 1053 | wire done_mbox_dma2; |
| 1054 | wire mbox_dma2_scheduled; |
| 1055 | wire [127:0] mbox_dma2_data; |
| 1056 | wire mbox_dma2_data_valid; |
| 1057 | wire mbox_dma2_data_done; |
| 1058 | wire clear_cfg_dma2_mb; |
| 1059 | wire set_cfg_dma2_mmk; |
| 1060 | |
| 1061 | |
| 1062 | // DMA_3 |
| 1063 | wire mbox_ack_dma3_received; |
| 1064 | wire send_mbox_dma3; |
| 1065 | wire done_mbox_dma3; |
| 1066 | wire mbox_dma3_scheduled; |
| 1067 | wire [127:0] mbox_dma3_data; |
| 1068 | wire mbox_dma3_data_valid; |
| 1069 | wire mbox_dma3_data_done; |
| 1070 | wire clear_cfg_dma3_mb; |
| 1071 | wire set_cfg_dma3_mmk; |
| 1072 | |
| 1073 | |
| 1074 | // DMA_4 |
| 1075 | wire mbox_ack_dma4_received; |
| 1076 | wire send_mbox_dma4; |
| 1077 | wire done_mbox_dma4; |
| 1078 | wire mbox_dma4_scheduled; |
| 1079 | wire [127:0] mbox_dma4_data; |
| 1080 | wire mbox_dma4_data_valid; |
| 1081 | wire mbox_dma4_data_done; |
| 1082 | wire clear_cfg_dma4_mb; |
| 1083 | wire set_cfg_dma4_mmk; |
| 1084 | |
| 1085 | |
| 1086 | // DMA_5 |
| 1087 | wire mbox_ack_dma5_received; |
| 1088 | wire send_mbox_dma5; |
| 1089 | wire done_mbox_dma5; |
| 1090 | wire mbox_dma5_scheduled; |
| 1091 | wire [127:0] mbox_dma5_data; |
| 1092 | wire mbox_dma5_data_valid; |
| 1093 | wire mbox_dma5_data_done; |
| 1094 | wire clear_cfg_dma5_mb; |
| 1095 | wire set_cfg_dma5_mmk; |
| 1096 | |
| 1097 | |
| 1098 | // DMA_6 |
| 1099 | wire mbox_ack_dma6_received; |
| 1100 | wire send_mbox_dma6; |
| 1101 | wire done_mbox_dma6; |
| 1102 | wire mbox_dma6_scheduled; |
| 1103 | wire [127:0] mbox_dma6_data; |
| 1104 | wire mbox_dma6_data_valid; |
| 1105 | wire mbox_dma6_data_done; |
| 1106 | wire clear_cfg_dma6_mb; |
| 1107 | wire set_cfg_dma6_mmk; |
| 1108 | |
| 1109 | |
| 1110 | // DMA_7 |
| 1111 | wire mbox_ack_dma7_received; |
| 1112 | wire send_mbox_dma7; |
| 1113 | wire done_mbox_dma7; |
| 1114 | wire mbox_dma7_scheduled; |
| 1115 | wire [127:0] mbox_dma7_data; |
| 1116 | wire mbox_dma7_data_valid; |
| 1117 | wire mbox_dma7_data_done; |
| 1118 | wire clear_cfg_dma7_mb; |
| 1119 | wire set_cfg_dma7_mmk; |
| 1120 | |
| 1121 | |
| 1122 | // DMA_8 |
| 1123 | wire mbox_ack_dma8_received; |
| 1124 | wire send_mbox_dma8; |
| 1125 | wire done_mbox_dma8; |
| 1126 | wire mbox_dma8_scheduled; |
| 1127 | wire [127:0] mbox_dma8_data; |
| 1128 | wire mbox_dma8_data_valid; |
| 1129 | wire mbox_dma8_data_done; |
| 1130 | wire clear_cfg_dma8_mb; |
| 1131 | wire set_cfg_dma8_mmk; |
| 1132 | |
| 1133 | |
| 1134 | // DMA_9 |
| 1135 | wire mbox_ack_dma9_received; |
| 1136 | wire send_mbox_dma9; |
| 1137 | wire done_mbox_dma9; |
| 1138 | wire mbox_dma9_scheduled; |
| 1139 | wire [127:0] mbox_dma9_data; |
| 1140 | wire mbox_dma9_data_valid; |
| 1141 | wire mbox_dma9_data_done; |
| 1142 | wire clear_cfg_dma9_mb; |
| 1143 | wire set_cfg_dma9_mmk; |
| 1144 | |
| 1145 | |
| 1146 | // DMA_10 |
| 1147 | wire mbox_ack_dma10_received; |
| 1148 | wire send_mbox_dma10; |
| 1149 | wire done_mbox_dma10; |
| 1150 | wire mbox_dma10_scheduled; |
| 1151 | wire [127:0] mbox_dma10_data; |
| 1152 | wire mbox_dma10_data_valid; |
| 1153 | wire mbox_dma10_data_done; |
| 1154 | wire clear_cfg_dma10_mb; |
| 1155 | wire set_cfg_dma10_mmk; |
| 1156 | |
| 1157 | |
| 1158 | // DMA_11 |
| 1159 | wire mbox_ack_dma11_received; |
| 1160 | wire send_mbox_dma11; |
| 1161 | wire done_mbox_dma11; |
| 1162 | wire mbox_dma11_scheduled; |
| 1163 | wire [127:0] mbox_dma11_data; |
| 1164 | wire mbox_dma11_data_valid; |
| 1165 | wire mbox_dma11_data_done; |
| 1166 | wire clear_cfg_dma11_mb; |
| 1167 | wire set_cfg_dma11_mmk; |
| 1168 | |
| 1169 | |
| 1170 | // DMA_12 |
| 1171 | wire mbox_ack_dma12_received; |
| 1172 | wire send_mbox_dma12; |
| 1173 | wire done_mbox_dma12; |
| 1174 | wire mbox_dma12_scheduled; |
| 1175 | wire [127:0] mbox_dma12_data; |
| 1176 | wire mbox_dma12_data_valid; |
| 1177 | wire mbox_dma12_data_done; |
| 1178 | wire clear_cfg_dma12_mb; |
| 1179 | wire set_cfg_dma12_mmk; |
| 1180 | |
| 1181 | |
| 1182 | // DMA_13 |
| 1183 | wire mbox_ack_dma13_received; |
| 1184 | wire send_mbox_dma13; |
| 1185 | wire done_mbox_dma13; |
| 1186 | wire mbox_dma13_scheduled; |
| 1187 | wire [127:0] mbox_dma13_data; |
| 1188 | wire mbox_dma13_data_valid; |
| 1189 | wire mbox_dma13_data_done; |
| 1190 | wire clear_cfg_dma13_mb; |
| 1191 | wire set_cfg_dma13_mmk; |
| 1192 | |
| 1193 | |
| 1194 | // DMA_14 |
| 1195 | wire mbox_ack_dma14_received; |
| 1196 | wire send_mbox_dma14; |
| 1197 | wire done_mbox_dma14; |
| 1198 | wire mbox_dma14_scheduled; |
| 1199 | wire [127:0] mbox_dma14_data; |
| 1200 | wire mbox_dma14_data_valid; |
| 1201 | wire mbox_dma14_data_done; |
| 1202 | wire clear_cfg_dma14_mb; |
| 1203 | wire set_cfg_dma14_mmk; |
| 1204 | |
| 1205 | |
| 1206 | // DMA_15 |
| 1207 | wire mbox_ack_dma15_received; |
| 1208 | wire send_mbox_dma15; |
| 1209 | wire done_mbox_dma15; |
| 1210 | wire mbox_dma15_scheduled; |
| 1211 | wire [127:0] mbox_dma15_data; |
| 1212 | wire mbox_dma15_data_valid; |
| 1213 | wire mbox_dma15_data_done; |
| 1214 | wire clear_cfg_dma15_mb; |
| 1215 | wire set_cfg_dma15_mmk; |
| 1216 | |
| 1217 | |
| 1218 | `ifdef NEPTUNE |
| 1219 | |
| 1220 | // DMA_16 |
| 1221 | wire mbox_ack_dma16_received; |
| 1222 | wire send_mbox_dma16; |
| 1223 | wire done_mbox_dma16; |
| 1224 | wire mbox_dma16_scheduled; |
| 1225 | wire [127:0] mbox_dma16_data; |
| 1226 | wire mbox_dma16_data_valid; |
| 1227 | wire mbox_dma16_data_done; |
| 1228 | wire clear_cfg_dma16_mb; |
| 1229 | wire set_cfg_dma16_mmk; |
| 1230 | |
| 1231 | |
| 1232 | // DMA_17 |
| 1233 | wire mbox_ack_dma17_received; |
| 1234 | wire send_mbox_dma17; |
| 1235 | wire done_mbox_dma17; |
| 1236 | wire mbox_dma17_scheduled; |
| 1237 | wire [127:0] mbox_dma17_data; |
| 1238 | wire mbox_dma17_data_valid; |
| 1239 | wire mbox_dma17_data_done; |
| 1240 | wire clear_cfg_dma17_mb; |
| 1241 | wire set_cfg_dma17_mmk; |
| 1242 | |
| 1243 | |
| 1244 | // DMA_18 |
| 1245 | wire mbox_ack_dma18_received; |
| 1246 | wire send_mbox_dma18; |
| 1247 | wire done_mbox_dma18; |
| 1248 | wire mbox_dma18_scheduled; |
| 1249 | wire [127:0] mbox_dma18_data; |
| 1250 | wire mbox_dma18_data_valid; |
| 1251 | wire mbox_dma18_data_done; |
| 1252 | wire clear_cfg_dma18_mb; |
| 1253 | wire set_cfg_dma18_mmk; |
| 1254 | |
| 1255 | |
| 1256 | // DMA_19 |
| 1257 | wire mbox_ack_dma19_received; |
| 1258 | wire send_mbox_dma19; |
| 1259 | wire done_mbox_dma19; |
| 1260 | wire mbox_dma19_scheduled; |
| 1261 | wire [127:0] mbox_dma19_data; |
| 1262 | wire mbox_dma19_data_valid; |
| 1263 | wire mbox_dma19_data_done; |
| 1264 | wire clear_cfg_dma19_mb; |
| 1265 | wire set_cfg_dma19_mmk; |
| 1266 | |
| 1267 | |
| 1268 | // DMA_20 |
| 1269 | wire mbox_ack_dma20_received; |
| 1270 | wire send_mbox_dma20; |
| 1271 | wire done_mbox_dma20; |
| 1272 | wire mbox_dma20_scheduled; |
| 1273 | wire [127:0] mbox_dma20_data; |
| 1274 | wire mbox_dma20_data_valid; |
| 1275 | wire mbox_dma20_data_done; |
| 1276 | wire clear_cfg_dma20_mb; |
| 1277 | wire set_cfg_dma20_mmk; |
| 1278 | |
| 1279 | |
| 1280 | // DMA_21 |
| 1281 | wire mbox_ack_dma21_received; |
| 1282 | wire send_mbox_dma21; |
| 1283 | wire done_mbox_dma21; |
| 1284 | wire mbox_dma21_scheduled; |
| 1285 | wire [127:0] mbox_dma21_data; |
| 1286 | wire mbox_dma21_data_valid; |
| 1287 | wire mbox_dma21_data_done; |
| 1288 | wire clear_cfg_dma21_mb; |
| 1289 | wire set_cfg_dma21_mmk; |
| 1290 | |
| 1291 | |
| 1292 | // DMA_22 |
| 1293 | wire mbox_ack_dma22_received; |
| 1294 | wire send_mbox_dma22; |
| 1295 | wire done_mbox_dma22; |
| 1296 | wire mbox_dma22_scheduled; |
| 1297 | wire [127:0] mbox_dma22_data; |
| 1298 | wire mbox_dma22_data_valid; |
| 1299 | wire mbox_dma22_data_done; |
| 1300 | wire clear_cfg_dma22_mb; |
| 1301 | wire set_cfg_dma22_mmk; |
| 1302 | |
| 1303 | |
| 1304 | // DMA_23 |
| 1305 | wire mbox_ack_dma23_received; |
| 1306 | wire send_mbox_dma23; |
| 1307 | wire done_mbox_dma23; |
| 1308 | wire mbox_dma23_scheduled; |
| 1309 | wire [127:0] mbox_dma23_data; |
| 1310 | wire mbox_dma23_data_valid; |
| 1311 | wire mbox_dma23_data_done; |
| 1312 | wire clear_cfg_dma23_mb; |
| 1313 | wire set_cfg_dma23_mmk; |
| 1314 | |
| 1315 | `else |
| 1316 | `endif |
| 1317 | |
| 1318 | wire set_cfg_dma0_mk; |
| 1319 | wire set_cfg_dma1_mk; |
| 1320 | wire set_cfg_dma2_mk; |
| 1321 | wire set_cfg_dma3_mk; |
| 1322 | wire set_cfg_dma4_mk; |
| 1323 | wire set_cfg_dma5_mk; |
| 1324 | wire set_cfg_dma6_mk; |
| 1325 | wire set_cfg_dma7_mk; |
| 1326 | wire set_cfg_dma8_mk; |
| 1327 | wire set_cfg_dma9_mk; |
| 1328 | wire set_cfg_dma10_mk; |
| 1329 | wire set_cfg_dma11_mk; |
| 1330 | wire set_cfg_dma12_mk; |
| 1331 | wire set_cfg_dma13_mk; |
| 1332 | wire set_cfg_dma14_mk; |
| 1333 | wire set_cfg_dma15_mk; |
| 1334 | `ifdef NEPTUNE |
| 1335 | wire set_cfg_dma16_mk; |
| 1336 | wire set_cfg_dma17_mk; |
| 1337 | wire set_cfg_dma18_mk; |
| 1338 | wire set_cfg_dma19_mk; |
| 1339 | wire set_cfg_dma20_mk; |
| 1340 | wire set_cfg_dma21_mk; |
| 1341 | wire set_cfg_dma22_mk; |
| 1342 | wire set_cfg_dma23_mk; |
| 1343 | |
| 1344 | `else |
| 1345 | `endif |
| 1346 | |
| 1347 | wire meta_data_req; |
| 1348 | |
| 1349 | |
| 1350 | // DMA_0 |
| 1351 | niu_tdmc_mbox_context niu_tdmc_mbox_context_0 (/**/ |
| 1352 | // Outputs |
| 1353 | .send_mbox_dma(send_mbox_dma0), |
| 1354 | .mbox_dma_data(mbox_dma0_data[127:0]), |
| 1355 | .mbox_dma_data_valid(mbox_dma0_data_valid), |
| 1356 | .mbox_dma_data_done(mbox_dma0_data_done), |
| 1357 | .clear_cfg_dma_mb(clear_cfg_dma0_mb), |
| 1358 | .set_cfg_dma_mmk(set_cfg_dma0_mmk), |
| 1359 | .set_cfg_dma_mk(set_cfg_dma0_mk), |
| 1360 | // Inputs |
| 1361 | .SysClk(SysClk), |
| 1362 | .Reset_L(Reset_L), |
| 1363 | .txc_dmc_dma_mark_bit(txc_dmc_dma0_mark_bit), |
| 1364 | .tx_cfg_dma_mk(tx_cfg_dma0_mk), |
| 1365 | .tx_cfg_dma_mmk(tx_cfg_dma0_mmk), |
| 1366 | .tx_cfg_dma_enable_mb(tx_cfg_dma0_enable_mb), |
| 1367 | .tx_cs_dma(tx_cs_dma0[63:0]), |
| 1368 | .tx_dma_pre_st(tx_dma0_pre_st[63:0]), |
| 1369 | .tx_rng_head_dma(tx_rng_head_dma0[`PTR_WIDTH:0]), |
| 1370 | .tx_rng_tail_dma(tx_rng_tail_dma0[`PTR_WIDTH:0]), |
| 1371 | .tx_dma_rng_err_logh(tx_dma0_rng_err_logh), |
| 1372 | .tx_dma_rng_err_logl(tx_dma0_rng_err_logl), |
| 1373 | .mbox_ack_dma_received(mbox_ack_dma0_received), |
| 1374 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[0]), |
| 1375 | .done_mbox_dma(done_mbox_dma0), |
| 1376 | .mbox_dma_scheduled(mbox_dma0_scheduled), |
| 1377 | .meta_data_req(meta_data_req)); |
| 1378 | |
| 1379 | // DMA_1 |
| 1380 | niu_tdmc_mbox_context niu_tdmc_mbox_context_1 (/**/ |
| 1381 | // Outputs |
| 1382 | .send_mbox_dma(send_mbox_dma1), |
| 1383 | .mbox_dma_data(mbox_dma1_data[127:0]), |
| 1384 | .mbox_dma_data_valid(mbox_dma1_data_valid), |
| 1385 | .mbox_dma_data_done(mbox_dma1_data_done), |
| 1386 | .clear_cfg_dma_mb(clear_cfg_dma1_mb), |
| 1387 | .set_cfg_dma_mmk(set_cfg_dma1_mmk), |
| 1388 | .set_cfg_dma_mk(set_cfg_dma1_mk), |
| 1389 | // Inputs |
| 1390 | .SysClk(SysClk), |
| 1391 | .Reset_L(Reset_L), |
| 1392 | .txc_dmc_dma_mark_bit(txc_dmc_dma1_mark_bit), |
| 1393 | .tx_cfg_dma_mk(tx_cfg_dma1_mk), |
| 1394 | .tx_cfg_dma_mmk(tx_cfg_dma1_mmk), |
| 1395 | .tx_cfg_dma_enable_mb(tx_cfg_dma1_enable_mb), |
| 1396 | .tx_cs_dma(tx_cs_dma1[63:0]), |
| 1397 | .tx_dma_pre_st(tx_dma1_pre_st[63:0]), |
| 1398 | .tx_rng_head_dma(tx_rng_head_dma1[`PTR_WIDTH:0]), |
| 1399 | .tx_rng_tail_dma(tx_rng_tail_dma1[`PTR_WIDTH:0]), |
| 1400 | .tx_dma_rng_err_logh(tx_dma1_rng_err_logh), |
| 1401 | .tx_dma_rng_err_logl(tx_dma1_rng_err_logl), |
| 1402 | .mbox_ack_dma_received(mbox_ack_dma1_received), |
| 1403 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[1]), |
| 1404 | .done_mbox_dma(done_mbox_dma1), |
| 1405 | .mbox_dma_scheduled(mbox_dma1_scheduled), |
| 1406 | .meta_data_req(meta_data_req)); |
| 1407 | |
| 1408 | // DMA_2 |
| 1409 | niu_tdmc_mbox_context niu_tdmc_mbox_context_2 (/**/ |
| 1410 | // Outputs |
| 1411 | .send_mbox_dma(send_mbox_dma2), |
| 1412 | .mbox_dma_data(mbox_dma2_data[127:0]), |
| 1413 | .mbox_dma_data_valid(mbox_dma2_data_valid), |
| 1414 | .mbox_dma_data_done(mbox_dma2_data_done), |
| 1415 | .clear_cfg_dma_mb(clear_cfg_dma2_mb), |
| 1416 | .set_cfg_dma_mmk(set_cfg_dma2_mmk), |
| 1417 | .set_cfg_dma_mk(set_cfg_dma2_mk), |
| 1418 | // Inputs |
| 1419 | .SysClk(SysClk), |
| 1420 | .Reset_L(Reset_L), |
| 1421 | .txc_dmc_dma_mark_bit(txc_dmc_dma2_mark_bit), |
| 1422 | .tx_cfg_dma_mk(tx_cfg_dma2_mk), |
| 1423 | .tx_cfg_dma_mmk(tx_cfg_dma2_mmk), |
| 1424 | .tx_cfg_dma_enable_mb(tx_cfg_dma2_enable_mb), |
| 1425 | .tx_cs_dma(tx_cs_dma2[63:0]), |
| 1426 | .tx_dma_pre_st(tx_dma2_pre_st[63:0]), |
| 1427 | .tx_rng_head_dma(tx_rng_head_dma2[`PTR_WIDTH:0]), |
| 1428 | .tx_rng_tail_dma(tx_rng_tail_dma2[`PTR_WIDTH:0]), |
| 1429 | .tx_dma_rng_err_logh(tx_dma2_rng_err_logh), |
| 1430 | .tx_dma_rng_err_logl(tx_dma2_rng_err_logl), |
| 1431 | .mbox_ack_dma_received(mbox_ack_dma2_received), |
| 1432 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[2]), |
| 1433 | .done_mbox_dma(done_mbox_dma2), |
| 1434 | .mbox_dma_scheduled(mbox_dma2_scheduled), |
| 1435 | .meta_data_req(meta_data_req)); |
| 1436 | |
| 1437 | // DMA_3 |
| 1438 | niu_tdmc_mbox_context niu_tdmc_mbox_context_3 (/**/ |
| 1439 | // Outputs |
| 1440 | .send_mbox_dma(send_mbox_dma3), |
| 1441 | .mbox_dma_data(mbox_dma3_data[127:0]), |
| 1442 | .mbox_dma_data_valid(mbox_dma3_data_valid), |
| 1443 | .mbox_dma_data_done(mbox_dma3_data_done), |
| 1444 | .clear_cfg_dma_mb(clear_cfg_dma3_mb), |
| 1445 | .set_cfg_dma_mmk(set_cfg_dma3_mmk), |
| 1446 | .set_cfg_dma_mk(set_cfg_dma3_mk), |
| 1447 | // Inputs |
| 1448 | .SysClk(SysClk), |
| 1449 | .Reset_L(Reset_L), |
| 1450 | .txc_dmc_dma_mark_bit(txc_dmc_dma3_mark_bit), |
| 1451 | .tx_cfg_dma_mk(tx_cfg_dma3_mk), |
| 1452 | .tx_cfg_dma_mmk(tx_cfg_dma3_mmk), |
| 1453 | .tx_cfg_dma_enable_mb(tx_cfg_dma3_enable_mb), |
| 1454 | .tx_cs_dma(tx_cs_dma3[63:0]), |
| 1455 | .tx_dma_pre_st(tx_dma3_pre_st[63:0]), |
| 1456 | .tx_rng_head_dma(tx_rng_head_dma3[`PTR_WIDTH:0]), |
| 1457 | .tx_rng_tail_dma(tx_rng_tail_dma3[`PTR_WIDTH:0]), |
| 1458 | .tx_dma_rng_err_logh(tx_dma3_rng_err_logh), |
| 1459 | .tx_dma_rng_err_logl(tx_dma3_rng_err_logl), |
| 1460 | .mbox_ack_dma_received(mbox_ack_dma3_received), |
| 1461 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[3]), |
| 1462 | .done_mbox_dma(done_mbox_dma3), |
| 1463 | .mbox_dma_scheduled(mbox_dma3_scheduled), |
| 1464 | .meta_data_req(meta_data_req)); |
| 1465 | |
| 1466 | // DMA_4 |
| 1467 | niu_tdmc_mbox_context niu_tdmc_mbox_context_4 (/**/ |
| 1468 | // Outputs |
| 1469 | .send_mbox_dma(send_mbox_dma4), |
| 1470 | .mbox_dma_data(mbox_dma4_data[127:0]), |
| 1471 | .mbox_dma_data_valid(mbox_dma4_data_valid), |
| 1472 | .mbox_dma_data_done(mbox_dma4_data_done), |
| 1473 | .clear_cfg_dma_mb(clear_cfg_dma4_mb), |
| 1474 | .set_cfg_dma_mmk(set_cfg_dma4_mmk), |
| 1475 | .set_cfg_dma_mk(set_cfg_dma4_mk), |
| 1476 | // Inputs |
| 1477 | .SysClk(SysClk), |
| 1478 | .Reset_L(Reset_L), |
| 1479 | .txc_dmc_dma_mark_bit(txc_dmc_dma4_mark_bit), |
| 1480 | .tx_cfg_dma_mk(tx_cfg_dma4_mk), |
| 1481 | .tx_cfg_dma_mmk(tx_cfg_dma4_mmk), |
| 1482 | .tx_cfg_dma_enable_mb(tx_cfg_dma4_enable_mb), |
| 1483 | .tx_cs_dma(tx_cs_dma4[63:0]), |
| 1484 | .tx_dma_pre_st(tx_dma4_pre_st[63:0]), |
| 1485 | .tx_rng_head_dma(tx_rng_head_dma4[`PTR_WIDTH:0]), |
| 1486 | .tx_rng_tail_dma(tx_rng_tail_dma4[`PTR_WIDTH:0]), |
| 1487 | .tx_dma_rng_err_logh(tx_dma4_rng_err_logh), |
| 1488 | .tx_dma_rng_err_logl(tx_dma4_rng_err_logl), |
| 1489 | .mbox_ack_dma_received(mbox_ack_dma4_received), |
| 1490 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[4]), |
| 1491 | .done_mbox_dma(done_mbox_dma4), |
| 1492 | .mbox_dma_scheduled(mbox_dma4_scheduled), |
| 1493 | .meta_data_req(meta_data_req)); |
| 1494 | |
| 1495 | // DMA_5 |
| 1496 | niu_tdmc_mbox_context niu_tdmc_mbox_context_5 (/**/ |
| 1497 | // Outputs |
| 1498 | .send_mbox_dma(send_mbox_dma5), |
| 1499 | .mbox_dma_data(mbox_dma5_data[127:0]), |
| 1500 | .mbox_dma_data_valid(mbox_dma5_data_valid), |
| 1501 | .mbox_dma_data_done(mbox_dma5_data_done), |
| 1502 | .clear_cfg_dma_mb(clear_cfg_dma5_mb), |
| 1503 | .set_cfg_dma_mmk(set_cfg_dma5_mmk), |
| 1504 | .set_cfg_dma_mk(set_cfg_dma5_mk), |
| 1505 | // Inputs |
| 1506 | .SysClk(SysClk), |
| 1507 | .Reset_L(Reset_L), |
| 1508 | .txc_dmc_dma_mark_bit(txc_dmc_dma5_mark_bit), |
| 1509 | .tx_cfg_dma_mk(tx_cfg_dma5_mk), |
| 1510 | .tx_cfg_dma_mmk(tx_cfg_dma5_mmk), |
| 1511 | .tx_cfg_dma_enable_mb(tx_cfg_dma5_enable_mb), |
| 1512 | .tx_cs_dma(tx_cs_dma5[63:0]), |
| 1513 | .tx_dma_pre_st(tx_dma5_pre_st[63:0]), |
| 1514 | .tx_rng_head_dma(tx_rng_head_dma5[`PTR_WIDTH:0]), |
| 1515 | .tx_rng_tail_dma(tx_rng_tail_dma5[`PTR_WIDTH:0]), |
| 1516 | .tx_dma_rng_err_logh(tx_dma5_rng_err_logh), |
| 1517 | .tx_dma_rng_err_logl(tx_dma5_rng_err_logl), |
| 1518 | .mbox_ack_dma_received(mbox_ack_dma5_received), |
| 1519 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[5]), |
| 1520 | .done_mbox_dma(done_mbox_dma5), |
| 1521 | .mbox_dma_scheduled(mbox_dma5_scheduled), |
| 1522 | .meta_data_req(meta_data_req)); |
| 1523 | |
| 1524 | // DMA_6 |
| 1525 | niu_tdmc_mbox_context niu_tdmc_mbox_context_6 (/**/ |
| 1526 | // Outputs |
| 1527 | .send_mbox_dma(send_mbox_dma6), |
| 1528 | .mbox_dma_data(mbox_dma6_data[127:0]), |
| 1529 | .mbox_dma_data_valid(mbox_dma6_data_valid), |
| 1530 | .mbox_dma_data_done(mbox_dma6_data_done), |
| 1531 | .clear_cfg_dma_mb(clear_cfg_dma6_mb), |
| 1532 | .set_cfg_dma_mmk(set_cfg_dma6_mmk), |
| 1533 | .set_cfg_dma_mk(set_cfg_dma6_mk), |
| 1534 | // Inputs |
| 1535 | .SysClk(SysClk), |
| 1536 | .Reset_L(Reset_L), |
| 1537 | .txc_dmc_dma_mark_bit(txc_dmc_dma6_mark_bit), |
| 1538 | .tx_cfg_dma_mk(tx_cfg_dma6_mk), |
| 1539 | .tx_cfg_dma_mmk(tx_cfg_dma6_mmk), |
| 1540 | .tx_cfg_dma_enable_mb(tx_cfg_dma6_enable_mb), |
| 1541 | .tx_cs_dma(tx_cs_dma6[63:0]), |
| 1542 | .tx_dma_pre_st(tx_dma6_pre_st[63:0]), |
| 1543 | .tx_rng_head_dma(tx_rng_head_dma6[`PTR_WIDTH:0]), |
| 1544 | .tx_rng_tail_dma(tx_rng_tail_dma6[`PTR_WIDTH:0]), |
| 1545 | .tx_dma_rng_err_logh(tx_dma6_rng_err_logh), |
| 1546 | .tx_dma_rng_err_logl(tx_dma6_rng_err_logl), |
| 1547 | .mbox_ack_dma_received(mbox_ack_dma6_received), |
| 1548 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[6]), |
| 1549 | .done_mbox_dma(done_mbox_dma6), |
| 1550 | .mbox_dma_scheduled(mbox_dma6_scheduled), |
| 1551 | .meta_data_req(meta_data_req)); |
| 1552 | |
| 1553 | // DMA_7 |
| 1554 | niu_tdmc_mbox_context niu_tdmc_mbox_context_7 (/**/ |
| 1555 | // Outputs |
| 1556 | .send_mbox_dma(send_mbox_dma7), |
| 1557 | .mbox_dma_data(mbox_dma7_data[127:0]), |
| 1558 | .mbox_dma_data_valid(mbox_dma7_data_valid), |
| 1559 | .mbox_dma_data_done(mbox_dma7_data_done), |
| 1560 | .clear_cfg_dma_mb(clear_cfg_dma7_mb), |
| 1561 | .set_cfg_dma_mmk(set_cfg_dma7_mmk), |
| 1562 | .set_cfg_dma_mk(set_cfg_dma7_mk), |
| 1563 | // Inputs |
| 1564 | .SysClk(SysClk), |
| 1565 | .Reset_L(Reset_L), |
| 1566 | .txc_dmc_dma_mark_bit(txc_dmc_dma7_mark_bit), |
| 1567 | .tx_cfg_dma_mk(tx_cfg_dma7_mk), |
| 1568 | .tx_cfg_dma_mmk(tx_cfg_dma7_mmk), |
| 1569 | .tx_cfg_dma_enable_mb(tx_cfg_dma7_enable_mb), |
| 1570 | .tx_cs_dma(tx_cs_dma7[63:0]), |
| 1571 | .tx_dma_pre_st(tx_dma7_pre_st[63:0]), |
| 1572 | .tx_rng_head_dma(tx_rng_head_dma7[`PTR_WIDTH:0]), |
| 1573 | .tx_rng_tail_dma(tx_rng_tail_dma7[`PTR_WIDTH:0]), |
| 1574 | .tx_dma_rng_err_logh(tx_dma7_rng_err_logh), |
| 1575 | .tx_dma_rng_err_logl(tx_dma7_rng_err_logl), |
| 1576 | .mbox_ack_dma_received(mbox_ack_dma7_received), |
| 1577 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[7]), |
| 1578 | .done_mbox_dma(done_mbox_dma7), |
| 1579 | .mbox_dma_scheduled(mbox_dma7_scheduled), |
| 1580 | .meta_data_req(meta_data_req)); |
| 1581 | |
| 1582 | // DMA_8 |
| 1583 | niu_tdmc_mbox_context niu_tdmc_mbox_context_8 (/**/ |
| 1584 | // Outputs |
| 1585 | .send_mbox_dma(send_mbox_dma8), |
| 1586 | .mbox_dma_data(mbox_dma8_data[127:0]), |
| 1587 | .mbox_dma_data_valid(mbox_dma8_data_valid), |
| 1588 | .mbox_dma_data_done(mbox_dma8_data_done), |
| 1589 | .clear_cfg_dma_mb(clear_cfg_dma8_mb), |
| 1590 | .set_cfg_dma_mmk(set_cfg_dma8_mmk), |
| 1591 | .set_cfg_dma_mk(set_cfg_dma8_mk), |
| 1592 | // Inputs |
| 1593 | .SysClk(SysClk), |
| 1594 | .Reset_L(Reset_L), |
| 1595 | .txc_dmc_dma_mark_bit(txc_dmc_dma8_mark_bit), |
| 1596 | .tx_cfg_dma_mk(tx_cfg_dma8_mk), |
| 1597 | .tx_cfg_dma_mmk(tx_cfg_dma8_mmk), |
| 1598 | .tx_cfg_dma_enable_mb(tx_cfg_dma8_enable_mb), |
| 1599 | .tx_cs_dma(tx_cs_dma8[63:0]), |
| 1600 | .tx_dma_pre_st(tx_dma8_pre_st[63:0]), |
| 1601 | .tx_rng_head_dma(tx_rng_head_dma8[`PTR_WIDTH:0]), |
| 1602 | .tx_rng_tail_dma(tx_rng_tail_dma8[`PTR_WIDTH:0]), |
| 1603 | .tx_dma_rng_err_logh(tx_dma8_rng_err_logh), |
| 1604 | .tx_dma_rng_err_logl(tx_dma8_rng_err_logl), |
| 1605 | .mbox_ack_dma_received(mbox_ack_dma8_received), |
| 1606 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[8]), |
| 1607 | .done_mbox_dma(done_mbox_dma8), |
| 1608 | .mbox_dma_scheduled(mbox_dma8_scheduled), |
| 1609 | .meta_data_req(meta_data_req)); |
| 1610 | |
| 1611 | // DMA_9 |
| 1612 | niu_tdmc_mbox_context niu_tdmc_mbox_context_9 (/**/ |
| 1613 | // Outputs |
| 1614 | .send_mbox_dma(send_mbox_dma9), |
| 1615 | .mbox_dma_data(mbox_dma9_data[127:0]), |
| 1616 | .mbox_dma_data_valid(mbox_dma9_data_valid), |
| 1617 | .mbox_dma_data_done(mbox_dma9_data_done), |
| 1618 | .clear_cfg_dma_mb(clear_cfg_dma9_mb), |
| 1619 | .set_cfg_dma_mmk(set_cfg_dma9_mmk), |
| 1620 | .set_cfg_dma_mk(set_cfg_dma9_mk), |
| 1621 | // Inputs |
| 1622 | .SysClk(SysClk), |
| 1623 | .Reset_L(Reset_L), |
| 1624 | .txc_dmc_dma_mark_bit(txc_dmc_dma9_mark_bit), |
| 1625 | .tx_cfg_dma_mk(tx_cfg_dma9_mk), |
| 1626 | .tx_cfg_dma_mmk(tx_cfg_dma9_mmk), |
| 1627 | .tx_cfg_dma_enable_mb(tx_cfg_dma9_enable_mb), |
| 1628 | .tx_cs_dma(tx_cs_dma9[63:0]), |
| 1629 | .tx_dma_pre_st(tx_dma9_pre_st[63:0]), |
| 1630 | .tx_rng_head_dma(tx_rng_head_dma9[`PTR_WIDTH:0]), |
| 1631 | .tx_rng_tail_dma(tx_rng_tail_dma9[`PTR_WIDTH:0]), |
| 1632 | .tx_dma_rng_err_logh(tx_dma9_rng_err_logh), |
| 1633 | .tx_dma_rng_err_logl(tx_dma9_rng_err_logl), |
| 1634 | .mbox_ack_dma_received(mbox_ack_dma9_received), |
| 1635 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[9]), |
| 1636 | .done_mbox_dma(done_mbox_dma9), |
| 1637 | .mbox_dma_scheduled(mbox_dma9_scheduled), |
| 1638 | .meta_data_req(meta_data_req)); |
| 1639 | |
| 1640 | // DMA_10 |
| 1641 | niu_tdmc_mbox_context niu_tdmc_mbox_context_10 (/**/ |
| 1642 | // Outputs |
| 1643 | .send_mbox_dma(send_mbox_dma10), |
| 1644 | .mbox_dma_data(mbox_dma10_data[127:0]), |
| 1645 | .mbox_dma_data_valid(mbox_dma10_data_valid), |
| 1646 | .mbox_dma_data_done(mbox_dma10_data_done), |
| 1647 | .clear_cfg_dma_mb(clear_cfg_dma10_mb), |
| 1648 | .set_cfg_dma_mmk(set_cfg_dma10_mmk), |
| 1649 | .set_cfg_dma_mk(set_cfg_dma10_mk), |
| 1650 | // Inputs |
| 1651 | .SysClk(SysClk), |
| 1652 | .Reset_L(Reset_L), |
| 1653 | .txc_dmc_dma_mark_bit(txc_dmc_dma10_mark_bit), |
| 1654 | .tx_cfg_dma_mk(tx_cfg_dma10_mk), |
| 1655 | .tx_cfg_dma_mmk(tx_cfg_dma10_mmk), |
| 1656 | .tx_cfg_dma_enable_mb(tx_cfg_dma10_enable_mb), |
| 1657 | .tx_cs_dma(tx_cs_dma10[63:0]), |
| 1658 | .tx_dma_pre_st(tx_dma10_pre_st[63:0]), |
| 1659 | .tx_rng_head_dma(tx_rng_head_dma10[`PTR_WIDTH:0]), |
| 1660 | .tx_rng_tail_dma(tx_rng_tail_dma10[`PTR_WIDTH:0]), |
| 1661 | .tx_dma_rng_err_logh(tx_dma10_rng_err_logh), |
| 1662 | .tx_dma_rng_err_logl(tx_dma10_rng_err_logl), |
| 1663 | .mbox_ack_dma_received(mbox_ack_dma10_received), |
| 1664 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[10]), |
| 1665 | .done_mbox_dma(done_mbox_dma10), |
| 1666 | .mbox_dma_scheduled(mbox_dma10_scheduled), |
| 1667 | .meta_data_req(meta_data_req)); |
| 1668 | |
| 1669 | // DMA_11 |
| 1670 | niu_tdmc_mbox_context niu_tdmc_mbox_context_11 (/**/ |
| 1671 | // Outputs |
| 1672 | .send_mbox_dma(send_mbox_dma11), |
| 1673 | .mbox_dma_data(mbox_dma11_data[127:0]), |
| 1674 | .mbox_dma_data_valid(mbox_dma11_data_valid), |
| 1675 | .mbox_dma_data_done(mbox_dma11_data_done), |
| 1676 | .clear_cfg_dma_mb(clear_cfg_dma11_mb), |
| 1677 | .set_cfg_dma_mmk(set_cfg_dma11_mmk), |
| 1678 | .set_cfg_dma_mk(set_cfg_dma11_mk), |
| 1679 | // Inputs |
| 1680 | .SysClk(SysClk), |
| 1681 | .Reset_L(Reset_L), |
| 1682 | .txc_dmc_dma_mark_bit(txc_dmc_dma11_mark_bit), |
| 1683 | .tx_cfg_dma_mk(tx_cfg_dma11_mk), |
| 1684 | .tx_cfg_dma_mmk(tx_cfg_dma11_mmk), |
| 1685 | .tx_cfg_dma_enable_mb(tx_cfg_dma11_enable_mb), |
| 1686 | .tx_cs_dma(tx_cs_dma11[63:0]), |
| 1687 | .tx_dma_pre_st(tx_dma11_pre_st[63:0]), |
| 1688 | .tx_rng_head_dma(tx_rng_head_dma11[`PTR_WIDTH:0]), |
| 1689 | .tx_rng_tail_dma(tx_rng_tail_dma11[`PTR_WIDTH:0]), |
| 1690 | .tx_dma_rng_err_logh(tx_dma11_rng_err_logh), |
| 1691 | .tx_dma_rng_err_logl(tx_dma11_rng_err_logl), |
| 1692 | .mbox_ack_dma_received(mbox_ack_dma11_received), |
| 1693 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[11]), |
| 1694 | .done_mbox_dma(done_mbox_dma11), |
| 1695 | .mbox_dma_scheduled(mbox_dma11_scheduled), |
| 1696 | .meta_data_req(meta_data_req)); |
| 1697 | |
| 1698 | // DMA_12 |
| 1699 | niu_tdmc_mbox_context niu_tdmc_mbox_context_12 (/**/ |
| 1700 | // Outputs |
| 1701 | .send_mbox_dma(send_mbox_dma12), |
| 1702 | .mbox_dma_data(mbox_dma12_data[127:0]), |
| 1703 | .mbox_dma_data_valid(mbox_dma12_data_valid), |
| 1704 | .mbox_dma_data_done(mbox_dma12_data_done), |
| 1705 | .clear_cfg_dma_mb(clear_cfg_dma12_mb), |
| 1706 | .set_cfg_dma_mmk(set_cfg_dma12_mmk), |
| 1707 | .set_cfg_dma_mk(set_cfg_dma12_mk), |
| 1708 | // Inputs |
| 1709 | .SysClk(SysClk), |
| 1710 | .Reset_L(Reset_L), |
| 1711 | .txc_dmc_dma_mark_bit(txc_dmc_dma12_mark_bit), |
| 1712 | .tx_cfg_dma_mk(tx_cfg_dma12_mk), |
| 1713 | .tx_cfg_dma_mmk(tx_cfg_dma12_mmk), |
| 1714 | .tx_cfg_dma_enable_mb(tx_cfg_dma12_enable_mb), |
| 1715 | .tx_cs_dma(tx_cs_dma12[63:0]), |
| 1716 | .tx_dma_pre_st(tx_dma12_pre_st[63:0]), |
| 1717 | .tx_rng_head_dma(tx_rng_head_dma12[`PTR_WIDTH:0]), |
| 1718 | .tx_rng_tail_dma(tx_rng_tail_dma12[`PTR_WIDTH:0]), |
| 1719 | .tx_dma_rng_err_logh(tx_dma12_rng_err_logh), |
| 1720 | .tx_dma_rng_err_logl(tx_dma12_rng_err_logl), |
| 1721 | .mbox_ack_dma_received(mbox_ack_dma12_received), |
| 1722 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[12]), |
| 1723 | .done_mbox_dma(done_mbox_dma12), |
| 1724 | .mbox_dma_scheduled(mbox_dma12_scheduled), |
| 1725 | .meta_data_req(meta_data_req)); |
| 1726 | |
| 1727 | // DMA_13 |
| 1728 | niu_tdmc_mbox_context niu_tdmc_mbox_context_13 (/**/ |
| 1729 | // Outputs |
| 1730 | .send_mbox_dma(send_mbox_dma13), |
| 1731 | .mbox_dma_data(mbox_dma13_data[127:0]), |
| 1732 | .mbox_dma_data_valid(mbox_dma13_data_valid), |
| 1733 | .mbox_dma_data_done(mbox_dma13_data_done), |
| 1734 | .clear_cfg_dma_mb(clear_cfg_dma13_mb), |
| 1735 | .set_cfg_dma_mmk(set_cfg_dma13_mmk), |
| 1736 | .set_cfg_dma_mk(set_cfg_dma13_mk), |
| 1737 | // Inputs |
| 1738 | .SysClk(SysClk), |
| 1739 | .Reset_L(Reset_L), |
| 1740 | .txc_dmc_dma_mark_bit(txc_dmc_dma13_mark_bit), |
| 1741 | .tx_cfg_dma_mk(tx_cfg_dma13_mk), |
| 1742 | .tx_cfg_dma_mmk(tx_cfg_dma13_mmk), |
| 1743 | .tx_cfg_dma_enable_mb(tx_cfg_dma13_enable_mb), |
| 1744 | .tx_cs_dma(tx_cs_dma13[63:0]), |
| 1745 | .tx_dma_pre_st(tx_dma13_pre_st[63:0]), |
| 1746 | .tx_rng_head_dma(tx_rng_head_dma13[`PTR_WIDTH:0]), |
| 1747 | .tx_rng_tail_dma(tx_rng_tail_dma13[`PTR_WIDTH:0]), |
| 1748 | .tx_dma_rng_err_logh(tx_dma13_rng_err_logh), |
| 1749 | .tx_dma_rng_err_logl(tx_dma13_rng_err_logl), |
| 1750 | .mbox_ack_dma_received(mbox_ack_dma13_received), |
| 1751 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[13]), |
| 1752 | .done_mbox_dma(done_mbox_dma13), |
| 1753 | .mbox_dma_scheduled(mbox_dma13_scheduled), |
| 1754 | .meta_data_req(meta_data_req)); |
| 1755 | |
| 1756 | // DMA_14 |
| 1757 | niu_tdmc_mbox_context niu_tdmc_mbox_context_14 (/**/ |
| 1758 | // Outputs |
| 1759 | .send_mbox_dma(send_mbox_dma14), |
| 1760 | .mbox_dma_data(mbox_dma14_data[127:0]), |
| 1761 | .mbox_dma_data_valid(mbox_dma14_data_valid), |
| 1762 | .mbox_dma_data_done(mbox_dma14_data_done), |
| 1763 | .clear_cfg_dma_mb(clear_cfg_dma14_mb), |
| 1764 | .set_cfg_dma_mmk(set_cfg_dma14_mmk), |
| 1765 | .set_cfg_dma_mk(set_cfg_dma14_mk), |
| 1766 | // Inputs |
| 1767 | .SysClk(SysClk), |
| 1768 | .Reset_L(Reset_L), |
| 1769 | .txc_dmc_dma_mark_bit(txc_dmc_dma14_mark_bit), |
| 1770 | .tx_cfg_dma_mk(tx_cfg_dma14_mk), |
| 1771 | .tx_cfg_dma_mmk(tx_cfg_dma14_mmk), |
| 1772 | .tx_cfg_dma_enable_mb(tx_cfg_dma14_enable_mb), |
| 1773 | .tx_cs_dma(tx_cs_dma14[63:0]), |
| 1774 | .tx_dma_pre_st(tx_dma14_pre_st[63:0]), |
| 1775 | .tx_rng_head_dma(tx_rng_head_dma14[`PTR_WIDTH:0]), |
| 1776 | .tx_rng_tail_dma(tx_rng_tail_dma14[`PTR_WIDTH:0]), |
| 1777 | .tx_dma_rng_err_logh(tx_dma14_rng_err_logh), |
| 1778 | .tx_dma_rng_err_logl(tx_dma14_rng_err_logl), |
| 1779 | .mbox_ack_dma_received(mbox_ack_dma14_received), |
| 1780 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[14]), |
| 1781 | .done_mbox_dma(done_mbox_dma14), |
| 1782 | .mbox_dma_scheduled(mbox_dma14_scheduled), |
| 1783 | .meta_data_req(meta_data_req)); |
| 1784 | |
| 1785 | // DMA_15 |
| 1786 | niu_tdmc_mbox_context niu_tdmc_mbox_context_15 (/**/ |
| 1787 | // Outputs |
| 1788 | .send_mbox_dma(send_mbox_dma15), |
| 1789 | .mbox_dma_data(mbox_dma15_data[127:0]), |
| 1790 | .mbox_dma_data_valid(mbox_dma15_data_valid), |
| 1791 | .mbox_dma_data_done(mbox_dma15_data_done), |
| 1792 | .clear_cfg_dma_mb(clear_cfg_dma15_mb), |
| 1793 | .set_cfg_dma_mmk(set_cfg_dma15_mmk), |
| 1794 | .set_cfg_dma_mk(set_cfg_dma15_mk), |
| 1795 | // Inputs |
| 1796 | .SysClk(SysClk), |
| 1797 | .Reset_L(Reset_L), |
| 1798 | .txc_dmc_dma_mark_bit(txc_dmc_dma15_mark_bit), |
| 1799 | .tx_cfg_dma_mk(tx_cfg_dma15_mk), |
| 1800 | .tx_cfg_dma_mmk(tx_cfg_dma15_mmk), |
| 1801 | .tx_cfg_dma_enable_mb(tx_cfg_dma15_enable_mb), |
| 1802 | .tx_cs_dma(tx_cs_dma15[63:0]), |
| 1803 | .tx_dma_pre_st(tx_dma15_pre_st[63:0]), |
| 1804 | .tx_rng_head_dma(tx_rng_head_dma15[`PTR_WIDTH:0]), |
| 1805 | .tx_rng_tail_dma(tx_rng_tail_dma15[`PTR_WIDTH:0]), |
| 1806 | .tx_dma_rng_err_logh(tx_dma15_rng_err_logh), |
| 1807 | .tx_dma_rng_err_logl(tx_dma15_rng_err_logl), |
| 1808 | .mbox_ack_dma_received(mbox_ack_dma15_received), |
| 1809 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[15]), |
| 1810 | .done_mbox_dma(done_mbox_dma15), |
| 1811 | .mbox_dma_scheduled(mbox_dma15_scheduled), |
| 1812 | .meta_data_req(meta_data_req)); |
| 1813 | |
| 1814 | `ifdef NEPTUNE |
| 1815 | // DMA_16 |
| 1816 | niu_tdmc_mbox_context niu_tdmc_mbox_context_16 (/**/ |
| 1817 | // Outputs |
| 1818 | .send_mbox_dma(send_mbox_dma16), |
| 1819 | .mbox_dma_data(mbox_dma16_data[127:0]), |
| 1820 | .mbox_dma_data_valid(mbox_dma16_data_valid), |
| 1821 | .mbox_dma_data_done(mbox_dma16_data_done), |
| 1822 | .clear_cfg_dma_mb(clear_cfg_dma16_mb), |
| 1823 | .set_cfg_dma_mmk(set_cfg_dma16_mmk), |
| 1824 | .set_cfg_dma_mk(set_cfg_dma16_mk), |
| 1825 | // Inputs |
| 1826 | .SysClk(SysClk), |
| 1827 | .Reset_L(Reset_L), |
| 1828 | .txc_dmc_dma_mark_bit(txc_dmc_dma16_mark_bit), |
| 1829 | .tx_cfg_dma_mk(tx_cfg_dma16_mk), |
| 1830 | .tx_cfg_dma_mmk(tx_cfg_dma16_mmk), |
| 1831 | .tx_cfg_dma_enable_mb(tx_cfg_dma16_enable_mb), |
| 1832 | .tx_cs_dma(tx_cs_dma16[63:0]), |
| 1833 | .tx_dma_pre_st(tx_dma16_pre_st[63:0]), |
| 1834 | .tx_rng_head_dma(tx_rng_head_dma16[`PTR_WIDTH:0]), |
| 1835 | .tx_rng_tail_dma(tx_rng_tail_dma16[`PTR_WIDTH:0]), |
| 1836 | .tx_dma_rng_err_logh(tx_dma16_rng_err_logh), |
| 1837 | .tx_dma_rng_err_logl(tx_dma16_rng_err_logl), |
| 1838 | .mbox_ack_dma_received(mbox_ack_dma16_received), |
| 1839 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[16]), |
| 1840 | .done_mbox_dma(done_mbox_dma16), |
| 1841 | .mbox_dma_scheduled(mbox_dma16_scheduled), |
| 1842 | .meta_data_req(meta_data_req)); |
| 1843 | |
| 1844 | // DMA_17 |
| 1845 | niu_tdmc_mbox_context niu_tdmc_mbox_context_17 (/**/ |
| 1846 | // Outputs |
| 1847 | .send_mbox_dma(send_mbox_dma17), |
| 1848 | .mbox_dma_data(mbox_dma17_data[127:0]), |
| 1849 | .mbox_dma_data_valid(mbox_dma17_data_valid), |
| 1850 | .mbox_dma_data_done(mbox_dma17_data_done), |
| 1851 | .clear_cfg_dma_mb(clear_cfg_dma17_mb), |
| 1852 | .set_cfg_dma_mmk(set_cfg_dma17_mmk), |
| 1853 | .set_cfg_dma_mk(set_cfg_dma17_mk), |
| 1854 | // Inputs |
| 1855 | .SysClk(SysClk), |
| 1856 | .Reset_L(Reset_L), |
| 1857 | .txc_dmc_dma_mark_bit(txc_dmc_dma17_mark_bit), |
| 1858 | .tx_cfg_dma_mk(tx_cfg_dma17_mk), |
| 1859 | .tx_cfg_dma_mmk(tx_cfg_dma17_mmk), |
| 1860 | .tx_cfg_dma_enable_mb(tx_cfg_dma17_enable_mb), |
| 1861 | .tx_cs_dma(tx_cs_dma17[63:0]), |
| 1862 | .tx_dma_pre_st(tx_dma17_pre_st[63:0]), |
| 1863 | .tx_rng_head_dma(tx_rng_head_dma17[`PTR_WIDTH:0]), |
| 1864 | .tx_rng_tail_dma(tx_rng_tail_dma17[`PTR_WIDTH:0]), |
| 1865 | .tx_dma_rng_err_logh(tx_dma17_rng_err_logh), |
| 1866 | .tx_dma_rng_err_logl(tx_dma17_rng_err_logl), |
| 1867 | .mbox_ack_dma_received(mbox_ack_dma17_received), |
| 1868 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[17]), |
| 1869 | .done_mbox_dma(done_mbox_dma17), |
| 1870 | .mbox_dma_scheduled(mbox_dma17_scheduled), |
| 1871 | .meta_data_req(meta_data_req)); |
| 1872 | |
| 1873 | // DMA_18 |
| 1874 | niu_tdmc_mbox_context niu_tdmc_mbox_context_18 (/**/ |
| 1875 | // Outputs |
| 1876 | .send_mbox_dma(send_mbox_dma18), |
| 1877 | .mbox_dma_data(mbox_dma18_data[127:0]), |
| 1878 | .mbox_dma_data_valid(mbox_dma18_data_valid), |
| 1879 | .mbox_dma_data_done(mbox_dma18_data_done), |
| 1880 | .clear_cfg_dma_mb(clear_cfg_dma18_mb), |
| 1881 | .set_cfg_dma_mmk(set_cfg_dma18_mmk), |
| 1882 | .set_cfg_dma_mk(set_cfg_dma18_mk), |
| 1883 | // Inputs |
| 1884 | .SysClk(SysClk), |
| 1885 | .Reset_L(Reset_L), |
| 1886 | .txc_dmc_dma_mark_bit(txc_dmc_dma18_mark_bit), |
| 1887 | .tx_cfg_dma_mk(tx_cfg_dma18_mk), |
| 1888 | .tx_cfg_dma_mmk(tx_cfg_dma18_mmk), |
| 1889 | .tx_cfg_dma_enable_mb(tx_cfg_dma18_enable_mb), |
| 1890 | .tx_cs_dma(tx_cs_dma18[63:0]), |
| 1891 | .tx_dma_pre_st(tx_dma18_pre_st[63:0]), |
| 1892 | .tx_rng_head_dma(tx_rng_head_dma18[`PTR_WIDTH:0]), |
| 1893 | .tx_rng_tail_dma(tx_rng_tail_dma18[`PTR_WIDTH:0]), |
| 1894 | .tx_dma_rng_err_logh(tx_dma18_rng_err_logh), |
| 1895 | .tx_dma_rng_err_logl(tx_dma18_rng_err_logl), |
| 1896 | .mbox_ack_dma_received(mbox_ack_dma18_received), |
| 1897 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[18]), |
| 1898 | .done_mbox_dma(done_mbox_dma18), |
| 1899 | .mbox_dma_scheduled(mbox_dma18_scheduled), |
| 1900 | .meta_data_req(meta_data_req)); |
| 1901 | |
| 1902 | // DMA_19 |
| 1903 | niu_tdmc_mbox_context niu_tdmc_mbox_context_19 (/**/ |
| 1904 | // Outputs |
| 1905 | .send_mbox_dma(send_mbox_dma19), |
| 1906 | .mbox_dma_data(mbox_dma19_data[127:0]), |
| 1907 | .mbox_dma_data_valid(mbox_dma19_data_valid), |
| 1908 | .mbox_dma_data_done(mbox_dma19_data_done), |
| 1909 | .clear_cfg_dma_mb(clear_cfg_dma19_mb), |
| 1910 | .set_cfg_dma_mmk(set_cfg_dma19_mmk), |
| 1911 | .set_cfg_dma_mk(set_cfg_dma19_mk), |
| 1912 | // Inputs |
| 1913 | .SysClk(SysClk), |
| 1914 | .Reset_L(Reset_L), |
| 1915 | .txc_dmc_dma_mark_bit(txc_dmc_dma19_mark_bit), |
| 1916 | .tx_cfg_dma_mk(tx_cfg_dma19_mk), |
| 1917 | .tx_cfg_dma_mmk(tx_cfg_dma19_mmk), |
| 1918 | .tx_cfg_dma_enable_mb(tx_cfg_dma19_enable_mb), |
| 1919 | .tx_cs_dma(tx_cs_dma19[63:0]), |
| 1920 | .tx_dma_pre_st(tx_dma19_pre_st[63:0]), |
| 1921 | .tx_rng_head_dma(tx_rng_head_dma19[`PTR_WIDTH:0]), |
| 1922 | .tx_rng_tail_dma(tx_rng_tail_dma19[`PTR_WIDTH:0]), |
| 1923 | .tx_dma_rng_err_logh(tx_dma19_rng_err_logh), |
| 1924 | .tx_dma_rng_err_logl(tx_dma19_rng_err_logl), |
| 1925 | .mbox_ack_dma_received(mbox_ack_dma19_received), |
| 1926 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[19]), |
| 1927 | .done_mbox_dma(done_mbox_dma19), |
| 1928 | .mbox_dma_scheduled(mbox_dma19_scheduled), |
| 1929 | .meta_data_req(meta_data_req)); |
| 1930 | |
| 1931 | // DMA_20 |
| 1932 | niu_tdmc_mbox_context niu_tdmc_mbox_context_20 (/**/ |
| 1933 | // Outputs |
| 1934 | .send_mbox_dma(send_mbox_dma20), |
| 1935 | .mbox_dma_data(mbox_dma20_data[127:0]), |
| 1936 | .mbox_dma_data_valid(mbox_dma20_data_valid), |
| 1937 | .mbox_dma_data_done(mbox_dma20_data_done), |
| 1938 | .clear_cfg_dma_mb(clear_cfg_dma20_mb), |
| 1939 | .set_cfg_dma_mmk(set_cfg_dma20_mmk), |
| 1940 | .set_cfg_dma_mk(set_cfg_dma20_mk), |
| 1941 | // Inputs |
| 1942 | .SysClk(SysClk), |
| 1943 | .Reset_L(Reset_L), |
| 1944 | .txc_dmc_dma_mark_bit(txc_dmc_dma20_mark_bit), |
| 1945 | .tx_cfg_dma_mk(tx_cfg_dma20_mk), |
| 1946 | .tx_cfg_dma_mmk(tx_cfg_dma20_mmk), |
| 1947 | .tx_cfg_dma_enable_mb(tx_cfg_dma20_enable_mb), |
| 1948 | .tx_cs_dma(tx_cs_dma20[63:0]), |
| 1949 | .tx_dma_pre_st(tx_dma20_pre_st[63:0]), |
| 1950 | .tx_rng_head_dma(tx_rng_head_dma20[`PTR_WIDTH:0]), |
| 1951 | .tx_rng_tail_dma(tx_rng_tail_dma20[`PTR_WIDTH:0]), |
| 1952 | .tx_dma_rng_err_logh(tx_dma20_rng_err_logh), |
| 1953 | .tx_dma_rng_err_logl(tx_dma20_rng_err_logl), |
| 1954 | .mbox_ack_dma_received(mbox_ack_dma20_received), |
| 1955 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[20]), |
| 1956 | .done_mbox_dma(done_mbox_dma20), |
| 1957 | .mbox_dma_scheduled(mbox_dma20_scheduled), |
| 1958 | .meta_data_req(meta_data_req)); |
| 1959 | |
| 1960 | // DMA_21 |
| 1961 | niu_tdmc_mbox_context niu_tdmc_mbox_context_21 (/**/ |
| 1962 | // Outputs |
| 1963 | .send_mbox_dma(send_mbox_dma21), |
| 1964 | .mbox_dma_data(mbox_dma21_data[127:0]), |
| 1965 | .mbox_dma_data_valid(mbox_dma21_data_valid), |
| 1966 | .mbox_dma_data_done(mbox_dma21_data_done), |
| 1967 | .clear_cfg_dma_mb(clear_cfg_dma21_mb), |
| 1968 | .set_cfg_dma_mmk(set_cfg_dma21_mmk), |
| 1969 | .set_cfg_dma_mk(set_cfg_dma21_mk), |
| 1970 | // Inputs |
| 1971 | .SysClk(SysClk), |
| 1972 | .Reset_L(Reset_L), |
| 1973 | .txc_dmc_dma_mark_bit(txc_dmc_dma21_mark_bit), |
| 1974 | .tx_cfg_dma_mk(tx_cfg_dma21_mk), |
| 1975 | .tx_cfg_dma_mmk(tx_cfg_dma21_mmk), |
| 1976 | .tx_cfg_dma_enable_mb(tx_cfg_dma21_enable_mb), |
| 1977 | .tx_cs_dma(tx_cs_dma21[63:0]), |
| 1978 | .tx_dma_pre_st(tx_dma21_pre_st[63:0]), |
| 1979 | .tx_rng_head_dma(tx_rng_head_dma21[`PTR_WIDTH:0]), |
| 1980 | .tx_rng_tail_dma(tx_rng_tail_dma21[`PTR_WIDTH:0]), |
| 1981 | .tx_dma_rng_err_logh(tx_dma21_rng_err_logh), |
| 1982 | .tx_dma_rng_err_logl(tx_dma21_rng_err_logl), |
| 1983 | .mbox_ack_dma_received(mbox_ack_dma21_received), |
| 1984 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[21]), |
| 1985 | .done_mbox_dma(done_mbox_dma21), |
| 1986 | .mbox_dma_scheduled(mbox_dma21_scheduled), |
| 1987 | .meta_data_req(meta_data_req)); |
| 1988 | |
| 1989 | // DMA_22 |
| 1990 | niu_tdmc_mbox_context niu_tdmc_mbox_context_22 (/**/ |
| 1991 | // Outputs |
| 1992 | .send_mbox_dma(send_mbox_dma22), |
| 1993 | .mbox_dma_data(mbox_dma22_data[127:0]), |
| 1994 | .mbox_dma_data_valid(mbox_dma22_data_valid), |
| 1995 | .mbox_dma_data_done(mbox_dma22_data_done), |
| 1996 | .clear_cfg_dma_mb(clear_cfg_dma22_mb), |
| 1997 | .set_cfg_dma_mmk(set_cfg_dma22_mmk), |
| 1998 | .set_cfg_dma_mk(set_cfg_dma22_mk), |
| 1999 | // Inputs |
| 2000 | .SysClk(SysClk), |
| 2001 | .Reset_L(Reset_L), |
| 2002 | .txc_dmc_dma_mark_bit(txc_dmc_dma22_mark_bit), |
| 2003 | .tx_cfg_dma_mk(tx_cfg_dma22_mk), |
| 2004 | .tx_cfg_dma_mmk(tx_cfg_dma22_mmk), |
| 2005 | .tx_cfg_dma_enable_mb(tx_cfg_dma22_enable_mb), |
| 2006 | .tx_cs_dma(tx_cs_dma22[63:0]), |
| 2007 | .tx_dma_pre_st(tx_dma22_pre_st[63:0]), |
| 2008 | .tx_rng_head_dma(tx_rng_head_dma22[`PTR_WIDTH:0]), |
| 2009 | .tx_rng_tail_dma(tx_rng_tail_dma22[`PTR_WIDTH:0]), |
| 2010 | .tx_dma_rng_err_logh(tx_dma22_rng_err_logh), |
| 2011 | .tx_dma_rng_err_logl(tx_dma22_rng_err_logl), |
| 2012 | .mbox_ack_dma_received(mbox_ack_dma22_received), |
| 2013 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[22]), |
| 2014 | .done_mbox_dma(done_mbox_dma22), |
| 2015 | .mbox_dma_scheduled(mbox_dma22_scheduled), |
| 2016 | .meta_data_req(meta_data_req)); |
| 2017 | |
| 2018 | // DMA_23 |
| 2019 | niu_tdmc_mbox_context niu_tdmc_mbox_context_23 (/**/ |
| 2020 | // Outputs |
| 2021 | .send_mbox_dma(send_mbox_dma23), |
| 2022 | .mbox_dma_data(mbox_dma23_data[127:0]), |
| 2023 | .mbox_dma_data_valid(mbox_dma23_data_valid), |
| 2024 | .mbox_dma_data_done(mbox_dma23_data_done), |
| 2025 | .clear_cfg_dma_mb(clear_cfg_dma23_mb), |
| 2026 | .set_cfg_dma_mmk(set_cfg_dma23_mmk), |
| 2027 | .set_cfg_dma_mk(set_cfg_dma23_mk), |
| 2028 | // Inputs |
| 2029 | .SysClk(SysClk), |
| 2030 | .Reset_L(Reset_L), |
| 2031 | .txc_dmc_dma_mark_bit(txc_dmc_dma23_mark_bit), |
| 2032 | .tx_cfg_dma_mk(tx_cfg_dma23_mk), |
| 2033 | .tx_cfg_dma_mmk(tx_cfg_dma23_mmk), |
| 2034 | .tx_cfg_dma_enable_mb(tx_cfg_dma23_enable_mb), |
| 2035 | .tx_cs_dma(tx_cs_dma23[63:0]), |
| 2036 | .tx_dma_pre_st(tx_dma23_pre_st[63:0]), |
| 2037 | .tx_rng_head_dma(tx_rng_head_dma23[`PTR_WIDTH:0]), |
| 2038 | .tx_rng_tail_dma(tx_rng_tail_dma23[`PTR_WIDTH:0]), |
| 2039 | .tx_dma_rng_err_logh(tx_dma23_rng_err_logh), |
| 2040 | .tx_dma_rng_err_logl(tx_dma23_rng_err_logl), |
| 2041 | .mbox_ack_dma_received(mbox_ack_dma23_received), |
| 2042 | .mbox_ack_dma_received_error(mbox_ack_dma_err_received[23]), |
| 2043 | .done_mbox_dma(done_mbox_dma23), |
| 2044 | .mbox_dma_scheduled(mbox_dma23_scheduled), |
| 2045 | .meta_data_req(meta_data_req)); |
| 2046 | |
| 2047 | `else |
| 2048 | `endif |
| 2049 | |
| 2050 | |
| 2051 | |
| 2052 | niu_tdmc_sendmbox niu_tdmc_sendmbox(/*AUTOJUNK*/ |
| 2053 | // Outputs |
| 2054 | .mbox_dma0_scheduled(mbox_dma0_scheduled), |
| 2055 | .done_mbox_dma0(done_mbox_dma0), |
| 2056 | .mbox_ack_dma0_received(mbox_ack_dma0_received), |
| 2057 | .mbox_dma1_scheduled(mbox_dma1_scheduled), |
| 2058 | .done_mbox_dma1(done_mbox_dma1), |
| 2059 | .mbox_ack_dma1_received(mbox_ack_dma1_received), |
| 2060 | .mbox_dma2_scheduled(mbox_dma2_scheduled), |
| 2061 | .done_mbox_dma2(done_mbox_dma2), |
| 2062 | .mbox_ack_dma2_received(mbox_ack_dma2_received), |
| 2063 | .mbox_dma3_scheduled(mbox_dma3_scheduled), |
| 2064 | .done_mbox_dma3(done_mbox_dma3), |
| 2065 | .mbox_ack_dma3_received(mbox_ack_dma3_received), |
| 2066 | .mbox_dma4_scheduled(mbox_dma4_scheduled), |
| 2067 | .done_mbox_dma4(done_mbox_dma4), |
| 2068 | .mbox_ack_dma4_received(mbox_ack_dma4_received), |
| 2069 | .mbox_dma5_scheduled(mbox_dma5_scheduled), |
| 2070 | .done_mbox_dma5(done_mbox_dma5), |
| 2071 | .mbox_ack_dma5_received(mbox_ack_dma5_received), |
| 2072 | .mbox_dma6_scheduled(mbox_dma6_scheduled), |
| 2073 | .done_mbox_dma6(done_mbox_dma6), |
| 2074 | .mbox_ack_dma6_received(mbox_ack_dma6_received), |
| 2075 | .mbox_dma7_scheduled(mbox_dma7_scheduled), |
| 2076 | .done_mbox_dma7(done_mbox_dma7), |
| 2077 | .mbox_ack_dma7_received(mbox_ack_dma7_received), |
| 2078 | .mbox_dma8_scheduled(mbox_dma8_scheduled), |
| 2079 | .done_mbox_dma8(done_mbox_dma8), |
| 2080 | .mbox_ack_dma8_received(mbox_ack_dma8_received), |
| 2081 | .mbox_dma9_scheduled(mbox_dma9_scheduled), |
| 2082 | .done_mbox_dma9(done_mbox_dma9), |
| 2083 | .mbox_ack_dma9_received(mbox_ack_dma9_received), |
| 2084 | .mbox_dma10_scheduled(mbox_dma10_scheduled), |
| 2085 | .done_mbox_dma10(done_mbox_dma10), |
| 2086 | .mbox_ack_dma10_received(mbox_ack_dma10_received), |
| 2087 | .mbox_dma11_scheduled(mbox_dma11_scheduled), |
| 2088 | .done_mbox_dma11(done_mbox_dma11), |
| 2089 | .mbox_ack_dma11_received(mbox_ack_dma11_received), |
| 2090 | .mbox_dma12_scheduled(mbox_dma12_scheduled), |
| 2091 | .done_mbox_dma12(done_mbox_dma12), |
| 2092 | .mbox_ack_dma12_received(mbox_ack_dma12_received), |
| 2093 | .mbox_dma13_scheduled(mbox_dma13_scheduled), |
| 2094 | .done_mbox_dma13(done_mbox_dma13), |
| 2095 | .mbox_ack_dma13_received(mbox_ack_dma13_received), |
| 2096 | .mbox_dma14_scheduled(mbox_dma14_scheduled), |
| 2097 | .done_mbox_dma14(done_mbox_dma14), |
| 2098 | .mbox_ack_dma14_received(mbox_ack_dma14_received), |
| 2099 | .mbox_dma15_scheduled(mbox_dma15_scheduled), |
| 2100 | .done_mbox_dma15(done_mbox_dma15), |
| 2101 | .mbox_ack_dma15_received(mbox_ack_dma15_received), |
| 2102 | `ifdef NEPTUNE |
| 2103 | .mbox_dma16_scheduled(mbox_dma16_scheduled), |
| 2104 | .done_mbox_dma16(done_mbox_dma16), |
| 2105 | .mbox_ack_dma16_received(mbox_ack_dma16_received), |
| 2106 | .mbox_dma17_scheduled(mbox_dma17_scheduled), |
| 2107 | .done_mbox_dma17(done_mbox_dma17), |
| 2108 | .mbox_ack_dma17_received(mbox_ack_dma17_received), |
| 2109 | .mbox_dma18_scheduled(mbox_dma18_scheduled), |
| 2110 | .done_mbox_dma18(done_mbox_dma18), |
| 2111 | .mbox_ack_dma18_received(mbox_ack_dma18_received), |
| 2112 | .mbox_dma19_scheduled(mbox_dma19_scheduled), |
| 2113 | .done_mbox_dma19(done_mbox_dma19), |
| 2114 | .mbox_ack_dma19_received(mbox_ack_dma19_received), |
| 2115 | .mbox_dma20_scheduled(mbox_dma20_scheduled), |
| 2116 | .done_mbox_dma20(done_mbox_dma20), |
| 2117 | .mbox_ack_dma20_received(mbox_ack_dma20_received), |
| 2118 | .mbox_dma21_scheduled(mbox_dma21_scheduled), |
| 2119 | .done_mbox_dma21(done_mbox_dma21), |
| 2120 | .mbox_ack_dma21_received(mbox_ack_dma21_received), |
| 2121 | .mbox_dma22_scheduled(mbox_dma22_scheduled), |
| 2122 | .done_mbox_dma22(done_mbox_dma22), |
| 2123 | .mbox_ack_dma22_received(mbox_ack_dma22_received), |
| 2124 | .mbox_dma23_scheduled(mbox_dma23_scheduled), |
| 2125 | .done_mbox_dma23(done_mbox_dma23), |
| 2126 | .mbox_ack_dma23_received(mbox_ack_dma23_received), |
| 2127 | `else |
| 2128 | `endif |
| 2129 | .set_mbox_part_error_dma(set_mbox_part_error_dma[`NO_OF_DMAS-1:0]), |
| 2130 | .mbox_ack_dma_err_received(mbox_ack_dma_err_received[`NO_OF_DMAS-1:0]), |
| 2131 | .mbox_err_received(mbox_err_received), |
| 2132 | .meta_data_req(meta_data_req), |
| 2133 | .tdmc_arb0_data(tdmc_arb0_data[127:0]), |
| 2134 | .tdmc_arb0_data_valid(tdmc_arb0_data_valid), |
| 2135 | .tdmc_arb0_req(tdmc_arb0_req), |
| 2136 | .tdmc_arb0_req_address(tdmc_arb0_req_address[63:0]), |
| 2137 | .tdmc_arb0_req_byteenable(tdmc_arb0_req_byteenable[15:0]), |
| 2138 | .tdmc_arb0_req_cmd(tdmc_arb0_req_cmd[7:0]), |
| 2139 | .tdmc_arb0_req_dma_num(tdmc_arb0_req_dma_num[4:0]), |
| 2140 | .tdmc_arb0_req_length(tdmc_arb0_req_length[13:0]), |
| 2141 | .tdmc_arb0_req_port_num(tdmc_arb0_req_port_num[1:0]), |
| 2142 | .tdmc_arb0_status(tdmc_arb0_status[3:0]), |
| 2143 | .tdmc_arb0_transfer_complete(tdmc_arb0_transfer_complete), |
| 2144 | .tdmc_arb0_req_func_num(tdmc_arb0_req_func_num[1:0]), |
| 2145 | .dmc_meta_ack_accept(dmc_meta_ack_accept), |
| 2146 | .mbox_debug_state(mbox_debug_state[11:0]), |
| 2147 | // Inputs |
| 2148 | .SysClk(SysClk), |
| 2149 | .Reset_L(Reset_L), |
| 2150 | .send_mbox_dma0(send_mbox_dma0), |
| 2151 | .mbox_dma0_data_valid(mbox_dma0_data_valid), |
| 2152 | .mbox_dma0_data_done(mbox_dma0_data_done), |
| 2153 | .mbox_dma0_data(mbox_dma0_data[127:0]), |
| 2154 | .dmc_txc_dma0_page_handle(dmc_txc_dma0_page_handle[19:0]), |
| 2155 | .tx_dma_cfg_dma0_mbaddr(tx_dma_cfg_dma0_mbaddr[37:0]), |
| 2156 | .page0_mask_dma0(page0_mask_dma0[31:0]), |
| 2157 | .page0_value_dma0(page0_value_dma0[31:0]), |
| 2158 | .page0_reloc_dma0(page0_reloc_dma0[31:0]), |
| 2159 | .page0_valid_dma0(page0_valid_dma0), |
| 2160 | .page1_mask_dma0(page1_mask_dma0[31:0]), |
| 2161 | .page1_value_dma0(page1_value_dma0[31:0]), |
| 2162 | .page1_reloc_dma0(page1_reloc_dma0[31:0]), |
| 2163 | .page1_valid_dma0(page1_valid_dma0), |
| 2164 | .send_mbox_dma1(send_mbox_dma1), |
| 2165 | .mbox_dma1_data_valid(mbox_dma1_data_valid), |
| 2166 | .mbox_dma1_data_done(mbox_dma1_data_done), |
| 2167 | .mbox_dma1_data(mbox_dma1_data[127:0]), |
| 2168 | .dmc_txc_dma1_page_handle(dmc_txc_dma1_page_handle[19:0]), |
| 2169 | .tx_dma_cfg_dma1_mbaddr(tx_dma_cfg_dma1_mbaddr[37:0]), |
| 2170 | .page0_mask_dma1(page0_mask_dma1[31:0]), |
| 2171 | .page0_value_dma1(page0_value_dma1[31:0]), |
| 2172 | .page0_reloc_dma1(page0_reloc_dma1[31:0]), |
| 2173 | .page0_valid_dma1(page0_valid_dma1), |
| 2174 | .page1_mask_dma1(page1_mask_dma1[31:0]), |
| 2175 | .page1_value_dma1(page1_value_dma1[31:0]), |
| 2176 | .page1_reloc_dma1(page1_reloc_dma1[31:0]), |
| 2177 | .page1_valid_dma1(page1_valid_dma1), |
| 2178 | .send_mbox_dma2(send_mbox_dma2), |
| 2179 | .mbox_dma2_data_valid(mbox_dma2_data_valid), |
| 2180 | .mbox_dma2_data_done(mbox_dma2_data_done), |
| 2181 | .mbox_dma2_data(mbox_dma2_data[127:0]), |
| 2182 | .dmc_txc_dma2_page_handle(dmc_txc_dma2_page_handle[19:0]), |
| 2183 | .tx_dma_cfg_dma2_mbaddr(tx_dma_cfg_dma2_mbaddr[37:0]), |
| 2184 | .page0_mask_dma2(page0_mask_dma2[31:0]), |
| 2185 | .page0_value_dma2(page0_value_dma2[31:0]), |
| 2186 | .page0_reloc_dma2(page0_reloc_dma2[31:0]), |
| 2187 | .page0_valid_dma2(page0_valid_dma2), |
| 2188 | .page1_mask_dma2(page1_mask_dma2[31:0]), |
| 2189 | .page1_value_dma2(page1_value_dma2[31:0]), |
| 2190 | .page1_reloc_dma2(page1_reloc_dma2[31:0]), |
| 2191 | .page1_valid_dma2(page1_valid_dma2), |
| 2192 | .send_mbox_dma3(send_mbox_dma3), |
| 2193 | .mbox_dma3_data_valid(mbox_dma3_data_valid), |
| 2194 | .mbox_dma3_data_done(mbox_dma3_data_done), |
| 2195 | .mbox_dma3_data(mbox_dma3_data[127:0]), |
| 2196 | .dmc_txc_dma3_page_handle(dmc_txc_dma3_page_handle[19:0]), |
| 2197 | .tx_dma_cfg_dma3_mbaddr(tx_dma_cfg_dma3_mbaddr[37:0]), |
| 2198 | .page0_mask_dma3(page0_mask_dma3[31:0]), |
| 2199 | .page0_value_dma3(page0_value_dma3[31:0]), |
| 2200 | .page0_reloc_dma3(page0_reloc_dma3[31:0]), |
| 2201 | .page0_valid_dma3(page0_valid_dma3), |
| 2202 | .page1_mask_dma3(page1_mask_dma3[31:0]), |
| 2203 | .page1_value_dma3(page1_value_dma3[31:0]), |
| 2204 | .page1_reloc_dma3(page1_reloc_dma3[31:0]), |
| 2205 | .page1_valid_dma3(page1_valid_dma3), |
| 2206 | .send_mbox_dma4(send_mbox_dma4), |
| 2207 | .mbox_dma4_data_valid(mbox_dma4_data_valid), |
| 2208 | .mbox_dma4_data_done(mbox_dma4_data_done), |
| 2209 | .mbox_dma4_data(mbox_dma4_data[127:0]), |
| 2210 | .dmc_txc_dma4_page_handle(dmc_txc_dma4_page_handle[19:0]), |
| 2211 | .tx_dma_cfg_dma4_mbaddr(tx_dma_cfg_dma4_mbaddr[37:0]), |
| 2212 | .page0_mask_dma4(page0_mask_dma4[31:0]), |
| 2213 | .page0_value_dma4(page0_value_dma4[31:0]), |
| 2214 | .page0_reloc_dma4(page0_reloc_dma4[31:0]), |
| 2215 | .page0_valid_dma4(page0_valid_dma4), |
| 2216 | .page1_mask_dma4(page1_mask_dma4[31:0]), |
| 2217 | .page1_value_dma4(page1_value_dma4[31:0]), |
| 2218 | .page1_reloc_dma4(page1_reloc_dma4[31:0]), |
| 2219 | .page1_valid_dma4(page1_valid_dma4), |
| 2220 | .send_mbox_dma5(send_mbox_dma5), |
| 2221 | .mbox_dma5_data_valid(mbox_dma5_data_valid), |
| 2222 | .mbox_dma5_data_done(mbox_dma5_data_done), |
| 2223 | .mbox_dma5_data(mbox_dma5_data[127:0]), |
| 2224 | .dmc_txc_dma5_page_handle(dmc_txc_dma5_page_handle[19:0]), |
| 2225 | .tx_dma_cfg_dma5_mbaddr(tx_dma_cfg_dma5_mbaddr[37:0]), |
| 2226 | .page0_mask_dma5(page0_mask_dma5[31:0]), |
| 2227 | .page0_value_dma5(page0_value_dma5[31:0]), |
| 2228 | .page0_reloc_dma5(page0_reloc_dma5[31:0]), |
| 2229 | .page0_valid_dma5(page0_valid_dma5), |
| 2230 | .page1_mask_dma5(page1_mask_dma5[31:0]), |
| 2231 | .page1_value_dma5(page1_value_dma5[31:0]), |
| 2232 | .page1_reloc_dma5(page1_reloc_dma5[31:0]), |
| 2233 | .page1_valid_dma5(page1_valid_dma5), |
| 2234 | .send_mbox_dma6(send_mbox_dma6), |
| 2235 | .mbox_dma6_data_valid(mbox_dma6_data_valid), |
| 2236 | .mbox_dma6_data_done(mbox_dma6_data_done), |
| 2237 | .mbox_dma6_data(mbox_dma6_data[127:0]), |
| 2238 | .dmc_txc_dma6_page_handle(dmc_txc_dma6_page_handle[19:0]), |
| 2239 | .tx_dma_cfg_dma6_mbaddr(tx_dma_cfg_dma6_mbaddr[37:0]), |
| 2240 | .page0_mask_dma6(page0_mask_dma6[31:0]), |
| 2241 | .page0_value_dma6(page0_value_dma6[31:0]), |
| 2242 | .page0_reloc_dma6(page0_reloc_dma6[31:0]), |
| 2243 | .page0_valid_dma6(page0_valid_dma6), |
| 2244 | .page1_mask_dma6(page1_mask_dma6[31:0]), |
| 2245 | .page1_value_dma6(page1_value_dma6[31:0]), |
| 2246 | .page1_reloc_dma6(page1_reloc_dma6[31:0]), |
| 2247 | .page1_valid_dma6(page1_valid_dma6), |
| 2248 | .send_mbox_dma7(send_mbox_dma7), |
| 2249 | .mbox_dma7_data_valid(mbox_dma7_data_valid), |
| 2250 | .mbox_dma7_data_done(mbox_dma7_data_done), |
| 2251 | .mbox_dma7_data(mbox_dma7_data[127:0]), |
| 2252 | .dmc_txc_dma7_page_handle(dmc_txc_dma7_page_handle[19:0]), |
| 2253 | .tx_dma_cfg_dma7_mbaddr(tx_dma_cfg_dma7_mbaddr[37:0]), |
| 2254 | .page0_mask_dma7(page0_mask_dma7[31:0]), |
| 2255 | .page0_value_dma7(page0_value_dma7[31:0]), |
| 2256 | .page0_reloc_dma7(page0_reloc_dma7[31:0]), |
| 2257 | .page0_valid_dma7(page0_valid_dma7), |
| 2258 | .page1_mask_dma7(page1_mask_dma7[31:0]), |
| 2259 | .page1_value_dma7(page1_value_dma7[31:0]), |
| 2260 | .page1_reloc_dma7(page1_reloc_dma7[31:0]), |
| 2261 | .page1_valid_dma7(page1_valid_dma7), |
| 2262 | .send_mbox_dma8(send_mbox_dma8), |
| 2263 | .mbox_dma8_data_valid(mbox_dma8_data_valid), |
| 2264 | .mbox_dma8_data_done(mbox_dma8_data_done), |
| 2265 | .mbox_dma8_data(mbox_dma8_data[127:0]), |
| 2266 | .dmc_txc_dma8_page_handle(dmc_txc_dma8_page_handle[19:0]), |
| 2267 | .tx_dma_cfg_dma8_mbaddr(tx_dma_cfg_dma8_mbaddr[37:0]), |
| 2268 | .page0_mask_dma8(page0_mask_dma8[31:0]), |
| 2269 | .page0_value_dma8(page0_value_dma8[31:0]), |
| 2270 | .page0_reloc_dma8(page0_reloc_dma8[31:0]), |
| 2271 | .page0_valid_dma8(page0_valid_dma8), |
| 2272 | .page1_mask_dma8(page1_mask_dma8[31:0]), |
| 2273 | .page1_value_dma8(page1_value_dma8[31:0]), |
| 2274 | .page1_reloc_dma8(page1_reloc_dma8[31:0]), |
| 2275 | .page1_valid_dma8(page1_valid_dma8), |
| 2276 | .send_mbox_dma9(send_mbox_dma9), |
| 2277 | .mbox_dma9_data_valid(mbox_dma9_data_valid), |
| 2278 | .mbox_dma9_data_done(mbox_dma9_data_done), |
| 2279 | .mbox_dma9_data(mbox_dma9_data[127:0]), |
| 2280 | .dmc_txc_dma9_page_handle(dmc_txc_dma9_page_handle[19:0]), |
| 2281 | .tx_dma_cfg_dma9_mbaddr(tx_dma_cfg_dma9_mbaddr[37:0]), |
| 2282 | .page0_mask_dma9(page0_mask_dma9[31:0]), |
| 2283 | .page0_value_dma9(page0_value_dma9[31:0]), |
| 2284 | .page0_reloc_dma9(page0_reloc_dma9[31:0]), |
| 2285 | .page0_valid_dma9(page0_valid_dma9), |
| 2286 | .page1_mask_dma9(page1_mask_dma9[31:0]), |
| 2287 | .page1_value_dma9(page1_value_dma9[31:0]), |
| 2288 | .page1_reloc_dma9(page1_reloc_dma9[31:0]), |
| 2289 | .page1_valid_dma9(page1_valid_dma9), |
| 2290 | .send_mbox_dma10(send_mbox_dma10), |
| 2291 | .mbox_dma10_data_valid(mbox_dma10_data_valid), |
| 2292 | .mbox_dma10_data_done(mbox_dma10_data_done), |
| 2293 | .mbox_dma10_data(mbox_dma10_data[127:0]), |
| 2294 | .dmc_txc_dma10_page_handle(dmc_txc_dma10_page_handle[19:0]), |
| 2295 | .tx_dma_cfg_dma10_mbaddr(tx_dma_cfg_dma10_mbaddr[37:0]), |
| 2296 | .page0_mask_dma10(page0_mask_dma10[31:0]), |
| 2297 | .page0_value_dma10(page0_value_dma10[31:0]), |
| 2298 | .page0_reloc_dma10(page0_reloc_dma10[31:0]), |
| 2299 | .page0_valid_dma10(page0_valid_dma10), |
| 2300 | .page1_mask_dma10(page1_mask_dma10[31:0]), |
| 2301 | .page1_value_dma10(page1_value_dma10[31:0]), |
| 2302 | .page1_reloc_dma10(page1_reloc_dma10[31:0]), |
| 2303 | .page1_valid_dma10(page1_valid_dma10), |
| 2304 | .send_mbox_dma11(send_mbox_dma11), |
| 2305 | .mbox_dma11_data_valid(mbox_dma11_data_valid), |
| 2306 | .mbox_dma11_data_done(mbox_dma11_data_done), |
| 2307 | .mbox_dma11_data(mbox_dma11_data[127:0]), |
| 2308 | .dmc_txc_dma11_page_handle(dmc_txc_dma11_page_handle[19:0]), |
| 2309 | .tx_dma_cfg_dma11_mbaddr(tx_dma_cfg_dma11_mbaddr[37:0]), |
| 2310 | .page0_mask_dma11(page0_mask_dma11[31:0]), |
| 2311 | .page0_value_dma11(page0_value_dma11[31:0]), |
| 2312 | .page0_reloc_dma11(page0_reloc_dma11[31:0]), |
| 2313 | .page0_valid_dma11(page0_valid_dma11), |
| 2314 | .page1_mask_dma11(page1_mask_dma11[31:0]), |
| 2315 | .page1_value_dma11(page1_value_dma11[31:0]), |
| 2316 | .page1_reloc_dma11(page1_reloc_dma11[31:0]), |
| 2317 | .page1_valid_dma11(page1_valid_dma11), |
| 2318 | .send_mbox_dma12(send_mbox_dma12), |
| 2319 | .mbox_dma12_data_valid(mbox_dma12_data_valid), |
| 2320 | .mbox_dma12_data_done(mbox_dma12_data_done), |
| 2321 | .mbox_dma12_data(mbox_dma12_data[127:0]), |
| 2322 | .dmc_txc_dma12_page_handle(dmc_txc_dma12_page_handle[19:0]), |
| 2323 | .tx_dma_cfg_dma12_mbaddr(tx_dma_cfg_dma12_mbaddr[37:0]), |
| 2324 | .page0_mask_dma12(page0_mask_dma12[31:0]), |
| 2325 | .page0_value_dma12(page0_value_dma12[31:0]), |
| 2326 | .page0_reloc_dma12(page0_reloc_dma12[31:0]), |
| 2327 | .page0_valid_dma12(page0_valid_dma12), |
| 2328 | .page1_mask_dma12(page1_mask_dma12[31:0]), |
| 2329 | .page1_value_dma12(page1_value_dma12[31:0]), |
| 2330 | .page1_reloc_dma12(page1_reloc_dma12[31:0]), |
| 2331 | .page1_valid_dma12(page1_valid_dma12), |
| 2332 | .send_mbox_dma13(send_mbox_dma13), |
| 2333 | .mbox_dma13_data_valid(mbox_dma13_data_valid), |
| 2334 | .mbox_dma13_data_done(mbox_dma13_data_done), |
| 2335 | .mbox_dma13_data(mbox_dma13_data[127:0]), |
| 2336 | .dmc_txc_dma13_page_handle(dmc_txc_dma13_page_handle[19:0]), |
| 2337 | .tx_dma_cfg_dma13_mbaddr(tx_dma_cfg_dma13_mbaddr[37:0]), |
| 2338 | .page0_mask_dma13(page0_mask_dma13[31:0]), |
| 2339 | .page0_value_dma13(page0_value_dma13[31:0]), |
| 2340 | .page0_reloc_dma13(page0_reloc_dma13[31:0]), |
| 2341 | .page0_valid_dma13(page0_valid_dma13), |
| 2342 | .page1_mask_dma13(page1_mask_dma13[31:0]), |
| 2343 | .page1_value_dma13(page1_value_dma13[31:0]), |
| 2344 | .page1_reloc_dma13(page1_reloc_dma13[31:0]), |
| 2345 | .page1_valid_dma13(page1_valid_dma13), |
| 2346 | .send_mbox_dma14(send_mbox_dma14), |
| 2347 | .mbox_dma14_data_valid(mbox_dma14_data_valid), |
| 2348 | .mbox_dma14_data_done(mbox_dma14_data_done), |
| 2349 | .mbox_dma14_data(mbox_dma14_data[127:0]), |
| 2350 | .dmc_txc_dma14_page_handle(dmc_txc_dma14_page_handle[19:0]), |
| 2351 | .tx_dma_cfg_dma14_mbaddr(tx_dma_cfg_dma14_mbaddr[37:0]), |
| 2352 | .page0_mask_dma14(page0_mask_dma14[31:0]), |
| 2353 | .page0_value_dma14(page0_value_dma14[31:0]), |
| 2354 | .page0_reloc_dma14(page0_reloc_dma14[31:0]), |
| 2355 | .page0_valid_dma14(page0_valid_dma14), |
| 2356 | .page1_mask_dma14(page1_mask_dma14[31:0]), |
| 2357 | .page1_value_dma14(page1_value_dma14[31:0]), |
| 2358 | .page1_reloc_dma14(page1_reloc_dma14[31:0]), |
| 2359 | .page1_valid_dma14(page1_valid_dma14), |
| 2360 | .send_mbox_dma15(send_mbox_dma15), |
| 2361 | .mbox_dma15_data_valid(mbox_dma15_data_valid), |
| 2362 | .mbox_dma15_data_done(mbox_dma15_data_done), |
| 2363 | .mbox_dma15_data(mbox_dma15_data[127:0]), |
| 2364 | .dmc_txc_dma15_page_handle(dmc_txc_dma15_page_handle[19:0]), |
| 2365 | .tx_dma_cfg_dma15_mbaddr(tx_dma_cfg_dma15_mbaddr[37:0]), |
| 2366 | .page0_mask_dma15(page0_mask_dma15[31:0]), |
| 2367 | .page0_value_dma15(page0_value_dma15[31:0]), |
| 2368 | .page0_reloc_dma15(page0_reloc_dma15[31:0]), |
| 2369 | .page0_valid_dma15(page0_valid_dma15), |
| 2370 | .page1_mask_dma15(page1_mask_dma15[31:0]), |
| 2371 | .page1_value_dma15(page1_value_dma15[31:0]), |
| 2372 | .page1_reloc_dma15(page1_reloc_dma15[31:0]), |
| 2373 | .page1_valid_dma15(page1_valid_dma15), |
| 2374 | `ifdef NEPTUNE |
| 2375 | .send_mbox_dma16(send_mbox_dma16), |
| 2376 | .mbox_dma16_data_valid(mbox_dma16_data_valid), |
| 2377 | .mbox_dma16_data_done(mbox_dma16_data_done), |
| 2378 | .mbox_dma16_data(mbox_dma16_data[127:0]), |
| 2379 | .dmc_txc_dma16_page_handle(dmc_txc_dma16_page_handle[19:0]), |
| 2380 | .tx_dma_cfg_dma16_mbaddr(tx_dma_cfg_dma16_mbaddr[37:0]), |
| 2381 | .page0_mask_dma16(page0_mask_dma16[31:0]), |
| 2382 | .page0_value_dma16(page0_value_dma16[31:0]), |
| 2383 | .page0_reloc_dma16(page0_reloc_dma16[31:0]), |
| 2384 | .page0_valid_dma16(page0_valid_dma16), |
| 2385 | .page1_mask_dma16(page1_mask_dma16[31:0]), |
| 2386 | .page1_value_dma16(page1_value_dma16[31:0]), |
| 2387 | .page1_reloc_dma16(page1_reloc_dma16[31:0]), |
| 2388 | .page1_valid_dma16(page1_valid_dma16), |
| 2389 | .send_mbox_dma17(send_mbox_dma17), |
| 2390 | .mbox_dma17_data_valid(mbox_dma17_data_valid), |
| 2391 | .mbox_dma17_data_done(mbox_dma17_data_done), |
| 2392 | .mbox_dma17_data(mbox_dma17_data[127:0]), |
| 2393 | .dmc_txc_dma17_page_handle(dmc_txc_dma17_page_handle[19:0]), |
| 2394 | .tx_dma_cfg_dma17_mbaddr(tx_dma_cfg_dma17_mbaddr[37:0]), |
| 2395 | .page0_mask_dma17(page0_mask_dma17[31:0]), |
| 2396 | .page0_value_dma17(page0_value_dma17[31:0]), |
| 2397 | .page0_reloc_dma17(page0_reloc_dma17[31:0]), |
| 2398 | .page0_valid_dma17(page0_valid_dma17), |
| 2399 | .page1_mask_dma17(page1_mask_dma17[31:0]), |
| 2400 | .page1_value_dma17(page1_value_dma17[31:0]), |
| 2401 | .page1_reloc_dma17(page1_reloc_dma17[31:0]), |
| 2402 | .page1_valid_dma17(page1_valid_dma17), |
| 2403 | .send_mbox_dma18(send_mbox_dma18), |
| 2404 | .mbox_dma18_data_valid(mbox_dma18_data_valid), |
| 2405 | .mbox_dma18_data_done(mbox_dma18_data_done), |
| 2406 | .mbox_dma18_data(mbox_dma18_data[127:0]), |
| 2407 | .dmc_txc_dma18_page_handle(dmc_txc_dma18_page_handle[19:0]), |
| 2408 | .tx_dma_cfg_dma18_mbaddr(tx_dma_cfg_dma18_mbaddr[37:0]), |
| 2409 | .page0_mask_dma18(page0_mask_dma18[31:0]), |
| 2410 | .page0_value_dma18(page0_value_dma18[31:0]), |
| 2411 | .page0_reloc_dma18(page0_reloc_dma18[31:0]), |
| 2412 | .page0_valid_dma18(page0_valid_dma18), |
| 2413 | .page1_mask_dma18(page1_mask_dma18[31:0]), |
| 2414 | .page1_value_dma18(page1_value_dma18[31:0]), |
| 2415 | .page1_reloc_dma18(page1_reloc_dma18[31:0]), |
| 2416 | .page1_valid_dma18(page1_valid_dma18), |
| 2417 | .send_mbox_dma19(send_mbox_dma19), |
| 2418 | .mbox_dma19_data_valid(mbox_dma19_data_valid), |
| 2419 | .mbox_dma19_data_done(mbox_dma19_data_done), |
| 2420 | .mbox_dma19_data(mbox_dma19_data[127:0]), |
| 2421 | .dmc_txc_dma19_page_handle(dmc_txc_dma19_page_handle[19:0]), |
| 2422 | .tx_dma_cfg_dma19_mbaddr(tx_dma_cfg_dma19_mbaddr[37:0]), |
| 2423 | .page0_mask_dma19(page0_mask_dma19[31:0]), |
| 2424 | .page0_value_dma19(page0_value_dma19[31:0]), |
| 2425 | .page0_reloc_dma19(page0_reloc_dma19[31:0]), |
| 2426 | .page0_valid_dma19(page0_valid_dma19), |
| 2427 | .page1_mask_dma19(page1_mask_dma19[31:0]), |
| 2428 | .page1_value_dma19(page1_value_dma19[31:0]), |
| 2429 | .page1_reloc_dma19(page1_reloc_dma19[31:0]), |
| 2430 | .page1_valid_dma19(page1_valid_dma19), |
| 2431 | .send_mbox_dma20(send_mbox_dma20), |
| 2432 | .mbox_dma20_data_valid(mbox_dma20_data_valid), |
| 2433 | .mbox_dma20_data_done(mbox_dma20_data_done), |
| 2434 | .mbox_dma20_data(mbox_dma20_data[127:0]), |
| 2435 | .dmc_txc_dma20_page_handle(dmc_txc_dma20_page_handle[19:0]), |
| 2436 | .tx_dma_cfg_dma20_mbaddr(tx_dma_cfg_dma20_mbaddr[37:0]), |
| 2437 | .page0_mask_dma20(page0_mask_dma20[31:0]), |
| 2438 | .page0_value_dma20(page0_value_dma20[31:0]), |
| 2439 | .page0_reloc_dma20(page0_reloc_dma20[31:0]), |
| 2440 | .page0_valid_dma20(page0_valid_dma20), |
| 2441 | .page1_mask_dma20(page1_mask_dma20[31:0]), |
| 2442 | .page1_value_dma20(page1_value_dma20[31:0]), |
| 2443 | .page1_reloc_dma20(page1_reloc_dma20[31:0]), |
| 2444 | .page1_valid_dma20(page1_valid_dma20), |
| 2445 | .send_mbox_dma21(send_mbox_dma21), |
| 2446 | .mbox_dma21_data_valid(mbox_dma21_data_valid), |
| 2447 | .mbox_dma21_data_done(mbox_dma21_data_done), |
| 2448 | .mbox_dma21_data(mbox_dma21_data[127:0]), |
| 2449 | .dmc_txc_dma21_page_handle(dmc_txc_dma21_page_handle[19:0]), |
| 2450 | .tx_dma_cfg_dma21_mbaddr(tx_dma_cfg_dma21_mbaddr[37:0]), |
| 2451 | .page0_mask_dma21(page0_mask_dma21[31:0]), |
| 2452 | .page0_value_dma21(page0_value_dma21[31:0]), |
| 2453 | .page0_reloc_dma21(page0_reloc_dma21[31:0]), |
| 2454 | .page0_valid_dma21(page0_valid_dma21), |
| 2455 | .page1_mask_dma21(page1_mask_dma21[31:0]), |
| 2456 | .page1_value_dma21(page1_value_dma21[31:0]), |
| 2457 | .page1_reloc_dma21(page1_reloc_dma21[31:0]), |
| 2458 | .page1_valid_dma21(page1_valid_dma21), |
| 2459 | .send_mbox_dma22(send_mbox_dma22), |
| 2460 | .mbox_dma22_data_valid(mbox_dma22_data_valid), |
| 2461 | .mbox_dma22_data_done(mbox_dma22_data_done), |
| 2462 | .mbox_dma22_data(mbox_dma22_data[127:0]), |
| 2463 | .dmc_txc_dma22_page_handle(dmc_txc_dma22_page_handle[19:0]), |
| 2464 | .tx_dma_cfg_dma22_mbaddr(tx_dma_cfg_dma22_mbaddr[37:0]), |
| 2465 | .page0_mask_dma22(page0_mask_dma22[31:0]), |
| 2466 | .page0_value_dma22(page0_value_dma22[31:0]), |
| 2467 | .page0_reloc_dma22(page0_reloc_dma22[31:0]), |
| 2468 | .page0_valid_dma22(page0_valid_dma22), |
| 2469 | .page1_mask_dma22(page1_mask_dma22[31:0]), |
| 2470 | .page1_value_dma22(page1_value_dma22[31:0]), |
| 2471 | .page1_reloc_dma22(page1_reloc_dma22[31:0]), |
| 2472 | .page1_valid_dma22(page1_valid_dma22), |
| 2473 | .send_mbox_dma23(send_mbox_dma23), |
| 2474 | .mbox_dma23_data_valid(mbox_dma23_data_valid), |
| 2475 | .mbox_dma23_data_done(mbox_dma23_data_done), |
| 2476 | .mbox_dma23_data(mbox_dma23_data[127:0]), |
| 2477 | .dmc_txc_dma23_page_handle(dmc_txc_dma23_page_handle[19:0]), |
| 2478 | .tx_dma_cfg_dma23_mbaddr(tx_dma_cfg_dma23_mbaddr[37:0]), |
| 2479 | .page0_mask_dma23(page0_mask_dma23[31:0]), |
| 2480 | .page0_value_dma23(page0_value_dma23[31:0]), |
| 2481 | .page0_reloc_dma23(page0_reloc_dma23[31:0]), |
| 2482 | .page0_valid_dma23(page0_valid_dma23), |
| 2483 | .page1_mask_dma23(page1_mask_dma23[31:0]), |
| 2484 | .page1_value_dma23(page1_value_dma23[31:0]), |
| 2485 | .page1_reloc_dma23(page1_reloc_dma23[31:0]), |
| 2486 | .page1_valid_dma23(page1_valid_dma23), |
| 2487 | `else |
| 2488 | `endif |
| 2489 | .dmc_txc_dma0_func_num(dmc_txc_dma0_func_num[1:0]), |
| 2490 | .dmc_txc_dma1_func_num(dmc_txc_dma1_func_num[1:0]), |
| 2491 | .dmc_txc_dma2_func_num(dmc_txc_dma2_func_num[1:0]), |
| 2492 | .dmc_txc_dma3_func_num(dmc_txc_dma3_func_num[1:0]), |
| 2493 | .dmc_txc_dma4_func_num(dmc_txc_dma4_func_num[1:0]), |
| 2494 | .dmc_txc_dma5_func_num(dmc_txc_dma5_func_num[1:0]), |
| 2495 | .dmc_txc_dma6_func_num(dmc_txc_dma6_func_num[1:0]), |
| 2496 | .dmc_txc_dma7_func_num(dmc_txc_dma7_func_num[1:0]), |
| 2497 | .dmc_txc_dma8_func_num(dmc_txc_dma8_func_num[1:0]), |
| 2498 | .dmc_txc_dma9_func_num(dmc_txc_dma9_func_num[1:0]), |
| 2499 | .dmc_txc_dma10_func_num(dmc_txc_dma10_func_num[1:0]), |
| 2500 | .dmc_txc_dma11_func_num(dmc_txc_dma11_func_num[1:0]), |
| 2501 | .dmc_txc_dma12_func_num(dmc_txc_dma12_func_num[1:0]), |
| 2502 | .dmc_txc_dma13_func_num(dmc_txc_dma13_func_num[1:0]), |
| 2503 | .dmc_txc_dma14_func_num(dmc_txc_dma14_func_num[1:0]), |
| 2504 | .dmc_txc_dma15_func_num(dmc_txc_dma15_func_num[1:0]), |
| 2505 | `ifdef NEPTUNE |
| 2506 | .dmc_txc_dma16_func_num(dmc_txc_dma16_func_num[1:0]), |
| 2507 | .dmc_txc_dma17_func_num(dmc_txc_dma17_func_num[1:0]), |
| 2508 | .dmc_txc_dma18_func_num(dmc_txc_dma18_func_num[1:0]), |
| 2509 | .dmc_txc_dma19_func_num(dmc_txc_dma19_func_num[1:0]), |
| 2510 | .dmc_txc_dma20_func_num(dmc_txc_dma20_func_num[1:0]), |
| 2511 | .dmc_txc_dma21_func_num(dmc_txc_dma21_func_num[1:0]), |
| 2512 | .dmc_txc_dma22_func_num(dmc_txc_dma22_func_num[1:0]), |
| 2513 | .dmc_txc_dma23_func_num(dmc_txc_dma23_func_num[1:0]), |
| 2514 | `else |
| 2515 | `endif |
| 2516 | .arb0_tdmc_data_req(arb0_tdmc_data_req), |
| 2517 | .arb0_tdmc_req_accept(arb0_tdmc_req_accept), |
| 2518 | .meta_dmc_ack_dma_num(meta_dmc_ack_dma_num[4:0]), |
| 2519 | .meta_dmc_ack_client(meta_dmc_ack_client), |
| 2520 | .meta_dmc_ack_complete(meta_dmc_ack_complete), |
| 2521 | .meta_dmc_ack_ready(meta_dmc_ack_ready), |
| 2522 | .meta_dmc_ack_cmd(meta_dmc_ack_cmd[7:0]), |
| 2523 | .meta_dmc_ack_cmd_status(meta_dmc_ack_cmd_status[3:0])); |
| 2524 | |
| 2525 | |
| 2526 | |
| 2527 | endmodule |
| 2528 | |