| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_txc_RegisterControl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
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| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /********************************************************************* |
| 36 | * |
| 37 | * niu_txc_RegisterControl.v |
| 38 | * |
| 39 | * NIU Transmit Register Decodes & Controller |
| 40 | * |
| 41 | * Orignal Author(s): Rahoul Puri |
| 42 | * Modifier(s): |
| 43 | * Project(s): Neptune |
| 44 | * |
| 45 | * Copyright (c) 2005 Sun Microsystems, Inc. |
| 46 | * |
| 47 | * All Rights Reserved. |
| 48 | * |
| 49 | * This verilog model is the confidential and proprietary property of |
| 50 | * Sun Microsystems, Inc., and the possession or use of this model |
| 51 | * requires a written license from Sun Microsystems, Inc. |
| 52 | * |
| 53 | **********************************************************************/ |
| 54 | |
| 55 | `include "timescale.v" |
| 56 | |
| 57 | module niu_txc_RegisterControl ( |
| 58 | SysClk, |
| 59 | Reset_L, |
| 60 | niu_txc_interrupts, |
| 61 | |
| 62 | Slave_32BitMode, |
| 63 | Slave_Read, // Slave Read & Write Bar |
| 64 | Slave_Sel, // Slave Sel |
| 65 | Slave_Addr, // Slave Address |
| 66 | Slave_DataIn, // Slave Write Data |
| 67 | Slave_Ack, // Slave PIO Ack |
| 68 | Slave_Err, // Slave PIO Error |
| 69 | SlaveStrobe, |
| 70 | SlaveAddrB1, |
| 71 | SlaveAddrB0, |
| 72 | SlaveDataInB0, |
| 73 | Slave_DataOut, // Slave Read Data |
| 74 | |
| 75 | Txc_Enabled, |
| 76 | Port0_Enabled, |
| 77 | Port1_Enabled, |
| 78 | `ifdef NEPTUNE |
| 79 | Port2_Enabled, |
| 80 | Port3_Enabled, |
| 81 | `endif |
| 82 | FlushEngine, |
| 83 | |
| 84 | DMA0to3_Slave_Data, |
| 85 | DMA4to7_Slave_Data, |
| 86 | DMA8to11_Slave_Data, |
| 87 | DMA12to15_Slave_Data, |
| 88 | Read_DMA0_Register, |
| 89 | Read_DMA1_Register, |
| 90 | Read_DMA2_Register, |
| 91 | Read_DMA3_Register, |
| 92 | Read_DMA4_Register, |
| 93 | Read_DMA5_Register, |
| 94 | Read_DMA6_Register, |
| 95 | Read_DMA7_Register, |
| 96 | Read_DMA8_Register, |
| 97 | Read_DMA9_Register, |
| 98 | Read_DMA10_Register, |
| 99 | Read_DMA11_Register, |
| 100 | Read_DMA12_Register, |
| 101 | Read_DMA13_Register, |
| 102 | Read_DMA14_Register, |
| 103 | Read_DMA15_Register, |
| 104 | Write_DMA0_Register, |
| 105 | Write_DMA1_Register, |
| 106 | Write_DMA2_Register, |
| 107 | Write_DMA3_Register, |
| 108 | Write_DMA4_Register, |
| 109 | Write_DMA5_Register, |
| 110 | Write_DMA6_Register, |
| 111 | Write_DMA7_Register, |
| 112 | Write_DMA8_Register, |
| 113 | Write_DMA9_Register, |
| 114 | Write_DMA10_Register, |
| 115 | Write_DMA11_Register, |
| 116 | Write_DMA12_Register, |
| 117 | Write_DMA13_Register, |
| 118 | Write_DMA14_Register, |
| 119 | Write_DMA15_Register, |
| 120 | |
| 121 | `ifdef NEPTUNE |
| 122 | DMA16to19_Slave_Data, |
| 123 | DMA20to23_Slave_Data, |
| 124 | Read_DMA16_Register, |
| 125 | Read_DMA17_Register, |
| 126 | Read_DMA18_Register, |
| 127 | Read_DMA19_Register, |
| 128 | Read_DMA20_Register, |
| 129 | Read_DMA21_Register, |
| 130 | Read_DMA22_Register, |
| 131 | Read_DMA23_Register, |
| 132 | Write_DMA16_Register, |
| 133 | Write_DMA17_Register, |
| 134 | Write_DMA18_Register, |
| 135 | Write_DMA19_Register, |
| 136 | Write_DMA20_Register, |
| 137 | Write_DMA21_Register, |
| 138 | Write_DMA22_Register, |
| 139 | Write_DMA23_Register, |
| 140 | `endif |
| 141 | |
| 142 | Port0to1_Slave_Data, |
| 143 | Read_Port0_Register, |
| 144 | Write_Port0_Register, |
| 145 | PosEdgeWritePort0, |
| 146 | |
| 147 | `ifdef NEPTUNE |
| 148 | Port2to3_Slave_Data, |
| 149 | Read_Port2_Register, |
| 150 | Write_Port2_Register, |
| 151 | PosEdgeWritePort2, |
| 152 | `endif |
| 153 | |
| 154 | Port0_PioDataIn, |
| 155 | Port0_ReOrder_ECC_State, |
| 156 | Port0_StoreForward_ECC_State, |
| 157 | Port0_PacketAssyDead, |
| 158 | Port0_ReOrder_Error, |
| 159 | Port0_MaxReorderNumber, |
| 160 | |
| 161 | Port1_PioDataIn, |
| 162 | Port1_ReOrder_ECC_State, |
| 163 | Port1_StoreForward_ECC_State, |
| 164 | Port1_PacketAssyDead, |
| 165 | Port1_ReOrder_Error, |
| 166 | Port1_MaxReorderNumber, |
| 167 | |
| 168 | `ifdef NEPTUNE |
| 169 | Port2_PioDataIn, |
| 170 | Port2_ReOrder_ECC_State, |
| 171 | Port2_StoreForward_ECC_State, |
| 172 | Port2_PacketAssyDead, |
| 173 | Port2_ReOrder_Error, |
| 174 | Port2_MaxReorderNumber, |
| 175 | |
| 176 | Port3_PioDataIn, |
| 177 | Port3_ReOrder_ECC_State, |
| 178 | Port3_StoreForward_ECC_State, |
| 179 | Port3_PacketAssyDead, |
| 180 | Port3_ReOrder_Error, |
| 181 | Port3_MaxReorderNumber, |
| 182 | `endif |
| 183 | Debug_Select, |
| 184 | TrainingVector |
| 185 | ); |
| 186 | |
| 187 | // Include Header Files |
| 188 | `include "txc_defines.h" |
| 189 | `include "niu_txc_reg_defines.h" |
| 190 | |
| 191 | // Global Signals |
| 192 | input SysClk; |
| 193 | input Reset_L; |
| 194 | |
| 195 | // Interrupts Interface |
| 196 | output niu_txc_interrupts; |
| 197 | |
| 198 | reg niu_txc_interrupts; |
| 199 | |
| 200 | // Slave Interface |
| 201 | input Slave_32BitMode; |
| 202 | input Slave_Read; |
| 203 | input Slave_Sel; |
| 204 | input [19:0] Slave_Addr; |
| 205 | input [31:0] Slave_DataIn; |
| 206 | |
| 207 | output Slave_Ack; |
| 208 | output Slave_Err; |
| 209 | output SlaveStrobe; |
| 210 | output [8:2] SlaveAddrB1; |
| 211 | output [11:2] SlaveAddrB0; |
| 212 | output [31:0] SlaveDataInB0; |
| 213 | output [63:0] Slave_DataOut; |
| 214 | |
| 215 | reg Slave_Ack; |
| 216 | reg Slave_Err; |
| 217 | reg [31:0] SlaveDataInB0; |
| 218 | |
| 219 | // |
| 220 | output Txc_Enabled; |
| 221 | output Port0_Enabled; |
| 222 | output Port1_Enabled; |
| 223 | output FlushEngine; |
| 224 | output [5:0] Debug_Select; |
| 225 | output [31:0] TrainingVector; |
| 226 | |
| 227 | reg Txc_Enabled; |
| 228 | reg Port0_Enabled; |
| 229 | reg Port1_Enabled; |
| 230 | //reg FlushEngine; |
| 231 | reg [5:0] Debug_Select; |
| 232 | reg [31:0] TrainingVector; |
| 233 | |
| 234 | `ifdef NEPTUNE |
| 235 | output Port2_Enabled; |
| 236 | output Port3_Enabled; |
| 237 | |
| 238 | reg Port2_Enabled; |
| 239 | reg Port3_Enabled; |
| 240 | `endif |
| 241 | |
| 242 | /*--------------------------------------------------------------*/ |
| 243 | // DMA Registers |
| 244 | /*--------------------------------------------------------------*/ |
| 245 | input [31:0] DMA0to3_Slave_Data; |
| 246 | input [31:0] DMA4to7_Slave_Data; |
| 247 | input [31:0] DMA8to11_Slave_Data; |
| 248 | input [31:0] DMA12to15_Slave_Data; |
| 249 | |
| 250 | output Read_DMA0_Register; |
| 251 | output Read_DMA1_Register; |
| 252 | output Read_DMA2_Register; |
| 253 | output Read_DMA3_Register; |
| 254 | output Read_DMA4_Register; |
| 255 | output Read_DMA5_Register; |
| 256 | output Read_DMA6_Register; |
| 257 | output Read_DMA7_Register; |
| 258 | output Read_DMA8_Register; |
| 259 | output Read_DMA9_Register; |
| 260 | output Read_DMA10_Register; |
| 261 | output Read_DMA11_Register; |
| 262 | output Read_DMA12_Register; |
| 263 | output Read_DMA13_Register; |
| 264 | output Read_DMA14_Register; |
| 265 | output Read_DMA15_Register; |
| 266 | output Write_DMA0_Register; |
| 267 | output Write_DMA1_Register; |
| 268 | output Write_DMA2_Register; |
| 269 | output Write_DMA3_Register; |
| 270 | output Write_DMA4_Register; |
| 271 | output Write_DMA5_Register; |
| 272 | output Write_DMA6_Register; |
| 273 | output Write_DMA7_Register; |
| 274 | output Write_DMA8_Register; |
| 275 | output Write_DMA9_Register; |
| 276 | output Write_DMA10_Register; |
| 277 | output Write_DMA11_Register; |
| 278 | output Write_DMA12_Register; |
| 279 | output Write_DMA13_Register; |
| 280 | output Write_DMA14_Register; |
| 281 | output Write_DMA15_Register; |
| 282 | |
| 283 | `ifdef NEPTUNE |
| 284 | input [31:0] DMA16to19_Slave_Data; |
| 285 | input [31:0] DMA20to23_Slave_Data; |
| 286 | |
| 287 | output Read_DMA16_Register; |
| 288 | output Read_DMA17_Register; |
| 289 | output Read_DMA18_Register; |
| 290 | output Read_DMA19_Register; |
| 291 | output Read_DMA20_Register; |
| 292 | output Read_DMA21_Register; |
| 293 | output Read_DMA22_Register; |
| 294 | output Read_DMA23_Register; |
| 295 | output Write_DMA16_Register; |
| 296 | output Write_DMA17_Register; |
| 297 | output Write_DMA18_Register; |
| 298 | output Write_DMA19_Register; |
| 299 | output Write_DMA20_Register; |
| 300 | output Write_DMA21_Register; |
| 301 | output Write_DMA22_Register; |
| 302 | output Write_DMA23_Register; |
| 303 | `endif |
| 304 | |
| 305 | /*--------------------------------------------------------------*/ |
| 306 | // Grouped Port Registers |
| 307 | /*--------------------------------------------------------------*/ |
| 308 | input [31:0] Port0to1_Slave_Data; |
| 309 | |
| 310 | output Read_Port0_Register; |
| 311 | output Write_Port0_Register; |
| 312 | output PosEdgeWritePort0; |
| 313 | |
| 314 | `ifdef NEPTUNE |
| 315 | input [31:0] Port2to3_Slave_Data; |
| 316 | |
| 317 | output Read_Port2_Register; |
| 318 | output Write_Port2_Register; |
| 319 | output PosEdgeWritePort2; |
| 320 | `endif |
| 321 | |
| 322 | /*--------------------------------------------------------------*/ |
| 323 | // Port 0 Registers |
| 324 | /*--------------------------------------------------------------*/ |
| 325 | // Port 0 ReOrder PIO Control Registers |
| 326 | output [31:0] Port0_PioDataIn; |
| 327 | |
| 328 | reg [31:0] Port0_PioDataIn; |
| 329 | |
| 330 | // ECC Error Reporting PIO Control Registers |
| 331 | input [17:16] Port0_ReOrder_ECC_State; |
| 332 | input [17:16] Port0_StoreForward_ECC_State; |
| 333 | |
| 334 | // ECC Control & Status Registers |
| 335 | input Port0_PacketAssyDead; |
| 336 | input Port0_ReOrder_Error; |
| 337 | |
| 338 | // Control Registers |
| 339 | output [3:0] Port0_MaxReorderNumber; |
| 340 | |
| 341 | reg [3:0] Port0_MaxReorderNumber; |
| 342 | |
| 343 | /*--------------------------------------------------------------*/ |
| 344 | // Port 1 Registers |
| 345 | /*--------------------------------------------------------------*/ |
| 346 | // ReOrder PIO Control Registers |
| 347 | output [31:0] Port1_PioDataIn; |
| 348 | |
| 349 | reg [31:0] Port1_PioDataIn; |
| 350 | |
| 351 | // ECC Error Reporting PIO Control Registers |
| 352 | input [17:16] Port1_ReOrder_ECC_State; |
| 353 | input [17:16] Port1_StoreForward_ECC_State; |
| 354 | |
| 355 | // ECC Control & Status Registers |
| 356 | input Port1_PacketAssyDead; |
| 357 | input Port1_ReOrder_Error; |
| 358 | |
| 359 | // Control Registers |
| 360 | output [3:0] Port1_MaxReorderNumber; |
| 361 | |
| 362 | reg [3:0] Port1_MaxReorderNumber; |
| 363 | |
| 364 | /*--------------------------------------------------------------*/ |
| 365 | // Port 2 Registers |
| 366 | /*--------------------------------------------------------------*/ |
| 367 | `ifdef NEPTUNE |
| 368 | // ReOrder PIO Control Registers |
| 369 | output [31:0] Port2_PioDataIn; |
| 370 | |
| 371 | reg [31:0] Port2_PioDataIn; |
| 372 | |
| 373 | // ECC Error Reporting PIO Control Registers |
| 374 | input [17:16] Port2_ReOrder_ECC_State; |
| 375 | input [17:16] Port2_StoreForward_ECC_State; |
| 376 | |
| 377 | // ECC Control & Status Registers |
| 378 | input Port2_PacketAssyDead; |
| 379 | input Port2_ReOrder_Error; |
| 380 | |
| 381 | // Control Registers |
| 382 | output [3:0] Port2_MaxReorderNumber; |
| 383 | |
| 384 | reg [3:0] Port2_MaxReorderNumber; |
| 385 | |
| 386 | /*--------------------------------------------------------------*/ |
| 387 | // Port 3 Registers |
| 388 | /*--------------------------------------------------------------*/ |
| 389 | // ReOrder PIO Control Registers |
| 390 | output [31:0] Port3_PioDataIn; |
| 391 | |
| 392 | reg [31:0] Port3_PioDataIn; |
| 393 | |
| 394 | // ECC Error Reporting PIO Control Registers |
| 395 | input [17:16] Port3_ReOrder_ECC_State; |
| 396 | input [17:16] Port3_StoreForward_ECC_State; |
| 397 | |
| 398 | // ECC Control & Status Registers |
| 399 | input Port3_PacketAssyDead; |
| 400 | input Port3_ReOrder_Error; |
| 401 | |
| 402 | // Control Registers |
| 403 | output [3:0] Port3_MaxReorderNumber; |
| 404 | |
| 405 | reg [3:0] Port3_MaxReorderNumber; |
| 406 | |
| 407 | `endif |
| 408 | |
| 409 | /*--------------------------------------------------------------*/ |
| 410 | // Wires & Registers |
| 411 | /*--------------------------------------------------------------*/ |
| 412 | wire reserved32Bit; |
| 413 | wire generateNACK; |
| 414 | wire readSlaveRegB0; |
| 415 | wire readSlaveRegB1; |
| 416 | wire writeSlaveRegB0; |
| 417 | wire writeSlaveRegB1; |
| 418 | wire niu_txc_RSV_decode; |
| 419 | wire niu_txc_valid_decode; |
| 420 | wire txc_pio_decode; |
| 421 | wire txc_port0_decode; |
| 422 | wire txc_port1_decode; |
| 423 | wire ports0and1_decode; |
| 424 | wire read_PIO_Register; |
| 425 | wire write_PIO_Register; |
| 426 | wire dma0_decode; |
| 427 | wire dma1_decode; |
| 428 | wire dma2_decode; |
| 429 | wire dma3_decode; |
| 430 | wire dma4_decode; |
| 431 | wire dma5_decode; |
| 432 | wire dma6_decode; |
| 433 | wire dma7_decode; |
| 434 | wire dma8_decode; |
| 435 | wire dma9_decode; |
| 436 | wire dma10_decode; |
| 437 | wire dma11_decode; |
| 438 | wire dma12_decode; |
| 439 | wire dma13_decode; |
| 440 | wire dma14_decode; |
| 441 | wire dma15_decode; |
| 442 | wire dma_rsv_space; |
| 443 | wire dma_decode_space; |
| 444 | wire posEdgeSetIntEvent; |
| 445 | wire posEdgeClrIntEvent; |
| 446 | wire read_DMA0to3_Register; |
| 447 | wire read_DMA4to7_Register; |
| 448 | wire read_DMA8to11_Register; |
| 449 | wire read_DMA12to15_Register; |
| 450 | wire [31:0] setTxcIntEvents; |
| 451 | wire [31:0] txcInterruptMask; |
| 452 | |
| 453 | reg en_Slave_Ack; |
| 454 | reg en_Slave_AckD1; |
| 455 | reg write_Port0_RegisterD1; |
| 456 | reg functionZero; |
| 457 | reg setIntEvent; |
| 458 | reg setIntEventD1; |
| 459 | reg clrIntEvent; |
| 460 | reg clrIntEventD1; |
| 461 | reg slaveReadB0; |
| 462 | reg slaveReadB1; |
| 463 | reg slaveSelB0; |
| 464 | reg slaveSelB1; |
| 465 | reg [5:0] port0_txcInterruptMask; |
| 466 | reg [5:0] port1_txcInterruptMask; |
| 467 | reg [11:2] slaveAddrBuf1; |
| 468 | reg [18:0] slaveAddrBuf0; |
| 469 | reg [31:0] iSlave_DataOut; |
| 470 | reg [31:0] txcInterruptEvents; |
| 471 | reg [31:0] pio_sl_data; |
| 472 | |
| 473 | `ifdef NEPTUNE |
| 474 | wire dma16_decode; |
| 475 | wire dma17_decode; |
| 476 | wire dma18_decode; |
| 477 | wire dma19_decode; |
| 478 | wire dma20_decode; |
| 479 | wire dma21_decode; |
| 480 | wire dma22_decode; |
| 481 | wire dma23_decode; |
| 482 | wire read_DMA16to19_Register; |
| 483 | wire read_DMA20to23_Register; |
| 484 | wire txc_port2_decode; |
| 485 | wire txc_port3_decode; |
| 486 | wire posEdgeWritePort2; |
| 487 | wire ports2and3_decode; |
| 488 | |
| 489 | reg write_Port2_RegisterD1; |
| 490 | reg [5:0] port2_txcInterruptMask; |
| 491 | reg [5:0] port3_txcInterruptMask; |
| 492 | `endif |
| 493 | |
| 494 | /*--------------------------------------------------------------*/ |
| 495 | // Parameters and Defines |
| 496 | /*--------------------------------------------------------------*/ |
| 497 | |
| 498 | /*--------------------------------------------------------------*/ |
| 499 | // Zero In Checks |
| 500 | /*--------------------------------------------------------------*/ |
| 501 | |
| 502 | /*--------------------------------------------------------------*/ |
| 503 | // Interrupt |
| 504 | // Give Precedance to setting when clearing interrupts |
| 505 | /*--------------------------------------------------------------*/ |
| 506 | `ifdef NEPTUNE |
| 507 | assign setTxcIntEvents = {2'h0, |
| 508 | Port3_PacketAssyDead, Port3_ReOrder_Error, |
| 509 | Port3_ReOrder_ECC_State[16], |
| 510 | Port3_ReOrder_ECC_State[17], |
| 511 | Port3_StoreForward_ECC_State[16], |
| 512 | Port3_StoreForward_ECC_State[17], |
| 513 | 2'h0, |
| 514 | Port2_PacketAssyDead, Port2_ReOrder_Error, |
| 515 | Port2_ReOrder_ECC_State[16], |
| 516 | Port2_ReOrder_ECC_State[17], |
| 517 | Port2_StoreForward_ECC_State[16], |
| 518 | Port2_StoreForward_ECC_State[17], |
| 519 | 2'h0, |
| 520 | Port1_PacketAssyDead, Port1_ReOrder_Error, |
| 521 | Port1_ReOrder_ECC_State[16], |
| 522 | Port1_ReOrder_ECC_State[17], |
| 523 | Port1_StoreForward_ECC_State[16], |
| 524 | Port1_StoreForward_ECC_State[17], |
| 525 | 2'h0, |
| 526 | Port0_PacketAssyDead, Port0_ReOrder_Error, |
| 527 | Port0_ReOrder_ECC_State[16], |
| 528 | Port0_ReOrder_ECC_State[17], |
| 529 | Port0_StoreForward_ECC_State[16], |
| 530 | Port0_StoreForward_ECC_State[17] |
| 531 | }; |
| 532 | |
| 533 | `else |
| 534 | assign setTxcIntEvents = {16'h0, |
| 535 | 2'h0, |
| 536 | Port1_PacketAssyDead, Port1_ReOrder_Error, |
| 537 | Port1_ReOrder_ECC_State[16], |
| 538 | Port1_ReOrder_ECC_State[17], |
| 539 | Port1_StoreForward_ECC_State[16], |
| 540 | Port1_StoreForward_ECC_State[17], |
| 541 | 2'h0, |
| 542 | Port0_PacketAssyDead, Port0_ReOrder_Error, |
| 543 | Port0_ReOrder_ECC_State[16], |
| 544 | Port0_ReOrder_ECC_State[17], |
| 545 | Port0_StoreForward_ECC_State[16], |
| 546 | Port0_StoreForward_ECC_State[17] |
| 547 | }; |
| 548 | `endif |
| 549 | |
| 550 | |
| 551 | `ifdef NEPTUNE |
| 552 | assign txcInterruptMask = {2'h0, port3_txcInterruptMask, |
| 553 | 2'h0, port2_txcInterruptMask, |
| 554 | 2'h0, port1_txcInterruptMask, |
| 555 | 2'h0, port0_txcInterruptMask |
| 556 | }; |
| 557 | `else |
| 558 | assign txcInterruptMask = {16'h0, |
| 559 | 2'h0, port1_txcInterruptMask, |
| 560 | 2'h0, port0_txcInterruptMask |
| 561 | }; |
| 562 | `endif |
| 563 | |
| 564 | |
| 565 | always @ (posedge SysClk) |
| 566 | if (!Reset_L) setIntEventD1 <= 1'b0; |
| 567 | else setIntEventD1 <= #`SD setIntEvent; |
| 568 | |
| 569 | assign posEdgeSetIntEvent = setIntEvent & ~setIntEventD1; |
| 570 | |
| 571 | always @ (posedge SysClk) |
| 572 | if (!Reset_L) clrIntEventD1 <= 1'b0; |
| 573 | else clrIntEventD1 <= #`SD clrIntEvent; |
| 574 | |
| 575 | assign posEdgeClrIntEvent = clrIntEvent & ~clrIntEventD1; |
| 576 | |
| 577 | |
| 578 | always @ (posedge SysClk) |
| 579 | if (!Reset_L) |
| 580 | txcInterruptEvents <= 32'h0; |
| 581 | else if (posEdgeSetIntEvent) |
| 582 | `ifdef NEPTUNE |
| 583 | txcInterruptEvents <= #`SD {2'h0, SlaveDataInB0[29:24], |
| 584 | 2'h0, SlaveDataInB0[21:16], |
| 585 | 2'h0, SlaveDataInB0[13:8], |
| 586 | 2'h0, SlaveDataInB0[5:0] |
| 587 | }; |
| 588 | `else |
| 589 | txcInterruptEvents <= #`SD {16'h0, |
| 590 | 2'h0, SlaveDataInB0[13:8], |
| 591 | 2'h0, SlaveDataInB0[5:0] |
| 592 | }; |
| 593 | `endif |
| 594 | else if (posEdgeClrIntEvent) |
| 595 | `ifdef NEPTUNE |
| 596 | txcInterruptEvents <= #`SD ((txcInterruptEvents |
| 597 | & |
| 598 | {2'h0, ~SlaveDataInB0[29:24], |
| 599 | 2'h0, ~SlaveDataInB0[21:16], |
| 600 | 2'h0, ~SlaveDataInB0[13:8], |
| 601 | 2'h0, ~SlaveDataInB0[5:0] |
| 602 | } |
| 603 | ) |
| 604 | | |
| 605 | setTxcIntEvents |
| 606 | ); |
| 607 | `else |
| 608 | txcInterruptEvents <= #`SD ((txcInterruptEvents |
| 609 | & |
| 610 | {16'h0, |
| 611 | 2'h0, ~SlaveDataInB0[13:8], |
| 612 | 2'h0, ~SlaveDataInB0[5:0] |
| 613 | } |
| 614 | ) |
| 615 | | |
| 616 | setTxcIntEvents |
| 617 | ); |
| 618 | `endif |
| 619 | else |
| 620 | txcInterruptEvents <= #`SD (setTxcIntEvents | txcInterruptEvents); |
| 621 | |
| 622 | |
| 623 | always @ (posedge SysClk) |
| 624 | if (!Reset_L) niu_txc_interrupts <= 1'b0; |
| 625 | else niu_txc_interrupts <= #`SD |(txcInterruptEvents |
| 626 | & |
| 627 | ~txcInterruptMask); |
| 628 | |
| 629 | /*--------------------------------------------------------------*/ |
| 630 | // Address Decodes |
| 631 | /*--------------------------------------------------------------*/ |
| 632 | assign dma_rsv_space = (slaveAddrBuf0[11:0] >= `DMA_RSV_SPACE); |
| 633 | assign niu_txc_RSV_decode = (~niu_txc_valid_decode |
| 634 | || |
| 635 | ~functionZero |
| 636 | ); |
| 637 | |
| 638 | assign txc_pio_decode = ((((slaveAddrBuf0[18:0] >= `TXC_LOWER) |
| 639 | && |
| 640 | (slaveAddrBuf0[18:0] <= `TXC_UPPER) |
| 641 | ) |
| 642 | || |
| 643 | ((slaveAddrBuf0[18:0] >= `TXC_INT_LOWER) |
| 644 | && |
| 645 | (slaveAddrBuf0[18:0] <= `TXC_INT_UPPER) |
| 646 | ) |
| 647 | ) |
| 648 | && |
| 649 | functionZero |
| 650 | ); |
| 651 | |
| 652 | |
| 653 | assign ports0and1_decode = (txc_port0_decode | txc_port1_decode); |
| 654 | |
| 655 | assign txc_port0_decode = ((slaveAddrBuf0[18:0] >= `PORT0_LOWER) |
| 656 | && |
| 657 | (slaveAddrBuf0[18:0] <= `PORT0_UPPER) |
| 658 | && |
| 659 | functionZero |
| 660 | ); |
| 661 | |
| 662 | assign txc_port1_decode = ((slaveAddrBuf0[18:0] >= `PORT1_LOWER) |
| 663 | && |
| 664 | (slaveAddrBuf0[18:0] <= `PORT1_UPPER) |
| 665 | && |
| 666 | functionZero |
| 667 | ); |
| 668 | |
| 669 | assign niu_txc_valid_decode = ((dma_decode_space & ~dma_rsv_space) |
| 670 | || |
| 671 | txc_pio_decode |
| 672 | || |
| 673 | ports0and1_decode |
| 674 | `ifdef NEPTUNE |
| 675 | || |
| 676 | ports2and3_decode |
| 677 | `endif |
| 678 | ); |
| 679 | |
| 680 | assign dma_decode_space = ({functionZero, slaveAddrBuf0[18:12]} |
| 681 | `ifdef NEPTUNE |
| 682 | <= `DMA23_SPACE |
| 683 | `else |
| 684 | <= `DMA15_SPACE |
| 685 | `endif |
| 686 | ); |
| 687 | |
| 688 | assign SlaveAddrB0 = slaveAddrBuf0[11:2]; |
| 689 | assign SlaveAddrB1 = slaveAddrBuf1[8:2]; |
| 690 | |
| 691 | assign dma0_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA0_SPACE); |
| 692 | assign dma1_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA1_SPACE); |
| 693 | assign dma2_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA2_SPACE); |
| 694 | assign dma3_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA3_SPACE); |
| 695 | assign dma4_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA4_SPACE); |
| 696 | assign dma5_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA5_SPACE); |
| 697 | assign dma6_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA6_SPACE); |
| 698 | assign dma7_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA7_SPACE); |
| 699 | assign dma8_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA8_SPACE); |
| 700 | assign dma9_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA9_SPACE); |
| 701 | assign dma10_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA10_SPACE); |
| 702 | assign dma11_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA11_SPACE); |
| 703 | assign dma12_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA12_SPACE); |
| 704 | assign dma13_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA13_SPACE); |
| 705 | assign dma14_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA14_SPACE); |
| 706 | assign dma15_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA15_SPACE); |
| 707 | |
| 708 | assign Read_DMA0_Register = (readSlaveRegB0 & dma0_decode & ~dma_rsv_space); |
| 709 | assign Read_DMA1_Register = (readSlaveRegB0 & dma1_decode & ~dma_rsv_space); |
| 710 | assign Read_DMA2_Register = (readSlaveRegB0 & dma2_decode & ~dma_rsv_space); |
| 711 | assign Read_DMA3_Register = (readSlaveRegB0 & dma3_decode & ~dma_rsv_space); |
| 712 | assign Read_DMA4_Register = (readSlaveRegB0 & dma4_decode & ~dma_rsv_space); |
| 713 | assign Read_DMA5_Register = (readSlaveRegB0 & dma5_decode & ~dma_rsv_space); |
| 714 | assign Read_DMA6_Register = (readSlaveRegB0 & dma6_decode & ~dma_rsv_space); |
| 715 | assign Read_DMA7_Register = (readSlaveRegB0 & dma7_decode & ~dma_rsv_space); |
| 716 | assign Read_DMA8_Register = (readSlaveRegB0 & dma8_decode & ~dma_rsv_space); |
| 717 | assign Read_DMA9_Register = (readSlaveRegB0 & dma9_decode & ~dma_rsv_space); |
| 718 | assign Read_DMA10_Register = (readSlaveRegB0 & dma10_decode & ~dma_rsv_space); |
| 719 | assign Read_DMA11_Register = (readSlaveRegB0 & dma11_decode & ~dma_rsv_space); |
| 720 | assign Read_DMA12_Register = (readSlaveRegB1 & dma12_decode & ~dma_rsv_space); |
| 721 | assign Read_DMA13_Register = (readSlaveRegB1 & dma13_decode & ~dma_rsv_space); |
| 722 | assign Read_DMA14_Register = (readSlaveRegB1 & dma14_decode & ~dma_rsv_space); |
| 723 | assign Read_DMA15_Register = (readSlaveRegB1 & dma15_decode & ~dma_rsv_space); |
| 724 | |
| 725 | assign Write_DMA0_Register = (writeSlaveRegB0 & dma0_decode & ~dma_rsv_space); |
| 726 | assign Write_DMA1_Register = (writeSlaveRegB0 & dma1_decode & ~dma_rsv_space); |
| 727 | assign Write_DMA2_Register = (writeSlaveRegB0 & dma2_decode & ~dma_rsv_space); |
| 728 | assign Write_DMA3_Register = (writeSlaveRegB0 & dma3_decode & ~dma_rsv_space); |
| 729 | assign Write_DMA4_Register = (writeSlaveRegB0 & dma4_decode & ~dma_rsv_space); |
| 730 | assign Write_DMA5_Register = (writeSlaveRegB0 & dma5_decode & ~dma_rsv_space); |
| 731 | assign Write_DMA6_Register = (writeSlaveRegB0 & dma6_decode & ~dma_rsv_space); |
| 732 | assign Write_DMA7_Register = (writeSlaveRegB0 & dma7_decode & ~dma_rsv_space); |
| 733 | assign Write_DMA8_Register = (writeSlaveRegB0 & dma8_decode & ~dma_rsv_space); |
| 734 | assign Write_DMA9_Register = (writeSlaveRegB0 & dma9_decode & ~dma_rsv_space); |
| 735 | assign Write_DMA10_Register = (writeSlaveRegB0 & dma10_decode & ~dma_rsv_space); |
| 736 | assign Write_DMA11_Register = (writeSlaveRegB0 & dma11_decode & ~dma_rsv_space); |
| 737 | assign Write_DMA12_Register = (writeSlaveRegB0 & dma12_decode & ~dma_rsv_space); |
| 738 | assign Write_DMA13_Register = (writeSlaveRegB1 & dma13_decode & ~dma_rsv_space); |
| 739 | assign Write_DMA14_Register = (writeSlaveRegB1 & dma14_decode & ~dma_rsv_space); |
| 740 | assign Write_DMA15_Register = (writeSlaveRegB1 & dma15_decode & ~dma_rsv_space); |
| 741 | |
| 742 | assign read_PIO_Register = (readSlaveRegB0 & txc_pio_decode); |
| 743 | assign write_PIO_Register = (writeSlaveRegB0 & txc_pio_decode); |
| 744 | |
| 745 | assign Read_Port0_Register = (readSlaveRegB0 & ports0and1_decode); |
| 746 | assign Write_Port0_Register = (writeSlaveRegB0 & ports0and1_decode); |
| 747 | |
| 748 | |
| 749 | `ifdef NEPTUNE |
| 750 | |
| 751 | assign ports2and3_decode = (txc_port2_decode | txc_port3_decode); |
| 752 | |
| 753 | assign txc_port2_decode = ((slaveAddrBuf0[18:0] >= `PORT2_LOWER) |
| 754 | && |
| 755 | (slaveAddrBuf0[18:0] <= `PORT2_UPPER) |
| 756 | && |
| 757 | functionZero |
| 758 | ); |
| 759 | |
| 760 | assign txc_port3_decode = ((slaveAddrBuf0[18:0] >= `PORT3_LOWER) |
| 761 | && |
| 762 | (slaveAddrBuf0[18:0] <= `PORT3_UPPER) |
| 763 | && |
| 764 | functionZero |
| 765 | ); |
| 766 | |
| 767 | assign dma16_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA16_SPACE); |
| 768 | assign dma17_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA17_SPACE); |
| 769 | assign dma18_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA18_SPACE); |
| 770 | assign dma19_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA19_SPACE); |
| 771 | assign dma20_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA20_SPACE); |
| 772 | assign dma21_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA21_SPACE); |
| 773 | assign dma22_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA22_SPACE); |
| 774 | assign dma23_decode = ({functionZero, slaveAddrBuf0[18:12]} == `DMA23_SPACE); |
| 775 | |
| 776 | assign Read_DMA16_Register = (readSlaveRegB1 & dma16_decode & ~dma_rsv_space); |
| 777 | assign Read_DMA17_Register = (readSlaveRegB1 & dma17_decode & ~dma_rsv_space); |
| 778 | assign Read_DMA18_Register = (readSlaveRegB1 & dma18_decode & ~dma_rsv_space); |
| 779 | assign Read_DMA19_Register = (readSlaveRegB1 & dma19_decode & ~dma_rsv_space); |
| 780 | assign Read_DMA20_Register = (readSlaveRegB1 & dma20_decode & ~dma_rsv_space); |
| 781 | assign Read_DMA21_Register = (readSlaveRegB1 & dma21_decode & ~dma_rsv_space); |
| 782 | assign Read_DMA22_Register = (readSlaveRegB1 & dma22_decode & ~dma_rsv_space); |
| 783 | assign Read_DMA23_Register = (readSlaveRegB1 & dma23_decode & ~dma_rsv_space); |
| 784 | |
| 785 | assign Write_DMA16_Register = (writeSlaveRegB1 & dma16_decode & ~dma_rsv_space); |
| 786 | assign Write_DMA17_Register = (writeSlaveRegB1 & dma17_decode & ~dma_rsv_space); |
| 787 | assign Write_DMA18_Register = (writeSlaveRegB1 & dma18_decode & ~dma_rsv_space); |
| 788 | assign Write_DMA19_Register = (writeSlaveRegB1 & dma19_decode & ~dma_rsv_space); |
| 789 | assign Write_DMA20_Register = (writeSlaveRegB1 & dma20_decode & ~dma_rsv_space); |
| 790 | assign Write_DMA21_Register = (writeSlaveRegB1 & dma21_decode & ~dma_rsv_space); |
| 791 | assign Write_DMA22_Register = (writeSlaveRegB1 & dma22_decode & ~dma_rsv_space); |
| 792 | assign Write_DMA23_Register = (writeSlaveRegB1 & dma23_decode & ~dma_rsv_space); |
| 793 | |
| 794 | assign Read_Port2_Register = (readSlaveRegB0 & ports2and3_decode); |
| 795 | assign Write_Port2_Register = (writeSlaveRegB0 & ports2and3_decode); |
| 796 | |
| 797 | `endif |
| 798 | |
| 799 | /*--------------------------------------------------------------*/ |
| 800 | // Pipeline Delay for PIO Signals |
| 801 | /*--------------------------------------------------------------*/ |
| 802 | assign readSlaveRegB0 = (slaveSelB0 & slaveReadB0); |
| 803 | assign readSlaveRegB1 = (slaveSelB1 & slaveReadB1); |
| 804 | assign writeSlaveRegB0 = (slaveSelB0 & ~slaveReadB0); |
| 805 | assign writeSlaveRegB1 = (slaveSelB1 & ~slaveReadB1); |
| 806 | |
| 807 | always @ (posedge SysClk) |
| 808 | if (!Reset_L) slaveReadB0 <= 1'b0; |
| 809 | else slaveReadB0 <= #`SD Slave_Read; |
| 810 | |
| 811 | always @ (posedge SysClk) |
| 812 | if (!Reset_L) slaveReadB1 <= 1'b0; |
| 813 | else slaveReadB1 <= #`SD Slave_Read; |
| 814 | |
| 815 | always @ (posedge SysClk) |
| 816 | if (!Reset_L) slaveSelB0 <= 1'b0; |
| 817 | else slaveSelB0 <= #`SD Slave_Sel; |
| 818 | |
| 819 | always @ (posedge SysClk) |
| 820 | if (!Reset_L) slaveSelB1 <= 1'b0; |
| 821 | else slaveSelB1 <= #`SD Slave_Sel; |
| 822 | |
| 823 | always @ (posedge SysClk) |
| 824 | if (!Reset_L) functionZero <= 1'b0; |
| 825 | else functionZero <= #`SD Slave_Addr[19]; |
| 826 | |
| 827 | always @ (posedge SysClk) |
| 828 | if (!Reset_L) slaveAddrBuf0 <= 19'h0; |
| 829 | else slaveAddrBuf0 <= #`SD Slave_Addr[18:0]; |
| 830 | |
| 831 | always @ (posedge SysClk) |
| 832 | if (!Reset_L) slaveAddrBuf1 <= 10'h0; |
| 833 | else slaveAddrBuf1 <= #`SD Slave_Addr[11:2]; |
| 834 | |
| 835 | always @ (posedge SysClk) |
| 836 | if (!Reset_L) SlaveDataInB0 <= 32'h0; |
| 837 | else SlaveDataInB0 <= #`SD Slave_DataIn; |
| 838 | |
| 839 | always @ (posedge SysClk) |
| 840 | if (!Reset_L) Port0_PioDataIn <= 32'h0; |
| 841 | else Port0_PioDataIn <= #`SD Slave_DataIn; |
| 842 | |
| 843 | always @ (posedge SysClk) |
| 844 | if (!Reset_L) Port1_PioDataIn <= 32'h0; |
| 845 | else Port1_PioDataIn <= #`SD Slave_DataIn; |
| 846 | |
| 847 | `ifdef NEPTUNE |
| 848 | always @ (posedge SysClk) |
| 849 | if (!Reset_L) Port2_PioDataIn <= 32'h0; |
| 850 | else Port2_PioDataIn <= #`SD Slave_DataIn; |
| 851 | |
| 852 | always @ (posedge SysClk) |
| 853 | if (!Reset_L) Port3_PioDataIn <= 32'h0; |
| 854 | else Port3_PioDataIn <= #`SD Slave_DataIn; |
| 855 | `endif |
| 856 | |
| 857 | /*--------------------------------------------------------------*/ |
| 858 | // Slave Control Logic |
| 859 | /*--------------------------------------------------------------*/ |
| 860 | always @ (posedge SysClk) |
| 861 | if (!Reset_L) en_Slave_Ack <= 1'b0; |
| 862 | else en_Slave_Ack <= #`SD slaveSelB0; |
| 863 | |
| 864 | always @ (posedge SysClk) |
| 865 | if (!Reset_L) en_Slave_AckD1 <= 1'b0; |
| 866 | else en_Slave_AckD1 <= #`SD en_Slave_Ack; |
| 867 | |
| 868 | assign SlaveStrobe = en_Slave_Ack & ~en_Slave_AckD1; |
| 869 | |
| 870 | /*--------------------------------------------------------------*/ |
| 871 | // Posedge NIU PIO Write Logic |
| 872 | /*--------------------------------------------------------------*/ |
| 873 | always @ (posedge SysClk) |
| 874 | if (!Reset_L) write_Port0_RegisterD1 <= 1'b0; |
| 875 | else write_Port0_RegisterD1 <= #`SD Write_Port0_Register; |
| 876 | |
| 877 | assign PosEdgeWritePort0 = (Write_Port0_Register & ~write_Port0_RegisterD1); |
| 878 | |
| 879 | `ifdef NEPTUNE |
| 880 | always @ (posedge SysClk) |
| 881 | if (!Reset_L) write_Port2_RegisterD1 <= 1'b0; |
| 882 | else write_Port2_RegisterD1 <= #`SD Write_Port2_Register; |
| 883 | |
| 884 | assign PosEdgeWritePort2 = (Write_Port2_Register & ~write_Port2_RegisterD1); |
| 885 | `endif |
| 886 | |
| 887 | /*--------------------------------------------------------------*/ |
| 888 | // Slave Interface |
| 889 | /*--------------------------------------------------------------*/ |
| 890 | always @ (posedge SysClk) |
| 891 | if (!Reset_L) Slave_Ack <= 1'b0; |
| 892 | else if (SlaveStrobe) Slave_Ack <= #`SD 1'b1; |
| 893 | else Slave_Ack <= #`SD 1'b0; |
| 894 | |
| 895 | assign generateNACK = (SlaveStrobe & Slave_Read & niu_txc_RSV_decode); |
| 896 | |
| 897 | always @ (posedge SysClk) |
| 898 | if (!Reset_L) Slave_Err <= 1'b0; |
| 899 | else if (generateNACK) Slave_Err <= #`SD 1'b1; |
| 900 | else Slave_Err <= #`SD 1'b0; |
| 901 | |
| 902 | assign Slave_DataOut = {32'h0, iSlave_DataOut}; |
| 903 | |
| 904 | assign reserved32Bit = Slave_32BitMode & slaveAddrBuf0[2]; |
| 905 | |
| 906 | always @ (posedge SysClk) |
| 907 | if (!Reset_L) iSlave_DataOut <= 32'h0; |
| 908 | else if (reserved32Bit) iSlave_DataOut <= #`SD 32'h0; |
| 909 | else if (read_PIO_Register) iSlave_DataOut <= #`SD pio_sl_data; |
| 910 | else if (Read_Port0_Register) iSlave_DataOut <= #`SD Port0to1_Slave_Data; |
| 911 | `ifdef NEPTUNE |
| 912 | else if (Read_Port2_Register) iSlave_DataOut <= #`SD Port2to3_Slave_Data; |
| 913 | `endif |
| 914 | else if (read_DMA0to3_Register) iSlave_DataOut <= #`SD DMA0to3_Slave_Data; |
| 915 | else if (read_DMA4to7_Register) iSlave_DataOut <= #`SD DMA4to7_Slave_Data; |
| 916 | else if (read_DMA8to11_Register) iSlave_DataOut <= #`SD DMA8to11_Slave_Data; |
| 917 | else if (read_DMA12to15_Register) iSlave_DataOut <= #`SD DMA12to15_Slave_Data; |
| 918 | |
| 919 | `ifdef NEPTUNE |
| 920 | else if (read_DMA16to19_Register) iSlave_DataOut <= #`SD DMA16to19_Slave_Data; |
| 921 | else if (read_DMA20to23_Register) iSlave_DataOut <= #`SD DMA20to23_Slave_Data; |
| 922 | `endif |
| 923 | else iSlave_DataOut <= #`SD 32'hDEADBEEF; |
| 924 | |
| 925 | |
| 926 | assign read_DMA0to3_Register = (Read_DMA0_Register | Read_DMA1_Register |
| 927 | | |
| 928 | Read_DMA2_Register | Read_DMA3_Register); |
| 929 | |
| 930 | assign read_DMA4to7_Register = (Read_DMA4_Register | Read_DMA5_Register |
| 931 | | |
| 932 | Read_DMA6_Register | Read_DMA7_Register); |
| 933 | |
| 934 | assign read_DMA8to11_Register = (Read_DMA8_Register | Read_DMA9_Register |
| 935 | | |
| 936 | Read_DMA10_Register | Read_DMA11_Register); |
| 937 | |
| 938 | assign read_DMA12to15_Register = (Read_DMA12_Register | Read_DMA13_Register |
| 939 | | |
| 940 | Read_DMA14_Register | Read_DMA15_Register); |
| 941 | |
| 942 | `ifdef NEPTUNE |
| 943 | assign read_DMA16to19_Register = (Read_DMA16_Register | Read_DMA17_Register |
| 944 | | |
| 945 | Read_DMA18_Register | Read_DMA19_Register); |
| 946 | |
| 947 | assign read_DMA20to23_Register = (Read_DMA20_Register | Read_DMA21_Register |
| 948 | | |
| 949 | Read_DMA22_Register | Read_DMA23_Register); |
| 950 | `endif |
| 951 | |
| 952 | /*--------------------------------------------------------------*/ |
| 953 | // NIU TXC PIO Read & Write Registers |
| 954 | /*--------------------------------------------------------------*/ |
| 955 | assign FlushEngine = 1'b0; |
| 956 | |
| 957 | always @ (posedge SysClk) |
| 958 | if (!Reset_L) |
| 959 | pio_sl_data <= 32'h0; |
| 960 | else if (read_PIO_Register) |
| 961 | case ({slaveAddrBuf1[11:2], 2'h0}) // synopsys parallel_case |
| 962 | /* 0in < case -parallel */ |
| 963 | |
| 964 | `TXC_CONTROL: pio_sl_data <= {27'h0, |
| 965 | Txc_Enabled, |
| 966 | `ifdef NEPTUNE |
| 967 | Port3_Enabled, Port2_Enabled, |
| 968 | `else |
| 969 | 2'h0, |
| 970 | `endif |
| 971 | Port1_Enabled, Port0_Enabled}; |
| 972 | |
| 973 | `TXC_TRAINING: pio_sl_data <= TrainingVector; |
| 974 | |
| 975 | `TXC_DEBUG_SELECT: pio_sl_data <= {26'h0, Debug_Select}; |
| 976 | |
| 977 | `TXC_MAX_REORDER: pio_sl_data <= { |
| 978 | `ifdef NEPTUNE |
| 979 | 4'h0, Port3_MaxReorderNumber, |
| 980 | 4'h0, Port2_MaxReorderNumber, |
| 981 | `else |
| 982 | 16'h0, |
| 983 | `endif |
| 984 | 4'h0, Port1_MaxReorderNumber, |
| 985 | 4'h0, Port0_MaxReorderNumber |
| 986 | }; |
| 987 | |
| 988 | `TXC_INT_SET_EVENT, |
| 989 | `TXC_INT_CLR_EVENT: pio_sl_data <= txcInterruptEvents; |
| 990 | |
| 991 | `TXC_INT_MASK: pio_sl_data <= txcInterruptMask; |
| 992 | |
| 993 | default: pio_sl_data <= 32'h0; |
| 994 | |
| 995 | endcase |
| 996 | |
| 997 | |
| 998 | always @ (posedge SysClk) |
| 999 | if (!Reset_L) |
| 1000 | begin |
| 1001 | Txc_Enabled <= 1'b0; |
| 1002 | TrainingVector <= 32'h0; |
| 1003 | Debug_Select <= 6'b0; |
| 1004 | setIntEvent <= 1'b0; |
| 1005 | clrIntEvent <= 1'b0; |
| 1006 | Port0_Enabled <= 1'b0; |
| 1007 | Port0_MaxReorderNumber <= 4'HF; |
| 1008 | port0_txcInterruptMask <= 6'h3F; |
| 1009 | Port1_Enabled <= 1'b0; |
| 1010 | Port1_MaxReorderNumber <= 4'HF; |
| 1011 | port1_txcInterruptMask <= 6'h3F; |
| 1012 | |
| 1013 | `ifdef NEPTUNE |
| 1014 | Port3_Enabled <= 1'b0; |
| 1015 | Port2_Enabled <= 1'b0; |
| 1016 | Port2_MaxReorderNumber <= 4'H7; |
| 1017 | Port3_MaxReorderNumber <= 4'H7; |
| 1018 | port2_txcInterruptMask <= 6'h3F; |
| 1019 | port3_txcInterruptMask <= 6'h3F; |
| 1020 | `endif |
| 1021 | |
| 1022 | end |
| 1023 | else if (write_PIO_Register) |
| 1024 | begin |
| 1025 | case ({slaveAddrBuf1[11:2], 2'h0}) // synopsys parallel_case |
| 1026 | /* 0in < case -parallel */ |
| 1027 | |
| 1028 | `TXC_CONTROL: begin Txc_Enabled <= SlaveDataInB0[4]; |
| 1029 | `ifdef NEPTUNE |
| 1030 | Port3_Enabled <= SlaveDataInB0[3]; |
| 1031 | Port2_Enabled <= SlaveDataInB0[2]; |
| 1032 | `endif |
| 1033 | Port1_Enabled <= SlaveDataInB0[1]; |
| 1034 | Port0_Enabled <= SlaveDataInB0[0]; |
| 1035 | end |
| 1036 | |
| 1037 | `TXC_TRAINING: TrainingVector <= SlaveDataInB0; |
| 1038 | |
| 1039 | `TXC_DEBUG_SELECT: Debug_Select <= SlaveDataInB0[5:0]; |
| 1040 | |
| 1041 | `TXC_MAX_REORDER: begin |
| 1042 | `ifdef NEPTUNE |
| 1043 | Port3_MaxReorderNumber <= SlaveDataInB0[27:24]; |
| 1044 | Port2_MaxReorderNumber <= SlaveDataInB0[19:16]; |
| 1045 | `endif |
| 1046 | Port1_MaxReorderNumber <= SlaveDataInB0[11:8]; |
| 1047 | Port0_MaxReorderNumber <= SlaveDataInB0[3:0]; |
| 1048 | end |
| 1049 | |
| 1050 | `TXC_INT_SET_EVENT: setIntEvent <= 1'b1; |
| 1051 | `TXC_INT_CLR_EVENT: clrIntEvent <= 1'b1; |
| 1052 | `TXC_INT_MASK: begin |
| 1053 | `ifdef NEPTUNE |
| 1054 | port3_txcInterruptMask <= SlaveDataInB0[29:24]; |
| 1055 | port2_txcInterruptMask <= SlaveDataInB0[21:16]; |
| 1056 | `endif |
| 1057 | port1_txcInterruptMask <= SlaveDataInB0[13:8]; |
| 1058 | port0_txcInterruptMask <= SlaveDataInB0[5:0]; |
| 1059 | end |
| 1060 | |
| 1061 | endcase |
| 1062 | end |
| 1063 | else |
| 1064 | begin |
| 1065 | setIntEvent <= 1'b0; |
| 1066 | clrIntEvent <= 1'b0; |
| 1067 | end |
| 1068 | |
| 1069 | endmodule |