| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_txc_dmaRegisters.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
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| 24 | // the General Public License version 2 (GPLv2) at this time for any |
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| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /********************************************************************* |
| 36 | * |
| 37 | * niu_txc_dmaRegisters.v |
| 38 | * |
| 39 | * NIU Transmit DMA Registers |
| 40 | * |
| 41 | * Orignal Author(s): Rahoul Puri |
| 42 | * Modifier(s): |
| 43 | * Project(s): Neptune |
| 44 | * |
| 45 | * Copyright (c) 2005 Sun Microsystems, Inc. |
| 46 | * |
| 47 | * All Rights Reserved. |
| 48 | * |
| 49 | * This verilog model is the confidential and proprietary property of |
| 50 | * Sun Microsystems, Inc., and the possession or use of this model |
| 51 | * requires a written license from Sun Microsystems, Inc. |
| 52 | * |
| 53 | **********************************************************************/ |
| 54 | |
| 55 | `include "timescale.v" |
| 56 | |
| 57 | module niu_txc_dmaRegisters ( |
| 58 | SysClk, |
| 59 | Reset_L, |
| 60 | Read_DMA0_Register, |
| 61 | Read_DMA1_Register, |
| 62 | Read_DMA2_Register, |
| 63 | Read_DMA3_Register, |
| 64 | Write_DMA0_Register, |
| 65 | Write_DMA1_Register, |
| 66 | Write_DMA2_Register, |
| 67 | Write_DMA3_Register, |
| 68 | SlaveStrobe, |
| 69 | SlaveAddr, |
| 70 | SlaveDataIn, |
| 71 | DMA_Slave_DataOut, |
| 72 | |
| 73 | Port0_ClrMaxBurst, |
| 74 | Port0_UpdateDMA, |
| 75 | Port0_DMA_List, |
| 76 | Port0_UpdateDMANumber, |
| 77 | Port0_UpdateDMALength, |
| 78 | |
| 79 | Port1_ClrMaxBurst, |
| 80 | Port1_UpdateDMA, |
| 81 | Port1_DMA_List, |
| 82 | Port1_UpdateDMANumber, |
| 83 | Port1_UpdateDMALength, |
| 84 | `ifdef NEPTUNE |
| 85 | Port2_ClrMaxBurst, |
| 86 | Port2_UpdateDMA, |
| 87 | Port2_DMA_List, |
| 88 | Port2_UpdateDMANumber, |
| 89 | Port2_UpdateDMALength, |
| 90 | |
| 91 | Port3_ClrMaxBurst, |
| 92 | Port3_UpdateDMA, |
| 93 | Port3_DMA_List, |
| 94 | Port3_UpdateDMANumber, |
| 95 | Port3_UpdateDMALength, |
| 96 | `endif |
| 97 | DMA0_NewMaxBurst, |
| 98 | DMA0_MaxBurst, |
| 99 | DMA1_NewMaxBurst, |
| 100 | DMA1_MaxBurst, |
| 101 | DMA2_NewMaxBurst, |
| 102 | DMA2_MaxBurst, |
| 103 | DMA3_NewMaxBurst, |
| 104 | DMA3_MaxBurst |
| 105 | ); |
| 106 | |
| 107 | // Include Header Files |
| 108 | `include "txc_defines.h" |
| 109 | `include "niu_txc_reg_defines.h" |
| 110 | |
| 111 | // Global Signals |
| 112 | input SysClk; |
| 113 | input Reset_L; |
| 114 | |
| 115 | // Slave Interface |
| 116 | input Read_DMA0_Register; |
| 117 | input Read_DMA1_Register; |
| 118 | input Read_DMA2_Register; |
| 119 | input Read_DMA3_Register; |
| 120 | input Write_DMA0_Register; |
| 121 | input Write_DMA1_Register; |
| 122 | input Write_DMA2_Register; |
| 123 | input Write_DMA3_Register; |
| 124 | input SlaveStrobe; |
| 125 | input [11:2] SlaveAddr; |
| 126 | input [27:0] SlaveDataIn; |
| 127 | |
| 128 | output [31:0] DMA_Slave_DataOut; |
| 129 | |
| 130 | reg [31:0] DMA_Slave_DataOut; |
| 131 | |
| 132 | // DMA Port Signals |
| 133 | input Port0_ClrMaxBurst; |
| 134 | input Port0_UpdateDMA; |
| 135 | input [3:0] Port0_DMA_List; |
| 136 | input [3:0] Port0_UpdateDMANumber; |
| 137 | input [13:0] Port0_UpdateDMALength; |
| 138 | |
| 139 | input Port1_ClrMaxBurst; |
| 140 | input Port1_UpdateDMA; |
| 141 | input [3:0] Port1_DMA_List; |
| 142 | input [3:0] Port1_UpdateDMANumber; |
| 143 | input [13:0] Port1_UpdateDMALength; |
| 144 | |
| 145 | `ifdef NEPTUNE |
| 146 | input Port2_ClrMaxBurst; |
| 147 | input Port2_UpdateDMA; |
| 148 | input [3:0] Port2_DMA_List; |
| 149 | input [3:0] Port2_UpdateDMANumber; |
| 150 | input [13:0] Port2_UpdateDMALength; |
| 151 | |
| 152 | input Port3_ClrMaxBurst; |
| 153 | input Port3_UpdateDMA; |
| 154 | input [3:0] Port3_DMA_List; |
| 155 | input [3:0] Port3_UpdateDMANumber; |
| 156 | input [13:0] Port3_UpdateDMALength; |
| 157 | `endif |
| 158 | |
| 159 | // DMA Registers Grouped in Banks or Four |
| 160 | output DMA0_NewMaxBurst; |
| 161 | output [19:0] DMA0_MaxBurst; |
| 162 | |
| 163 | output DMA1_NewMaxBurst; |
| 164 | output [19:0] DMA1_MaxBurst; |
| 165 | |
| 166 | output DMA2_NewMaxBurst; |
| 167 | output [19:0] DMA2_MaxBurst; |
| 168 | |
| 169 | output DMA3_NewMaxBurst; |
| 170 | output [19:0] DMA3_MaxBurst; |
| 171 | |
| 172 | reg DMA0_NewMaxBurst; |
| 173 | reg DMA1_NewMaxBurst; |
| 174 | reg DMA2_NewMaxBurst; |
| 175 | reg DMA3_NewMaxBurst; |
| 176 | reg [19:0] DMA0_MaxBurst; |
| 177 | reg [19:0] DMA1_MaxBurst; |
| 178 | reg [19:0] DMA2_MaxBurst; |
| 179 | reg [19:0] DMA3_MaxBurst; |
| 180 | |
| 181 | /*--------------------------------------------------------------*/ |
| 182 | // Wires & Registers |
| 183 | /*--------------------------------------------------------------*/ |
| 184 | wire setNewMaxBurstDMA0; |
| 185 | wire setNewMaxBurstDMA1; |
| 186 | wire setNewMaxBurstDMA2; |
| 187 | wire setNewMaxBurstDMA3; |
| 188 | wire collisionDma0Update; |
| 189 | wire collisionDma1Update; |
| 190 | wire collisionDma2Update; |
| 191 | wire collisionDma3Update; |
| 192 | wire dma0Update; |
| 193 | wire dma1Update; |
| 194 | wire dma2Update; |
| 195 | wire dma3Update; |
| 196 | wire readDMAregister; |
| 197 | wire writeDMAregister; |
| 198 | wire [3:0] dma0Select; |
| 199 | wire [3:0] dma1Select; |
| 200 | wire [3:0] dma2Select; |
| 201 | wire [3:0] dma3Select; |
| 202 | wire [3:0] readIndex; |
| 203 | wire [3:0] writeIndex; |
| 204 | wire [13:0] writeAddress; |
| 205 | wire [13:0] readAddress; |
| 206 | |
| 207 | reg clrNewMaxBurstDMA0; |
| 208 | reg clrNewMaxBurstDMA1; |
| 209 | reg clrNewMaxBurstDMA2; |
| 210 | reg clrNewMaxBurstDMA3; |
| 211 | reg updateDMA0Strobe; |
| 212 | reg updateDMA1Strobe; |
| 213 | reg updateDMA2Strobe; |
| 214 | reg updateDMA3Strobe; |
| 215 | reg dma0Valid; |
| 216 | reg dma1Valid; |
| 217 | reg dma2Valid; |
| 218 | reg dma3Valid; |
| 219 | reg wrDMA0_Length; |
| 220 | reg wrDMA1_Length; |
| 221 | reg wrDMA2_Length; |
| 222 | reg wrDMA3_Length; |
| 223 | reg [1:0] dmaReadIndex; |
| 224 | reg [1:0] dmaWriteIndex; |
| 225 | reg [13:0] dma0LengthUpdate; |
| 226 | reg [13:0] dma1LengthUpdate; |
| 227 | reg [13:0] dma2LengthUpdate; |
| 228 | reg [13:0] dma3LengthUpdate; |
| 229 | reg [27:0] dma0_Length; |
| 230 | reg [27:0] dma1_Length; |
| 231 | reg [27:0] dma2_Length; |
| 232 | reg [27:0] dma3_Length; |
| 233 | |
| 234 | /*--------------------------------------------------------------*/ |
| 235 | // Parameters and Defines |
| 236 | /*--------------------------------------------------------------*/ |
| 237 | |
| 238 | /*--------------------------------------------------------------*/ |
| 239 | // Zero In Checks |
| 240 | /*--------------------------------------------------------------*/ |
| 241 | |
| 242 | /*--------------------------------------------------------------*/ |
| 243 | // TXC DMA 0-3 decodes |
| 244 | /*--------------------------------------------------------------*/ |
| 245 | assign readDMAregister = (Read_DMA3_Register | Read_DMA2_Register |
| 246 | | |
| 247 | Read_DMA1_Register | Read_DMA0_Register |
| 248 | ); |
| 249 | |
| 250 | assign readIndex = {Read_DMA3_Register, Read_DMA2_Register, |
| 251 | Read_DMA1_Register, Read_DMA0_Register |
| 252 | }; |
| 253 | |
| 254 | assign readAddress = {dmaReadIndex, SlaveAddr[11:2], 2'h0}; |
| 255 | |
| 256 | always @(readIndex) |
| 257 | begin |
| 258 | case (readIndex) // synopsys parallel_case |
| 259 | /* 0in < case -parallel */ |
| 260 | |
| 261 | 4'h1: dmaReadIndex = 2'h0; |
| 262 | 4'h2: dmaReadIndex = 2'h1; |
| 263 | 4'h4: dmaReadIndex = 2'h2; |
| 264 | 4'h8: dmaReadIndex = 2'h3; |
| 265 | default: dmaReadIndex = 2'hx; |
| 266 | endcase |
| 267 | end |
| 268 | |
| 269 | assign writeDMAregister = (Write_DMA3_Register | Write_DMA2_Register |
| 270 | | |
| 271 | Write_DMA1_Register | Write_DMA0_Register |
| 272 | ); |
| 273 | |
| 274 | assign writeIndex = {Write_DMA3_Register, Write_DMA2_Register, |
| 275 | Write_DMA1_Register, Write_DMA0_Register |
| 276 | }; |
| 277 | |
| 278 | assign writeAddress = {dmaWriteIndex, SlaveAddr[11:2], 2'h0}; |
| 279 | |
| 280 | always @(writeIndex) |
| 281 | begin |
| 282 | case (writeIndex) // synopsys parallel_case |
| 283 | /* 0in < case -parallel */ |
| 284 | |
| 285 | 4'h1: dmaWriteIndex = 2'h0; |
| 286 | 4'h2: dmaWriteIndex = 2'h1; |
| 287 | 4'h4: dmaWriteIndex = 2'h2; |
| 288 | 4'h8: dmaWriteIndex = 2'h3; |
| 289 | default: dmaWriteIndex = 2'hx; |
| 290 | endcase |
| 291 | end |
| 292 | |
| 293 | /*--------------------------------------------------------------*/ |
| 294 | // TXC DMA 0 PIO Read & Write Registers |
| 295 | /*--------------------------------------------------------------*/ |
| 296 | `ifdef NEPTUNE |
| 297 | assign dma0Select = {Port3_DMA_List[0], Port2_DMA_List[0], |
| 298 | Port1_DMA_List[0], Port0_DMA_List[0]}; |
| 299 | `else |
| 300 | assign dma0Select = {2'h0, Port1_DMA_List[0], Port0_DMA_List[0]}; |
| 301 | `endif |
| 302 | |
| 303 | `ifdef NEPTUNE |
| 304 | always @(dma0Select or Port3_ClrMaxBurst |
| 305 | or Port2_ClrMaxBurst or Port1_ClrMaxBurst or Port0_ClrMaxBurst |
| 306 | ) |
| 307 | `else |
| 308 | always @(dma0Select or Port1_ClrMaxBurst or Port0_ClrMaxBurst) |
| 309 | `endif |
| 310 | begin |
| 311 | casex(dma0Select) // Synopsys full_case parallel_case |
| 312 | 4'bxxx1: clrNewMaxBurstDMA0 = Port0_ClrMaxBurst; |
| 313 | 4'bxx10: clrNewMaxBurstDMA0 = Port1_ClrMaxBurst; |
| 314 | `ifdef NEPTUNE |
| 315 | 4'bx100: clrNewMaxBurstDMA0 = Port2_ClrMaxBurst; |
| 316 | 4'b1000: clrNewMaxBurstDMA0 = Port3_ClrMaxBurst; |
| 317 | `endif |
| 318 | default: clrNewMaxBurstDMA0 = 1'b0; |
| 319 | endcase |
| 320 | end |
| 321 | |
| 322 | `ifdef NEPTUNE |
| 323 | always @(dma0Select or Port3_UpdateDMA |
| 324 | or Port2_UpdateDMA or Port1_UpdateDMA or Port0_UpdateDMA |
| 325 | ) |
| 326 | `else |
| 327 | always @(dma0Select or Port1_UpdateDMA or Port0_UpdateDMA) |
| 328 | `endif |
| 329 | begin |
| 330 | casex(dma0Select) // Synopsys full_case parallel_case |
| 331 | 4'bxxx1: updateDMA0Strobe = Port0_UpdateDMA; |
| 332 | 4'bxx10: updateDMA0Strobe = Port1_UpdateDMA; |
| 333 | `ifdef NEPTUNE |
| 334 | 4'bx100: updateDMA0Strobe = Port2_UpdateDMA; |
| 335 | 4'b1000: updateDMA0Strobe = Port3_UpdateDMA; |
| 336 | `endif |
| 337 | default: updateDMA0Strobe = 1'b0; |
| 338 | endcase |
| 339 | end |
| 340 | |
| 341 | `ifdef NEPTUNE |
| 342 | always @(dma0Select or Port3_UpdateDMANumber |
| 343 | or Port2_UpdateDMANumber or Port1_UpdateDMANumber |
| 344 | or Port0_UpdateDMANumber |
| 345 | ) |
| 346 | `else |
| 347 | always @(dma0Select or Port1_UpdateDMANumber or Port0_UpdateDMANumber) |
| 348 | `endif |
| 349 | begin |
| 350 | casex(dma0Select) // Synopsys full_case parallel_case |
| 351 | 4'bxxx1: dma0Valid = Port0_UpdateDMANumber[0]; |
| 352 | 4'bxx10: dma0Valid = Port1_UpdateDMANumber[0]; |
| 353 | `ifdef NEPTUNE |
| 354 | 4'bx100: dma0Valid = Port2_UpdateDMANumber[0]; |
| 355 | 4'b1000: dma0Valid = Port3_UpdateDMANumber[0]; |
| 356 | `endif |
| 357 | default: dma0Valid = 1'b0; |
| 358 | endcase |
| 359 | end |
| 360 | |
| 361 | `ifdef NEPTUNE |
| 362 | always @(dma0Select or Port3_UpdateDMALength |
| 363 | or Port2_UpdateDMALength or Port1_UpdateDMALength |
| 364 | or Port0_UpdateDMALength |
| 365 | ) |
| 366 | `else |
| 367 | always @(dma0Select or Port1_UpdateDMALength or Port0_UpdateDMALength) |
| 368 | `endif |
| 369 | begin |
| 370 | casex(dma0Select) // Synopsys full_case parallel_case |
| 371 | 4'bxxx1: dma0LengthUpdate = Port0_UpdateDMALength; |
| 372 | 4'bxx10: dma0LengthUpdate = Port1_UpdateDMALength; |
| 373 | `ifdef NEPTUNE |
| 374 | 4'bx100: dma0LengthUpdate = Port2_UpdateDMALength; |
| 375 | 4'b1000: dma0LengthUpdate = Port3_UpdateDMALength; |
| 376 | `endif |
| 377 | default: dma0LengthUpdate = 14'h0; |
| 378 | endcase |
| 379 | end |
| 380 | |
| 381 | assign dma0Update = updateDMA0Strobe & dma0Valid; |
| 382 | |
| 383 | assign collisionDma0Update = (dma0Update |
| 384 | & |
| 385 | (({SlaveAddr[11:2], 2'h0} == `DMA_LENGTH) |
| 386 | && |
| 387 | Read_DMA0_Register && SlaveStrobe) |
| 388 | ); |
| 389 | |
| 390 | always @ (posedge SysClk) |
| 391 | if (!Reset_L) |
| 392 | dma0_Length <= 28'h0; |
| 393 | else if (wrDMA0_Length) |
| 394 | dma0_Length <= #`SD SlaveDataIn[27:0]; |
| 395 | else if (collisionDma0Update) |
| 396 | dma0_Length <= #`SD {14'h0, dma0LengthUpdate}; |
| 397 | else if (dma0Update) |
| 398 | dma0_Length <= #`SD ((dma0_Length + {14'h0, dma0LengthUpdate}) |
| 399 | | |
| 400 | {dma0_Length[27], 27'h0} |
| 401 | ); |
| 402 | |
| 403 | |
| 404 | assign setNewMaxBurstDMA0 = (({SlaveAddr[11:2], 2'h0} == `DMA_MAXBURST) |
| 405 | && |
| 406 | Write_DMA0_Register && SlaveStrobe); |
| 407 | |
| 408 | always @ (posedge SysClk) |
| 409 | if (!Reset_L) DMA0_NewMaxBurst <= 1'b0; |
| 410 | else if (setNewMaxBurstDMA0) DMA0_NewMaxBurst <= 1'b1; |
| 411 | else if (clrNewMaxBurstDMA0) DMA0_NewMaxBurst <= 1'b0; |
| 412 | |
| 413 | /*--------------------------------------------------------------*/ |
| 414 | // TXC DMA 1 PIO Read & Write Registers |
| 415 | /*--------------------------------------------------------------*/ |
| 416 | `ifdef NEPTUNE |
| 417 | assign dma1Select = {Port3_DMA_List[1], Port2_DMA_List[1], |
| 418 | Port1_DMA_List[1], Port0_DMA_List[1]}; |
| 419 | `else |
| 420 | assign dma1Select = {2'h0, Port1_DMA_List[1], Port0_DMA_List[1]}; |
| 421 | `endif |
| 422 | |
| 423 | `ifdef NEPTUNE |
| 424 | always @(dma1Select or Port3_ClrMaxBurst |
| 425 | or Port2_ClrMaxBurst or Port1_ClrMaxBurst or Port0_ClrMaxBurst |
| 426 | ) |
| 427 | `else |
| 428 | always @(dma1Select or Port1_ClrMaxBurst or Port0_ClrMaxBurst) |
| 429 | `endif |
| 430 | begin |
| 431 | casex(dma1Select) // Synopsys full_case parallel_case |
| 432 | 4'bxxx1: clrNewMaxBurstDMA1 = Port0_ClrMaxBurst; |
| 433 | 4'bxx10: clrNewMaxBurstDMA1 = Port1_ClrMaxBurst; |
| 434 | `ifdef NEPTUNE |
| 435 | 4'bx100: clrNewMaxBurstDMA1 = Port2_ClrMaxBurst; |
| 436 | 4'b1000: clrNewMaxBurstDMA1 = Port3_ClrMaxBurst; |
| 437 | `endif |
| 438 | default: clrNewMaxBurstDMA1 = 1'b0; |
| 439 | endcase |
| 440 | end |
| 441 | |
| 442 | `ifdef NEPTUNE |
| 443 | always @(dma1Select or Port3_UpdateDMA |
| 444 | or Port2_UpdateDMA or Port1_UpdateDMA or Port0_UpdateDMA |
| 445 | ) |
| 446 | `else |
| 447 | always @(dma1Select or Port1_UpdateDMA or Port0_UpdateDMA) |
| 448 | `endif |
| 449 | begin |
| 450 | casex(dma1Select) // Synopsys full_case parallel_case |
| 451 | 4'bxxx1: updateDMA1Strobe = Port0_UpdateDMA; |
| 452 | 4'bxx10: updateDMA1Strobe = Port1_UpdateDMA; |
| 453 | `ifdef NEPTUNE |
| 454 | 4'bx100: updateDMA1Strobe = Port2_UpdateDMA; |
| 455 | 4'b1000: updateDMA1Strobe = Port3_UpdateDMA; |
| 456 | `endif |
| 457 | default: updateDMA1Strobe = 1'b0; |
| 458 | endcase |
| 459 | end |
| 460 | |
| 461 | `ifdef NEPTUNE |
| 462 | always @(dma1Select or Port3_UpdateDMANumber |
| 463 | or Port2_UpdateDMANumber or Port1_UpdateDMANumber |
| 464 | or Port0_UpdateDMANumber |
| 465 | ) |
| 466 | `else |
| 467 | always @(dma1Select or Port1_UpdateDMANumber or Port0_UpdateDMANumber) |
| 468 | `endif |
| 469 | begin |
| 470 | casex(dma1Select) // Synopsys full_case parallel_case |
| 471 | 4'bxxx1: dma1Valid = Port0_UpdateDMANumber[1]; |
| 472 | 4'bxx10: dma1Valid = Port1_UpdateDMANumber[1]; |
| 473 | `ifdef NEPTUNE |
| 474 | 4'bx100: dma1Valid = Port2_UpdateDMANumber[1]; |
| 475 | 4'b1000: dma1Valid = Port3_UpdateDMANumber[1]; |
| 476 | `endif |
| 477 | default: dma1Valid = 1'b0; |
| 478 | endcase |
| 479 | end |
| 480 | |
| 481 | `ifdef NEPTUNE |
| 482 | always @(dma1Select or Port3_UpdateDMALength |
| 483 | or Port2_UpdateDMALength or Port1_UpdateDMALength |
| 484 | or Port0_UpdateDMALength |
| 485 | ) |
| 486 | `else |
| 487 | always @(dma1Select or Port1_UpdateDMALength or Port0_UpdateDMALength) |
| 488 | `endif |
| 489 | begin |
| 490 | casex(dma1Select) // Synopsys full_case parallel_case |
| 491 | 4'bxxx1: dma1LengthUpdate = Port0_UpdateDMALength; |
| 492 | 4'bxx10: dma1LengthUpdate = Port1_UpdateDMALength; |
| 493 | `ifdef NEPTUNE |
| 494 | 4'bx100: dma1LengthUpdate = Port2_UpdateDMALength; |
| 495 | 4'b1000: dma1LengthUpdate = Port3_UpdateDMALength; |
| 496 | `endif |
| 497 | default: dma1LengthUpdate = 14'h0; |
| 498 | endcase |
| 499 | end |
| 500 | |
| 501 | |
| 502 | assign dma1Update = updateDMA1Strobe & dma1Valid; |
| 503 | |
| 504 | assign collisionDma1Update = (dma1Update |
| 505 | & |
| 506 | (({SlaveAddr[11:2], 2'h0} == `DMA_LENGTH) |
| 507 | && |
| 508 | Read_DMA1_Register && SlaveStrobe) |
| 509 | ); |
| 510 | |
| 511 | always @ (posedge SysClk) |
| 512 | if (!Reset_L) |
| 513 | dma1_Length <= 28'h0; |
| 514 | else if (wrDMA1_Length) |
| 515 | dma1_Length <= #`SD SlaveDataIn[27:0]; |
| 516 | else if (collisionDma1Update) |
| 517 | dma1_Length <= #`SD {14'h0, dma1LengthUpdate}; |
| 518 | else if (dma1Update) |
| 519 | dma1_Length <= #`SD ((dma1_Length + {14'h0, dma1LengthUpdate}) |
| 520 | | |
| 521 | {dma1_Length[27], 27'h0} |
| 522 | ); |
| 523 | |
| 524 | |
| 525 | assign setNewMaxBurstDMA1 = (({SlaveAddr[11:2], 2'h0} == `DMA_MAXBURST) |
| 526 | && |
| 527 | Write_DMA1_Register && SlaveStrobe); |
| 528 | |
| 529 | always @ (posedge SysClk) |
| 530 | if (!Reset_L) DMA1_NewMaxBurst <= 1'b0; |
| 531 | else if (setNewMaxBurstDMA1) DMA1_NewMaxBurst <= 1'b1; |
| 532 | else if (clrNewMaxBurstDMA1) DMA1_NewMaxBurst <= 1'b0; |
| 533 | |
| 534 | /*--------------------------------------------------------------*/ |
| 535 | // TXC DMA 2 PIO Read & Write Registers |
| 536 | /*--------------------------------------------------------------*/ |
| 537 | `ifdef NEPTUNE |
| 538 | assign dma2Select = {Port3_DMA_List[2], Port2_DMA_List[2], |
| 539 | Port1_DMA_List[2], Port0_DMA_List[2]}; |
| 540 | `else |
| 541 | assign dma2Select = {2'h0, Port1_DMA_List[2], Port0_DMA_List[2]}; |
| 542 | `endif |
| 543 | |
| 544 | `ifdef NEPTUNE |
| 545 | always @(dma2Select or Port3_ClrMaxBurst |
| 546 | or Port2_ClrMaxBurst or Port1_ClrMaxBurst or Port0_ClrMaxBurst |
| 547 | ) |
| 548 | `else |
| 549 | always @(dma2Select or Port1_ClrMaxBurst or Port0_ClrMaxBurst) |
| 550 | `endif |
| 551 | begin |
| 552 | casex(dma2Select) // Synopsys full_case parallel_case |
| 553 | 4'bxxx1: clrNewMaxBurstDMA2 = Port0_ClrMaxBurst; |
| 554 | 4'bxx10: clrNewMaxBurstDMA2 = Port1_ClrMaxBurst; |
| 555 | `ifdef NEPTUNE |
| 556 | 4'bx100: clrNewMaxBurstDMA2 = Port2_ClrMaxBurst; |
| 557 | 4'b1000: clrNewMaxBurstDMA2 = Port3_ClrMaxBurst; |
| 558 | `endif |
| 559 | default: clrNewMaxBurstDMA2 = 1'b0; |
| 560 | endcase |
| 561 | end |
| 562 | |
| 563 | `ifdef NEPTUNE |
| 564 | always @(dma2Select or Port3_UpdateDMA |
| 565 | or Port2_UpdateDMA or Port1_UpdateDMA or Port0_UpdateDMA |
| 566 | ) |
| 567 | `else |
| 568 | always @(dma2Select or Port1_UpdateDMA or Port0_UpdateDMA) |
| 569 | `endif |
| 570 | begin |
| 571 | casex(dma2Select) // Synopsys full_case parallel_case |
| 572 | 4'bxxx1: updateDMA2Strobe = Port0_UpdateDMA; |
| 573 | 4'bxx10: updateDMA2Strobe = Port1_UpdateDMA; |
| 574 | `ifdef NEPTUNE |
| 575 | 4'bx100: updateDMA2Strobe = Port2_UpdateDMA; |
| 576 | 4'b1000: updateDMA2Strobe = Port3_UpdateDMA; |
| 577 | `endif |
| 578 | default: updateDMA2Strobe = 1'b0; |
| 579 | endcase |
| 580 | end |
| 581 | |
| 582 | `ifdef NEPTUNE |
| 583 | always @(dma2Select or Port3_UpdateDMANumber |
| 584 | or Port2_UpdateDMANumber or Port1_UpdateDMANumber |
| 585 | or Port0_UpdateDMANumber |
| 586 | ) |
| 587 | `else |
| 588 | always @(dma2Select or Port1_UpdateDMANumber or Port0_UpdateDMANumber) |
| 589 | `endif |
| 590 | begin |
| 591 | casex(dma2Select) // Synopsys full_case parallel_case |
| 592 | 4'bxxx1: dma2Valid = Port0_UpdateDMANumber[2]; |
| 593 | 4'bxx10: dma2Valid = Port1_UpdateDMANumber[2]; |
| 594 | `ifdef NEPTUNE |
| 595 | 4'bx100: dma2Valid = Port2_UpdateDMANumber[2]; |
| 596 | 4'b1000: dma2Valid = Port3_UpdateDMANumber[2]; |
| 597 | `endif |
| 598 | default: dma2Valid = 1'b0; |
| 599 | endcase |
| 600 | end |
| 601 | |
| 602 | `ifdef NEPTUNE |
| 603 | always @(dma2Select or Port3_UpdateDMALength |
| 604 | or Port2_UpdateDMALength or Port1_UpdateDMALength |
| 605 | or Port0_UpdateDMALength |
| 606 | ) |
| 607 | `else |
| 608 | always @(dma2Select or Port1_UpdateDMALength or Port0_UpdateDMALength) |
| 609 | `endif |
| 610 | begin |
| 611 | casex(dma2Select) // Synopsys full_case parallel_case |
| 612 | 4'bxxx1: dma2LengthUpdate = Port0_UpdateDMALength; |
| 613 | 4'bxx10: dma2LengthUpdate = Port1_UpdateDMALength; |
| 614 | `ifdef NEPTUNE |
| 615 | 4'bx100: dma2LengthUpdate = Port2_UpdateDMALength; |
| 616 | 4'b1000: dma2LengthUpdate = Port3_UpdateDMALength; |
| 617 | `endif |
| 618 | default: dma2LengthUpdate = 14'h0; |
| 619 | endcase |
| 620 | end |
| 621 | |
| 622 | |
| 623 | assign dma2Update = updateDMA2Strobe & dma2Valid; |
| 624 | |
| 625 | assign collisionDma2Update = (dma2Update |
| 626 | & |
| 627 | (({SlaveAddr[11:2], 2'h0} == `DMA_LENGTH) |
| 628 | && |
| 629 | Read_DMA2_Register && SlaveStrobe) |
| 630 | ); |
| 631 | |
| 632 | always @ (posedge SysClk) |
| 633 | if (!Reset_L) |
| 634 | dma2_Length <= 28'h0; |
| 635 | else if (wrDMA2_Length) |
| 636 | dma2_Length <= #`SD SlaveDataIn[27:0]; |
| 637 | else if (collisionDma2Update) |
| 638 | dma2_Length <= #`SD {14'h0, dma2LengthUpdate}; |
| 639 | else if (dma2Update) |
| 640 | dma2_Length <= #`SD ((dma2_Length + {14'h0, dma2LengthUpdate}) |
| 641 | | |
| 642 | {dma2_Length[27], 27'h0} |
| 643 | ); |
| 644 | |
| 645 | |
| 646 | assign setNewMaxBurstDMA2 = (({SlaveAddr[11:2], 2'h0} == `DMA_MAXBURST) |
| 647 | && |
| 648 | Write_DMA2_Register && SlaveStrobe); |
| 649 | |
| 650 | always @ (posedge SysClk) |
| 651 | if (!Reset_L) DMA2_NewMaxBurst <= 1'b0; |
| 652 | else if (setNewMaxBurstDMA2) DMA2_NewMaxBurst <= 1'b1; |
| 653 | else if (clrNewMaxBurstDMA2) DMA2_NewMaxBurst <= 1'b0; |
| 654 | |
| 655 | /*--------------------------------------------------------------*/ |
| 656 | // TXC DMA 3 PIO Read & Write Registers |
| 657 | /*--------------------------------------------------------------*/ |
| 658 | `ifdef NEPTUNE |
| 659 | assign dma3Select = {Port3_DMA_List[3], Port2_DMA_List[3], |
| 660 | Port1_DMA_List[3], Port0_DMA_List[3]}; |
| 661 | `else |
| 662 | assign dma3Select = {2'h0, Port1_DMA_List[3], Port0_DMA_List[3]}; |
| 663 | `endif |
| 664 | |
| 665 | `ifdef NEPTUNE |
| 666 | always @(dma3Select or Port3_ClrMaxBurst |
| 667 | or Port2_ClrMaxBurst or Port1_ClrMaxBurst or Port0_ClrMaxBurst |
| 668 | ) |
| 669 | `else |
| 670 | always @(dma3Select or Port1_ClrMaxBurst or Port0_ClrMaxBurst) |
| 671 | `endif |
| 672 | begin |
| 673 | casex(dma3Select) // Synopsys full_case parallel_case |
| 674 | 4'bxxx1: clrNewMaxBurstDMA3 = Port0_ClrMaxBurst; |
| 675 | 4'bxx10: clrNewMaxBurstDMA3 = Port1_ClrMaxBurst; |
| 676 | `ifdef NEPTUNE |
| 677 | 4'bx100: clrNewMaxBurstDMA3 = Port2_ClrMaxBurst; |
| 678 | 4'b1000: clrNewMaxBurstDMA3 = Port3_ClrMaxBurst; |
| 679 | `endif |
| 680 | default: clrNewMaxBurstDMA3 = 1'b0; |
| 681 | endcase |
| 682 | end |
| 683 | |
| 684 | `ifdef NEPTUNE |
| 685 | always @(dma3Select or Port3_UpdateDMA |
| 686 | or Port2_UpdateDMA or Port1_UpdateDMA or Port0_UpdateDMA |
| 687 | ) |
| 688 | `else |
| 689 | always @(dma3Select or Port1_UpdateDMA or Port0_UpdateDMA) |
| 690 | `endif |
| 691 | begin |
| 692 | casex(dma3Select) // Synopsys full_case parallel_case |
| 693 | 4'bxxx1: updateDMA3Strobe = Port0_UpdateDMA; |
| 694 | 4'bxx10: updateDMA3Strobe = Port1_UpdateDMA; |
| 695 | `ifdef NEPTUNE |
| 696 | 4'bx100: updateDMA3Strobe = Port2_UpdateDMA; |
| 697 | 4'b1000: updateDMA3Strobe = Port3_UpdateDMA; |
| 698 | `endif |
| 699 | default: updateDMA3Strobe = 1'b0; |
| 700 | endcase |
| 701 | end |
| 702 | |
| 703 | `ifdef NEPTUNE |
| 704 | always @(dma3Select or Port3_UpdateDMANumber |
| 705 | or Port2_UpdateDMANumber or Port1_UpdateDMANumber |
| 706 | or Port0_UpdateDMANumber |
| 707 | ) |
| 708 | `else |
| 709 | always @(dma3Select or Port1_UpdateDMANumber or Port0_UpdateDMANumber) |
| 710 | `endif |
| 711 | begin |
| 712 | casex(dma3Select) // Synopsys full_case parallel_case |
| 713 | 4'bxxx1: dma3Valid = Port0_UpdateDMANumber[3]; |
| 714 | 4'bxx10: dma3Valid = Port1_UpdateDMANumber[3]; |
| 715 | `ifdef NEPTUNE |
| 716 | 4'bx100: dma3Valid = Port2_UpdateDMANumber[3]; |
| 717 | 4'b1000: dma3Valid = Port3_UpdateDMANumber[3]; |
| 718 | `endif |
| 719 | default: dma3Valid = 1'b0; |
| 720 | endcase |
| 721 | end |
| 722 | |
| 723 | `ifdef NEPTUNE |
| 724 | always @(dma3Select or Port3_UpdateDMALength |
| 725 | or Port2_UpdateDMALength or Port1_UpdateDMALength |
| 726 | or Port0_UpdateDMALength |
| 727 | ) |
| 728 | `else |
| 729 | always @(dma3Select or Port1_UpdateDMALength or Port0_UpdateDMALength) |
| 730 | `endif |
| 731 | begin |
| 732 | casex(dma3Select) // Synopsys full_case parallel_case |
| 733 | 4'bxxx1: dma3LengthUpdate = Port0_UpdateDMALength; |
| 734 | 4'bxx10: dma3LengthUpdate = Port1_UpdateDMALength; |
| 735 | `ifdef NEPTUNE |
| 736 | 4'bx100: dma3LengthUpdate = Port2_UpdateDMALength; |
| 737 | 4'b1000: dma3LengthUpdate = Port3_UpdateDMALength; |
| 738 | `endif |
| 739 | default: dma3LengthUpdate = 14'h0; |
| 740 | endcase |
| 741 | end |
| 742 | |
| 743 | |
| 744 | assign dma3Update = updateDMA3Strobe & dma3Valid; |
| 745 | |
| 746 | assign collisionDma3Update = (dma3Update |
| 747 | & |
| 748 | (({SlaveAddr[11:2], 2'h0} == `DMA_LENGTH) |
| 749 | && |
| 750 | Read_DMA3_Register && SlaveStrobe) |
| 751 | ); |
| 752 | |
| 753 | always @ (posedge SysClk) |
| 754 | if (!Reset_L) |
| 755 | dma3_Length <= 28'h0; |
| 756 | else if (wrDMA3_Length) |
| 757 | dma3_Length <= #`SD SlaveDataIn[27:0]; |
| 758 | else if (collisionDma3Update) |
| 759 | dma3_Length <= #`SD {14'h0, dma3LengthUpdate}; |
| 760 | else if (dma3Update) |
| 761 | dma3_Length <= #`SD ((dma3_Length + {14'h0, dma3LengthUpdate}) |
| 762 | | |
| 763 | {dma3_Length[27], 27'h0} |
| 764 | ); |
| 765 | |
| 766 | |
| 767 | assign setNewMaxBurstDMA3 = (({SlaveAddr[11:2], 2'h0} == `DMA_MAXBURST) |
| 768 | && |
| 769 | Write_DMA3_Register && SlaveStrobe); |
| 770 | |
| 771 | always @ (posedge SysClk) |
| 772 | if (!Reset_L) DMA3_NewMaxBurst <= 1'b0; |
| 773 | else if (setNewMaxBurstDMA3) DMA3_NewMaxBurst <= 1'b1; |
| 774 | else if (clrNewMaxBurstDMA3) DMA3_NewMaxBurst <= 1'b0; |
| 775 | |
| 776 | /*--------------------------------------------------------------*/ |
| 777 | // TXC DMA 0-3 PIO Read & Write Registers |
| 778 | /*--------------------------------------------------------------*/ |
| 779 | always @ (posedge SysClk) |
| 780 | if (!Reset_L) |
| 781 | DMA_Slave_DataOut <= 32'h0; |
| 782 | else if (readDMAregister) |
| 783 | begin |
| 784 | case (readAddress) // synopsys parallel_case |
| 785 | /* 0in < case -parallel */ |
| 786 | |
| 787 | `DMA_0_MAXBURST: DMA_Slave_DataOut <= {12'h0, DMA0_MaxBurst}; |
| 788 | `DMA_0_LENGTH: DMA_Slave_DataOut <= {4'h0, dma0_Length}; |
| 789 | `DMA_1_MAXBURST: DMA_Slave_DataOut <= {12'h0, DMA1_MaxBurst}; |
| 790 | `DMA_1_LENGTH: DMA_Slave_DataOut <= {4'h0, dma1_Length}; |
| 791 | `DMA_2_MAXBURST: DMA_Slave_DataOut <= {12'h0, DMA2_MaxBurst}; |
| 792 | `DMA_2_LENGTH: DMA_Slave_DataOut <= {4'h0, dma2_Length}; |
| 793 | `DMA_3_MAXBURST: DMA_Slave_DataOut <= {12'h0, DMA3_MaxBurst}; |
| 794 | `DMA_3_LENGTH: DMA_Slave_DataOut <= {4'h0, dma3_Length}; |
| 795 | default: DMA_Slave_DataOut <= 32'h0; |
| 796 | endcase |
| 797 | end |
| 798 | else |
| 799 | DMA_Slave_DataOut <= 32'h0; |
| 800 | |
| 801 | |
| 802 | always @ (posedge SysClk) |
| 803 | if (!Reset_L) |
| 804 | begin |
| 805 | DMA0_MaxBurst <= 20'h0; |
| 806 | wrDMA0_Length <= 1'b0; |
| 807 | DMA1_MaxBurst <= 20'h0; |
| 808 | wrDMA1_Length <= 1'b0; |
| 809 | DMA2_MaxBurst <= 20'h0; |
| 810 | wrDMA2_Length <= 1'b0; |
| 811 | DMA3_MaxBurst <= 20'h0; |
| 812 | wrDMA3_Length <= 1'b0; |
| 813 | end |
| 814 | else if (writeDMAregister) |
| 815 | begin |
| 816 | case (writeAddress) // synopsys parallel_case |
| 817 | /* 0in < case -parallel */ |
| 818 | |
| 819 | `DMA_0_MAXBURST: DMA0_MaxBurst <= SlaveDataIn[19:0]; |
| 820 | `DMA_0_LENGTH: wrDMA0_Length <= 1'b1; |
| 821 | `DMA_1_MAXBURST: DMA1_MaxBurst <= SlaveDataIn[19:0]; |
| 822 | `DMA_1_LENGTH: wrDMA1_Length <= 1'b1; |
| 823 | `DMA_2_MAXBURST: DMA2_MaxBurst <= SlaveDataIn[19:0]; |
| 824 | `DMA_2_LENGTH: wrDMA2_Length <= 1'b1; |
| 825 | `DMA_3_MAXBURST: DMA3_MaxBurst <= SlaveDataIn[19:0]; |
| 826 | `DMA_3_LENGTH: wrDMA3_Length <= 1'b1; |
| 827 | |
| 828 | endcase |
| 829 | end |
| 830 | else |
| 831 | begin |
| 832 | wrDMA0_Length <= 1'b0; |
| 833 | wrDMA1_Length <= 1'b0; |
| 834 | wrDMA2_Length <= 1'b0; |
| 835 | wrDMA3_Length <= 1'b0; |
| 836 | end |
| 837 | |
| 838 | /*--------------------------------------------------------------*/ |
| 839 | // End PIO Read & Write |
| 840 | /*--------------------------------------------------------------*/ |
| 841 | |
| 842 | endmodule |