| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_txc_drr_engine.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /********************************************************************* |
| 36 | * |
| 37 | * niu_txc_drr_engine.v |
| 38 | * |
| 39 | * NIU Transmit Controller Deficit Round Robin Engine |
| 40 | * |
| 41 | * Orignal Author(s): Rahoul Puri |
| 42 | * Modifier(s): |
| 43 | * Project(s): Neptune |
| 44 | * |
| 45 | * Copyright (c) 2004 Sun Microsystems, Inc. |
| 46 | * |
| 47 | * All Rights Reserved. |
| 48 | * |
| 49 | * This verilog model is the confidential and proprietary property of |
| 50 | * Sun Microsystems, Inc., and the possession or use of this model |
| 51 | * requires a written license from Sun Microsystems, Inc. |
| 52 | * |
| 53 | **********************************************************************/ |
| 54 | |
| 55 | `include "timescale.v" |
| 56 | |
| 57 | module niu_txc_drr_engine ( |
| 58 | SysClk, |
| 59 | Reset_L, |
| 60 | Txc_Enabled, |
| 61 | MAC_Enabled, |
| 62 | FlushEngine, |
| 63 | |
| 64 | DMA0_Active, |
| 65 | DMA0_Error, |
| 66 | DMA0_EofList, |
| 67 | DMA0_CacheReady, |
| 68 | DMA0_Partial, |
| 69 | DMA0_Reset_Scheduled, |
| 70 | DMA0_Reset_Done, |
| 71 | DMA1_Active, |
| 72 | DMA1_Error, |
| 73 | DMA1_EofList, |
| 74 | DMA1_CacheReady, |
| 75 | DMA1_Partial, |
| 76 | DMA1_Reset_Scheduled, |
| 77 | DMA1_Reset_Done, |
| 78 | DMA2_Active, |
| 79 | DMA2_Error, |
| 80 | DMA2_EofList, |
| 81 | DMA2_CacheReady, |
| 82 | DMA2_Partial, |
| 83 | DMA2_Reset_Scheduled, |
| 84 | DMA2_Reset_Done, |
| 85 | DMA3_Active, |
| 86 | DMA3_Error, |
| 87 | DMA3_EofList, |
| 88 | DMA3_CacheReady, |
| 89 | DMA3_Partial, |
| 90 | DMA3_Reset_Scheduled, |
| 91 | DMA3_Reset_Done, |
| 92 | DMA4_Active, |
| 93 | DMA4_Error, |
| 94 | DMA4_EofList, |
| 95 | DMA4_CacheReady, |
| 96 | DMA4_Partial, |
| 97 | DMA4_Reset_Scheduled, |
| 98 | DMA4_Reset_Done, |
| 99 | DMA5_Active, |
| 100 | DMA5_Error, |
| 101 | DMA5_EofList, |
| 102 | DMA5_CacheReady, |
| 103 | DMA5_Partial, |
| 104 | DMA5_Reset_Scheduled, |
| 105 | DMA5_Reset_Done, |
| 106 | DMA6_Active, |
| 107 | DMA6_Error, |
| 108 | DMA6_EofList, |
| 109 | DMA6_CacheReady, |
| 110 | DMA6_Partial, |
| 111 | DMA6_Reset_Scheduled, |
| 112 | DMA6_Reset_Done, |
| 113 | DMA7_Active, |
| 114 | DMA7_Error, |
| 115 | DMA7_EofList, |
| 116 | DMA7_CacheReady, |
| 117 | DMA7_Partial, |
| 118 | DMA7_Reset_Scheduled, |
| 119 | DMA7_Reset_Done, |
| 120 | DMA8_Active, |
| 121 | DMA8_Error, |
| 122 | DMA8_EofList, |
| 123 | DMA8_CacheReady, |
| 124 | DMA8_Partial, |
| 125 | DMA8_Reset_Scheduled, |
| 126 | DMA8_Reset_Done, |
| 127 | DMA9_Active, |
| 128 | DMA9_Error, |
| 129 | DMA9_EofList, |
| 130 | DMA9_CacheReady, |
| 131 | DMA9_Partial, |
| 132 | DMA9_Reset_Scheduled, |
| 133 | DMA9_Reset_Done, |
| 134 | DMA10_Active, |
| 135 | DMA10_Error, |
| 136 | DMA10_EofList, |
| 137 | DMA10_CacheReady, |
| 138 | DMA10_Partial, |
| 139 | DMA10_Reset_Scheduled, |
| 140 | DMA10_Reset_Done, |
| 141 | DMA11_Active, |
| 142 | DMA11_Error, |
| 143 | DMA11_EofList, |
| 144 | DMA11_CacheReady, |
| 145 | DMA11_Partial, |
| 146 | DMA11_Reset_Scheduled, |
| 147 | DMA11_Reset_Done, |
| 148 | DMA12_Active, |
| 149 | DMA12_Error, |
| 150 | DMA12_EofList, |
| 151 | DMA12_CacheReady, |
| 152 | DMA12_Partial, |
| 153 | DMA12_Reset_Scheduled, |
| 154 | DMA12_Reset_Done, |
| 155 | DMA13_Active, |
| 156 | DMA13_Error, |
| 157 | DMA13_EofList, |
| 158 | DMA13_CacheReady, |
| 159 | DMA13_Partial, |
| 160 | DMA13_Reset_Scheduled, |
| 161 | DMA13_Reset_Done, |
| 162 | DMA14_Active, |
| 163 | DMA14_Error, |
| 164 | DMA14_EofList, |
| 165 | DMA14_CacheReady, |
| 166 | DMA14_Partial, |
| 167 | DMA14_Reset_Scheduled, |
| 168 | DMA14_Reset_Done, |
| 169 | DMA15_Active, |
| 170 | DMA15_Error, |
| 171 | DMA15_EofList, |
| 172 | DMA15_CacheReady, |
| 173 | DMA15_Partial, |
| 174 | DMA15_Reset_Scheduled, |
| 175 | DMA15_Reset_Done, |
| 176 | DMA16_Active, |
| 177 | DMA16_Error, |
| 178 | DMA16_EofList, |
| 179 | DMA16_CacheReady, |
| 180 | DMA16_Partial, |
| 181 | DMA16_Reset_Scheduled, |
| 182 | DMA16_Reset_Done, |
| 183 | DMA17_Active, |
| 184 | DMA17_Error, |
| 185 | DMA17_EofList, |
| 186 | DMA17_CacheReady, |
| 187 | DMA17_Partial, |
| 188 | DMA17_Reset_Scheduled, |
| 189 | DMA17_Reset_Done, |
| 190 | DMA18_Active, |
| 191 | DMA18_Error, |
| 192 | DMA18_EofList, |
| 193 | DMA18_CacheReady, |
| 194 | DMA18_Partial, |
| 195 | DMA18_Reset_Scheduled, |
| 196 | DMA18_Reset_Done, |
| 197 | DMA19_Active, |
| 198 | DMA19_Error, |
| 199 | DMA19_EofList, |
| 200 | DMA19_CacheReady, |
| 201 | DMA19_Partial, |
| 202 | DMA19_Reset_Scheduled, |
| 203 | DMA19_Reset_Done, |
| 204 | DMA20_Active, |
| 205 | DMA20_Error, |
| 206 | DMA20_EofList, |
| 207 | DMA20_CacheReady, |
| 208 | DMA20_Partial, |
| 209 | DMA20_Reset_Scheduled, |
| 210 | DMA20_Reset_Done, |
| 211 | DMA21_Active, |
| 212 | DMA21_Error, |
| 213 | DMA21_EofList, |
| 214 | DMA21_CacheReady, |
| 215 | DMA21_Partial, |
| 216 | DMA21_Reset_Scheduled, |
| 217 | DMA21_Reset_Done, |
| 218 | DMA22_Active, |
| 219 | DMA22_Error, |
| 220 | DMA22_EofList, |
| 221 | DMA22_CacheReady, |
| 222 | DMA22_Partial, |
| 223 | DMA22_Reset_Scheduled, |
| 224 | DMA22_Reset_Done, |
| 225 | DMA23_Active, |
| 226 | DMA23_Error, |
| 227 | DMA23_EofList, |
| 228 | DMA23_CacheReady, |
| 229 | DMA23_Partial, |
| 230 | DMA23_Reset_Scheduled, |
| 231 | DMA23_Reset_Done, |
| 232 | |
| 233 | DMA0_NewMaxBurst, |
| 234 | DMA1_NewMaxBurst, |
| 235 | DMA2_NewMaxBurst, |
| 236 | DMA3_NewMaxBurst, |
| 237 | DMA4_NewMaxBurst, |
| 238 | DMA5_NewMaxBurst, |
| 239 | DMA6_NewMaxBurst, |
| 240 | DMA7_NewMaxBurst, |
| 241 | DMA8_NewMaxBurst, |
| 242 | DMA9_NewMaxBurst, |
| 243 | DMA10_NewMaxBurst, |
| 244 | DMA11_NewMaxBurst, |
| 245 | DMA12_NewMaxBurst, |
| 246 | DMA13_NewMaxBurst, |
| 247 | DMA14_NewMaxBurst, |
| 248 | DMA15_NewMaxBurst, |
| 249 | DMA16_NewMaxBurst, |
| 250 | DMA17_NewMaxBurst, |
| 251 | DMA18_NewMaxBurst, |
| 252 | DMA19_NewMaxBurst, |
| 253 | DMA20_NewMaxBurst, |
| 254 | DMA21_NewMaxBurst, |
| 255 | DMA22_NewMaxBurst, |
| 256 | DMA23_NewMaxBurst, |
| 257 | DMA0_MaxBurst, |
| 258 | DMA1_MaxBurst, |
| 259 | DMA2_MaxBurst, |
| 260 | DMA3_MaxBurst, |
| 261 | DMA4_MaxBurst, |
| 262 | DMA5_MaxBurst, |
| 263 | DMA6_MaxBurst, |
| 264 | DMA7_MaxBurst, |
| 265 | DMA8_MaxBurst, |
| 266 | DMA9_MaxBurst, |
| 267 | DMA10_MaxBurst, |
| 268 | DMA11_MaxBurst, |
| 269 | DMA12_MaxBurst, |
| 270 | DMA13_MaxBurst, |
| 271 | DMA14_MaxBurst, |
| 272 | DMA15_MaxBurst, |
| 273 | DMA16_MaxBurst, |
| 274 | DMA17_MaxBurst, |
| 275 | DMA18_MaxBurst, |
| 276 | DMA19_MaxBurst, |
| 277 | DMA20_MaxBurst, |
| 278 | DMA21_MaxBurst, |
| 279 | DMA22_MaxBurst, |
| 280 | DMA23_MaxBurst, |
| 281 | Port_DMA_List, |
| 282 | ClrMaxBurst, // Clear max burst bit in control register |
| 283 | |
| 284 | DRR_PacketDone, |
| 285 | DRR_PacketByteCount, |
| 286 | |
| 287 | DRR_Arb_Valid, |
| 288 | DRR_NextDMAChannel, |
| 289 | |
| 290 | LatchActiveDMA, |
| 291 | ContextActiveList, |
| 292 | |
| 293 | DRR_ArbState |
| 294 | ); |
| 295 | |
| 296 | `include "txc_defines.h" |
| 297 | |
| 298 | // Global Signals |
| 299 | input SysClk; |
| 300 | input Reset_L; |
| 301 | input Txc_Enabled; |
| 302 | input MAC_Enabled; |
| 303 | input FlushEngine; |
| 304 | |
| 305 | // DMA Cache Registers |
| 306 | |
| 307 | //DMA0 |
| 308 | input DMA0_Active; |
| 309 | input DMA0_Error; |
| 310 | input DMA0_EofList; |
| 311 | input DMA0_CacheReady; |
| 312 | input DMA0_Partial; |
| 313 | input DMA0_Reset_Scheduled; |
| 314 | |
| 315 | output DMA0_Reset_Done; |
| 316 | |
| 317 | //DMA1 |
| 318 | input DMA1_Active; |
| 319 | input DMA1_Error; |
| 320 | input DMA1_EofList; |
| 321 | input DMA1_CacheReady; |
| 322 | input DMA1_Partial; |
| 323 | input DMA1_Reset_Scheduled; |
| 324 | |
| 325 | output DMA1_Reset_Done; |
| 326 | |
| 327 | //DMA2 |
| 328 | input DMA2_Active; |
| 329 | input DMA2_Error; |
| 330 | input DMA2_EofList; |
| 331 | input DMA2_CacheReady; |
| 332 | input DMA2_Partial; |
| 333 | input DMA2_Reset_Scheduled; |
| 334 | |
| 335 | output DMA2_Reset_Done; |
| 336 | |
| 337 | //DMA3 |
| 338 | input DMA3_Active; |
| 339 | input DMA3_Error; |
| 340 | input DMA3_EofList; |
| 341 | input DMA3_CacheReady; |
| 342 | input DMA3_Partial; |
| 343 | input DMA3_Reset_Scheduled; |
| 344 | |
| 345 | output DMA3_Reset_Done; |
| 346 | |
| 347 | //DMA4 |
| 348 | input DMA4_Active; |
| 349 | input DMA4_Error; |
| 350 | input DMA4_EofList; |
| 351 | input DMA4_CacheReady; |
| 352 | input DMA4_Partial; |
| 353 | input DMA4_Reset_Scheduled; |
| 354 | |
| 355 | output DMA4_Reset_Done; |
| 356 | |
| 357 | //DMA5 |
| 358 | input DMA5_Active; |
| 359 | input DMA5_Error; |
| 360 | input DMA5_EofList; |
| 361 | input DMA5_CacheReady; |
| 362 | input DMA5_Partial; |
| 363 | input DMA5_Reset_Scheduled; |
| 364 | |
| 365 | output DMA5_Reset_Done; |
| 366 | |
| 367 | //DMA6 |
| 368 | input DMA6_Active; |
| 369 | input DMA6_Error; |
| 370 | input DMA6_EofList; |
| 371 | input DMA6_CacheReady; |
| 372 | input DMA6_Partial; |
| 373 | input DMA6_Reset_Scheduled; |
| 374 | |
| 375 | output DMA6_Reset_Done; |
| 376 | |
| 377 | //DMA7 |
| 378 | input DMA7_Active; |
| 379 | input DMA7_Error; |
| 380 | input DMA7_EofList; |
| 381 | input DMA7_CacheReady; |
| 382 | input DMA7_Partial; |
| 383 | input DMA7_Reset_Scheduled; |
| 384 | |
| 385 | output DMA7_Reset_Done; |
| 386 | |
| 387 | //DMA8 |
| 388 | input DMA8_Active; |
| 389 | input DMA8_Error; |
| 390 | input DMA8_EofList; |
| 391 | input DMA8_CacheReady; |
| 392 | input DMA8_Partial; |
| 393 | input DMA8_Reset_Scheduled; |
| 394 | |
| 395 | output DMA8_Reset_Done; |
| 396 | |
| 397 | //DMA9 |
| 398 | input DMA9_Active; |
| 399 | input DMA9_Error; |
| 400 | input DMA9_EofList; |
| 401 | input DMA9_CacheReady; |
| 402 | input DMA9_Partial; |
| 403 | input DMA9_Reset_Scheduled; |
| 404 | |
| 405 | output DMA9_Reset_Done; |
| 406 | |
| 407 | //DMA10 |
| 408 | input DMA10_Active; |
| 409 | input DMA10_Error; |
| 410 | input DMA10_EofList; |
| 411 | input DMA10_CacheReady; |
| 412 | input DMA10_Partial; |
| 413 | input DMA10_Reset_Scheduled; |
| 414 | |
| 415 | output DMA10_Reset_Done; |
| 416 | |
| 417 | //DMA11 |
| 418 | input DMA11_Active; |
| 419 | input DMA11_Error; |
| 420 | input DMA11_EofList; |
| 421 | input DMA11_CacheReady; |
| 422 | input DMA11_Partial; |
| 423 | input DMA11_Reset_Scheduled; |
| 424 | |
| 425 | output DMA11_Reset_Done; |
| 426 | |
| 427 | //DMA12 |
| 428 | input DMA12_Active; |
| 429 | input DMA12_Error; |
| 430 | input DMA12_EofList; |
| 431 | input DMA12_CacheReady; |
| 432 | input DMA12_Partial; |
| 433 | input DMA12_Reset_Scheduled; |
| 434 | |
| 435 | output DMA12_Reset_Done; |
| 436 | |
| 437 | //DMA13 |
| 438 | input DMA13_Active; |
| 439 | input DMA13_Error; |
| 440 | input DMA13_EofList; |
| 441 | input DMA13_CacheReady; |
| 442 | input DMA13_Partial; |
| 443 | input DMA13_Reset_Scheduled; |
| 444 | |
| 445 | output DMA13_Reset_Done; |
| 446 | |
| 447 | //DMA14 |
| 448 | input DMA14_Active; |
| 449 | input DMA14_Error; |
| 450 | input DMA14_EofList; |
| 451 | input DMA14_CacheReady; |
| 452 | input DMA14_Partial; |
| 453 | input DMA14_Reset_Scheduled; |
| 454 | |
| 455 | output DMA14_Reset_Done; |
| 456 | |
| 457 | //DMA15 |
| 458 | input DMA15_Active; |
| 459 | input DMA15_Error; |
| 460 | input DMA15_EofList; |
| 461 | input DMA15_CacheReady; |
| 462 | input DMA15_Partial; |
| 463 | input DMA15_Reset_Scheduled; |
| 464 | |
| 465 | output DMA15_Reset_Done; |
| 466 | |
| 467 | //DMA16 |
| 468 | input DMA16_Active; |
| 469 | input DMA16_Error; |
| 470 | input DMA16_EofList; |
| 471 | input DMA16_CacheReady; |
| 472 | input DMA16_Partial; |
| 473 | input DMA16_Reset_Scheduled; |
| 474 | |
| 475 | output DMA16_Reset_Done; |
| 476 | |
| 477 | //DMA17 |
| 478 | input DMA17_Active; |
| 479 | input DMA17_Error; |
| 480 | input DMA17_EofList; |
| 481 | input DMA17_CacheReady; |
| 482 | input DMA17_Partial; |
| 483 | input DMA17_Reset_Scheduled; |
| 484 | |
| 485 | output DMA17_Reset_Done; |
| 486 | |
| 487 | //DMA18 |
| 488 | input DMA18_Active; |
| 489 | input DMA18_Error; |
| 490 | input DMA18_EofList; |
| 491 | input DMA18_CacheReady; |
| 492 | input DMA18_Partial; |
| 493 | input DMA18_Reset_Scheduled; |
| 494 | |
| 495 | output DMA18_Reset_Done; |
| 496 | |
| 497 | //DMA19 |
| 498 | input DMA19_Active; |
| 499 | input DMA19_Error; |
| 500 | input DMA19_EofList; |
| 501 | input DMA19_CacheReady; |
| 502 | input DMA19_Partial; |
| 503 | input DMA19_Reset_Scheduled; |
| 504 | |
| 505 | output DMA19_Reset_Done; |
| 506 | |
| 507 | //DMA20 |
| 508 | input DMA20_Active; |
| 509 | input DMA20_Error; |
| 510 | input DMA20_EofList; |
| 511 | input DMA20_CacheReady; |
| 512 | input DMA20_Partial; |
| 513 | input DMA20_Reset_Scheduled; |
| 514 | |
| 515 | output DMA20_Reset_Done; |
| 516 | |
| 517 | //DMA21 |
| 518 | input DMA21_Active; |
| 519 | input DMA21_Error; |
| 520 | input DMA21_EofList; |
| 521 | input DMA21_CacheReady; |
| 522 | input DMA21_Partial; |
| 523 | input DMA21_Reset_Scheduled; |
| 524 | |
| 525 | output DMA21_Reset_Done; |
| 526 | |
| 527 | //DMA22 |
| 528 | input DMA22_Active; |
| 529 | input DMA22_Error; |
| 530 | input DMA22_EofList; |
| 531 | input DMA22_CacheReady; |
| 532 | input DMA22_Partial; |
| 533 | input DMA22_Reset_Scheduled; |
| 534 | |
| 535 | output DMA22_Reset_Done; |
| 536 | |
| 537 | //DMA23 |
| 538 | input DMA23_Active; |
| 539 | input DMA23_Error; |
| 540 | input DMA23_EofList; |
| 541 | input DMA23_CacheReady; |
| 542 | input DMA23_Partial; |
| 543 | input DMA23_Reset_Scheduled; |
| 544 | |
| 545 | output DMA23_Reset_Done; |
| 546 | |
| 547 | // Control Registers |
| 548 | input DMA0_NewMaxBurst; |
| 549 | input DMA1_NewMaxBurst; |
| 550 | input DMA2_NewMaxBurst; |
| 551 | input DMA3_NewMaxBurst; |
| 552 | input DMA4_NewMaxBurst; |
| 553 | input DMA5_NewMaxBurst; |
| 554 | input DMA6_NewMaxBurst; |
| 555 | input DMA7_NewMaxBurst; |
| 556 | input DMA8_NewMaxBurst; |
| 557 | input DMA9_NewMaxBurst; |
| 558 | input DMA10_NewMaxBurst; |
| 559 | input DMA11_NewMaxBurst; |
| 560 | input DMA12_NewMaxBurst; |
| 561 | input DMA13_NewMaxBurst; |
| 562 | input DMA14_NewMaxBurst; |
| 563 | input DMA15_NewMaxBurst; |
| 564 | input DMA16_NewMaxBurst; |
| 565 | input DMA17_NewMaxBurst; |
| 566 | input DMA18_NewMaxBurst; |
| 567 | input DMA19_NewMaxBurst; |
| 568 | input DMA20_NewMaxBurst; |
| 569 | input DMA21_NewMaxBurst; |
| 570 | input DMA22_NewMaxBurst; |
| 571 | input DMA23_NewMaxBurst; |
| 572 | input [19:0] DMA0_MaxBurst; |
| 573 | input [19:0] DMA1_MaxBurst; |
| 574 | input [19:0] DMA2_MaxBurst; |
| 575 | input [19:0] DMA3_MaxBurst; |
| 576 | input [19:0] DMA4_MaxBurst; |
| 577 | input [19:0] DMA5_MaxBurst; |
| 578 | input [19:0] DMA6_MaxBurst; |
| 579 | input [19:0] DMA7_MaxBurst; |
| 580 | input [19:0] DMA8_MaxBurst; |
| 581 | input [19:0] DMA9_MaxBurst; |
| 582 | input [19:0] DMA10_MaxBurst; |
| 583 | input [19:0] DMA11_MaxBurst; |
| 584 | input [19:0] DMA12_MaxBurst; |
| 585 | input [19:0] DMA13_MaxBurst; |
| 586 | input [19:0] DMA14_MaxBurst; |
| 587 | input [19:0] DMA15_MaxBurst; |
| 588 | input [19:0] DMA16_MaxBurst; |
| 589 | input [19:0] DMA17_MaxBurst; |
| 590 | input [19:0] DMA18_MaxBurst; |
| 591 | input [19:0] DMA19_MaxBurst; |
| 592 | input [19:0] DMA20_MaxBurst; |
| 593 | input [19:0] DMA21_MaxBurst; |
| 594 | input [19:0] DMA22_MaxBurst; |
| 595 | input [19:0] DMA23_MaxBurst; |
| 596 | input [23:0] Port_DMA_List; |
| 597 | |
| 598 | output ClrMaxBurst; |
| 599 | |
| 600 | // Data Fetsch State Machine |
| 601 | input DRR_PacketDone; |
| 602 | input [15:0] DRR_PacketByteCount; |
| 603 | |
| 604 | output DRR_Arb_Valid; |
| 605 | output [4:0] DRR_NextDMAChannel; |
| 606 | |
| 607 | // Debug Block |
| 608 | output LatchActiveDMA; |
| 609 | output [23:0] ContextActiveList; |
| 610 | |
| 611 | // State Machine |
| 612 | output [3:0] DRR_ArbState; |
| 613 | |
| 614 | /*--------------------------------------------------------------*/ |
| 615 | // Wires & Registers |
| 616 | /*--------------------------------------------------------------*/ |
| 617 | wire dma0_NoDeficit; |
| 618 | wire dma1_NoDeficit; |
| 619 | wire dma2_NoDeficit; |
| 620 | wire dma3_NoDeficit; |
| 621 | wire dma4_NoDeficit; |
| 622 | wire dma5_NoDeficit; |
| 623 | wire dma6_NoDeficit; |
| 624 | wire dma7_NoDeficit; |
| 625 | wire dma8_NoDeficit; |
| 626 | wire dma9_NoDeficit; |
| 627 | wire dma10_NoDeficit; |
| 628 | wire dma11_NoDeficit; |
| 629 | wire dma12_NoDeficit; |
| 630 | wire dma13_NoDeficit; |
| 631 | wire dma14_NoDeficit; |
| 632 | wire dma15_NoDeficit; |
| 633 | wire dma16_NoDeficit; |
| 634 | wire dma17_NoDeficit; |
| 635 | wire dma18_NoDeficit; |
| 636 | wire dma19_NoDeficit; |
| 637 | wire dma20_NoDeficit; |
| 638 | wire dma21_NoDeficit; |
| 639 | wire dma22_NoDeficit; |
| 640 | wire dma23_NoDeficit; |
| 641 | wire addCreditToContext; |
| 642 | wire clrDeficitForEofList; |
| 643 | |
| 644 | /*--------------------------------------------------------------*/ |
| 645 | // Parameters and Defines |
| 646 | /*--------------------------------------------------------------*/ |
| 647 | |
| 648 | /*--------------------------------------------------------------*/ |
| 649 | // Zero In Checks |
| 650 | /*--------------------------------------------------------------*/ |
| 651 | |
| 652 | |
| 653 | /*--------------------------------------------------------------*/ |
| 654 | // Module Instantiations |
| 655 | /*--------------------------------------------------------------*/ |
| 656 | |
| 657 | niu_txc_drr_arbiter niu_txc_drr_arbiter ( |
| 658 | |
| 659 | .SysClk (SysClk), |
| 660 | .Reset_L (Reset_L), |
| 661 | .Txc_Enabled (Txc_Enabled), |
| 662 | .MAC_Enabled (MAC_Enabled), |
| 663 | .FlushEngine (FlushEngine), |
| 664 | |
| 665 | .DMA0_Active (DMA0_Active), |
| 666 | .DMA0_Error (DMA0_Error), |
| 667 | .DMA0_EofList (DMA0_EofList), |
| 668 | .DMA0_CacheReady (DMA0_CacheReady), |
| 669 | .DMA0_Partial (DMA0_Partial), |
| 670 | .DMA0_Reset_Scheduled (DMA0_Reset_Scheduled), |
| 671 | .DMA0_Reset_Done (DMA0_Reset_Done), |
| 672 | .DMA1_Active (DMA1_Active), |
| 673 | .DMA1_Error (DMA1_Error), |
| 674 | .DMA1_EofList (DMA1_EofList), |
| 675 | .DMA1_CacheReady (DMA1_CacheReady), |
| 676 | .DMA1_Partial (DMA1_Partial), |
| 677 | .DMA1_Reset_Scheduled (DMA1_Reset_Scheduled), |
| 678 | .DMA1_Reset_Done (DMA1_Reset_Done), |
| 679 | .DMA2_Active (DMA2_Active), |
| 680 | .DMA2_Error (DMA2_Error), |
| 681 | .DMA2_EofList (DMA2_EofList), |
| 682 | .DMA2_CacheReady (DMA2_CacheReady), |
| 683 | .DMA2_Partial (DMA2_Partial), |
| 684 | .DMA2_Reset_Scheduled (DMA2_Reset_Scheduled), |
| 685 | .DMA2_Reset_Done (DMA2_Reset_Done), |
| 686 | .DMA3_Active (DMA3_Active), |
| 687 | .DMA3_Error (DMA3_Error), |
| 688 | .DMA3_EofList (DMA3_EofList), |
| 689 | .DMA3_CacheReady (DMA3_CacheReady), |
| 690 | .DMA3_Partial (DMA3_Partial), |
| 691 | .DMA3_Reset_Scheduled (DMA3_Reset_Scheduled), |
| 692 | .DMA3_Reset_Done (DMA3_Reset_Done), |
| 693 | .DMA4_Active (DMA4_Active), |
| 694 | .DMA4_Error (DMA4_Error), |
| 695 | .DMA4_EofList (DMA4_EofList), |
| 696 | .DMA4_CacheReady (DMA4_CacheReady), |
| 697 | .DMA4_Partial (DMA4_Partial), |
| 698 | .DMA4_Reset_Scheduled (DMA4_Reset_Scheduled), |
| 699 | .DMA4_Reset_Done (DMA4_Reset_Done), |
| 700 | .DMA5_Active (DMA5_Active), |
| 701 | .DMA5_Error (DMA5_Error), |
| 702 | .DMA5_EofList (DMA5_EofList), |
| 703 | .DMA5_CacheReady (DMA5_CacheReady), |
| 704 | .DMA5_Partial (DMA5_Partial), |
| 705 | .DMA5_Reset_Scheduled (DMA5_Reset_Scheduled), |
| 706 | .DMA5_Reset_Done (DMA5_Reset_Done), |
| 707 | .DMA6_Active (DMA6_Active), |
| 708 | .DMA6_Error (DMA6_Error), |
| 709 | .DMA6_EofList (DMA6_EofList), |
| 710 | .DMA6_CacheReady (DMA6_CacheReady), |
| 711 | .DMA6_Partial (DMA6_Partial), |
| 712 | .DMA6_Reset_Scheduled (DMA6_Reset_Scheduled), |
| 713 | .DMA6_Reset_Done (DMA6_Reset_Done), |
| 714 | .DMA7_Active (DMA7_Active), |
| 715 | .DMA7_Error (DMA7_Error), |
| 716 | .DMA7_EofList (DMA7_EofList), |
| 717 | .DMA7_CacheReady (DMA7_CacheReady), |
| 718 | .DMA7_Partial (DMA7_Partial), |
| 719 | .DMA7_Reset_Scheduled (DMA7_Reset_Scheduled), |
| 720 | .DMA7_Reset_Done (DMA7_Reset_Done), |
| 721 | .DMA8_Active (DMA8_Active), |
| 722 | .DMA8_Error (DMA8_Error), |
| 723 | .DMA8_EofList (DMA8_EofList), |
| 724 | .DMA8_CacheReady (DMA8_CacheReady), |
| 725 | .DMA8_Partial (DMA8_Partial), |
| 726 | .DMA8_Reset_Scheduled (DMA8_Reset_Scheduled), |
| 727 | .DMA8_Reset_Done (DMA8_Reset_Done), |
| 728 | .DMA9_Active (DMA9_Active), |
| 729 | .DMA9_Error (DMA9_Error), |
| 730 | .DMA9_EofList (DMA9_EofList), |
| 731 | .DMA9_CacheReady (DMA9_CacheReady), |
| 732 | .DMA9_Partial (DMA9_Partial), |
| 733 | .DMA9_Reset_Scheduled (DMA9_Reset_Scheduled), |
| 734 | .DMA9_Reset_Done (DMA9_Reset_Done), |
| 735 | .DMA10_Active (DMA10_Active), |
| 736 | .DMA10_Error (DMA10_Error), |
| 737 | .DMA10_EofList (DMA10_EofList), |
| 738 | .DMA10_CacheReady (DMA10_CacheReady), |
| 739 | .DMA10_Partial (DMA10_Partial), |
| 740 | .DMA10_Reset_Scheduled (DMA10_Reset_Scheduled), |
| 741 | .DMA10_Reset_Done (DMA10_Reset_Done), |
| 742 | .DMA11_Active (DMA11_Active), |
| 743 | .DMA11_Error (DMA11_Error), |
| 744 | .DMA11_EofList (DMA11_EofList), |
| 745 | .DMA11_CacheReady (DMA11_CacheReady), |
| 746 | .DMA11_Partial (DMA11_Partial), |
| 747 | .DMA11_Reset_Scheduled (DMA11_Reset_Scheduled), |
| 748 | .DMA11_Reset_Done (DMA11_Reset_Done), |
| 749 | .DMA12_Active (DMA12_Active), |
| 750 | .DMA12_Error (DMA12_Error), |
| 751 | .DMA12_EofList (DMA12_EofList), |
| 752 | .DMA12_CacheReady (DMA12_CacheReady), |
| 753 | .DMA12_Partial (DMA12_Partial), |
| 754 | .DMA12_Reset_Scheduled (DMA12_Reset_Scheduled), |
| 755 | .DMA12_Reset_Done (DMA12_Reset_Done), |
| 756 | .DMA13_Active (DMA13_Active), |
| 757 | .DMA13_Error (DMA13_Error), |
| 758 | .DMA13_EofList (DMA13_EofList), |
| 759 | .DMA13_CacheReady (DMA13_CacheReady), |
| 760 | .DMA13_Partial (DMA13_Partial), |
| 761 | .DMA13_Reset_Scheduled (DMA13_Reset_Scheduled), |
| 762 | .DMA13_Reset_Done (DMA13_Reset_Done), |
| 763 | .DMA14_Active (DMA14_Active), |
| 764 | .DMA14_Error (DMA14_Error), |
| 765 | .DMA14_EofList (DMA14_EofList), |
| 766 | .DMA14_CacheReady (DMA14_CacheReady), |
| 767 | .DMA14_Partial (DMA14_Partial), |
| 768 | .DMA14_Reset_Scheduled (DMA14_Reset_Scheduled), |
| 769 | .DMA14_Reset_Done (DMA14_Reset_Done), |
| 770 | .DMA15_Active (DMA15_Active), |
| 771 | .DMA15_Error (DMA15_Error), |
| 772 | .DMA15_EofList (DMA15_EofList), |
| 773 | .DMA15_CacheReady (DMA15_CacheReady), |
| 774 | .DMA15_Partial (DMA15_Partial), |
| 775 | .DMA15_Reset_Scheduled (DMA15_Reset_Scheduled), |
| 776 | .DMA15_Reset_Done (DMA15_Reset_Done), |
| 777 | .DMA16_Active (DMA16_Active), |
| 778 | .DMA16_Error (DMA16_Error), |
| 779 | .DMA16_EofList (DMA16_EofList), |
| 780 | .DMA16_CacheReady (DMA16_CacheReady), |
| 781 | .DMA16_Partial (DMA16_Partial), |
| 782 | .DMA16_Reset_Scheduled (DMA16_Reset_Scheduled), |
| 783 | .DMA16_Reset_Done (DMA16_Reset_Done), |
| 784 | .DMA17_Active (DMA17_Active), |
| 785 | .DMA17_Error (DMA17_Error), |
| 786 | .DMA17_EofList (DMA17_EofList), |
| 787 | .DMA17_CacheReady (DMA17_CacheReady), |
| 788 | .DMA17_Partial (DMA17_Partial), |
| 789 | .DMA17_Reset_Scheduled (DMA17_Reset_Scheduled), |
| 790 | .DMA17_Reset_Done (DMA17_Reset_Done), |
| 791 | .DMA18_Active (DMA18_Active), |
| 792 | .DMA18_Error (DMA18_Error), |
| 793 | .DMA18_EofList (DMA18_EofList), |
| 794 | .DMA18_CacheReady (DMA18_CacheReady), |
| 795 | .DMA18_Partial (DMA18_Partial), |
| 796 | .DMA18_Reset_Scheduled (DMA18_Reset_Scheduled), |
| 797 | .DMA18_Reset_Done (DMA18_Reset_Done), |
| 798 | .DMA19_Active (DMA19_Active), |
| 799 | .DMA19_Error (DMA19_Error), |
| 800 | .DMA19_EofList (DMA19_EofList), |
| 801 | .DMA19_CacheReady (DMA19_CacheReady), |
| 802 | .DMA19_Partial (DMA19_Partial), |
| 803 | .DMA19_Reset_Scheduled (DMA19_Reset_Scheduled), |
| 804 | .DMA19_Reset_Done (DMA19_Reset_Done), |
| 805 | .DMA20_Active (DMA20_Active), |
| 806 | .DMA20_Error (DMA20_Error), |
| 807 | .DMA20_EofList (DMA20_EofList), |
| 808 | .DMA20_CacheReady (DMA20_CacheReady), |
| 809 | .DMA20_Partial (DMA20_Partial), |
| 810 | .DMA20_Reset_Scheduled (DMA20_Reset_Scheduled), |
| 811 | .DMA20_Reset_Done (DMA20_Reset_Done), |
| 812 | .DMA21_Active (DMA21_Active), |
| 813 | .DMA21_Error (DMA21_Error), |
| 814 | .DMA21_EofList (DMA21_EofList), |
| 815 | .DMA21_CacheReady (DMA21_CacheReady), |
| 816 | .DMA21_Partial (DMA21_Partial), |
| 817 | .DMA21_Reset_Scheduled (DMA21_Reset_Scheduled), |
| 818 | .DMA21_Reset_Done (DMA21_Reset_Done), |
| 819 | .DMA22_Active (DMA22_Active), |
| 820 | .DMA22_Error (DMA22_Error), |
| 821 | .DMA22_EofList (DMA22_EofList), |
| 822 | .DMA22_CacheReady (DMA22_CacheReady), |
| 823 | .DMA22_Partial (DMA22_Partial), |
| 824 | .DMA22_Reset_Scheduled (DMA22_Reset_Scheduled), |
| 825 | .DMA22_Reset_Done (DMA22_Reset_Done), |
| 826 | .DMA23_Active (DMA23_Active), |
| 827 | .DMA23_Error (DMA23_Error), |
| 828 | .DMA23_EofList (DMA23_EofList), |
| 829 | .DMA23_CacheReady (DMA23_CacheReady), |
| 830 | .DMA23_Partial (DMA23_Partial), |
| 831 | .DMA23_Reset_Scheduled (DMA23_Reset_Scheduled), |
| 832 | .DMA23_Reset_Done (DMA23_Reset_Done), |
| 833 | |
| 834 | .DMA0_NewMaxBurst (DMA0_NewMaxBurst), |
| 835 | .DMA1_NewMaxBurst (DMA1_NewMaxBurst), |
| 836 | .DMA2_NewMaxBurst (DMA2_NewMaxBurst), |
| 837 | .DMA3_NewMaxBurst (DMA3_NewMaxBurst), |
| 838 | .DMA4_NewMaxBurst (DMA4_NewMaxBurst), |
| 839 | .DMA5_NewMaxBurst (DMA5_NewMaxBurst), |
| 840 | .DMA6_NewMaxBurst (DMA6_NewMaxBurst), |
| 841 | .DMA7_NewMaxBurst (DMA7_NewMaxBurst), |
| 842 | .DMA8_NewMaxBurst (DMA8_NewMaxBurst), |
| 843 | .DMA9_NewMaxBurst (DMA9_NewMaxBurst), |
| 844 | .DMA10_NewMaxBurst (DMA10_NewMaxBurst), |
| 845 | .DMA11_NewMaxBurst (DMA11_NewMaxBurst), |
| 846 | .DMA12_NewMaxBurst (DMA12_NewMaxBurst), |
| 847 | .DMA13_NewMaxBurst (DMA13_NewMaxBurst), |
| 848 | .DMA14_NewMaxBurst (DMA14_NewMaxBurst), |
| 849 | .DMA15_NewMaxBurst (DMA15_NewMaxBurst), |
| 850 | .DMA16_NewMaxBurst (DMA16_NewMaxBurst), |
| 851 | .DMA17_NewMaxBurst (DMA17_NewMaxBurst), |
| 852 | .DMA18_NewMaxBurst (DMA18_NewMaxBurst), |
| 853 | .DMA19_NewMaxBurst (DMA19_NewMaxBurst), |
| 854 | .DMA20_NewMaxBurst (DMA20_NewMaxBurst), |
| 855 | .DMA21_NewMaxBurst (DMA21_NewMaxBurst), |
| 856 | .DMA22_NewMaxBurst (DMA22_NewMaxBurst), |
| 857 | .DMA23_NewMaxBurst (DMA23_NewMaxBurst), |
| 858 | .Port_DMA_List (Port_DMA_List), |
| 859 | .ClrMaxBurst (ClrMaxBurst), |
| 860 | |
| 861 | .DMA0_NoDeficit (dma0_NoDeficit), |
| 862 | .DMA1_NoDeficit (dma1_NoDeficit), |
| 863 | .DMA2_NoDeficit (dma2_NoDeficit), |
| 864 | .DMA3_NoDeficit (dma3_NoDeficit), |
| 865 | .DMA4_NoDeficit (dma4_NoDeficit), |
| 866 | .DMA5_NoDeficit (dma5_NoDeficit), |
| 867 | .DMA6_NoDeficit (dma6_NoDeficit), |
| 868 | .DMA7_NoDeficit (dma7_NoDeficit), |
| 869 | .DMA8_NoDeficit (dma8_NoDeficit), |
| 870 | .DMA9_NoDeficit (dma9_NoDeficit), |
| 871 | .DMA10_NoDeficit (dma10_NoDeficit), |
| 872 | .DMA11_NoDeficit (dma11_NoDeficit), |
| 873 | .DMA12_NoDeficit (dma12_NoDeficit), |
| 874 | .DMA13_NoDeficit (dma13_NoDeficit), |
| 875 | .DMA14_NoDeficit (dma14_NoDeficit), |
| 876 | .DMA15_NoDeficit (dma15_NoDeficit), |
| 877 | .DMA16_NoDeficit (dma16_NoDeficit), |
| 878 | .DMA17_NoDeficit (dma17_NoDeficit), |
| 879 | .DMA18_NoDeficit (dma18_NoDeficit), |
| 880 | .DMA19_NoDeficit (dma19_NoDeficit), |
| 881 | .DMA20_NoDeficit (dma20_NoDeficit), |
| 882 | .DMA21_NoDeficit (dma21_NoDeficit), |
| 883 | .DMA22_NoDeficit (dma22_NoDeficit), |
| 884 | .DMA23_NoDeficit (dma23_NoDeficit), |
| 885 | .AddCreditToContext (addCreditToContext), |
| 886 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 887 | .ContextActiveList (ContextActiveList), |
| 888 | |
| 889 | .DRR_PacketDone (DRR_PacketDone), |
| 890 | .DRR_Arb_Valid (DRR_Arb_Valid), |
| 891 | .DRR_NextDMAChannel (DRR_NextDMAChannel), |
| 892 | |
| 893 | .LatchActiveDMA (LatchActiveDMA), |
| 894 | |
| 895 | .DRR_ArbState (DRR_ArbState) |
| 896 | ); |
| 897 | |
| 898 | |
| 899 | niu_txc_drr_context niu_txc_drr_context0 ( |
| 900 | .SysClk (SysClk), |
| 901 | .Reset_L (Reset_L), |
| 902 | .FlushEngine (FlushEngine), |
| 903 | .ClrMaxBurst (ClrMaxBurst), |
| 904 | .NewMaxBurst (DMA0_NewMaxBurst), |
| 905 | .MaxBurst (DMA0_MaxBurst), |
| 906 | .PacketDone (DRR_PacketDone), |
| 907 | .PacketByteCount (DRR_PacketByteCount), |
| 908 | .DMA_Reset_Done (DMA0_Reset_Done), |
| 909 | .DMA_EofList (DMA0_EofList), |
| 910 | .AddCreditToContext (addCreditToContext), |
| 911 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 912 | .ContextActiveList (ContextActiveList[0]), |
| 913 | .NoDeficit (dma0_NoDeficit), |
| 914 | .NextDMAChannel (DRR_NextDMAChannel), |
| 915 | .ContextNumber (`DMA_CHANNEL_ZERO) |
| 916 | ); |
| 917 | |
| 918 | niu_txc_drr_context niu_txc_drr_context1 ( |
| 919 | .SysClk (SysClk), |
| 920 | .Reset_L (Reset_L), |
| 921 | .FlushEngine (FlushEngine), |
| 922 | .ClrMaxBurst (ClrMaxBurst), |
| 923 | .NewMaxBurst (DMA1_NewMaxBurst), |
| 924 | .MaxBurst (DMA1_MaxBurst), |
| 925 | .PacketDone (DRR_PacketDone), |
| 926 | .PacketByteCount (DRR_PacketByteCount), |
| 927 | .DMA_Reset_Done (DMA1_Reset_Done), |
| 928 | .DMA_EofList (DMA1_EofList), |
| 929 | .AddCreditToContext (addCreditToContext), |
| 930 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 931 | .ContextActiveList (ContextActiveList[1]), |
| 932 | .NoDeficit (dma1_NoDeficit), |
| 933 | .NextDMAChannel (DRR_NextDMAChannel), |
| 934 | .ContextNumber (`DMA_CHANNEL_ONE) |
| 935 | ); |
| 936 | |
| 937 | niu_txc_drr_context niu_txc_drr_context2 ( |
| 938 | .SysClk (SysClk), |
| 939 | .Reset_L (Reset_L), |
| 940 | .FlushEngine (FlushEngine), |
| 941 | .ClrMaxBurst (ClrMaxBurst), |
| 942 | .NewMaxBurst (DMA2_NewMaxBurst), |
| 943 | .MaxBurst (DMA2_MaxBurst), |
| 944 | .PacketDone (DRR_PacketDone), |
| 945 | .PacketByteCount (DRR_PacketByteCount), |
| 946 | .DMA_Reset_Done (DMA2_Reset_Done), |
| 947 | .DMA_EofList (DMA2_EofList), |
| 948 | .AddCreditToContext (addCreditToContext), |
| 949 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 950 | .ContextActiveList (ContextActiveList[2]), |
| 951 | .NoDeficit (dma2_NoDeficit), |
| 952 | .NextDMAChannel (DRR_NextDMAChannel), |
| 953 | .ContextNumber (`DMA_CHANNEL_TWO) |
| 954 | ); |
| 955 | |
| 956 | niu_txc_drr_context niu_txc_drr_context3 ( |
| 957 | .SysClk (SysClk), |
| 958 | .Reset_L (Reset_L), |
| 959 | .FlushEngine (FlushEngine), |
| 960 | .ClrMaxBurst (ClrMaxBurst), |
| 961 | .NewMaxBurst (DMA3_NewMaxBurst), |
| 962 | .MaxBurst (DMA3_MaxBurst), |
| 963 | .PacketDone (DRR_PacketDone), |
| 964 | .PacketByteCount (DRR_PacketByteCount), |
| 965 | .DMA_Reset_Done (DMA3_Reset_Done), |
| 966 | .DMA_EofList (DMA3_EofList), |
| 967 | .AddCreditToContext (addCreditToContext), |
| 968 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 969 | .ContextActiveList (ContextActiveList[3]), |
| 970 | .NoDeficit (dma3_NoDeficit), |
| 971 | .NextDMAChannel (DRR_NextDMAChannel), |
| 972 | .ContextNumber (`DMA_CHANNEL_THREE) |
| 973 | ); |
| 974 | |
| 975 | niu_txc_drr_context niu_txc_drr_context4 ( |
| 976 | .SysClk (SysClk), |
| 977 | .Reset_L (Reset_L), |
| 978 | .FlushEngine (FlushEngine), |
| 979 | .ClrMaxBurst (ClrMaxBurst), |
| 980 | .NewMaxBurst (DMA4_NewMaxBurst), |
| 981 | .MaxBurst (DMA4_MaxBurst), |
| 982 | .PacketDone (DRR_PacketDone), |
| 983 | .PacketByteCount (DRR_PacketByteCount), |
| 984 | .DMA_Reset_Done (DMA4_Reset_Done), |
| 985 | .DMA_EofList (DMA4_EofList), |
| 986 | .AddCreditToContext (addCreditToContext), |
| 987 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 988 | .ContextActiveList (ContextActiveList[4]), |
| 989 | .NoDeficit (dma4_NoDeficit), |
| 990 | .NextDMAChannel (DRR_NextDMAChannel), |
| 991 | .ContextNumber (`DMA_CHANNEL_FOUR) |
| 992 | ); |
| 993 | |
| 994 | niu_txc_drr_context niu_txc_drr_context5 ( |
| 995 | .SysClk (SysClk), |
| 996 | .Reset_L (Reset_L), |
| 997 | .FlushEngine (FlushEngine), |
| 998 | .ClrMaxBurst (ClrMaxBurst), |
| 999 | .NewMaxBurst (DMA5_NewMaxBurst), |
| 1000 | .MaxBurst (DMA5_MaxBurst), |
| 1001 | .PacketDone (DRR_PacketDone), |
| 1002 | .PacketByteCount (DRR_PacketByteCount), |
| 1003 | .DMA_Reset_Done (DMA5_Reset_Done), |
| 1004 | .DMA_EofList (DMA5_EofList), |
| 1005 | .AddCreditToContext (addCreditToContext), |
| 1006 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 1007 | .ContextActiveList (ContextActiveList[5]), |
| 1008 | .NoDeficit (dma5_NoDeficit), |
| 1009 | .NextDMAChannel (DRR_NextDMAChannel), |
| 1010 | .ContextNumber (`DMA_CHANNEL_FIVE) |
| 1011 | ); |
| 1012 | |
| 1013 | niu_txc_drr_context niu_txc_drr_context6 ( |
| 1014 | .SysClk (SysClk), |
| 1015 | .Reset_L (Reset_L), |
| 1016 | .FlushEngine (FlushEngine), |
| 1017 | .ClrMaxBurst (ClrMaxBurst), |
| 1018 | .NewMaxBurst (DMA6_NewMaxBurst), |
| 1019 | .MaxBurst (DMA6_MaxBurst), |
| 1020 | .PacketDone (DRR_PacketDone), |
| 1021 | .PacketByteCount (DRR_PacketByteCount), |
| 1022 | .DMA_Reset_Done (DMA6_Reset_Done), |
| 1023 | .DMA_EofList (DMA6_EofList), |
| 1024 | .AddCreditToContext (addCreditToContext), |
| 1025 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 1026 | .ContextActiveList (ContextActiveList[6]), |
| 1027 | .NoDeficit (dma6_NoDeficit), |
| 1028 | .NextDMAChannel (DRR_NextDMAChannel), |
| 1029 | .ContextNumber (`DMA_CHANNEL_SIX) |
| 1030 | ); |
| 1031 | |
| 1032 | niu_txc_drr_context niu_txc_drr_context7 ( |
| 1033 | .SysClk (SysClk), |
| 1034 | .Reset_L (Reset_L), |
| 1035 | .FlushEngine (FlushEngine), |
| 1036 | .ClrMaxBurst (ClrMaxBurst), |
| 1037 | .NewMaxBurst (DMA7_NewMaxBurst), |
| 1038 | .MaxBurst (DMA7_MaxBurst), |
| 1039 | .PacketDone (DRR_PacketDone), |
| 1040 | .PacketByteCount (DRR_PacketByteCount), |
| 1041 | .DMA_Reset_Done (DMA7_Reset_Done), |
| 1042 | .DMA_EofList (DMA7_EofList), |
| 1043 | .AddCreditToContext (addCreditToContext), |
| 1044 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 1045 | .ContextActiveList (ContextActiveList[7]), |
| 1046 | .NoDeficit (dma7_NoDeficit), |
| 1047 | .NextDMAChannel (DRR_NextDMAChannel), |
| 1048 | .ContextNumber (`DMA_CHANNEL_SEVEN) |
| 1049 | ); |
| 1050 | |
| 1051 | niu_txc_drr_context niu_txc_drr_context8 ( |
| 1052 | .SysClk (SysClk), |
| 1053 | .Reset_L (Reset_L), |
| 1054 | .FlushEngine (FlushEngine), |
| 1055 | .ClrMaxBurst (ClrMaxBurst), |
| 1056 | .NewMaxBurst (DMA8_NewMaxBurst), |
| 1057 | .MaxBurst (DMA8_MaxBurst), |
| 1058 | .PacketDone (DRR_PacketDone), |
| 1059 | .PacketByteCount (DRR_PacketByteCount), |
| 1060 | .DMA_Reset_Done (DMA8_Reset_Done), |
| 1061 | .DMA_EofList (DMA8_EofList), |
| 1062 | .AddCreditToContext (addCreditToContext), |
| 1063 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 1064 | .ContextActiveList (ContextActiveList[8]), |
| 1065 | .NoDeficit (dma8_NoDeficit), |
| 1066 | .NextDMAChannel (DRR_NextDMAChannel), |
| 1067 | .ContextNumber (`DMA_CHANNEL_EIGHT) |
| 1068 | ); |
| 1069 | |
| 1070 | niu_txc_drr_context niu_txc_drr_context9 ( |
| 1071 | .SysClk (SysClk), |
| 1072 | .Reset_L (Reset_L), |
| 1073 | .FlushEngine (FlushEngine), |
| 1074 | .ClrMaxBurst (ClrMaxBurst), |
| 1075 | .NewMaxBurst (DMA9_NewMaxBurst), |
| 1076 | .MaxBurst (DMA9_MaxBurst), |
| 1077 | .PacketDone (DRR_PacketDone), |
| 1078 | .PacketByteCount (DRR_PacketByteCount), |
| 1079 | .DMA_Reset_Done (DMA9_Reset_Done), |
| 1080 | .DMA_EofList (DMA9_EofList), |
| 1081 | .AddCreditToContext (addCreditToContext), |
| 1082 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 1083 | .ContextActiveList (ContextActiveList[9]), |
| 1084 | .NoDeficit (dma9_NoDeficit), |
| 1085 | .NextDMAChannel (DRR_NextDMAChannel), |
| 1086 | .ContextNumber (`DMA_CHANNEL_NINE) |
| 1087 | ); |
| 1088 | |
| 1089 | |
| 1090 | |
| 1091 | |
| 1092 | niu_txc_drr_context niu_txc_drr_context10 ( |
| 1093 | .SysClk (SysClk), |
| 1094 | .Reset_L (Reset_L), |
| 1095 | .FlushEngine (FlushEngine), |
| 1096 | .ClrMaxBurst (ClrMaxBurst), |
| 1097 | .NewMaxBurst (DMA10_NewMaxBurst), |
| 1098 | .MaxBurst (DMA10_MaxBurst), |
| 1099 | .PacketDone (DRR_PacketDone), |
| 1100 | .PacketByteCount (DRR_PacketByteCount), |
| 1101 | .DMA_Reset_Done (DMA10_Reset_Done), |
| 1102 | .DMA_EofList (DMA10_EofList), |
| 1103 | .AddCreditToContext (addCreditToContext), |
| 1104 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 1105 | .ContextActiveList (ContextActiveList[10]), |
| 1106 | .NoDeficit (dma10_NoDeficit), |
| 1107 | .NextDMAChannel (DRR_NextDMAChannel), |
| 1108 | .ContextNumber (`DMA_CHANNEL_TEN) |
| 1109 | ); |
| 1110 | |
| 1111 | niu_txc_drr_context niu_txc_drr_context11 ( |
| 1112 | .SysClk (SysClk), |
| 1113 | .Reset_L (Reset_L), |
| 1114 | .FlushEngine (FlushEngine), |
| 1115 | .ClrMaxBurst (ClrMaxBurst), |
| 1116 | .NewMaxBurst (DMA11_NewMaxBurst), |
| 1117 | .MaxBurst (DMA11_MaxBurst), |
| 1118 | .PacketDone (DRR_PacketDone), |
| 1119 | .PacketByteCount (DRR_PacketByteCount), |
| 1120 | .DMA_Reset_Done (DMA11_Reset_Done), |
| 1121 | .DMA_EofList (DMA11_EofList), |
| 1122 | .AddCreditToContext (addCreditToContext), |
| 1123 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 1124 | .ContextActiveList (ContextActiveList[11]), |
| 1125 | .NoDeficit (dma11_NoDeficit), |
| 1126 | .NextDMAChannel (DRR_NextDMAChannel), |
| 1127 | .ContextNumber (`DMA_CHANNEL_ELEVEN) |
| 1128 | ); |
| 1129 | |
| 1130 | niu_txc_drr_context niu_txc_drr_context12 ( |
| 1131 | .SysClk (SysClk), |
| 1132 | .Reset_L (Reset_L), |
| 1133 | .FlushEngine (FlushEngine), |
| 1134 | .ClrMaxBurst (ClrMaxBurst), |
| 1135 | .NewMaxBurst (DMA12_NewMaxBurst), |
| 1136 | .MaxBurst (DMA12_MaxBurst), |
| 1137 | .PacketDone (DRR_PacketDone), |
| 1138 | .PacketByteCount (DRR_PacketByteCount), |
| 1139 | .DMA_Reset_Done (DMA12_Reset_Done), |
| 1140 | .DMA_EofList (DMA12_EofList), |
| 1141 | .AddCreditToContext (addCreditToContext), |
| 1142 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 1143 | .ContextActiveList (ContextActiveList[12]), |
| 1144 | .NoDeficit (dma12_NoDeficit), |
| 1145 | .NextDMAChannel (DRR_NextDMAChannel), |
| 1146 | .ContextNumber (`DMA_CHANNEL_TWELVE) |
| 1147 | ); |
| 1148 | |
| 1149 | niu_txc_drr_context niu_txc_drr_context13 ( |
| 1150 | .SysClk (SysClk), |
| 1151 | .Reset_L (Reset_L), |
| 1152 | .FlushEngine (FlushEngine), |
| 1153 | .ClrMaxBurst (ClrMaxBurst), |
| 1154 | .NewMaxBurst (DMA13_NewMaxBurst), |
| 1155 | .MaxBurst (DMA13_MaxBurst), |
| 1156 | .PacketDone (DRR_PacketDone), |
| 1157 | .PacketByteCount (DRR_PacketByteCount), |
| 1158 | .DMA_Reset_Done (DMA13_Reset_Done), |
| 1159 | .DMA_EofList (DMA13_EofList), |
| 1160 | .AddCreditToContext (addCreditToContext), |
| 1161 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 1162 | .ContextActiveList (ContextActiveList[13]), |
| 1163 | .NoDeficit (dma13_NoDeficit), |
| 1164 | .NextDMAChannel (DRR_NextDMAChannel), |
| 1165 | .ContextNumber (`DMA_CHANNEL_THIRTEEN) |
| 1166 | ); |
| 1167 | |
| 1168 | niu_txc_drr_context niu_txc_drr_context14 ( |
| 1169 | .SysClk (SysClk), |
| 1170 | .Reset_L (Reset_L), |
| 1171 | .FlushEngine (FlushEngine), |
| 1172 | .ClrMaxBurst (ClrMaxBurst), |
| 1173 | .NewMaxBurst (DMA14_NewMaxBurst), |
| 1174 | .MaxBurst (DMA14_MaxBurst), |
| 1175 | .PacketDone (DRR_PacketDone), |
| 1176 | .PacketByteCount (DRR_PacketByteCount), |
| 1177 | .DMA_Reset_Done (DMA14_Reset_Done), |
| 1178 | .DMA_EofList (DMA14_EofList), |
| 1179 | .AddCreditToContext (addCreditToContext), |
| 1180 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 1181 | .ContextActiveList (ContextActiveList[14]), |
| 1182 | .NoDeficit (dma14_NoDeficit), |
| 1183 | .NextDMAChannel (DRR_NextDMAChannel), |
| 1184 | .ContextNumber (`DMA_CHANNEL_FOURTEEN) |
| 1185 | ); |
| 1186 | |
| 1187 | niu_txc_drr_context niu_txc_drr_context15 ( |
| 1188 | .SysClk (SysClk), |
| 1189 | .Reset_L (Reset_L), |
| 1190 | .FlushEngine (FlushEngine), |
| 1191 | .ClrMaxBurst (ClrMaxBurst), |
| 1192 | .NewMaxBurst (DMA15_NewMaxBurst), |
| 1193 | .MaxBurst (DMA15_MaxBurst), |
| 1194 | .PacketDone (DRR_PacketDone), |
| 1195 | .PacketByteCount (DRR_PacketByteCount), |
| 1196 | .DMA_Reset_Done (DMA15_Reset_Done), |
| 1197 | .DMA_EofList (DMA15_EofList), |
| 1198 | .AddCreditToContext (addCreditToContext), |
| 1199 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 1200 | .ContextActiveList (ContextActiveList[15]), |
| 1201 | .NoDeficit (dma15_NoDeficit), |
| 1202 | .NextDMAChannel (DRR_NextDMAChannel), |
| 1203 | .ContextNumber (`DMA_CHANNEL_FIFTEEN) |
| 1204 | ); |
| 1205 | |
| 1206 | niu_txc_drr_context niu_txc_drr_context16 ( |
| 1207 | .SysClk (SysClk), |
| 1208 | .Reset_L (Reset_L), |
| 1209 | .FlushEngine (FlushEngine), |
| 1210 | .ClrMaxBurst (ClrMaxBurst), |
| 1211 | .NewMaxBurst (DMA16_NewMaxBurst), |
| 1212 | .MaxBurst (DMA16_MaxBurst), |
| 1213 | .PacketDone (DRR_PacketDone), |
| 1214 | .PacketByteCount (DRR_PacketByteCount), |
| 1215 | .DMA_Reset_Done (DMA16_Reset_Done), |
| 1216 | .DMA_EofList (DMA16_EofList), |
| 1217 | .AddCreditToContext (addCreditToContext), |
| 1218 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 1219 | .ContextActiveList (ContextActiveList[16]), |
| 1220 | .NoDeficit (dma16_NoDeficit), |
| 1221 | .NextDMAChannel (DRR_NextDMAChannel), |
| 1222 | .ContextNumber (`DMA_CHANNEL_SIXTEEN) |
| 1223 | ); |
| 1224 | |
| 1225 | niu_txc_drr_context niu_txc_drr_context17 ( |
| 1226 | .SysClk (SysClk), |
| 1227 | .Reset_L (Reset_L), |
| 1228 | .FlushEngine (FlushEngine), |
| 1229 | .ClrMaxBurst (ClrMaxBurst), |
| 1230 | .NewMaxBurst (DMA17_NewMaxBurst), |
| 1231 | .MaxBurst (DMA17_MaxBurst), |
| 1232 | .PacketDone (DRR_PacketDone), |
| 1233 | .PacketByteCount (DRR_PacketByteCount), |
| 1234 | .DMA_Reset_Done (DMA17_Reset_Done), |
| 1235 | .DMA_EofList (DMA17_EofList), |
| 1236 | .AddCreditToContext (addCreditToContext), |
| 1237 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 1238 | .ContextActiveList (ContextActiveList[17]), |
| 1239 | .NoDeficit (dma17_NoDeficit), |
| 1240 | .NextDMAChannel (DRR_NextDMAChannel), |
| 1241 | .ContextNumber (`DMA_CHANNEL_SEVENTEEN) |
| 1242 | ); |
| 1243 | |
| 1244 | niu_txc_drr_context niu_txc_drr_context18 ( |
| 1245 | .SysClk (SysClk), |
| 1246 | .Reset_L (Reset_L), |
| 1247 | .FlushEngine (FlushEngine), |
| 1248 | .ClrMaxBurst (ClrMaxBurst), |
| 1249 | .NewMaxBurst (DMA18_NewMaxBurst), |
| 1250 | .MaxBurst (DMA18_MaxBurst), |
| 1251 | .PacketDone (DRR_PacketDone), |
| 1252 | .PacketByteCount (DRR_PacketByteCount), |
| 1253 | .DMA_Reset_Done (DMA18_Reset_Done), |
| 1254 | .DMA_EofList (DMA18_EofList), |
| 1255 | .AddCreditToContext (addCreditToContext), |
| 1256 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 1257 | .ContextActiveList (ContextActiveList[18]), |
| 1258 | .NoDeficit (dma18_NoDeficit), |
| 1259 | .NextDMAChannel (DRR_NextDMAChannel), |
| 1260 | .ContextNumber (`DMA_CHANNEL_EIGHTEEN) |
| 1261 | ); |
| 1262 | |
| 1263 | niu_txc_drr_context niu_txc_drr_context19 ( |
| 1264 | .SysClk (SysClk), |
| 1265 | .Reset_L (Reset_L), |
| 1266 | .FlushEngine (FlushEngine), |
| 1267 | .ClrMaxBurst (ClrMaxBurst), |
| 1268 | .NewMaxBurst (DMA19_NewMaxBurst), |
| 1269 | .MaxBurst (DMA19_MaxBurst), |
| 1270 | .PacketDone (DRR_PacketDone), |
| 1271 | .PacketByteCount (DRR_PacketByteCount), |
| 1272 | .DMA_Reset_Done (DMA19_Reset_Done), |
| 1273 | .DMA_EofList (DMA19_EofList), |
| 1274 | .AddCreditToContext (addCreditToContext), |
| 1275 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 1276 | .ContextActiveList (ContextActiveList[19]), |
| 1277 | .NoDeficit (dma19_NoDeficit), |
| 1278 | .NextDMAChannel (DRR_NextDMAChannel), |
| 1279 | .ContextNumber (`DMA_CHANNEL_NINETEEN) |
| 1280 | ); |
| 1281 | |
| 1282 | niu_txc_drr_context niu_txc_drr_context20 ( |
| 1283 | .SysClk (SysClk), |
| 1284 | .Reset_L (Reset_L), |
| 1285 | .FlushEngine (FlushEngine), |
| 1286 | .ClrMaxBurst (ClrMaxBurst), |
| 1287 | .NewMaxBurst (DMA20_NewMaxBurst), |
| 1288 | .MaxBurst (DMA20_MaxBurst), |
| 1289 | .PacketDone (DRR_PacketDone), |
| 1290 | .PacketByteCount (DRR_PacketByteCount), |
| 1291 | .DMA_Reset_Done (DMA20_Reset_Done), |
| 1292 | .DMA_EofList (DMA20_EofList), |
| 1293 | .AddCreditToContext (addCreditToContext), |
| 1294 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 1295 | .ContextActiveList (ContextActiveList[20]), |
| 1296 | .NoDeficit (dma20_NoDeficit), |
| 1297 | .NextDMAChannel (DRR_NextDMAChannel), |
| 1298 | .ContextNumber (`DMA_CHANNEL_TWENTY) |
| 1299 | ); |
| 1300 | |
| 1301 | niu_txc_drr_context niu_txc_drr_context21 ( |
| 1302 | .SysClk (SysClk), |
| 1303 | .Reset_L (Reset_L), |
| 1304 | .FlushEngine (FlushEngine), |
| 1305 | .ClrMaxBurst (ClrMaxBurst), |
| 1306 | .NewMaxBurst (DMA21_NewMaxBurst), |
| 1307 | .MaxBurst (DMA21_MaxBurst), |
| 1308 | .PacketDone (DRR_PacketDone), |
| 1309 | .PacketByteCount (DRR_PacketByteCount), |
| 1310 | .DMA_Reset_Done (DMA21_Reset_Done), |
| 1311 | .DMA_EofList (DMA21_EofList), |
| 1312 | .AddCreditToContext (addCreditToContext), |
| 1313 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 1314 | .ContextActiveList (ContextActiveList[21]), |
| 1315 | .NoDeficit (dma21_NoDeficit), |
| 1316 | .NextDMAChannel (DRR_NextDMAChannel), |
| 1317 | .ContextNumber (`DMA_CHANNEL_TWENTYONE) |
| 1318 | ); |
| 1319 | |
| 1320 | niu_txc_drr_context niu_txc_drr_context22 ( |
| 1321 | .SysClk (SysClk), |
| 1322 | .Reset_L (Reset_L), |
| 1323 | .FlushEngine (FlushEngine), |
| 1324 | .ClrMaxBurst (ClrMaxBurst), |
| 1325 | .NewMaxBurst (DMA22_NewMaxBurst), |
| 1326 | .MaxBurst (DMA22_MaxBurst), |
| 1327 | .PacketDone (DRR_PacketDone), |
| 1328 | .PacketByteCount (DRR_PacketByteCount), |
| 1329 | .DMA_Reset_Done (DMA22_Reset_Done), |
| 1330 | .DMA_EofList (DMA22_EofList), |
| 1331 | .AddCreditToContext (addCreditToContext), |
| 1332 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 1333 | .ContextActiveList (ContextActiveList[22]), |
| 1334 | .NoDeficit (dma22_NoDeficit), |
| 1335 | .NextDMAChannel (DRR_NextDMAChannel), |
| 1336 | .ContextNumber (`DMA_CHANNEL_TWENTYTWO) |
| 1337 | ); |
| 1338 | |
| 1339 | niu_txc_drr_context niu_txc_drr_context23 ( |
| 1340 | .SysClk (SysClk), |
| 1341 | .Reset_L (Reset_L), |
| 1342 | .FlushEngine (FlushEngine), |
| 1343 | .ClrMaxBurst (ClrMaxBurst), |
| 1344 | .NewMaxBurst (DMA23_NewMaxBurst), |
| 1345 | .MaxBurst (DMA23_MaxBurst), |
| 1346 | .PacketDone (DRR_PacketDone), |
| 1347 | .PacketByteCount (DRR_PacketByteCount), |
| 1348 | .DMA_Reset_Done (DMA23_Reset_Done), |
| 1349 | .DMA_EofList (DMA23_EofList), |
| 1350 | .AddCreditToContext (addCreditToContext), |
| 1351 | .ClrDeficitForEofList (clrDeficitForEofList), |
| 1352 | .ContextActiveList (ContextActiveList[23]), |
| 1353 | .NoDeficit (dma23_NoDeficit), |
| 1354 | .NextDMAChannel (DRR_NextDMAChannel), |
| 1355 | .ContextNumber (`DMA_CHANNEL_TWENTYTHREE) |
| 1356 | ); |
| 1357 | |
| 1358 | endmodule |