| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_txc_portRegisters.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
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| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /********************************************************************* |
| 36 | * |
| 37 | * niu_txc_portRegisters.v |
| 38 | * |
| 39 | * NIU Transmit Controller Deficit Round Robin Engine |
| 40 | * |
| 41 | * Orignal Author(s): Rahoul Puri |
| 42 | * Modifier(s): |
| 43 | * Project(s): Neptune |
| 44 | * |
| 45 | * Copyright (c) 2004 Sun Microsystems, Inc. |
| 46 | * |
| 47 | * All Rights Reserved. |
| 48 | * |
| 49 | * This verilog model is the confidential and proprietary property of |
| 50 | * Sun Microsystems, Inc., and the possession or use of this model |
| 51 | * requires a written license from Sun Microsystems, Inc. |
| 52 | * |
| 53 | **********************************************************************/ |
| 54 | |
| 55 | `include "timescale.v" |
| 56 | |
| 57 | module niu_txc_portRegisters ( |
| 58 | SysClk, |
| 59 | Reset_L, |
| 60 | |
| 61 | ReadPortRegister, |
| 62 | WritePortRegister, |
| 63 | PosEdgeWritePort, |
| 64 | Slave_Addr, // Slave Address |
| 65 | Slave_DataIn, // Slave Write Data |
| 66 | Slave_DataOut, // Slave Read Data |
| 67 | |
| 68 | Port0_TidsInUse, |
| 69 | Port0_DuplicateTid, |
| 70 | Port0_UnInitializedTID, |
| 71 | Port0_TimedoutTids, |
| 72 | Port0_ReOrderStateLogic, |
| 73 | Port0_ReOrderStateControl, |
| 74 | Port0_ReOrderStateData0, |
| 75 | Port0_ReOrderStateData1, |
| 76 | Port0_ReOrderStateData2, |
| 77 | Port0_ReOrderStateData3, |
| 78 | Port0_WrTidsInUse, |
| 79 | Port0_WrDuplicateTid, |
| 80 | Port0_WrUnInitializedTID, |
| 81 | Port0_WrTimedoutTids, |
| 82 | Port0_WrReOrderStateLogic, |
| 83 | Port0_WrReOrderStateControl, |
| 84 | Port0_WrReOrderStateData0, |
| 85 | Port0_WrReOrderStateData1, |
| 86 | Port0_WrReOrderStateData2, |
| 87 | Port0_WrReOrderStateData3, |
| 88 | Port0_ReOrder_ECC_State, |
| 89 | Port0_StoreForward_ECC_State, |
| 90 | Port0_ReOrder_EccData, |
| 91 | Port0_StoreForward_EccData, |
| 92 | Port0_ReOrder_ClearEccError, |
| 93 | Port0_WrReOrderEccState, |
| 94 | Port0_WrReOrderEccData0, |
| 95 | Port0_WrReOrderEccData1, |
| 96 | Port0_WrReOrderEccData2, |
| 97 | Port0_WrReOrderEccData3, |
| 98 | Port0_WrReOrderEccData4, |
| 99 | Port0_StoreForward_ClearEccError, |
| 100 | Port0_WrStoreForwardEccState, |
| 101 | Port0_WrStoreForwardEccData0, |
| 102 | Port0_WrStoreForwardEccData1, |
| 103 | Port0_WrStoreForwardEccData2, |
| 104 | Port0_WrStoreForwardEccData3, |
| 105 | Port0_WrStoreForwardEccData4, |
| 106 | Port0_ReOrderEccControl, |
| 107 | Port0_StoreForwardEccControl, |
| 108 | Port0_ClearStatistics, |
| 109 | Port0_WrPacketRequested, |
| 110 | Port0_WrPacketStuffed, |
| 111 | Port0_WrPacketXmitted, |
| 112 | Port0_GatherRequestCount, |
| 113 | Port0_PacketRequestCount, |
| 114 | Port0_PktErrAbortCount, |
| 115 | Port0_ReOrdersStuffed, |
| 116 | Port0_PacketsStuffed, |
| 117 | Port0_PacketsTransmitted, |
| 118 | Port0_BytesTransmitted, |
| 119 | Port0_DMA_List, |
| 120 | |
| 121 | Port1_TidsInUse, |
| 122 | Port1_DuplicateTid, |
| 123 | Port1_UnInitializedTID, |
| 124 | Port1_TimedoutTids, |
| 125 | Port1_ReOrderStateLogic, |
| 126 | Port1_ReOrderStateControl, |
| 127 | Port1_ReOrderStateData0, |
| 128 | Port1_ReOrderStateData1, |
| 129 | Port1_ReOrderStateData2, |
| 130 | Port1_ReOrderStateData3, |
| 131 | Port1_WrTidsInUse, |
| 132 | Port1_WrDuplicateTid, |
| 133 | Port1_WrUnInitializedTID, |
| 134 | Port1_WrTimedoutTids, |
| 135 | Port1_WrReOrderStateLogic, |
| 136 | Port1_WrReOrderStateControl, |
| 137 | Port1_WrReOrderStateData0, |
| 138 | Port1_WrReOrderStateData1, |
| 139 | Port1_WrReOrderStateData2, |
| 140 | Port1_WrReOrderStateData3, |
| 141 | Port1_ReOrder_ECC_State, |
| 142 | Port1_StoreForward_ECC_State, |
| 143 | Port1_ReOrder_EccData, |
| 144 | Port1_StoreForward_EccData, |
| 145 | Port1_ReOrder_ClearEccError, |
| 146 | Port1_WrReOrderEccState, |
| 147 | Port1_WrReOrderEccData0, |
| 148 | Port1_WrReOrderEccData1, |
| 149 | Port1_WrReOrderEccData2, |
| 150 | Port1_WrReOrderEccData3, |
| 151 | Port1_WrReOrderEccData4, |
| 152 | Port1_StoreForward_ClearEccError, |
| 153 | Port1_WrStoreForwardEccState, |
| 154 | Port1_WrStoreForwardEccData0, |
| 155 | Port1_WrStoreForwardEccData1, |
| 156 | Port1_WrStoreForwardEccData2, |
| 157 | Port1_WrStoreForwardEccData3, |
| 158 | Port1_WrStoreForwardEccData4, |
| 159 | Port1_ReOrderEccControl, |
| 160 | Port1_StoreForwardEccControl, |
| 161 | Port1_ClearStatistics, |
| 162 | Port1_WrPacketRequested, |
| 163 | Port1_WrPacketStuffed, |
| 164 | Port1_WrPacketXmitted, |
| 165 | Port1_GatherRequestCount, |
| 166 | Port1_PacketRequestCount, |
| 167 | Port1_PktErrAbortCount, |
| 168 | Port1_ReOrdersStuffed, |
| 169 | Port1_PacketsStuffed, |
| 170 | Port1_PacketsTransmitted, |
| 171 | Port1_BytesTransmitted, |
| 172 | Port1_DMA_List |
| 173 | ); |
| 174 | |
| 175 | // Include Header Files |
| 176 | `include "txc_defines.h" |
| 177 | `include "niu_txc_reg_defines.h" |
| 178 | |
| 179 | // Global Signals |
| 180 | input SysClk; |
| 181 | input Reset_L; |
| 182 | |
| 183 | // Slave Interface |
| 184 | input ReadPortRegister; |
| 185 | input WritePortRegister; |
| 186 | input PosEdgeWritePort; |
| 187 | input [8:2] Slave_Addr; |
| 188 | input [31:0] Slave_DataIn; |
| 189 | |
| 190 | output [31:0] Slave_DataOut; |
| 191 | |
| 192 | reg [31:0] Slave_DataOut; |
| 193 | |
| 194 | // Port 0 ReOrder PIO Control Registers |
| 195 | input [31:0] Port0_TidsInUse; |
| 196 | input [31:0] Port0_DuplicateTid; |
| 197 | input [31:0] Port0_UnInitializedTID; |
| 198 | input [31:0] Port0_TimedoutTids; |
| 199 | input [31:0] Port0_ReOrderStateLogic; |
| 200 | input [31:0] Port0_ReOrderStateControl; |
| 201 | input [31:0] Port0_ReOrderStateData0; |
| 202 | input [31:0] Port0_ReOrderStateData1; |
| 203 | input [31:0] Port0_ReOrderStateData2; |
| 204 | input [31:0] Port0_ReOrderStateData3; |
| 205 | |
| 206 | output Port0_WrTidsInUse; |
| 207 | output Port0_WrDuplicateTid; |
| 208 | output Port0_WrUnInitializedTID; |
| 209 | output Port0_WrTimedoutTids; |
| 210 | output Port0_WrReOrderStateLogic; |
| 211 | output Port0_WrReOrderStateControl; |
| 212 | output Port0_WrReOrderStateData0; |
| 213 | output Port0_WrReOrderStateData1; |
| 214 | output Port0_WrReOrderStateData2; |
| 215 | output Port0_WrReOrderStateData3; |
| 216 | |
| 217 | reg Port0_WrTidsInUse; |
| 218 | reg Port0_WrDuplicateTid; |
| 219 | reg Port0_WrUnInitializedTID; |
| 220 | reg Port0_WrTimedoutTids; |
| 221 | reg Port0_WrReOrderStateLogic; |
| 222 | reg Port0_WrReOrderStateControl; |
| 223 | reg Port0_WrReOrderStateData0; |
| 224 | reg Port0_WrReOrderStateData1; |
| 225 | reg Port0_WrReOrderStateData2; |
| 226 | reg Port0_WrReOrderStateData3; |
| 227 | |
| 228 | // Port 0 ECC Error Reporting PIO Control Registers |
| 229 | input [31:0] Port0_ReOrder_ECC_State; |
| 230 | input [31:0] Port0_StoreForward_ECC_State; |
| 231 | input [151:0] Port0_ReOrder_EccData; |
| 232 | input [151:0] Port0_StoreForward_EccData; |
| 233 | |
| 234 | output Port0_ReOrder_ClearEccError; |
| 235 | output Port0_WrReOrderEccState; |
| 236 | output Port0_WrReOrderEccData0; |
| 237 | output Port0_WrReOrderEccData1; |
| 238 | output Port0_WrReOrderEccData2; |
| 239 | output Port0_WrReOrderEccData3; |
| 240 | output Port0_WrReOrderEccData4; |
| 241 | output Port0_StoreForward_ClearEccError; |
| 242 | output Port0_WrStoreForwardEccState; |
| 243 | output Port0_WrStoreForwardEccData0; |
| 244 | output Port0_WrStoreForwardEccData1; |
| 245 | output Port0_WrStoreForwardEccData2; |
| 246 | output Port0_WrStoreForwardEccData3; |
| 247 | output Port0_WrStoreForwardEccData4; |
| 248 | |
| 249 | reg Port0_ReOrder_ClearEccError; |
| 250 | reg Port0_WrReOrderEccState; |
| 251 | reg Port0_WrReOrderEccData0; |
| 252 | reg Port0_WrReOrderEccData1; |
| 253 | reg Port0_WrReOrderEccData2; |
| 254 | reg Port0_WrReOrderEccData3; |
| 255 | reg Port0_WrReOrderEccData4; |
| 256 | reg Port0_StoreForward_ClearEccError; |
| 257 | reg Port0_WrStoreForwardEccState; |
| 258 | reg Port0_WrStoreForwardEccData0; |
| 259 | reg Port0_WrStoreForwardEccData1; |
| 260 | reg Port0_WrStoreForwardEccData2; |
| 261 | reg Port0_WrStoreForwardEccData3; |
| 262 | reg Port0_WrStoreForwardEccData4; |
| 263 | |
| 264 | // Port 0 ECC Control & Status Registers |
| 265 | output [31:0] Port0_ReOrderEccControl; |
| 266 | output [31:0] Port0_StoreForwardEccControl; |
| 267 | |
| 268 | // Port 0 Diagnostics Control Registers |
| 269 | input [3:0] Port0_GatherRequestCount; |
| 270 | input [11:0] Port0_PacketRequestCount; |
| 271 | input [15:0] Port0_PktErrAbortCount; |
| 272 | input [15:0] Port0_ReOrdersStuffed; |
| 273 | input [15:0] Port0_PacketsStuffed; |
| 274 | input [15:0] Port0_PacketsTransmitted; |
| 275 | input [15:0] Port0_BytesTransmitted; |
| 276 | |
| 277 | output Port0_ClearStatistics; |
| 278 | output Port0_WrPacketRequested; |
| 279 | output Port0_WrPacketStuffed; |
| 280 | output Port0_WrPacketXmitted; |
| 281 | |
| 282 | reg Port0_ClearStatistics; |
| 283 | reg Port0_WrPacketRequested; |
| 284 | reg Port0_WrPacketStuffed; |
| 285 | reg Port0_WrPacketXmitted; |
| 286 | |
| 287 | // Port 0 Bind Control Registers |
| 288 | output [23:0] Port0_DMA_List; |
| 289 | |
| 290 | reg [23:0] Port0_DMA_List; |
| 291 | |
| 292 | // Port 1 ReOrder PIO Control Registers |
| 293 | input [31:0] Port1_TidsInUse; |
| 294 | input [31:0] Port1_DuplicateTid; |
| 295 | input [31:0] Port1_UnInitializedTID; |
| 296 | input [31:0] Port1_TimedoutTids; |
| 297 | input [31:0] Port1_ReOrderStateLogic; |
| 298 | input [31:0] Port1_ReOrderStateControl; |
| 299 | input [31:0] Port1_ReOrderStateData0; |
| 300 | input [31:0] Port1_ReOrderStateData1; |
| 301 | input [31:0] Port1_ReOrderStateData2; |
| 302 | input [31:0] Port1_ReOrderStateData3; |
| 303 | |
| 304 | output Port1_WrTidsInUse; |
| 305 | output Port1_WrDuplicateTid; |
| 306 | output Port1_WrUnInitializedTID; |
| 307 | output Port1_WrTimedoutTids; |
| 308 | output Port1_WrReOrderStateLogic; |
| 309 | output Port1_WrReOrderStateControl; |
| 310 | output Port1_WrReOrderStateData0; |
| 311 | output Port1_WrReOrderStateData1; |
| 312 | output Port1_WrReOrderStateData2; |
| 313 | output Port1_WrReOrderStateData3; |
| 314 | |
| 315 | reg Port1_WrTidsInUse; |
| 316 | reg Port1_WrDuplicateTid; |
| 317 | reg Port1_WrUnInitializedTID; |
| 318 | reg Port1_WrTimedoutTids; |
| 319 | reg Port1_WrReOrderStateLogic; |
| 320 | reg Port1_WrReOrderStateControl; |
| 321 | reg Port1_WrReOrderStateData0; |
| 322 | reg Port1_WrReOrderStateData1; |
| 323 | reg Port1_WrReOrderStateData2; |
| 324 | reg Port1_WrReOrderStateData3; |
| 325 | |
| 326 | // Port 1 ECC Error Reporting PIO Control Registers |
| 327 | input [31:0] Port1_ReOrder_ECC_State; |
| 328 | input [31:0] Port1_StoreForward_ECC_State; |
| 329 | input [151:0] Port1_ReOrder_EccData; |
| 330 | input [151:0] Port1_StoreForward_EccData; |
| 331 | |
| 332 | output Port1_ReOrder_ClearEccError; |
| 333 | output Port1_WrReOrderEccState; |
| 334 | output Port1_WrReOrderEccData0; |
| 335 | output Port1_WrReOrderEccData1; |
| 336 | output Port1_WrReOrderEccData2; |
| 337 | output Port1_WrReOrderEccData3; |
| 338 | output Port1_WrReOrderEccData4; |
| 339 | output Port1_StoreForward_ClearEccError; |
| 340 | output Port1_WrStoreForwardEccState; |
| 341 | output Port1_WrStoreForwardEccData0; |
| 342 | output Port1_WrStoreForwardEccData1; |
| 343 | output Port1_WrStoreForwardEccData2; |
| 344 | output Port1_WrStoreForwardEccData3; |
| 345 | output Port1_WrStoreForwardEccData4; |
| 346 | |
| 347 | reg Port1_ReOrder_ClearEccError; |
| 348 | reg Port1_WrReOrderEccState; |
| 349 | reg Port1_WrReOrderEccData0; |
| 350 | reg Port1_WrReOrderEccData1; |
| 351 | reg Port1_WrReOrderEccData2; |
| 352 | reg Port1_WrReOrderEccData3; |
| 353 | reg Port1_WrReOrderEccData4; |
| 354 | reg Port1_StoreForward_ClearEccError; |
| 355 | reg Port1_WrStoreForwardEccState; |
| 356 | reg Port1_WrStoreForwardEccData0; |
| 357 | reg Port1_WrStoreForwardEccData1; |
| 358 | reg Port1_WrStoreForwardEccData2; |
| 359 | reg Port1_WrStoreForwardEccData3; |
| 360 | reg Port1_WrStoreForwardEccData4; |
| 361 | |
| 362 | // Port 1 ECC Control & Status Registers |
| 363 | output [31:0] Port1_ReOrderEccControl; |
| 364 | output [31:0] Port1_StoreForwardEccControl; |
| 365 | |
| 366 | // Port 1 Diagnostics Control Registers |
| 367 | input [3:0] Port1_GatherRequestCount; |
| 368 | input [11:0] Port1_PacketRequestCount; |
| 369 | input [15:0] Port1_PktErrAbortCount; |
| 370 | input [15:0] Port1_ReOrdersStuffed; |
| 371 | input [15:0] Port1_PacketsStuffed; |
| 372 | input [15:0] Port1_PacketsTransmitted; |
| 373 | input [15:0] Port1_BytesTransmitted; |
| 374 | |
| 375 | output Port1_ClearStatistics; |
| 376 | output Port1_WrPacketRequested; |
| 377 | output Port1_WrPacketStuffed; |
| 378 | output Port1_WrPacketXmitted; |
| 379 | |
| 380 | reg Port1_ClearStatistics; |
| 381 | reg Port1_WrPacketRequested; |
| 382 | reg Port1_WrPacketStuffed; |
| 383 | reg Port1_WrPacketXmitted; |
| 384 | |
| 385 | // Port 1 Bind Control Registers |
| 386 | output [23:0] Port1_DMA_List; |
| 387 | |
| 388 | reg [23:0] Port1_DMA_List; |
| 389 | |
| 390 | /*--------------------------------------------------------------*/ |
| 391 | // Wires & Registers |
| 392 | /*--------------------------------------------------------------*/ |
| 393 | reg port0_RO_Disable_UE; |
| 394 | reg port0_RO_Double_Bit_Err; |
| 395 | reg port0_RO_Single_Bit_Err; |
| 396 | reg port0_RO_All_Pkts; |
| 397 | reg port0_RO_Alt_Pkts; |
| 398 | reg port0_RO_One_Pkt_Only; |
| 399 | reg port0_RO_Last_Pkt_Line; |
| 400 | reg port0_RO_Second_Pkt_Line; |
| 401 | reg port0_RO_First_Pkt_Line; |
| 402 | reg port0_SF_Disable_UE; |
| 403 | reg port0_SF_Double_Bit_Err; |
| 404 | reg port0_SF_Single_Bit_Err; |
| 405 | reg port0_SF_All_Pkts; |
| 406 | reg port0_SF_Alt_Pkts; |
| 407 | reg port0_SF_One_Pkt_Only; |
| 408 | reg port0_SF_Last_Pkt_Line; |
| 409 | reg port0_SF_Second_Pkt_Line; |
| 410 | reg port0_SF_First_Pkt_Line; |
| 411 | |
| 412 | reg port1_RO_Disable_UE; |
| 413 | reg port1_RO_Double_Bit_Err; |
| 414 | reg port1_RO_Single_Bit_Err; |
| 415 | reg port1_RO_All_Pkts; |
| 416 | reg port1_RO_Alt_Pkts; |
| 417 | reg port1_RO_One_Pkt_Only; |
| 418 | reg port1_RO_Last_Pkt_Line; |
| 419 | reg port1_RO_Second_Pkt_Line; |
| 420 | reg port1_RO_First_Pkt_Line; |
| 421 | reg port1_SF_Disable_UE; |
| 422 | reg port1_SF_Double_Bit_Err; |
| 423 | reg port1_SF_Single_Bit_Err; |
| 424 | reg port1_SF_All_Pkts; |
| 425 | reg port1_SF_Alt_Pkts; |
| 426 | reg port1_SF_One_Pkt_Only; |
| 427 | reg port1_SF_Last_Pkt_Line; |
| 428 | reg port1_SF_Second_Pkt_Line; |
| 429 | reg port1_SF_First_Pkt_Line; |
| 430 | |
| 431 | /*--------------------------------------------------------------*/ |
| 432 | // ECC Control Logic |
| 433 | /*--------------------------------------------------------------*/ |
| 434 | assign Port0_ReOrderEccControl = {port0_RO_Disable_UE, // 31 |
| 435 | 13'h0, // 30:18 |
| 436 | port0_RO_Double_Bit_Err, // 17 |
| 437 | port0_RO_Single_Bit_Err, // 16 |
| 438 | 5'h0, // 15:11 |
| 439 | port0_RO_All_Pkts, // 10 |
| 440 | port0_RO_Alt_Pkts, // 9 |
| 441 | port0_RO_One_Pkt_Only, // 8 |
| 442 | 5'h0, // 7:3 |
| 443 | port0_RO_Last_Pkt_Line, // 2 |
| 444 | port0_RO_Second_Pkt_Line, // 1 |
| 445 | port0_RO_First_Pkt_Line // 0 |
| 446 | }; |
| 447 | |
| 448 | assign Port0_StoreForwardEccControl = {port0_SF_Disable_UE, // 31 |
| 449 | 13'h0, // 30:18 |
| 450 | port0_SF_Double_Bit_Err, // 17 |
| 451 | port0_SF_Single_Bit_Err, // 16 |
| 452 | 5'h0, // 15:11 |
| 453 | port0_SF_All_Pkts, // 10 |
| 454 | port0_SF_Alt_Pkts, // 9 |
| 455 | port0_SF_One_Pkt_Only, // 8 |
| 456 | 5'h0, // 7:3 |
| 457 | port0_SF_Last_Pkt_Line, // 2 |
| 458 | port0_SF_Second_Pkt_Line, // 1 |
| 459 | port0_SF_First_Pkt_Line // 0 |
| 460 | }; |
| 461 | |
| 462 | assign Port1_ReOrderEccControl = {port1_RO_Disable_UE, // 31 |
| 463 | 13'h0, // 30:18 |
| 464 | port1_RO_Double_Bit_Err, // 17 |
| 465 | port1_RO_Single_Bit_Err, // 16 |
| 466 | 5'h0, // 15:11 |
| 467 | port1_RO_All_Pkts, // 10 |
| 468 | port1_RO_Alt_Pkts, // 9 |
| 469 | port1_RO_One_Pkt_Only, // 8 |
| 470 | 5'h0, // 7:3 |
| 471 | port1_RO_Last_Pkt_Line, // 2 |
| 472 | port1_RO_Second_Pkt_Line, // 1 |
| 473 | port1_RO_First_Pkt_Line // 0 |
| 474 | }; |
| 475 | |
| 476 | assign Port1_StoreForwardEccControl = {port1_SF_Disable_UE, // 31 |
| 477 | 13'h0, // 30:18 |
| 478 | port1_SF_Double_Bit_Err, // 17 |
| 479 | port1_SF_Single_Bit_Err, // 16 |
| 480 | 5'h0, // 15:11 |
| 481 | port1_SF_All_Pkts, // 10 |
| 482 | port1_SF_Alt_Pkts, // 9 |
| 483 | port1_SF_One_Pkt_Only, // 8 |
| 484 | 5'h0, // 7:3 |
| 485 | port1_SF_Last_Pkt_Line, // 2 |
| 486 | port1_SF_Second_Pkt_Line, // 1 |
| 487 | port1_SF_First_Pkt_Line // 0 |
| 488 | }; |
| 489 | |
| 490 | /*--------------------------------------------------------------*/ |
| 491 | // NIU TXC Port PIO Read & Write Registers |
| 492 | /*--------------------------------------------------------------*/ |
| 493 | |
| 494 | always @ (posedge SysClk) |
| 495 | if (!Reset_L) |
| 496 | Slave_DataOut <= 32'h0; |
| 497 | else if (ReadPortRegister) |
| 498 | case ({3'h0, Slave_Addr[8:2], 2'h0}) // synopsys parallel_case |
| 499 | /* 0in < case -parallel */ |
| 500 | |
| 501 | `PORT0_DMA_ENABLE: Slave_DataOut <= {8'h0, Port0_DMA_List}; |
| 502 | `PORT0_PACKETS_STUFFED: Slave_DataOut <= {Port0_ReOrdersStuffed, |
| 503 | Port0_PacketsStuffed}; |
| 504 | `PORT0_PACKETS_XMITTED: Slave_DataOut <= {Port0_BytesTransmitted, |
| 505 | Port0_PacketsTransmitted}; |
| 506 | `PORT0_RO_ECC_CONTROL: Slave_DataOut <= Port0_ReOrderEccControl; |
| 507 | `PORT0_RO_ECC_ADDR: Slave_DataOut <= Port0_ReOrder_ECC_State; |
| 508 | `PORT0_RO_ECC_DATA0: Slave_DataOut <= Port0_ReOrder_EccData[31:0]; |
| 509 | `PORT0_RO_ECC_DATA1: Slave_DataOut <= Port0_ReOrder_EccData[63:32]; |
| 510 | `PORT0_RO_ECC_DATA2: Slave_DataOut <= Port0_ReOrder_EccData[95:64]; |
| 511 | `PORT0_RO_ECC_DATA3: Slave_DataOut <= Port0_ReOrder_EccData[127:96]; |
| 512 | `PORT0_RO_ECC_DATA4: Slave_DataOut <= {8'h0, |
| 513 | Port0_ReOrder_EccData[151:128]}; |
| 514 | |
| 515 | `PORT0_SF_ECC_CONTROL: Slave_DataOut <= Port0_StoreForwardEccControl; |
| 516 | `PORT0_SF_ECC_ADDR: Slave_DataOut <= Port0_StoreForward_ECC_State; |
| 517 | `PORT0_SF_ECC_DATA0: Slave_DataOut <= Port0_StoreForward_EccData[31:0]; |
| 518 | `PORT0_SF_ECC_DATA1: Slave_DataOut <= Port0_StoreForward_EccData[63:32]; |
| 519 | `PORT0_SF_ECC_DATA2: Slave_DataOut <= Port0_StoreForward_EccData[95:64]; |
| 520 | `PORT0_SF_ECC_DATA3: Slave_DataOut <= Port0_StoreForward_EccData[127:96]; |
| 521 | `PORT0_SF_ECC_DATA4: Slave_DataOut <= {8'h0, |
| 522 | Port0_StoreForward_EccData[151:128]}; |
| 523 | |
| 524 | `PORT0_REORDER_TID: Slave_DataOut <= Port0_TidsInUse; |
| 525 | `PORT0_REORDER_STATE0: Slave_DataOut <= Port0_DuplicateTid; |
| 526 | `PORT0_REORDER_STATE1: Slave_DataOut <= Port0_UnInitializedTID; |
| 527 | `PORT0_REORDER_STATE2: Slave_DataOut <= Port0_TimedoutTids; |
| 528 | `PORT0_REORDER_STATE3: Slave_DataOut <= Port0_ReOrderStateLogic; |
| 529 | `PORT0_REORDER_CONTROL: Slave_DataOut <= Port0_ReOrderStateControl; |
| 530 | `PORT0_REORDER_DATA0: Slave_DataOut <= Port0_ReOrderStateData0; |
| 531 | `PORT0_REORDER_DATA1: Slave_DataOut <= Port0_ReOrderStateData1; |
| 532 | `PORT0_REORDER_DATA2: Slave_DataOut <= Port0_ReOrderStateData2; |
| 533 | `PORT0_REORDER_DATA3: Slave_DataOut <= Port0_ReOrderStateData3; |
| 534 | `PORT0_PACKETS_REQUEST: Slave_DataOut <= {Port0_GatherRequestCount, |
| 535 | Port0_PacketRequestCount, |
| 536 | Port0_PktErrAbortCount}; |
| 537 | |
| 538 | `PORT1_DMA_ENABLE: Slave_DataOut <= {8'h0, Port1_DMA_List}; |
| 539 | `PORT1_PACKETS_STUFFED: Slave_DataOut <= {Port1_ReOrdersStuffed, |
| 540 | Port1_PacketsStuffed}; |
| 541 | `PORT1_PACKETS_XMITTED: Slave_DataOut <= {Port1_BytesTransmitted, |
| 542 | Port1_PacketsTransmitted}; |
| 543 | `PORT1_RO_ECC_CONTROL: Slave_DataOut <= Port1_ReOrderEccControl; |
| 544 | `PORT1_RO_ECC_ADDR: Slave_DataOut <= Port1_ReOrder_ECC_State; |
| 545 | `PORT1_RO_ECC_DATA0: Slave_DataOut <= Port1_ReOrder_EccData[31:0]; |
| 546 | `PORT1_RO_ECC_DATA1: Slave_DataOut <= Port1_ReOrder_EccData[63:32]; |
| 547 | `PORT1_RO_ECC_DATA2: Slave_DataOut <= Port1_ReOrder_EccData[95:64]; |
| 548 | `PORT1_RO_ECC_DATA3: Slave_DataOut <= Port1_ReOrder_EccData[127:96]; |
| 549 | `PORT1_RO_ECC_DATA4: Slave_DataOut <= {8'h0, |
| 550 | Port1_ReOrder_EccData[151:128]}; |
| 551 | |
| 552 | `PORT1_SF_ECC_CONTROL: Slave_DataOut <= Port1_StoreForwardEccControl; |
| 553 | `PORT1_SF_ECC_ADDR: Slave_DataOut <= Port1_StoreForward_ECC_State; |
| 554 | `PORT1_SF_ECC_DATA0: Slave_DataOut <= Port1_StoreForward_EccData[31:0]; |
| 555 | `PORT1_SF_ECC_DATA1: Slave_DataOut <= Port1_StoreForward_EccData[63:32]; |
| 556 | `PORT1_SF_ECC_DATA2: Slave_DataOut <= Port1_StoreForward_EccData[95:64]; |
| 557 | `PORT1_SF_ECC_DATA3: Slave_DataOut <= Port1_StoreForward_EccData[127:96]; |
| 558 | `PORT1_SF_ECC_DATA4: Slave_DataOut <= {8'h0, |
| 559 | Port1_StoreForward_EccData[151:128]}; |
| 560 | |
| 561 | `PORT1_REORDER_TID: Slave_DataOut <= Port1_TidsInUse; |
| 562 | `PORT1_REORDER_STATE0: Slave_DataOut <= Port1_DuplicateTid; |
| 563 | `PORT1_REORDER_STATE1: Slave_DataOut <= Port1_UnInitializedTID; |
| 564 | `PORT1_REORDER_STATE2: Slave_DataOut <= Port1_TimedoutTids; |
| 565 | `PORT1_REORDER_STATE3: Slave_DataOut <= Port1_ReOrderStateLogic; |
| 566 | `PORT1_REORDER_CONTROL: Slave_DataOut <= Port1_ReOrderStateControl; |
| 567 | `PORT1_REORDER_DATA0: Slave_DataOut <= Port1_ReOrderStateData0; |
| 568 | `PORT1_REORDER_DATA1: Slave_DataOut <= Port1_ReOrderStateData1; |
| 569 | `PORT1_REORDER_DATA2: Slave_DataOut <= Port1_ReOrderStateData2; |
| 570 | `PORT1_REORDER_DATA3: Slave_DataOut <= Port1_ReOrderStateData3; |
| 571 | `PORT1_PACKETS_REQUEST: Slave_DataOut <= {Port1_GatherRequestCount, |
| 572 | Port1_PacketRequestCount, |
| 573 | Port1_PktErrAbortCount}; |
| 574 | |
| 575 | default: Slave_DataOut <= 32'h0; |
| 576 | |
| 577 | endcase |
| 578 | |
| 579 | |
| 580 | always @ (posedge SysClk) |
| 581 | if (!Reset_L) |
| 582 | begin |
| 583 | Port0_ClearStatistics <= 1'b0; |
| 584 | Port0_ReOrder_ClearEccError <= 1'b0; |
| 585 | Port0_WrReOrderEccState <= 1'b0; |
| 586 | Port0_WrReOrderEccData0 <= 1'b0; |
| 587 | Port0_WrReOrderEccData1 <= 1'b0; |
| 588 | Port0_WrReOrderEccData2 <= 1'b0; |
| 589 | Port0_WrReOrderEccData3 <= 1'b0; |
| 590 | Port0_WrReOrderEccData4 <= 1'b0; |
| 591 | Port0_StoreForward_ClearEccError <= 1'b0; |
| 592 | Port0_WrStoreForwardEccState <= 1'b0; |
| 593 | Port0_WrStoreForwardEccData0 <= 1'b0; |
| 594 | Port0_WrStoreForwardEccData1 <= 1'b0; |
| 595 | Port0_WrStoreForwardEccData2 <= 1'b0; |
| 596 | Port0_WrStoreForwardEccData3 <= 1'b0; |
| 597 | Port0_WrStoreForwardEccData4 <= 1'b0; |
| 598 | Port1_ClearStatistics <= 1'b0; |
| 599 | Port1_ReOrder_ClearEccError <= 1'b0; |
| 600 | Port1_WrReOrderEccState <= 1'b0; |
| 601 | Port1_WrReOrderEccData0 <= 1'b0; |
| 602 | Port1_WrReOrderEccData1 <= 1'b0; |
| 603 | Port1_WrReOrderEccData2 <= 1'b0; |
| 604 | Port1_WrReOrderEccData3 <= 1'b0; |
| 605 | Port1_WrReOrderEccData4 <= 1'b0; |
| 606 | Port1_StoreForward_ClearEccError <= 1'b0; |
| 607 | Port1_WrStoreForwardEccState <= 1'b0; |
| 608 | Port1_WrStoreForwardEccData0 <= 1'b0; |
| 609 | Port1_WrStoreForwardEccData1 <= 1'b0; |
| 610 | Port1_WrStoreForwardEccData2 <= 1'b0; |
| 611 | Port1_WrStoreForwardEccData3 <= 1'b0; |
| 612 | Port1_WrStoreForwardEccData4 <= 1'b0; |
| 613 | end |
| 614 | else if (PosEdgeWritePort) |
| 615 | begin |
| 616 | case ({3'h0, Slave_Addr[8:2], 2'h0}) // synopsys parallel_case |
| 617 | /* 0in < case -parallel */ |
| 618 | |
| 619 | `PORT0_CONTROL: Port0_ClearStatistics <= Slave_DataIn[0]; |
| 620 | `PORT0_RO_ECC_ADDR: begin |
| 621 | Port0_ReOrder_ClearEccError <= Slave_DataIn[31]; |
| 622 | Port0_WrReOrderEccState <= 1'b1; |
| 623 | end |
| 624 | `PORT0_RO_ECC_DATA0: Port0_WrReOrderEccData0 <= 1'b1; |
| 625 | `PORT0_RO_ECC_DATA1: Port0_WrReOrderEccData1 <= 1'b1; |
| 626 | `PORT0_RO_ECC_DATA2: Port0_WrReOrderEccData2 <= 1'b1; |
| 627 | `PORT0_RO_ECC_DATA3: Port0_WrReOrderEccData3 <= 1'b1; |
| 628 | `PORT0_RO_ECC_DATA4: Port0_WrReOrderEccData4 <= 1'b1; |
| 629 | `PORT0_SF_ECC_ADDR: begin |
| 630 | Port0_StoreForward_ClearEccError <= Slave_DataIn[31]; |
| 631 | Port0_WrStoreForwardEccState <= 1'b1; |
| 632 | end |
| 633 | `PORT0_SF_ECC_DATA0: Port0_WrStoreForwardEccData0 <= 1'b1; |
| 634 | `PORT0_SF_ECC_DATA1: Port0_WrStoreForwardEccData1 <= 1'b1; |
| 635 | `PORT0_SF_ECC_DATA2: Port0_WrStoreForwardEccData2 <= 1'b1; |
| 636 | `PORT0_SF_ECC_DATA3: Port0_WrStoreForwardEccData3 <= 1'b1; |
| 637 | `PORT0_SF_ECC_DATA4: Port0_WrStoreForwardEccData4 <= 1'b1; |
| 638 | |
| 639 | `PORT1_CONTROL: Port1_ClearStatistics <= Slave_DataIn[0]; |
| 640 | `PORT1_RO_ECC_ADDR: begin |
| 641 | Port1_ReOrder_ClearEccError <= Slave_DataIn[31]; |
| 642 | Port1_WrReOrderEccState <= 1'b1; |
| 643 | end |
| 644 | `PORT1_RO_ECC_DATA0: Port1_WrReOrderEccData0 <= 1'b1; |
| 645 | `PORT1_RO_ECC_DATA1: Port1_WrReOrderEccData1 <= 1'b1; |
| 646 | `PORT1_RO_ECC_DATA2: Port1_WrReOrderEccData2 <= 1'b1; |
| 647 | `PORT1_RO_ECC_DATA3: Port1_WrReOrderEccData3 <= 1'b1; |
| 648 | `PORT1_RO_ECC_DATA4: Port1_WrReOrderEccData4 <= 1'b1; |
| 649 | `PORT1_SF_ECC_ADDR: begin |
| 650 | Port1_StoreForward_ClearEccError <= Slave_DataIn[31]; |
| 651 | Port1_WrStoreForwardEccState <= 1'b1; |
| 652 | end |
| 653 | `PORT1_SF_ECC_DATA0: Port1_WrStoreForwardEccData0 <= 1'b1; |
| 654 | `PORT1_SF_ECC_DATA1: Port1_WrStoreForwardEccData1 <= 1'b1; |
| 655 | `PORT1_SF_ECC_DATA2: Port1_WrStoreForwardEccData2 <= 1'b1; |
| 656 | `PORT1_SF_ECC_DATA3: Port1_WrStoreForwardEccData3 <= 1'b1; |
| 657 | `PORT1_SF_ECC_DATA4: Port1_WrStoreForwardEccData4 <= 1'b1; |
| 658 | endcase |
| 659 | end |
| 660 | else |
| 661 | begin |
| 662 | Port0_ClearStatistics <= 1'b0; |
| 663 | Port0_ReOrder_ClearEccError <= 1'b0; |
| 664 | Port0_WrReOrderEccState <= 1'b0; |
| 665 | Port0_WrReOrderEccData0 <= 1'b0; |
| 666 | Port0_WrReOrderEccData1 <= 1'b0; |
| 667 | Port0_WrReOrderEccData2 <= 1'b0; |
| 668 | Port0_WrReOrderEccData3 <= 1'b0; |
| 669 | Port0_WrReOrderEccData4 <= 1'b0; |
| 670 | Port0_StoreForward_ClearEccError <= 1'b0; |
| 671 | Port0_WrStoreForwardEccState <= 1'b0; |
| 672 | Port0_WrStoreForwardEccData0 <= 1'b0; |
| 673 | Port0_WrStoreForwardEccData1 <= 1'b0; |
| 674 | Port0_WrStoreForwardEccData2 <= 1'b0; |
| 675 | Port0_WrStoreForwardEccData3 <= 1'b0; |
| 676 | Port0_WrStoreForwardEccData4 <= 1'b0; |
| 677 | Port1_ClearStatistics <= 1'b0; |
| 678 | Port1_ReOrder_ClearEccError <= 1'b0; |
| 679 | Port1_WrReOrderEccState <= 1'b0; |
| 680 | Port1_WrReOrderEccData0 <= 1'b0; |
| 681 | Port1_WrReOrderEccData1 <= 1'b0; |
| 682 | Port1_WrReOrderEccData2 <= 1'b0; |
| 683 | Port1_WrReOrderEccData3 <= 1'b0; |
| 684 | Port1_WrReOrderEccData4 <= 1'b0; |
| 685 | Port1_StoreForward_ClearEccError <= 1'b0; |
| 686 | Port1_WrStoreForwardEccState <= 1'b0; |
| 687 | Port1_WrStoreForwardEccData0 <= 1'b0; |
| 688 | Port1_WrStoreForwardEccData1 <= 1'b0; |
| 689 | Port1_WrStoreForwardEccData2 <= 1'b0; |
| 690 | Port1_WrStoreForwardEccData3 <= 1'b0; |
| 691 | Port1_WrStoreForwardEccData4 <= 1'b0; |
| 692 | end |
| 693 | |
| 694 | |
| 695 | always @ (posedge SysClk) |
| 696 | if (!Reset_L) |
| 697 | begin |
| 698 | Port0_DMA_List <= 24'h0; |
| 699 | Port0_WrPacketRequested <= 1'b0; |
| 700 | Port0_WrPacketStuffed <= 1'b0; |
| 701 | Port0_WrPacketXmitted <= 1'b0; |
| 702 | port0_RO_Disable_UE <= 1'b0; |
| 703 | port0_RO_Double_Bit_Err <= 1'b0; |
| 704 | port0_RO_Single_Bit_Err <= 1'b0; |
| 705 | port0_RO_All_Pkts <= 1'b0; |
| 706 | port0_RO_Alt_Pkts <= 1'b0; |
| 707 | port0_RO_One_Pkt_Only <= 1'b0; |
| 708 | port0_RO_Last_Pkt_Line <= 1'b0; |
| 709 | port0_RO_Second_Pkt_Line <= 1'b0; |
| 710 | port0_RO_First_Pkt_Line <= 1'b0; |
| 711 | port0_SF_Disable_UE <= 1'b0; |
| 712 | port0_SF_Double_Bit_Err <= 1'b0; |
| 713 | port0_SF_Single_Bit_Err <= 1'b0; |
| 714 | port0_SF_All_Pkts <= 1'b0; |
| 715 | port0_SF_Alt_Pkts <= 1'b0; |
| 716 | port0_SF_One_Pkt_Only <= 1'b0; |
| 717 | port0_SF_Last_Pkt_Line <= 1'b0; |
| 718 | port0_SF_Second_Pkt_Line <= 1'b0; |
| 719 | port0_SF_First_Pkt_Line <= 1'b0; |
| 720 | Port0_WrTidsInUse <= 1'b0; |
| 721 | Port0_WrDuplicateTid <= 1'b0; |
| 722 | Port0_WrUnInitializedTID <= 1'b0; |
| 723 | Port0_WrTimedoutTids <= 1'b0; |
| 724 | Port0_WrReOrderStateLogic <= 1'b0; |
| 725 | Port0_WrReOrderStateControl <= 1'b0; |
| 726 | Port0_WrReOrderStateData0 <= 1'b0; |
| 727 | Port0_WrReOrderStateData1 <= 1'b0; |
| 728 | Port0_WrReOrderStateData2 <= 1'b0; |
| 729 | Port0_WrReOrderStateData3 <= 1'b0; |
| 730 | Port1_DMA_List <= 24'h0; |
| 731 | Port1_WrPacketRequested <= 1'b0; |
| 732 | Port1_WrPacketStuffed <= 1'b0; |
| 733 | Port1_WrPacketXmitted <= 1'b0; |
| 734 | port1_RO_Disable_UE <= 1'b0; |
| 735 | port1_RO_Double_Bit_Err <= 1'b0; |
| 736 | port1_RO_Single_Bit_Err <= 1'b0; |
| 737 | port1_RO_All_Pkts <= 1'b0; |
| 738 | port1_RO_Alt_Pkts <= 1'b0; |
| 739 | port1_RO_One_Pkt_Only <= 1'b0; |
| 740 | port1_RO_Last_Pkt_Line <= 1'b0; |
| 741 | port1_RO_Second_Pkt_Line <= 1'b0; |
| 742 | port1_RO_First_Pkt_Line <= 1'b0; |
| 743 | port1_SF_Disable_UE <= 1'b0; |
| 744 | port1_SF_Double_Bit_Err <= 1'b0; |
| 745 | port1_SF_Single_Bit_Err <= 1'b0; |
| 746 | port1_SF_All_Pkts <= 1'b0; |
| 747 | port1_SF_Alt_Pkts <= 1'b0; |
| 748 | port1_SF_One_Pkt_Only <= 1'b0; |
| 749 | port1_SF_Last_Pkt_Line <= 1'b0; |
| 750 | port1_SF_Second_Pkt_Line <= 1'b0; |
| 751 | port1_SF_First_Pkt_Line <= 1'b0; |
| 752 | Port1_WrTidsInUse <= 1'b0; |
| 753 | Port1_WrDuplicateTid <= 1'b0; |
| 754 | Port1_WrUnInitializedTID <= 1'b0; |
| 755 | Port1_WrTimedoutTids <= 1'b0; |
| 756 | Port1_WrReOrderStateLogic <= 1'b0; |
| 757 | Port1_WrReOrderStateControl <= 1'b0; |
| 758 | Port1_WrReOrderStateData0 <= 1'b0; |
| 759 | Port1_WrReOrderStateData1 <= 1'b0; |
| 760 | Port1_WrReOrderStateData2 <= 1'b0; |
| 761 | Port1_WrReOrderStateData3 <= 1'b0; |
| 762 | end |
| 763 | else if (WritePortRegister) |
| 764 | begin |
| 765 | case ({3'h0, Slave_Addr[8:2], 2'h0}) // synopsys parallel_case |
| 766 | /* 0in < case -parallel */ |
| 767 | |
| 768 | `ifdef NEPTUNE |
| 769 | `PORT0_DMA_ENABLE: Port0_DMA_List <= Slave_DataIn[23:0]; |
| 770 | `else |
| 771 | `PORT0_DMA_ENABLE: Port0_DMA_List <= {8'h0, Slave_DataIn[15:0]}; |
| 772 | `endif |
| 773 | `PORT0_PACKETS_STUFFED: Port0_WrPacketStuffed <= 1'b1; |
| 774 | `PORT0_PACKETS_XMITTED: Port0_WrPacketXmitted <= 1'b1; |
| 775 | |
| 776 | `PORT0_RO_ECC_CONTROL: begin |
| 777 | port0_RO_Disable_UE <= Slave_DataIn[31]; |
| 778 | port0_RO_Double_Bit_Err <= Slave_DataIn[17]; |
| 779 | port0_RO_Single_Bit_Err <= Slave_DataIn[16]; |
| 780 | port0_RO_All_Pkts <= Slave_DataIn[10]; |
| 781 | port0_RO_Alt_Pkts <= Slave_DataIn[9]; |
| 782 | port0_RO_One_Pkt_Only <= Slave_DataIn[8]; |
| 783 | port0_RO_Last_Pkt_Line <= Slave_DataIn[2]; |
| 784 | port0_RO_Second_Pkt_Line <= Slave_DataIn[1]; |
| 785 | port0_RO_First_Pkt_Line <= Slave_DataIn[0]; |
| 786 | end |
| 787 | |
| 788 | `PORT0_SF_ECC_CONTROL: begin |
| 789 | port0_SF_Disable_UE <= Slave_DataIn[31]; |
| 790 | port0_SF_Double_Bit_Err <= Slave_DataIn[17]; |
| 791 | port0_SF_Single_Bit_Err <= Slave_DataIn[16]; |
| 792 | port0_SF_All_Pkts <= Slave_DataIn[10]; |
| 793 | port0_SF_Alt_Pkts <= Slave_DataIn[9]; |
| 794 | port0_SF_One_Pkt_Only <= Slave_DataIn[8]; |
| 795 | port0_SF_Last_Pkt_Line <= Slave_DataIn[2]; |
| 796 | port0_SF_Second_Pkt_Line <= Slave_DataIn[1]; |
| 797 | port0_SF_First_Pkt_Line <= Slave_DataIn[0]; |
| 798 | end |
| 799 | |
| 800 | `PORT0_REORDER_TID: Port0_WrTidsInUse <= 1'b1; |
| 801 | `PORT0_REORDER_STATE0: Port0_WrDuplicateTid <= 1'b1; |
| 802 | `PORT0_REORDER_STATE1: Port0_WrUnInitializedTID <= 1'b1; |
| 803 | `PORT0_REORDER_STATE2: Port0_WrTimedoutTids <= 1'b1; |
| 804 | `PORT0_REORDER_STATE3: Port0_WrReOrderStateLogic <= 1'b1; |
| 805 | `PORT0_REORDER_CONTROL: Port0_WrReOrderStateControl <= 1'b1; |
| 806 | `PORT0_REORDER_DATA0: Port0_WrReOrderStateData0 <= 1'b1; |
| 807 | `PORT0_REORDER_DATA1: Port0_WrReOrderStateData1 <= 1'b1; |
| 808 | `PORT0_REORDER_DATA2: Port0_WrReOrderStateData2 <= 1'b1; |
| 809 | `PORT0_REORDER_DATA3: Port0_WrReOrderStateData3 <= 1'b1; |
| 810 | |
| 811 | `PORT0_PACKETS_REQUEST: Port0_WrPacketRequested <= 1'b1; |
| 812 | |
| 813 | `ifdef NEPTUNE |
| 814 | `PORT1_DMA_ENABLE: Port1_DMA_List <= Slave_DataIn[23:0]; |
| 815 | `else |
| 816 | `PORT1_DMA_ENABLE: Port1_DMA_List <= {8'h0, Slave_DataIn[15:0]}; |
| 817 | `endif |
| 818 | `PORT1_PACKETS_STUFFED: Port1_WrPacketStuffed <= 1'b1; |
| 819 | `PORT1_PACKETS_XMITTED: Port1_WrPacketXmitted <= 1'b1; |
| 820 | |
| 821 | `PORT1_RO_ECC_CONTROL: begin |
| 822 | port1_RO_Disable_UE <= Slave_DataIn[31]; |
| 823 | port1_RO_Double_Bit_Err <= Slave_DataIn[17]; |
| 824 | port1_RO_Single_Bit_Err <= Slave_DataIn[16]; |
| 825 | port1_RO_All_Pkts <= Slave_DataIn[10]; |
| 826 | port1_RO_Alt_Pkts <= Slave_DataIn[9]; |
| 827 | port1_RO_One_Pkt_Only <= Slave_DataIn[8]; |
| 828 | port1_RO_Last_Pkt_Line <= Slave_DataIn[2]; |
| 829 | port1_RO_Second_Pkt_Line <= Slave_DataIn[1]; |
| 830 | port1_RO_First_Pkt_Line <= Slave_DataIn[0]; |
| 831 | end |
| 832 | |
| 833 | `PORT1_SF_ECC_CONTROL: begin |
| 834 | port1_SF_Disable_UE <= Slave_DataIn[31]; |
| 835 | port1_SF_Double_Bit_Err <= Slave_DataIn[17]; |
| 836 | port1_SF_Single_Bit_Err <= Slave_DataIn[16]; |
| 837 | port1_SF_All_Pkts <= Slave_DataIn[10]; |
| 838 | port1_SF_Alt_Pkts <= Slave_DataIn[9]; |
| 839 | port1_SF_One_Pkt_Only <= Slave_DataIn[8]; |
| 840 | port1_SF_Last_Pkt_Line <= Slave_DataIn[2]; |
| 841 | port1_SF_Second_Pkt_Line <= Slave_DataIn[1]; |
| 842 | port1_SF_First_Pkt_Line <= Slave_DataIn[0]; |
| 843 | end |
| 844 | |
| 845 | `PORT1_REORDER_TID: Port1_WrTidsInUse <= 1'b1; |
| 846 | `PORT1_REORDER_STATE0: Port1_WrDuplicateTid <= 1'b1; |
| 847 | `PORT1_REORDER_STATE1: Port1_WrUnInitializedTID <= 1'b1; |
| 848 | `PORT1_REORDER_STATE2: Port1_WrTimedoutTids <= 1'b1; |
| 849 | `PORT1_REORDER_STATE3: Port1_WrReOrderStateLogic <= 1'b1; |
| 850 | `PORT1_REORDER_CONTROL: Port1_WrReOrderStateControl <= 1'b1; |
| 851 | `PORT1_REORDER_DATA0: Port1_WrReOrderStateData0 <= 1'b1; |
| 852 | `PORT1_REORDER_DATA1: Port1_WrReOrderStateData1 <= 1'b1; |
| 853 | `PORT1_REORDER_DATA2: Port1_WrReOrderStateData2 <= 1'b1; |
| 854 | `PORT1_REORDER_DATA3: Port1_WrReOrderStateData3 <= 1'b1; |
| 855 | `PORT1_PACKETS_REQUEST: Port1_WrPacketRequested <= 1'b1; |
| 856 | |
| 857 | endcase |
| 858 | end |
| 859 | else |
| 860 | begin |
| 861 | Port0_WrPacketRequested <= 1'b0; |
| 862 | Port0_WrPacketStuffed <= 1'b0; |
| 863 | Port0_WrPacketXmitted <= 1'b0; |
| 864 | Port0_WrTidsInUse <= 1'b0; |
| 865 | Port0_WrDuplicateTid <= 1'b0; |
| 866 | Port0_WrUnInitializedTID <= 1'b0; |
| 867 | Port0_WrTimedoutTids <= 1'b0; |
| 868 | Port0_WrReOrderStateLogic <= 1'b0; |
| 869 | Port0_WrReOrderStateControl <= 1'b0; |
| 870 | Port0_WrReOrderStateData0 <= 1'b0; |
| 871 | Port0_WrReOrderStateData1 <= 1'b0; |
| 872 | Port0_WrReOrderStateData2 <= 1'b0; |
| 873 | Port0_WrReOrderStateData3 <= 1'b0; |
| 874 | Port1_WrPacketRequested <= 1'b0; |
| 875 | Port1_WrPacketStuffed <= 1'b0; |
| 876 | Port1_WrPacketXmitted <= 1'b0; |
| 877 | Port1_WrTidsInUse <= 1'b0; |
| 878 | Port1_WrDuplicateTid <= 1'b0; |
| 879 | Port1_WrUnInitializedTID <= 1'b0; |
| 880 | Port1_WrTimedoutTids <= 1'b0; |
| 881 | Port1_WrReOrderStateLogic <= 1'b0; |
| 882 | Port1_WrReOrderStateControl <= 1'b0; |
| 883 | Port1_WrReOrderStateData0 <= 1'b0; |
| 884 | Port1_WrReOrderStateData1 <= 1'b0; |
| 885 | Port1_WrReOrderStateData2 <= 1'b0; |
| 886 | Port1_WrReOrderStateData3 <= 1'b0; |
| 887 | end |
| 888 | |
| 889 | endmodule |