| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_zcp_slv.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /*%W% %G%*/ |
| 36 | |
| 37 | /***************************************************************** |
| 38 | * |
| 39 | * File Name : niu_zcp_slv.v |
| 40 | * Author Name : John Lo |
| 41 | * Description : It contains ZCP read/write decoder, registers, |
| 42 | * |
| 43 | * Parent Module: niu_zcp.v |
| 44 | * Child Module: |
| 45 | * Interface Mod: |
| 46 | * Date Created : 3/26/04 |
| 47 | * |
| 48 | * Copyright (c) 2020, Sun Microsystems, Inc. |
| 49 | * Sun Proprietary and Confidential |
| 50 | * |
| 51 | * Modification : |
| 52 | * |
| 53 | ****************************************************************/ |
| 54 | |
| 55 | |
| 56 | `include "niu_zcp.h" |
| 57 | |
| 58 | |
| 59 | module niu_zcp_slv(/*AUTOARG*/ |
| 60 | // Outputs |
| 61 | zcp_debug_sel, ecc_chk_bypass0, double_bit_err0, single_bit_err0, |
| 62 | last_line_err0, second_line_err0, first_line_err0, |
| 63 | ecc_chk_bypass1, double_bit_err1, single_bit_err1, last_line_err1, |
| 64 | second_line_err1, first_line_err1, ecc_chk_bypass2, |
| 65 | double_bit_err2, single_bit_err2, last_line_err2, |
| 66 | second_line_err2, first_line_err2, ecc_chk_bypass3, |
| 67 | double_bit_err3, single_bit_err3, last_line_err3, |
| 68 | second_line_err3, first_line_err3, zcp_pio_ack, zcp_pio_rdata, |
| 69 | zcp_pio_err, zcp_pio_intr, handle, fn, default_rdc, table_rdc, |
| 70 | zc_rdc, tt_en, zcp_32bit_mode, req_dis, rsp_dis, par_chk_dis, |
| 71 | ecc_chk_dis, dmaw_threshold, reset_cfifo0, reset_cfifo1, |
| 72 | reset_cfifo2, reset_cfifo3, training_vector, slv_request, |
| 73 | slv_tt_index, slv_ram_addr, slv_ram_wdata, slv_ram_be, |
| 74 | va_ram_rwen, va_ram_rwen0, va_ram_rwen1, va_ram_rwen2, |
| 75 | va_ram_rwen3, va_ram_rwen4, va_ram_rwen5, va_ram_rwen6, |
| 76 | va_ram_rwen7, va_ram_ren, va_ram_wen, va_ram_ren0, va_ram_wen0, |
| 77 | va_ram_ren1, va_ram_wen1, va_ram_ren2, va_ram_wen2, va_ram_ren3, |
| 78 | va_ram_wen3, va_ram_ren4, va_ram_wen4, va_ram_ren5, va_ram_wen5, |
| 79 | va_ram_ren6, va_ram_wen6, va_ram_ren7, va_ram_wen7, st_ram_ren, |
| 80 | st_ram_wen, dn_ram_ren, dn_ram_wen, cfifo_ren0, cfifo_wen0, |
| 81 | cfifo_ren1, cfifo_wen1, cfifo_ren2, cfifo_wen2, cfifo_ren3, |
| 82 | cfifo_wen3, tt_offset0, tt_index_start0, tt_index_end0, |
| 83 | tt_index_chk0, tt_offset1, tt_index_start1, tt_index_end1, |
| 84 | tt_index_chk1, tt_offset2, tt_index_start2, tt_index_end2, |
| 85 | tt_index_chk2, tt_offset3, tt_index_start3, tt_index_end3, |
| 86 | tt_index_chk3, ds_offset0, ds_offset1, ds_offset2, ds_offset3, |
| 87 | chk_bit_data, ram_access_state, |
| 88 | // Inputs |
| 89 | clk, slv_reset, kickoff_tt_reg, ififo_state, tt_state, |
| 90 | req_load_state, req_unload_state, rsp_load_state, |
| 91 | rsp_unload_state, ififo_overrun, set_tt_program_err, |
| 92 | zcp_tt_index_err, slv_tt_index_err, rsp_tt_index_err, va_ram_perr, |
| 93 | dn_ram_perr, st_ram_perr, rrfifo_overrun, rrfifo_underrun, |
| 94 | rspfifo_uncorr_err, pio_clients_addr, pio_clients_rd, |
| 95 | pio_clients_wdata, pio_zcp_sel, zcp_dmc_dat_err0, |
| 96 | zcp_dmc_dat_err1, zcp_dmc_dat_err2, zcp_dmc_dat_err3, |
| 97 | decode_default_rdc, decode_table_rdc, decode_zc_rdc, tt_rdc_reg, |
| 98 | fflp_rdc, rdmc_zcp_func_num, page_handle, slv_accepted, |
| 99 | vram_slv_rdata, sram_slv_rdata, dram_slv_rdata, cfifo_slv_rdata0, |
| 100 | cfifo_slv_rdata1, cfifo_slv_rdata2, cfifo_slv_rdata3 |
| 101 | ); |
| 102 | |
| 103 | input clk; |
| 104 | input [21:0] slv_reset; |
| 105 | // debug signals |
| 106 | input kickoff_tt_reg; |
| 107 | input [2:0] ififo_state; |
| 108 | input [3:0] tt_state; |
| 109 | input [1:0] req_load_state; |
| 110 | input [1:0] req_unload_state; |
| 111 | input [3:0] rsp_load_state; |
| 112 | input [3:0] rsp_unload_state; |
| 113 | output [7:0] zcp_debug_sel; |
| 114 | // error handeling |
| 115 | input ififo_overrun; |
| 116 | input set_tt_program_err; |
| 117 | input zcp_tt_index_err; |
| 118 | input slv_tt_index_err; |
| 119 | input rsp_tt_index_err; |
| 120 | input va_ram_perr; |
| 121 | input dn_ram_perr; |
| 122 | input st_ram_perr; |
| 123 | input rrfifo_overrun; |
| 124 | input rrfifo_underrun; |
| 125 | input rspfifo_uncorr_err; |
| 126 | // ecc error control |
| 127 | output ecc_chk_bypass0; // per fifo ecc_chk disable |
| 128 | output double_bit_err0; |
| 129 | output single_bit_err0; |
| 130 | output last_line_err0; |
| 131 | output second_line_err0; |
| 132 | output first_line_err0; |
| 133 | output ecc_chk_bypass1; // per fifo ecc_chk disable |
| 134 | output double_bit_err1; |
| 135 | output single_bit_err1; |
| 136 | output last_line_err1; |
| 137 | output second_line_err1; |
| 138 | output first_line_err1; |
| 139 | output ecc_chk_bypass2; // per fifo ecc_chk disable |
| 140 | output double_bit_err2; |
| 141 | output single_bit_err2; |
| 142 | output last_line_err2; |
| 143 | output second_line_err2; |
| 144 | output first_line_err2; |
| 145 | output ecc_chk_bypass3; // per fifo ecc_chk disable |
| 146 | output double_bit_err3; |
| 147 | output single_bit_err3; |
| 148 | output last_line_err3; |
| 149 | output second_line_err3; |
| 150 | output first_line_err3; |
| 151 | // pio broadcast signals |
| 152 | // vlint flag_dangling_net_within_module off |
| 153 | // vlint flag_input_port_not_connected off |
| 154 | // vlint flag_net_has_no_load off |
| 155 | input [19:0] pio_clients_addr; |
| 156 | // vlint flag_dangling_net_within_module on |
| 157 | // vlint flag_input_port_not_connected on |
| 158 | // vlint flag_net_has_no_load on |
| 159 | input pio_clients_rd; |
| 160 | input [31:0] pio_clients_wdata; |
| 161 | input pio_zcp_sel; |
| 162 | output zcp_pio_ack; |
| 163 | output [63:0] zcp_pio_rdata; |
| 164 | output zcp_pio_err; |
| 165 | output zcp_pio_intr; |
| 166 | input zcp_dmc_dat_err0; |
| 167 | input zcp_dmc_dat_err1; |
| 168 | input zcp_dmc_dat_err2; |
| 169 | input zcp_dmc_dat_err3; |
| 170 | // rdc stuff |
| 171 | input decode_default_rdc; |
| 172 | input decode_table_rdc; |
| 173 | input decode_zc_rdc; |
| 174 | input [7:0] tt_rdc_reg; |
| 175 | input [7:0] fflp_rdc; |
| 176 | input [31:0] rdmc_zcp_func_num; |
| 177 | input [`PMS15:0] page_handle; // 20 bit per handle |
| 178 | output [19:0] handle; |
| 179 | output [1:0] fn; |
| 180 | output [4:0] default_rdc; |
| 181 | output [4:0] table_rdc; |
| 182 | output [4:0] zc_rdc; |
| 183 | // config stuff |
| 184 | output tt_en; |
| 185 | output zcp_32bit_mode; |
| 186 | output req_dis; |
| 187 | output rsp_dis; |
| 188 | output par_chk_dis; |
| 189 | output ecc_chk_dis; |
| 190 | output [10:0] dmaw_threshold; |
| 191 | output reset_cfifo0; |
| 192 | output reset_cfifo1; |
| 193 | output reset_cfifo2; |
| 194 | output reset_cfifo3; |
| 195 | output [31:0] training_vector; |
| 196 | // slave read/write |
| 197 | output slv_request; |
| 198 | input slv_accepted; |
| 199 | output [11:0] slv_tt_index; |
| 200 | output [10:0] slv_ram_addr; |
| 201 | output [`DN_R] slv_ram_wdata; |
| 202 | output [16:0] slv_ram_be; |
| 203 | input [1023:0] vram_slv_rdata; |
| 204 | // |
| 205 | output va_ram_rwen; |
| 206 | output va_ram_rwen0; |
| 207 | output va_ram_rwen1; |
| 208 | output va_ram_rwen2; |
| 209 | output va_ram_rwen3; |
| 210 | output va_ram_rwen4; |
| 211 | output va_ram_rwen5; |
| 212 | output va_ram_rwen6; |
| 213 | output va_ram_rwen7; |
| 214 | output va_ram_ren ; |
| 215 | output va_ram_wen ; |
| 216 | output va_ram_ren0; |
| 217 | output va_ram_wen0; |
| 218 | output va_ram_ren1; |
| 219 | output va_ram_wen1; |
| 220 | output va_ram_ren2; |
| 221 | output va_ram_wen2; |
| 222 | output va_ram_ren3; |
| 223 | output va_ram_wen3; |
| 224 | output va_ram_ren4; |
| 225 | output va_ram_wen4; |
| 226 | output va_ram_ren5; |
| 227 | output va_ram_wen5; |
| 228 | output va_ram_ren6; |
| 229 | output va_ram_wen6; |
| 230 | output va_ram_ren7; |
| 231 | output va_ram_wen7; |
| 232 | // |
| 233 | output st_ram_ren; |
| 234 | output st_ram_wen; |
| 235 | input [`ST_R] sram_slv_rdata; |
| 236 | output dn_ram_ren; |
| 237 | output dn_ram_wen; |
| 238 | input [`DN_R] dram_slv_rdata; |
| 239 | output cfifo_ren0; |
| 240 | output cfifo_wen0; |
| 241 | input [`CFIFO_W_R] cfifo_slv_rdata0; |
| 242 | output cfifo_ren1; |
| 243 | output cfifo_wen1; |
| 244 | input [`CFIFO_W_R] cfifo_slv_rdata1; |
| 245 | output cfifo_ren2; |
| 246 | output cfifo_wen2; |
| 247 | input [`CFIFO_W_R] cfifo_slv_rdata2; |
| 248 | output cfifo_ren3; |
| 249 | output cfifo_wen3; |
| 250 | input [`CFIFO_W_R] cfifo_slv_rdata3; |
| 251 | // |
| 252 | output [7:0] tt_offset0 ; |
| 253 | output [9:0] tt_index_start0 ; |
| 254 | output [9:0] tt_index_end0 ; |
| 255 | output tt_index_chk0 ; |
| 256 | output [7:0] tt_offset1 ; |
| 257 | output [9:0] tt_index_start1 ; |
| 258 | output [9:0] tt_index_end1 ; |
| 259 | output tt_index_chk1 ; |
| 260 | output [7:0] tt_offset2 ; |
| 261 | output [9:0] tt_index_start2 ; |
| 262 | output [9:0] tt_index_end2 ; |
| 263 | output tt_index_chk2 ; |
| 264 | output [7:0] tt_offset3 ; |
| 265 | output [9:0] tt_index_start3 ; |
| 266 | output [9:0] tt_index_end3 ; |
| 267 | output tt_index_chk3 ; |
| 268 | output [9:0] ds_offset0 ; |
| 269 | output [9:0] ds_offset1 ; |
| 270 | output [9:0] ds_offset2 ; |
| 271 | output [9:0] ds_offset3 ; |
| 272 | output [16:0] chk_bit_data ; |
| 273 | output [2:0] ram_access_state; // From niu_zcp_ram_access_sm of niu_zcp_ram_access_sm.v |
| 274 | |
| 275 | |
| 276 | /*AUTOWIRE*/ |
| 277 | // Beginning of automatic wires (for undeclared instantiated-module outputs) |
| 278 | wire ld_ram2reg; // From niu_zcp_ram_access_sm of niu_zcp_ram_access_sm.v |
| 279 | wire ram_ren; // From niu_zcp_ram_access_sm of niu_zcp_ram_access_sm.v |
| 280 | wire ram_wen; // From niu_zcp_ram_access_sm of niu_zcp_ram_access_sm.v |
| 281 | // End of automatics |
| 282 | |
| 283 | // |
| 284 | wire [21:0] reset = slv_reset; |
| 285 | wire reset10 = reset[10]; |
| 286 | wire ififo_overrun_stat; |
| 287 | wire [31:0] ecc_err_ctl0; |
| 288 | wire [31:0] ecc_err_ctl1; |
| 289 | wire [31:0] ecc_err_ctl2; |
| 290 | wire [31:0] ecc_err_ctl3; |
| 291 | wire ecc_chk_bypass0; // per fifo ecc_chk disable |
| 292 | wire double_bit_err0; |
| 293 | wire single_bit_err0; |
| 294 | wire last_line_err0; |
| 295 | wire second_line_err0; |
| 296 | wire first_line_err0; |
| 297 | wire ecc_chk_bypass1; // per fifo ecc_chk disable |
| 298 | wire double_bit_err1; |
| 299 | wire single_bit_err1; |
| 300 | wire last_line_err1; |
| 301 | wire second_line_err1; |
| 302 | wire first_line_err1; |
| 303 | wire ecc_chk_bypass2; // per fifo ecc_chk disable |
| 304 | wire double_bit_err2; |
| 305 | wire single_bit_err2; |
| 306 | wire last_line_err2; |
| 307 | wire second_line_err2; |
| 308 | wire first_line_err2; |
| 309 | wire ecc_chk_bypass3; // per fifo ecc_chk disable |
| 310 | wire double_bit_err3; |
| 311 | wire single_bit_err3; |
| 312 | wire last_line_err3; |
| 313 | wire second_line_err3; |
| 314 | wire first_line_err3; |
| 315 | // |
| 316 | wire va_ram_perr; |
| 317 | wire dn_ram_perr; |
| 318 | wire st_ram_perr; |
| 319 | wire va_ram_perr_pls; |
| 320 | wire dn_ram_perr_pls; |
| 321 | wire st_ram_perr_pls; |
| 322 | wire va_ram_perr_stat; |
| 323 | wire dn_ram_perr_stat; |
| 324 | wire st_ram_perr_stat; |
| 325 | wire zcp_dmc_dat_err0; |
| 326 | wire zcp_dmc_dat_err1; |
| 327 | wire zcp_dmc_dat_err2; |
| 328 | wire zcp_dmc_dat_err3; |
| 329 | reg zcp_pio_intr; |
| 330 | reg rd_wr; |
| 331 | reg zcp_sel; |
| 332 | // vlint flag_variable_assign_never_reference off |
| 333 | // vlint flag_dangling_net_within_module off |
| 334 | // vlint flag_net_has_no_load off |
| 335 | reg [19:0] addr_reg; |
| 336 | // vlint flag_net_has_no_load on |
| 337 | // vlint flag_dangling_net_within_module on |
| 338 | // vlint flag_variable_assign_never_reference on |
| 339 | reg [31:0] wr_data; |
| 340 | reg [63:0] zcp_pio_rdata; |
| 341 | reg zcp_sel_lead_d1; |
| 342 | reg zcp_sel_lead_d2; |
| 343 | reg ackgen; |
| 344 | reg zcp_pio_ack; |
| 345 | reg zcp_pio_err; |
| 346 | |
| 347 | wire addr_err; |
| 348 | // |
| 349 | reg non_qualified_addr_err; |
| 350 | reg [31:0] rd_data; |
| 351 | reg ld_config1 ; |
| 352 | reg ld_status ; |
| 353 | reg w1c_status ; |
| 354 | reg ld_mask ; |
| 355 | reg ld_buf4_region_ctl ; |
| 356 | reg ld_buf8_region_ctl ; |
| 357 | reg ld_buf16_region_ctl; |
| 358 | reg ld_buf32_region_ctl; |
| 359 | reg ld_ds4_region_ctl ; |
| 360 | reg ld_ds8_region_ctl ; |
| 361 | reg ld_ds16_region_ctl ; |
| 362 | reg ld_ds32_region_ctl ; |
| 363 | reg ld_ram_data0 ; |
| 364 | reg ld_ram_data1 ; |
| 365 | reg ld_ram_data2 ; |
| 366 | reg ld_ram_data3 ; |
| 367 | reg ld_ram_data4 ; |
| 368 | reg ld_ram_be ; |
| 369 | reg ld_ram_addr ; |
| 370 | reg ld_chk_bit_data ; |
| 371 | reg ld_reset_cfifo ; |
| 372 | reg ld_ecc_err_ctl0; |
| 373 | reg ld_ecc_err_ctl1; |
| 374 | reg ld_ecc_err_ctl2; |
| 375 | reg ld_ecc_err_ctl3; |
| 376 | reg ld_training_vector; |
| 377 | // ram selection |
| 378 | reg [`DN_R] ram_rdata ; |
| 379 | reg va_ram_rwen ; |
| 380 | reg va_ram_rwen0 ; |
| 381 | reg va_ram_rwen1 ; |
| 382 | reg va_ram_rwen2 ; |
| 383 | reg va_ram_rwen3 ; |
| 384 | reg va_ram_rwen4 ; |
| 385 | reg va_ram_rwen5 ; |
| 386 | reg va_ram_rwen6 ; |
| 387 | reg va_ram_rwen7 ; |
| 388 | reg va_ram_ren ; |
| 389 | reg va_ram_ren0 ; |
| 390 | reg va_ram_ren1 ; |
| 391 | reg va_ram_ren2 ; |
| 392 | reg va_ram_ren3 ; |
| 393 | reg va_ram_ren4 ; |
| 394 | reg va_ram_ren5 ; |
| 395 | reg va_ram_ren6 ; |
| 396 | reg va_ram_ren7 ; |
| 397 | reg st_ram_ren ; |
| 398 | reg dn_ram_ren ; |
| 399 | reg cfifo_ren0 ; |
| 400 | reg cfifo_ren1 ; |
| 401 | reg cfifo_ren2 ; |
| 402 | reg cfifo_ren3 ; |
| 403 | reg va_ram_wen ; |
| 404 | reg va_ram_wen0 ; |
| 405 | reg va_ram_wen1 ; |
| 406 | reg va_ram_wen2 ; |
| 407 | reg va_ram_wen3 ; |
| 408 | reg va_ram_wen4 ; |
| 409 | reg va_ram_wen5 ; |
| 410 | reg va_ram_wen6 ; |
| 411 | reg va_ram_wen7 ; |
| 412 | reg st_ram_wen ; |
| 413 | reg dn_ram_wen ; |
| 414 | reg cfifo_wen0 ; |
| 415 | reg cfifo_wen1 ; |
| 416 | reg cfifo_wen2 ; |
| 417 | reg cfifo_wen3 ; |
| 418 | wire [31:0] config1; |
| 419 | wire [31:0] status_dout; |
| 420 | wire [31:0] mask; |
| 421 | wire [31:0] buf4_region_ctl; |
| 422 | wire [31:0] buf8_region_ctl; |
| 423 | wire [31:0] buf16_region_ctl; |
| 424 | wire [31:0] buf32_region_ctl; |
| 425 | wire [31:0] ds4_region_ctl; |
| 426 | wire [31:0] ds8_region_ctl; |
| 427 | wire [31:0] ds16_region_ctl; |
| 428 | wire [31:0] ds32_region_ctl; |
| 429 | |
| 430 | wire [`ST_R] sram_slv_rdata; |
| 431 | wire [`DN_R] dram_slv_rdata; |
| 432 | wire [`CFIFO_W_R] cfifo_slv_rdata0; |
| 433 | wire [`CFIFO_W_R] cfifo_slv_rdata1; |
| 434 | wire [`CFIFO_W_R] cfifo_slv_rdata2; |
| 435 | wire [`CFIFO_W_R] cfifo_slv_rdata3; |
| 436 | |
| 437 | // vlint flag_dangling_net_within_module off |
| 438 | // vlint flag_net_has_no_load off |
| 439 | // vlint flag_undeclared_name_in_module off |
| 440 | wire ld_ram_addr_lead; |
| 441 | wire [31:0] ram_addr; |
| 442 | // vlint flag_dangling_net_within_module on |
| 443 | // vlint flag_net_has_no_load on |
| 444 | // vlint flag_undeclared_name_in_module on |
| 445 | |
| 446 | wire [31:0] ram_data0; |
| 447 | wire [31:0] ram_data1; |
| 448 | wire [31:0] ram_data2; |
| 449 | wire [31:0] ram_data3; |
| 450 | wire [7:0] ram_data4; |
| 451 | wire [`DN_R] ram_data; |
| 452 | wire [16:0] ram_be; |
| 453 | wire [`DN_R] slv_ram_wdata; |
| 454 | wire [16:0] slv_ram_be; |
| 455 | wire zcp_dmc_dat_err0_stat; |
| 456 | wire zcp_dmc_dat_err1_stat; |
| 457 | wire zcp_dmc_dat_err2_stat; |
| 458 | wire zcp_dmc_dat_err3_stat; |
| 459 | wire [7:0] tt_rdc_reg; |
| 460 | wire [7:0] fflp_rdc; |
| 461 | wire [3:0] tt_state; |
| 462 | wire [1:0] req_load_state; |
| 463 | wire [1:0] req_unload_state; |
| 464 | wire [3:0] rsp_load_state; |
| 465 | wire [3:0] rsp_unload_state; |
| 466 | wire zcp_tt_index_err_stat; |
| 467 | wire slv_tt_index_err_stat; |
| 468 | wire rsp_tt_index_err_stat; |
| 469 | wire tt_program_err_stat; |
| 470 | wire rspfifo_uncorr_err_stat; |
| 471 | wire rrfifo_overrun_stat; |
| 472 | wire rrfifo_underrun_stat; |
| 473 | wire ld_ram_addr_trail; |
| 474 | // rdc specific |
| 475 | // vlint flag_dangling_net_within_module off |
| 476 | // vlint flag_net_has_no_load off |
| 477 | wire [7:0] sel_rdc; |
| 478 | // vlint flag_dangling_net_within_module on |
| 479 | // vlint flag_net_has_no_load on |
| 480 | reg [3:0] rdc ; |
| 481 | wire [3:0] rdc0; |
| 482 | wire [3:0] rdc1; |
| 483 | wire [3:0] rdc2; |
| 484 | wire [3:0] rdc3; |
| 485 | wire [3:0] rdc4; |
| 486 | wire [3:0] rdc5; |
| 487 | wire [3:0] rdc6; |
| 488 | wire [3:0] rdc7; |
| 489 | wire [3:0] rdc8; |
| 490 | wire [3:0] rdc9; |
| 491 | wire [3:0] rdc10; |
| 492 | wire [3:0] rdc11; |
| 493 | wire [3:0] rdc12; |
| 494 | wire [3:0] rdc13; |
| 495 | wire [3:0] rdc14; |
| 496 | wire [3:0] rdc15; |
| 497 | wire [3:0] rdc16; |
| 498 | wire [3:0] rdc17; |
| 499 | wire [3:0] rdc18; |
| 500 | wire [3:0] rdc19; |
| 501 | wire [3:0] rdc20; |
| 502 | wire [3:0] rdc21; |
| 503 | wire [3:0] rdc22; |
| 504 | wire [3:0] rdc23; |
| 505 | wire [3:0] rdc24; |
| 506 | wire [3:0] rdc25; |
| 507 | wire [3:0] rdc26; |
| 508 | wire [3:0] rdc27; |
| 509 | wire [3:0] rdc28; |
| 510 | wire [3:0] rdc29; |
| 511 | wire [3:0] rdc30; |
| 512 | wire [3:0] rdc31; |
| 513 | wire [3:0] rdc32; |
| 514 | wire [3:0] rdc33; |
| 515 | wire [3:0] rdc34; |
| 516 | wire [3:0] rdc35; |
| 517 | wire [3:0] rdc36; |
| 518 | wire [3:0] rdc37; |
| 519 | wire [3:0] rdc38; |
| 520 | wire [3:0] rdc39; |
| 521 | wire [3:0] rdc40; |
| 522 | wire [3:0] rdc41; |
| 523 | wire [3:0] rdc42; |
| 524 | wire [3:0] rdc43; |
| 525 | wire [3:0] rdc44; |
| 526 | wire [3:0] rdc45; |
| 527 | wire [3:0] rdc46; |
| 528 | wire [3:0] rdc47; |
| 529 | wire [3:0] rdc48; |
| 530 | wire [3:0] rdc49; |
| 531 | wire [3:0] rdc50; |
| 532 | wire [3:0] rdc51; |
| 533 | wire [3:0] rdc52; |
| 534 | wire [3:0] rdc53; |
| 535 | wire [3:0] rdc54; |
| 536 | wire [3:0] rdc55; |
| 537 | wire [3:0] rdc56; |
| 538 | wire [3:0] rdc57; |
| 539 | wire [3:0] rdc58; |
| 540 | wire [3:0] rdc59; |
| 541 | wire [3:0] rdc60; |
| 542 | wire [3:0] rdc61; |
| 543 | wire [3:0] rdc62; |
| 544 | wire [3:0] rdc63; |
| 545 | wire [3:0] rdc64; |
| 546 | wire [3:0] rdc65; |
| 547 | wire [3:0] rdc66; |
| 548 | wire [3:0] rdc67; |
| 549 | wire [3:0] rdc68; |
| 550 | wire [3:0] rdc69; |
| 551 | wire [3:0] rdc70; |
| 552 | wire [3:0] rdc71; |
| 553 | wire [3:0] rdc72; |
| 554 | wire [3:0] rdc73; |
| 555 | wire [3:0] rdc74; |
| 556 | wire [3:0] rdc75; |
| 557 | wire [3:0] rdc76; |
| 558 | wire [3:0] rdc77; |
| 559 | wire [3:0] rdc78; |
| 560 | wire [3:0] rdc79; |
| 561 | wire [3:0] rdc80; |
| 562 | wire [3:0] rdc81; |
| 563 | wire [3:0] rdc82; |
| 564 | wire [3:0] rdc83; |
| 565 | wire [3:0] rdc84; |
| 566 | wire [3:0] rdc85; |
| 567 | wire [3:0] rdc86; |
| 568 | wire [3:0] rdc87; |
| 569 | wire [3:0] rdc88; |
| 570 | wire [3:0] rdc89; |
| 571 | wire [3:0] rdc90; |
| 572 | wire [3:0] rdc91; |
| 573 | wire [3:0] rdc92; |
| 574 | wire [3:0] rdc93; |
| 575 | wire [3:0] rdc94; |
| 576 | wire [3:0] rdc95; |
| 577 | wire [3:0] rdc96; |
| 578 | wire [3:0] rdc97; |
| 579 | wire [3:0] rdc98; |
| 580 | wire [3:0] rdc99; |
| 581 | wire [3:0] rdc100; |
| 582 | wire [3:0] rdc101; |
| 583 | wire [3:0] rdc102; |
| 584 | wire [3:0] rdc103; |
| 585 | wire [3:0] rdc104; |
| 586 | wire [3:0] rdc105; |
| 587 | wire [3:0] rdc106; |
| 588 | wire [3:0] rdc107; |
| 589 | wire [3:0] rdc108; |
| 590 | wire [3:0] rdc109; |
| 591 | wire [3:0] rdc110; |
| 592 | wire [3:0] rdc111; |
| 593 | wire [3:0] rdc112; |
| 594 | wire [3:0] rdc113; |
| 595 | wire [3:0] rdc114; |
| 596 | wire [3:0] rdc115; |
| 597 | wire [3:0] rdc116; |
| 598 | wire [3:0] rdc117; |
| 599 | wire [3:0] rdc118; |
| 600 | wire [3:0] rdc119; |
| 601 | wire [3:0] rdc120; |
| 602 | wire [3:0] rdc121; |
| 603 | wire [3:0] rdc122; |
| 604 | wire [3:0] rdc123; |
| 605 | wire [3:0] rdc124; |
| 606 | wire [3:0] rdc125; |
| 607 | wire [3:0] rdc126; |
| 608 | wire [3:0] rdc127; |
| 609 | |
| 610 | reg ld_rdc0; |
| 611 | reg ld_rdc1; |
| 612 | reg ld_rdc2; |
| 613 | reg ld_rdc3; |
| 614 | reg ld_rdc4; |
| 615 | reg ld_rdc5; |
| 616 | reg ld_rdc6; |
| 617 | reg ld_rdc7; |
| 618 | reg ld_rdc8; |
| 619 | reg ld_rdc9; |
| 620 | reg ld_rdc10; |
| 621 | reg ld_rdc11; |
| 622 | reg ld_rdc12; |
| 623 | reg ld_rdc13; |
| 624 | reg ld_rdc14; |
| 625 | reg ld_rdc15; |
| 626 | reg ld_rdc16; |
| 627 | reg ld_rdc17; |
| 628 | reg ld_rdc18; |
| 629 | reg ld_rdc19; |
| 630 | reg ld_rdc20; |
| 631 | reg ld_rdc21; |
| 632 | reg ld_rdc22; |
| 633 | reg ld_rdc23; |
| 634 | reg ld_rdc24; |
| 635 | reg ld_rdc25; |
| 636 | reg ld_rdc26; |
| 637 | reg ld_rdc27; |
| 638 | reg ld_rdc28; |
| 639 | reg ld_rdc29; |
| 640 | reg ld_rdc30; |
| 641 | reg ld_rdc31; |
| 642 | reg ld_rdc32; |
| 643 | reg ld_rdc33; |
| 644 | reg ld_rdc34; |
| 645 | reg ld_rdc35; |
| 646 | reg ld_rdc36; |
| 647 | reg ld_rdc37; |
| 648 | reg ld_rdc38; |
| 649 | reg ld_rdc39; |
| 650 | reg ld_rdc40; |
| 651 | reg ld_rdc41; |
| 652 | reg ld_rdc42; |
| 653 | reg ld_rdc43; |
| 654 | reg ld_rdc44; |
| 655 | reg ld_rdc45; |
| 656 | reg ld_rdc46; |
| 657 | reg ld_rdc47; |
| 658 | reg ld_rdc48; |
| 659 | reg ld_rdc49; |
| 660 | reg ld_rdc50; |
| 661 | reg ld_rdc51; |
| 662 | reg ld_rdc52; |
| 663 | reg ld_rdc53; |
| 664 | reg ld_rdc54; |
| 665 | reg ld_rdc55; |
| 666 | reg ld_rdc56; |
| 667 | reg ld_rdc57; |
| 668 | reg ld_rdc58; |
| 669 | reg ld_rdc59; |
| 670 | reg ld_rdc60; |
| 671 | reg ld_rdc61; |
| 672 | reg ld_rdc62; |
| 673 | reg ld_rdc63; |
| 674 | reg ld_rdc64; |
| 675 | reg ld_rdc65; |
| 676 | reg ld_rdc66; |
| 677 | reg ld_rdc67; |
| 678 | reg ld_rdc68; |
| 679 | reg ld_rdc69; |
| 680 | reg ld_rdc70; |
| 681 | reg ld_rdc71; |
| 682 | reg ld_rdc72; |
| 683 | reg ld_rdc73; |
| 684 | reg ld_rdc74; |
| 685 | reg ld_rdc75; |
| 686 | reg ld_rdc76; |
| 687 | reg ld_rdc77; |
| 688 | reg ld_rdc78; |
| 689 | reg ld_rdc79; |
| 690 | reg ld_rdc80; |
| 691 | reg ld_rdc81; |
| 692 | reg ld_rdc82; |
| 693 | reg ld_rdc83; |
| 694 | reg ld_rdc84; |
| 695 | reg ld_rdc85; |
| 696 | reg ld_rdc86; |
| 697 | reg ld_rdc87; |
| 698 | reg ld_rdc88; |
| 699 | reg ld_rdc89; |
| 700 | reg ld_rdc90; |
| 701 | reg ld_rdc91; |
| 702 | reg ld_rdc92; |
| 703 | reg ld_rdc93; |
| 704 | reg ld_rdc94; |
| 705 | reg ld_rdc95; |
| 706 | reg ld_rdc96; |
| 707 | reg ld_rdc97; |
| 708 | reg ld_rdc98; |
| 709 | reg ld_rdc99; |
| 710 | reg ld_rdc100; |
| 711 | reg ld_rdc101; |
| 712 | reg ld_rdc102; |
| 713 | reg ld_rdc103; |
| 714 | reg ld_rdc104; |
| 715 | reg ld_rdc105; |
| 716 | reg ld_rdc106; |
| 717 | reg ld_rdc107; |
| 718 | reg ld_rdc108; |
| 719 | reg ld_rdc109; |
| 720 | reg ld_rdc110; |
| 721 | reg ld_rdc111; |
| 722 | reg ld_rdc112; |
| 723 | reg ld_rdc113; |
| 724 | reg ld_rdc114; |
| 725 | reg ld_rdc115; |
| 726 | reg ld_rdc116; |
| 727 | reg ld_rdc117; |
| 728 | reg ld_rdc118; |
| 729 | reg ld_rdc119; |
| 730 | reg ld_rdc120; |
| 731 | reg ld_rdc121; |
| 732 | reg ld_rdc122; |
| 733 | reg ld_rdc123; |
| 734 | reg ld_rdc124; |
| 735 | reg ld_rdc125; |
| 736 | reg ld_rdc126; |
| 737 | reg ld_rdc127; |
| 738 | |
| 739 | |
| 740 | /* ----------- Read and Write logic ------------------------ */ |
| 741 | // regiser pio input signals |
| 742 | always @ (posedge clk) begin rd_wr <= pio_clients_rd; end |
| 743 | always @ (posedge clk) begin zcp_sel <= pio_zcp_sel; end |
| 744 | always @ (posedge clk) begin addr_reg <= pio_clients_addr[19:0]; end |
| 745 | always @ (posedge clk) begin wr_data <= pio_clients_wdata[31:0]; end |
| 746 | |
| 747 | // vlint flag_dangling_net_within_module off |
| 748 | // vlint flag_net_has_no_load off |
| 749 | wire zcp_sel_lead; |
| 750 | wire zcp_sel_trail; |
| 751 | wire rd_en = zcp_sel & rd_wr; |
| 752 | wire rac_ok = zcp_sel_lead & rd_wr; |
| 753 | // vlint flag_dangling_net_within_module on |
| 754 | // vlint flag_net_has_no_load on |
| 755 | wire wr_en = zcp_sel_lead & (~rd_wr) & (~addr_reg[2]); // prohibit illegal 32bit write |
| 756 | |
| 757 | zcp_pls_gen2 zcp_sel_pls_gen2(.sig_in(zcp_sel), |
| 758 | .clk(clk), |
| 759 | .lead(zcp_sel_lead), |
| 760 | .trail(zcp_sel_trail)); |
| 761 | |
| 762 | // register pio output signals |
| 763 | wire [31:0] rd_data_temp = addr_reg[2] ? 32'b0 : rd_data; // reserved field read. |
| 764 | |
| 765 | always @ (posedge clk) begin zcp_pio_rdata <= {32'b0,rd_data_temp[31:0]}; end |
| 766 | always @ (posedge clk) |
| 767 | begin zcp_sel_lead_d1 <= zcp_sel_lead; |
| 768 | zcp_sel_lead_d2 <= zcp_sel_lead_d1; |
| 769 | ackgen <= zcp_sel_lead_d2; |
| 770 | zcp_pio_ack <= ackgen; |
| 771 | end |
| 772 | |
| 773 | assign addr_err = non_qualified_addr_err & ackgen; |
| 774 | |
| 775 | always @ (posedge clk) begin zcp_pio_err <= addr_err; end |
| 776 | |
| 777 | always @ (/*AUTOSENSE*/addr_reg or buf16_region_ctl |
| 778 | or buf32_region_ctl or buf4_region_ctl or buf8_region_ctl |
| 779 | or chk_bit_data or config1 or ds16_region_ctl |
| 780 | or ds32_region_ctl or ds4_region_ctl or ds8_region_ctl |
| 781 | or ecc_err_ctl0 or ecc_err_ctl1 or ecc_err_ctl2 |
| 782 | or ecc_err_ctl3 or ififo_state or kickoff_tt_reg or mask |
| 783 | or ram_addr or ram_be or ram_data0 or ram_data1 or ram_data2 |
| 784 | or ram_data3 or ram_data4 or rdc0 or rdc1 or rdc10 or rdc100 |
| 785 | or rdc101 or rdc102 or rdc103 or rdc104 or rdc105 or rdc106 |
| 786 | or rdc107 or rdc108 or rdc109 or rdc11 or rdc110 or rdc111 |
| 787 | or rdc112 or rdc113 or rdc114 or rdc115 or rdc116 or rdc117 |
| 788 | or rdc118 or rdc119 or rdc12 or rdc120 or rdc121 or rdc122 |
| 789 | or rdc123 or rdc124 or rdc125 or rdc126 or rdc127 or rdc13 |
| 790 | or rdc14 or rdc15 or rdc16 or rdc17 or rdc18 or rdc19 |
| 791 | or rdc2 or rdc20 or rdc21 or rdc22 or rdc23 or rdc24 |
| 792 | or rdc25 or rdc26 or rdc27 or rdc28 or rdc29 or rdc3 |
| 793 | or rdc30 or rdc31 or rdc32 or rdc33 or rdc34 or rdc35 |
| 794 | or rdc36 or rdc37 or rdc38 or rdc39 or rdc4 or rdc40 |
| 795 | or rdc41 or rdc42 or rdc43 or rdc44 or rdc45 or rdc46 |
| 796 | or rdc47 or rdc48 or rdc49 or rdc5 or rdc50 or rdc51 |
| 797 | or rdc52 or rdc53 or rdc54 or rdc55 or rdc56 or rdc57 |
| 798 | or rdc58 or rdc59 or rdc6 or rdc60 or rdc61 or rdc62 |
| 799 | or rdc63 or rdc64 or rdc65 or rdc66 or rdc67 or rdc68 |
| 800 | or rdc69 or rdc7 or rdc70 or rdc71 or rdc72 or rdc73 |
| 801 | or rdc74 or rdc75 or rdc76 or rdc77 or rdc78 or rdc79 |
| 802 | or rdc8 or rdc80 or rdc81 or rdc82 or rdc83 or rdc84 |
| 803 | or rdc85 or rdc86 or rdc87 or rdc88 or rdc89 or rdc9 |
| 804 | or rdc90 or rdc91 or rdc92 or rdc93 or rdc94 or rdc95 |
| 805 | or rdc96 or rdc97 or rdc98 or rdc99 or req_load_state |
| 806 | or req_unload_state or reset_cfifo0 or reset_cfifo1 |
| 807 | or reset_cfifo2 or reset_cfifo3 or rsp_load_state |
| 808 | or rsp_unload_state or status_dout or training_vector |
| 809 | or tt_state or wr_en) |
| 810 | begin |
| 811 | non_qualified_addr_err = 0; |
| 812 | rd_data = 32'hDEADBEEF; |
| 813 | ld_config1 = 0; |
| 814 | ld_status = 0; |
| 815 | w1c_status = 0; |
| 816 | ld_mask = 0; |
| 817 | ld_buf4_region_ctl = 0; |
| 818 | ld_buf8_region_ctl = 0; |
| 819 | ld_buf16_region_ctl= 0; |
| 820 | ld_buf32_region_ctl= 0; |
| 821 | ld_ds4_region_ctl = 0; |
| 822 | ld_ds8_region_ctl = 0; |
| 823 | ld_ds16_region_ctl = 0; |
| 824 | ld_ds32_region_ctl = 0; |
| 825 | ld_ram_data0 = 0; |
| 826 | ld_ram_data1 = 0; |
| 827 | ld_ram_data2 = 0; |
| 828 | ld_ram_data3 = 0; |
| 829 | ld_ram_data4 = 0; |
| 830 | ld_ram_be = 0; |
| 831 | ld_ram_addr = 0; |
| 832 | ld_chk_bit_data = 0; |
| 833 | ld_reset_cfifo = 0; |
| 834 | ld_ecc_err_ctl0 = 0; |
| 835 | ld_ecc_err_ctl1 = 0; |
| 836 | ld_ecc_err_ctl2 = 0; |
| 837 | ld_ecc_err_ctl3 = 0; |
| 838 | ld_training_vector = 0; |
| 839 | // ram selection |
| 840 | ld_rdc0 = 0; |
| 841 | ld_rdc1 = 0; |
| 842 | ld_rdc2 = 0; |
| 843 | ld_rdc3 = 0; |
| 844 | ld_rdc4 = 0; |
| 845 | ld_rdc5 = 0; |
| 846 | ld_rdc6 = 0; |
| 847 | ld_rdc7 = 0; |
| 848 | ld_rdc8 = 0; |
| 849 | ld_rdc9 = 0; |
| 850 | ld_rdc10 = 0; |
| 851 | ld_rdc11 = 0; |
| 852 | ld_rdc12 = 0; |
| 853 | ld_rdc13 = 0; |
| 854 | ld_rdc14 = 0; |
| 855 | ld_rdc15 = 0; |
| 856 | ld_rdc16 = 0; |
| 857 | ld_rdc17 = 0; |
| 858 | ld_rdc18 = 0; |
| 859 | ld_rdc19 = 0; |
| 860 | ld_rdc20 = 0; |
| 861 | ld_rdc21 = 0; |
| 862 | ld_rdc22 = 0; |
| 863 | ld_rdc23 = 0; |
| 864 | ld_rdc24 = 0; |
| 865 | ld_rdc25 = 0; |
| 866 | ld_rdc26 = 0; |
| 867 | ld_rdc27 = 0; |
| 868 | ld_rdc28 = 0; |
| 869 | ld_rdc29 = 0; |
| 870 | ld_rdc30 = 0; |
| 871 | ld_rdc31 = 0; |
| 872 | ld_rdc32 = 0; |
| 873 | ld_rdc33 = 0; |
| 874 | ld_rdc34 = 0; |
| 875 | ld_rdc35 = 0; |
| 876 | ld_rdc36 = 0; |
| 877 | ld_rdc37 = 0; |
| 878 | ld_rdc38 = 0; |
| 879 | ld_rdc39 = 0; |
| 880 | ld_rdc40 = 0; |
| 881 | ld_rdc41 = 0; |
| 882 | ld_rdc42 = 0; |
| 883 | ld_rdc43 = 0; |
| 884 | ld_rdc44 = 0; |
| 885 | ld_rdc45 = 0; |
| 886 | ld_rdc46 = 0; |
| 887 | ld_rdc47 = 0; |
| 888 | ld_rdc48 = 0; |
| 889 | ld_rdc49 = 0; |
| 890 | ld_rdc50 = 0; |
| 891 | ld_rdc51 = 0; |
| 892 | ld_rdc52 = 0; |
| 893 | ld_rdc53 = 0; |
| 894 | ld_rdc54 = 0; |
| 895 | ld_rdc55 = 0; |
| 896 | ld_rdc56 = 0; |
| 897 | ld_rdc57 = 0; |
| 898 | ld_rdc58 = 0; |
| 899 | ld_rdc59 = 0; |
| 900 | ld_rdc60 = 0; |
| 901 | ld_rdc61 = 0; |
| 902 | ld_rdc62 = 0; |
| 903 | ld_rdc63 = 0; |
| 904 | ld_rdc64 = 0; |
| 905 | ld_rdc65 = 0; |
| 906 | ld_rdc66 = 0; |
| 907 | ld_rdc67 = 0; |
| 908 | ld_rdc68 = 0; |
| 909 | ld_rdc69 = 0; |
| 910 | ld_rdc70 = 0; |
| 911 | ld_rdc71 = 0; |
| 912 | ld_rdc72 = 0; |
| 913 | ld_rdc73 = 0; |
| 914 | ld_rdc74 = 0; |
| 915 | ld_rdc75 = 0; |
| 916 | ld_rdc76 = 0; |
| 917 | ld_rdc77 = 0; |
| 918 | ld_rdc78 = 0; |
| 919 | ld_rdc79 = 0; |
| 920 | ld_rdc80 = 0; |
| 921 | ld_rdc81 = 0; |
| 922 | ld_rdc82 = 0; |
| 923 | ld_rdc83 = 0; |
| 924 | ld_rdc84 = 0; |
| 925 | ld_rdc85 = 0; |
| 926 | ld_rdc86 = 0; |
| 927 | ld_rdc87 = 0; |
| 928 | ld_rdc88 = 0; |
| 929 | ld_rdc89 = 0; |
| 930 | ld_rdc90 = 0; |
| 931 | ld_rdc91 = 0; |
| 932 | ld_rdc92 = 0; |
| 933 | ld_rdc93 = 0; |
| 934 | ld_rdc94 = 0; |
| 935 | ld_rdc95 = 0; |
| 936 | ld_rdc96 = 0; |
| 937 | ld_rdc97 = 0; |
| 938 | ld_rdc98 = 0; |
| 939 | ld_rdc99 = 0; |
| 940 | ld_rdc100 = 0; |
| 941 | ld_rdc101 = 0; |
| 942 | ld_rdc102 = 0; |
| 943 | ld_rdc103 = 0; |
| 944 | ld_rdc104 = 0; |
| 945 | ld_rdc105 = 0; |
| 946 | ld_rdc106 = 0; |
| 947 | ld_rdc107 = 0; |
| 948 | ld_rdc108 = 0; |
| 949 | ld_rdc109 = 0; |
| 950 | ld_rdc110 = 0; |
| 951 | ld_rdc111 = 0; |
| 952 | ld_rdc112 = 0; |
| 953 | ld_rdc113 = 0; |
| 954 | ld_rdc114 = 0; |
| 955 | ld_rdc115 = 0; |
| 956 | ld_rdc116 = 0; |
| 957 | ld_rdc117 = 0; |
| 958 | ld_rdc118 = 0; |
| 959 | ld_rdc119 = 0; |
| 960 | ld_rdc120 = 0; |
| 961 | ld_rdc121 = 0; |
| 962 | ld_rdc122 = 0; |
| 963 | ld_rdc123 = 0; |
| 964 | ld_rdc124 = 0; |
| 965 | ld_rdc125 = 0; |
| 966 | ld_rdc126 = 0; |
| 967 | ld_rdc127 = 0; |
| 968 | |
| 969 | /* ----------------------------------------------- */ |
| 970 | if (~addr_reg[16]) |
| 971 | case ({addr_reg[11:3],3'b0}) // synopsys parallel_case full_case infer_mux |
| 972 | 12'h000:begin // Config1 Register |
| 973 | ld_config1 = wr_en; |
| 974 | rd_data = config1; |
| 975 | end |
| 976 | |
| 977 | /* --- Functional status register w/ w1c ---- */ |
| 978 | 12'h008:begin // Status Register |
| 979 | w1c_status = wr_en; |
| 980 | rd_data = status_dout; |
| 981 | end |
| 982 | |
| 983 | 12'h010:begin // Mask Register |
| 984 | ld_mask = wr_en; |
| 985 | rd_data = mask; |
| 986 | end |
| 987 | |
| 988 | /* --- tt va_ram access control registers --- */ |
| 989 | 12'h018:begin |
| 990 | ld_buf4_region_ctl = wr_en; |
| 991 | rd_data = buf4_region_ctl; |
| 992 | end |
| 993 | |
| 994 | 12'h020:begin |
| 995 | ld_buf8_region_ctl = wr_en; |
| 996 | rd_data = buf8_region_ctl; |
| 997 | end |
| 998 | |
| 999 | 12'h028:begin |
| 1000 | ld_buf16_region_ctl= wr_en; |
| 1001 | rd_data = buf16_region_ctl; |
| 1002 | end |
| 1003 | |
| 1004 | 12'h030:begin |
| 1005 | ld_buf32_region_ctl= wr_en; |
| 1006 | rd_data = buf32_region_ctl; |
| 1007 | end |
| 1008 | |
| 1009 | /* --- dn&st ram access control registers --- */ |
| 1010 | 12'h038:begin |
| 1011 | ld_ds4_region_ctl = wr_en; |
| 1012 | rd_data = ds4_region_ctl; |
| 1013 | end |
| 1014 | |
| 1015 | 12'h040:begin |
| 1016 | ld_ds8_region_ctl = wr_en; |
| 1017 | rd_data = ds8_region_ctl; |
| 1018 | end |
| 1019 | |
| 1020 | 12'h048:begin |
| 1021 | ld_ds16_region_ctl= wr_en; |
| 1022 | rd_data = ds16_region_ctl; |
| 1023 | end |
| 1024 | |
| 1025 | 12'h050:begin |
| 1026 | ld_ds32_region_ctl= wr_en; |
| 1027 | rd_data = ds32_region_ctl; |
| 1028 | end |
| 1029 | |
| 1030 | /* ------ zcp ram access data register ------ */ |
| 1031 | 12'h058:begin // |
| 1032 | ld_ram_data0 = wr_en; |
| 1033 | rd_data = ram_data0[31:0]; |
| 1034 | end |
| 1035 | |
| 1036 | 12'h060:begin // |
| 1037 | ld_ram_data1 = wr_en; |
| 1038 | rd_data = ram_data1[31:0]; |
| 1039 | end |
| 1040 | |
| 1041 | 12'h068:begin // |
| 1042 | ld_ram_data2 = wr_en; |
| 1043 | rd_data = ram_data2[31:0]; |
| 1044 | end |
| 1045 | |
| 1046 | 12'h070:begin // |
| 1047 | ld_ram_data3 = wr_en; |
| 1048 | rd_data = ram_data3[31:0]; |
| 1049 | end |
| 1050 | |
| 1051 | 12'h078:begin // |
| 1052 | ld_ram_data4 = wr_en; |
| 1053 | rd_data = {24'b0,ram_data4[7:0]}; |
| 1054 | end |
| 1055 | |
| 1056 | /* ------ zcp ram access bit enable register ------ */ |
| 1057 | 12'h080:begin // |
| 1058 | ld_ram_be = wr_en; |
| 1059 | rd_data = {15'b0,ram_be[16:0]}; |
| 1060 | end |
| 1061 | |
| 1062 | 12'h088:begin // |
| 1063 | ld_ram_addr = wr_en; |
| 1064 | rd_data = ram_addr[31:0]; |
| 1065 | end |
| 1066 | |
| 1067 | /* -------- par data register ------------------- */ |
| 1068 | 12'h090:begin // |
| 1069 | ld_chk_bit_data = wr_en; |
| 1070 | rd_data = {15'b0,chk_bit_data}; |
| 1071 | end |
| 1072 | |
| 1073 | /* -------- reset cfifo register ---------------- */ |
| 1074 | 12'h098:begin // |
| 1075 | ld_reset_cfifo = wr_en; |
| 1076 | rd_data = {28'b0,reset_cfifo3,reset_cfifo2,reset_cfifo1,reset_cfifo0}; |
| 1077 | end |
| 1078 | |
| 1079 | /* -------- ecc_err_ctl0 ------------------------ */ |
| 1080 | 12'h0a0:begin // |
| 1081 | ld_ecc_err_ctl0 = wr_en; |
| 1082 | rd_data = ecc_err_ctl0; |
| 1083 | end |
| 1084 | |
| 1085 | /* -------- ecc_err_ctl1 ------------------------ */ |
| 1086 | 12'h0a8:begin // |
| 1087 | ld_ecc_err_ctl1 = wr_en; |
| 1088 | rd_data = ecc_err_ctl1; |
| 1089 | end |
| 1090 | |
| 1091 | /* -------- ecc_err_ctl2 ------------------------ */ |
| 1092 | 12'h0b0:begin // |
| 1093 | ld_ecc_err_ctl2 = wr_en; |
| 1094 | rd_data = ecc_err_ctl2; |
| 1095 | end |
| 1096 | |
| 1097 | /* -------- ecc_err_ctl3 ------------------------ */ |
| 1098 | 12'h0b8:begin // |
| 1099 | ld_ecc_err_ctl3 = wr_en; |
| 1100 | rd_data = ecc_err_ctl3; |
| 1101 | end |
| 1102 | |
| 1103 | /* -------- debug_training_vector --------------- */ |
| 1104 | 12'h0c0:begin // |
| 1105 | ld_training_vector = wr_en; |
| 1106 | rd_data = training_vector; |
| 1107 | end |
| 1108 | |
| 1109 | /* -------- err log register -------------------- */ |
| 1110 | |
| 1111 | 12'h0c8: rd_data = {12'b0, |
| 1112 | kickoff_tt_reg, |
| 1113 | ififo_state[2:0], |
| 1114 | rsp_unload_state[3:0], // 4b |
| 1115 | rsp_load_state[3:0], // 4b |
| 1116 | req_unload_state[1:0], // 2b |
| 1117 | req_load_state[1:0], // 2b |
| 1118 | tt_state[3:0]}; // 4b |
| 1119 | |
| 1120 | |
| 1121 | /* --- Test status register w/o w1c ---- */ |
| 1122 | 12'h108:begin // Status Register |
| 1123 | ld_status = wr_en; |
| 1124 | rd_data = status_dout; |
| 1125 | end |
| 1126 | |
| 1127 | |
| 1128 | default:begin |
| 1129 | rd_data = 32'hdead_beef; |
| 1130 | non_qualified_addr_err = 1; |
| 1131 | end |
| 1132 | endcase |
| 1133 | |
| 1134 | /* -------- rdc registers ---------------------- */ |
| 1135 | else if (addr_reg[16]) // rdc |
| 1136 | case ({addr_reg[11:3],3'b0}) // synopsys parallel_case full_case infer_mux |
| 1137 | 12'h0 :begin |
| 1138 | ld_rdc0 = wr_en; |
| 1139 | rd_data = {28'b0,rdc0}; |
| 1140 | end |
| 1141 | |
| 1142 | 12'h8 :begin |
| 1143 | ld_rdc1 = wr_en; |
| 1144 | rd_data = {28'b0,rdc1}; |
| 1145 | end |
| 1146 | |
| 1147 | 12'h10 :begin |
| 1148 | ld_rdc2 = wr_en; |
| 1149 | rd_data = {28'b0,rdc2}; |
| 1150 | end |
| 1151 | |
| 1152 | 12'h18 :begin |
| 1153 | ld_rdc3 = wr_en; |
| 1154 | rd_data = {28'b0,rdc3}; |
| 1155 | end |
| 1156 | |
| 1157 | 12'h20 :begin |
| 1158 | ld_rdc4 = wr_en; |
| 1159 | rd_data = {28'b0,rdc4}; |
| 1160 | end |
| 1161 | |
| 1162 | 12'h28 :begin |
| 1163 | ld_rdc5 = wr_en; |
| 1164 | rd_data = {28'b0,rdc5}; |
| 1165 | end |
| 1166 | |
| 1167 | 12'h30 :begin |
| 1168 | ld_rdc6 = wr_en; |
| 1169 | rd_data = {28'b0,rdc6}; |
| 1170 | end |
| 1171 | |
| 1172 | 12'h38 :begin |
| 1173 | ld_rdc7 = wr_en; |
| 1174 | rd_data = {28'b0,rdc7}; |
| 1175 | end |
| 1176 | |
| 1177 | 12'h40 :begin |
| 1178 | ld_rdc8 = wr_en; |
| 1179 | rd_data = {28'b0,rdc8}; |
| 1180 | end |
| 1181 | |
| 1182 | 12'h48 :begin |
| 1183 | ld_rdc9 = wr_en; |
| 1184 | rd_data = {28'b0,rdc9}; |
| 1185 | end |
| 1186 | |
| 1187 | 12'h50 :begin |
| 1188 | ld_rdc10 = wr_en; |
| 1189 | rd_data = {28'b0,rdc10}; |
| 1190 | end |
| 1191 | |
| 1192 | 12'h58 :begin |
| 1193 | ld_rdc11 = wr_en; |
| 1194 | rd_data = {28'b0,rdc11}; |
| 1195 | end |
| 1196 | |
| 1197 | 12'h60 :begin |
| 1198 | ld_rdc12 = wr_en; |
| 1199 | rd_data = {28'b0,rdc12}; |
| 1200 | end |
| 1201 | |
| 1202 | 12'h68 :begin |
| 1203 | ld_rdc13 = wr_en; |
| 1204 | rd_data = {28'b0,rdc13}; |
| 1205 | end |
| 1206 | |
| 1207 | 12'h70 :begin |
| 1208 | ld_rdc14 = wr_en; |
| 1209 | rd_data = {28'b0,rdc14}; |
| 1210 | end |
| 1211 | |
| 1212 | 12'h78 :begin |
| 1213 | ld_rdc15 = wr_en; |
| 1214 | rd_data = {28'b0,rdc15}; |
| 1215 | end |
| 1216 | |
| 1217 | 12'h80 :begin |
| 1218 | ld_rdc16 = wr_en; |
| 1219 | rd_data = {28'b0,rdc16}; |
| 1220 | end |
| 1221 | |
| 1222 | 12'h88 :begin |
| 1223 | ld_rdc17 = wr_en; |
| 1224 | rd_data = {28'b0,rdc17}; |
| 1225 | end |
| 1226 | |
| 1227 | 12'h90 :begin |
| 1228 | ld_rdc18 = wr_en; |
| 1229 | rd_data = {28'b0,rdc18}; |
| 1230 | end |
| 1231 | |
| 1232 | 12'h98 :begin |
| 1233 | ld_rdc19 = wr_en; |
| 1234 | rd_data = {28'b0,rdc19}; |
| 1235 | end |
| 1236 | |
| 1237 | 12'ha0 :begin |
| 1238 | ld_rdc20 = wr_en; |
| 1239 | rd_data = {28'b0,rdc20}; |
| 1240 | end |
| 1241 | |
| 1242 | 12'ha8 :begin |
| 1243 | ld_rdc21 = wr_en; |
| 1244 | rd_data = {28'b0,rdc21}; |
| 1245 | end |
| 1246 | |
| 1247 | 12'hb0 :begin |
| 1248 | ld_rdc22 = wr_en; |
| 1249 | rd_data = {28'b0,rdc22}; |
| 1250 | end |
| 1251 | |
| 1252 | 12'hb8 :begin |
| 1253 | ld_rdc23 = wr_en; |
| 1254 | rd_data = {28'b0,rdc23}; |
| 1255 | end |
| 1256 | |
| 1257 | 12'hc0 :begin |
| 1258 | ld_rdc24 = wr_en; |
| 1259 | rd_data = {28'b0,rdc24}; |
| 1260 | end |
| 1261 | |
| 1262 | 12'hc8 :begin |
| 1263 | ld_rdc25 = wr_en; |
| 1264 | rd_data = {28'b0,rdc25}; |
| 1265 | end |
| 1266 | |
| 1267 | 12'hd0 :begin |
| 1268 | ld_rdc26 = wr_en; |
| 1269 | rd_data = {28'b0,rdc26}; |
| 1270 | end |
| 1271 | |
| 1272 | 12'hd8 :begin |
| 1273 | ld_rdc27 = wr_en; |
| 1274 | rd_data = {28'b0,rdc27}; |
| 1275 | end |
| 1276 | |
| 1277 | 12'he0 :begin |
| 1278 | ld_rdc28 = wr_en; |
| 1279 | rd_data = {28'b0,rdc28}; |
| 1280 | end |
| 1281 | |
| 1282 | 12'he8 :begin |
| 1283 | ld_rdc29 = wr_en; |
| 1284 | rd_data = {28'b0,rdc29}; |
| 1285 | end |
| 1286 | |
| 1287 | 12'hf0 :begin |
| 1288 | ld_rdc30 = wr_en; |
| 1289 | rd_data = {28'b0,rdc30}; |
| 1290 | end |
| 1291 | |
| 1292 | 12'hf8 :begin |
| 1293 | ld_rdc31 = wr_en; |
| 1294 | rd_data = {28'b0,rdc31}; |
| 1295 | end |
| 1296 | |
| 1297 | 12'h100:begin |
| 1298 | ld_rdc32 = wr_en; |
| 1299 | rd_data = {28'b0,rdc32}; |
| 1300 | end |
| 1301 | |
| 1302 | 12'h108:begin |
| 1303 | ld_rdc33 = wr_en; |
| 1304 | rd_data = {28'b0,rdc33}; |
| 1305 | end |
| 1306 | |
| 1307 | 12'h110:begin |
| 1308 | ld_rdc34 = wr_en; |
| 1309 | rd_data = {28'b0,rdc34}; |
| 1310 | end |
| 1311 | |
| 1312 | 12'h118:begin |
| 1313 | ld_rdc35 = wr_en; |
| 1314 | rd_data = {28'b0,rdc35}; |
| 1315 | end |
| 1316 | |
| 1317 | 12'h120:begin |
| 1318 | ld_rdc36 = wr_en; |
| 1319 | rd_data = {28'b0,rdc36}; |
| 1320 | end |
| 1321 | |
| 1322 | 12'h128:begin |
| 1323 | ld_rdc37 = wr_en; |
| 1324 | rd_data = {28'b0,rdc37}; |
| 1325 | end |
| 1326 | |
| 1327 | 12'h130:begin |
| 1328 | ld_rdc38 = wr_en; |
| 1329 | rd_data = {28'b0,rdc38}; |
| 1330 | end |
| 1331 | |
| 1332 | 12'h138:begin |
| 1333 | ld_rdc39 = wr_en; |
| 1334 | rd_data = {28'b0,rdc39}; |
| 1335 | end |
| 1336 | |
| 1337 | 12'h140:begin |
| 1338 | ld_rdc40 = wr_en; |
| 1339 | rd_data = {28'b0,rdc40}; |
| 1340 | end |
| 1341 | |
| 1342 | 12'h148:begin |
| 1343 | ld_rdc41 = wr_en; |
| 1344 | rd_data = {28'b0,rdc41}; |
| 1345 | end |
| 1346 | |
| 1347 | 12'h150:begin |
| 1348 | ld_rdc42 = wr_en; |
| 1349 | rd_data = {28'b0,rdc42}; |
| 1350 | end |
| 1351 | |
| 1352 | 12'h158:begin |
| 1353 | ld_rdc43 = wr_en; |
| 1354 | rd_data = {28'b0,rdc43}; |
| 1355 | end |
| 1356 | |
| 1357 | 12'h160:begin |
| 1358 | ld_rdc44 = wr_en; |
| 1359 | rd_data = {28'b0,rdc44}; |
| 1360 | end |
| 1361 | |
| 1362 | 12'h168:begin |
| 1363 | ld_rdc45 = wr_en; |
| 1364 | rd_data = {28'b0,rdc45}; |
| 1365 | end |
| 1366 | |
| 1367 | 12'h170:begin |
| 1368 | ld_rdc46 = wr_en; |
| 1369 | rd_data = {28'b0,rdc46}; |
| 1370 | end |
| 1371 | |
| 1372 | 12'h178:begin |
| 1373 | ld_rdc47 = wr_en; |
| 1374 | rd_data = {28'b0,rdc47}; |
| 1375 | end |
| 1376 | |
| 1377 | 12'h180:begin |
| 1378 | ld_rdc48 = wr_en; |
| 1379 | rd_data = {28'b0,rdc48}; |
| 1380 | end |
| 1381 | |
| 1382 | 12'h188:begin |
| 1383 | ld_rdc49 = wr_en; |
| 1384 | rd_data = {28'b0,rdc49}; |
| 1385 | end |
| 1386 | |
| 1387 | 12'h190:begin |
| 1388 | ld_rdc50 = wr_en; |
| 1389 | rd_data = {28'b0,rdc50}; |
| 1390 | end |
| 1391 | |
| 1392 | 12'h198:begin |
| 1393 | ld_rdc51 = wr_en; |
| 1394 | rd_data = {28'b0,rdc51}; |
| 1395 | end |
| 1396 | |
| 1397 | 12'h1a0:begin |
| 1398 | ld_rdc52 = wr_en; |
| 1399 | rd_data = {28'b0,rdc52}; |
| 1400 | end |
| 1401 | |
| 1402 | 12'h1a8:begin |
| 1403 | ld_rdc53 = wr_en; |
| 1404 | rd_data = {28'b0,rdc53}; |
| 1405 | end |
| 1406 | |
| 1407 | 12'h1b0:begin |
| 1408 | ld_rdc54 = wr_en; |
| 1409 | rd_data = {28'b0,rdc54}; |
| 1410 | end |
| 1411 | |
| 1412 | 12'h1b8:begin |
| 1413 | ld_rdc55 = wr_en; |
| 1414 | rd_data = {28'b0,rdc55}; |
| 1415 | end |
| 1416 | |
| 1417 | 12'h1c0:begin |
| 1418 | ld_rdc56 = wr_en; |
| 1419 | rd_data = {28'b0,rdc56}; |
| 1420 | end |
| 1421 | |
| 1422 | 12'h1c8:begin |
| 1423 | ld_rdc57 = wr_en; |
| 1424 | rd_data = {28'b0,rdc57}; |
| 1425 | end |
| 1426 | |
| 1427 | 12'h1d0:begin |
| 1428 | ld_rdc58 = wr_en; |
| 1429 | rd_data = {28'b0,rdc58}; |
| 1430 | end |
| 1431 | |
| 1432 | 12'h1d8:begin |
| 1433 | ld_rdc59 = wr_en; |
| 1434 | rd_data = {28'b0,rdc59}; |
| 1435 | end |
| 1436 | |
| 1437 | 12'h1e0:begin |
| 1438 | ld_rdc60 = wr_en; |
| 1439 | rd_data = {28'b0,rdc60}; |
| 1440 | end |
| 1441 | |
| 1442 | 12'h1e8:begin |
| 1443 | ld_rdc61 = wr_en; |
| 1444 | rd_data = {28'b0,rdc61}; |
| 1445 | end |
| 1446 | |
| 1447 | 12'h1f0:begin |
| 1448 | ld_rdc62 = wr_en; |
| 1449 | rd_data = {28'b0,rdc62}; |
| 1450 | end |
| 1451 | |
| 1452 | 12'h1f8:begin |
| 1453 | ld_rdc63 = wr_en; |
| 1454 | rd_data = {28'b0,rdc63}; |
| 1455 | end |
| 1456 | |
| 1457 | 12'h200:begin |
| 1458 | ld_rdc64 = wr_en; |
| 1459 | rd_data = {28'b0,rdc64}; |
| 1460 | end |
| 1461 | |
| 1462 | 12'h208:begin |
| 1463 | ld_rdc65 = wr_en; |
| 1464 | rd_data = {28'b0,rdc65}; |
| 1465 | end |
| 1466 | |
| 1467 | 12'h210:begin |
| 1468 | ld_rdc66 = wr_en; |
| 1469 | rd_data = {28'b0,rdc66}; |
| 1470 | end |
| 1471 | |
| 1472 | 12'h218:begin |
| 1473 | ld_rdc67 = wr_en; |
| 1474 | rd_data = {28'b0,rdc67}; |
| 1475 | end |
| 1476 | |
| 1477 | 12'h220:begin |
| 1478 | ld_rdc68 = wr_en; |
| 1479 | rd_data = {28'b0,rdc68}; |
| 1480 | end |
| 1481 | |
| 1482 | 12'h228:begin |
| 1483 | ld_rdc69 = wr_en; |
| 1484 | rd_data = {28'b0,rdc69}; |
| 1485 | end |
| 1486 | |
| 1487 | 12'h230:begin |
| 1488 | ld_rdc70 = wr_en; |
| 1489 | rd_data = {28'b0,rdc70}; |
| 1490 | end |
| 1491 | |
| 1492 | 12'h238:begin |
| 1493 | ld_rdc71 = wr_en; |
| 1494 | rd_data = {28'b0,rdc71}; |
| 1495 | end |
| 1496 | |
| 1497 | 12'h240:begin |
| 1498 | ld_rdc72 = wr_en; |
| 1499 | rd_data = {28'b0,rdc72}; |
| 1500 | end |
| 1501 | |
| 1502 | 12'h248:begin |
| 1503 | ld_rdc73 = wr_en; |
| 1504 | rd_data = {28'b0,rdc73}; |
| 1505 | end |
| 1506 | |
| 1507 | 12'h250:begin |
| 1508 | ld_rdc74 = wr_en; |
| 1509 | rd_data = {28'b0,rdc74}; |
| 1510 | end |
| 1511 | |
| 1512 | 12'h258:begin |
| 1513 | ld_rdc75 = wr_en; |
| 1514 | rd_data = {28'b0,rdc75}; |
| 1515 | end |
| 1516 | |
| 1517 | 12'h260:begin |
| 1518 | ld_rdc76 = wr_en; |
| 1519 | rd_data = {28'b0,rdc76}; |
| 1520 | end |
| 1521 | |
| 1522 | 12'h268:begin |
| 1523 | ld_rdc77 = wr_en; |
| 1524 | rd_data = {28'b0,rdc77}; |
| 1525 | end |
| 1526 | |
| 1527 | 12'h270:begin |
| 1528 | ld_rdc78 = wr_en; |
| 1529 | rd_data = {28'b0,rdc78}; |
| 1530 | end |
| 1531 | |
| 1532 | 12'h278:begin |
| 1533 | ld_rdc79 = wr_en; |
| 1534 | rd_data = {28'b0,rdc79}; |
| 1535 | end |
| 1536 | |
| 1537 | 12'h280:begin |
| 1538 | ld_rdc80 = wr_en; |
| 1539 | rd_data = {28'b0,rdc80}; |
| 1540 | end |
| 1541 | |
| 1542 | 12'h288:begin |
| 1543 | ld_rdc81 = wr_en; |
| 1544 | rd_data = {28'b0,rdc81}; |
| 1545 | end |
| 1546 | |
| 1547 | 12'h290:begin |
| 1548 | ld_rdc82 = wr_en; |
| 1549 | rd_data = {28'b0,rdc82}; |
| 1550 | end |
| 1551 | |
| 1552 | 12'h298:begin |
| 1553 | ld_rdc83 = wr_en; |
| 1554 | rd_data = {28'b0,rdc83}; |
| 1555 | end |
| 1556 | |
| 1557 | 12'h2a0:begin |
| 1558 | ld_rdc84 = wr_en; |
| 1559 | rd_data = {28'b0,rdc84}; |
| 1560 | end |
| 1561 | |
| 1562 | 12'h2a8:begin |
| 1563 | ld_rdc85 = wr_en; |
| 1564 | rd_data = {28'b0,rdc85}; |
| 1565 | end |
| 1566 | |
| 1567 | 12'h2b0:begin |
| 1568 | ld_rdc86 = wr_en; |
| 1569 | rd_data = {28'b0,rdc86}; |
| 1570 | end |
| 1571 | |
| 1572 | 12'h2b8:begin |
| 1573 | ld_rdc87 = wr_en; |
| 1574 | rd_data = {28'b0,rdc87}; |
| 1575 | end |
| 1576 | |
| 1577 | 12'h2c0:begin |
| 1578 | ld_rdc88 = wr_en; |
| 1579 | rd_data = {28'b0,rdc88}; |
| 1580 | end |
| 1581 | |
| 1582 | 12'h2c8:begin |
| 1583 | ld_rdc89 = wr_en; |
| 1584 | rd_data = {28'b0,rdc89}; |
| 1585 | end |
| 1586 | |
| 1587 | 12'h2d0:begin |
| 1588 | ld_rdc90 = wr_en; |
| 1589 | rd_data = {28'b0,rdc90}; |
| 1590 | end |
| 1591 | |
| 1592 | 12'h2d8:begin |
| 1593 | ld_rdc91 = wr_en; |
| 1594 | rd_data = {28'b0,rdc91}; |
| 1595 | end |
| 1596 | |
| 1597 | 12'h2e0:begin |
| 1598 | ld_rdc92 = wr_en; |
| 1599 | rd_data = {28'b0,rdc92}; |
| 1600 | end |
| 1601 | |
| 1602 | 12'h2e8:begin |
| 1603 | ld_rdc93 = wr_en; |
| 1604 | rd_data = {28'b0,rdc93}; |
| 1605 | end |
| 1606 | |
| 1607 | 12'h2f0:begin |
| 1608 | ld_rdc94 = wr_en; |
| 1609 | rd_data = {28'b0,rdc94}; |
| 1610 | end |
| 1611 | |
| 1612 | 12'h2f8:begin |
| 1613 | ld_rdc95 = wr_en; |
| 1614 | rd_data = {28'b0,rdc95}; |
| 1615 | end |
| 1616 | |
| 1617 | 12'h300:begin |
| 1618 | ld_rdc96 = wr_en; |
| 1619 | rd_data = {28'b0,rdc96}; |
| 1620 | end |
| 1621 | |
| 1622 | 12'h308:begin |
| 1623 | ld_rdc97 = wr_en; |
| 1624 | rd_data = {28'b0,rdc97}; |
| 1625 | end |
| 1626 | |
| 1627 | 12'h310:begin |
| 1628 | ld_rdc98 = wr_en; |
| 1629 | rd_data = {28'b0,rdc98}; |
| 1630 | end |
| 1631 | |
| 1632 | 12'h318:begin |
| 1633 | ld_rdc99 = wr_en; |
| 1634 | rd_data = {28'b0,rdc99}; |
| 1635 | end |
| 1636 | |
| 1637 | 12'h320:begin |
| 1638 | ld_rdc100 = wr_en; |
| 1639 | rd_data = {28'b0,rdc100}; |
| 1640 | end |
| 1641 | |
| 1642 | 12'h328:begin |
| 1643 | ld_rdc101 = wr_en; |
| 1644 | rd_data = {28'b0,rdc101}; |
| 1645 | end |
| 1646 | |
| 1647 | 12'h330:begin |
| 1648 | ld_rdc102 = wr_en; |
| 1649 | rd_data = {28'b0,rdc102}; |
| 1650 | end |
| 1651 | |
| 1652 | 12'h338:begin |
| 1653 | ld_rdc103 = wr_en; |
| 1654 | rd_data = {28'b0,rdc103}; |
| 1655 | end |
| 1656 | |
| 1657 | 12'h340:begin |
| 1658 | ld_rdc104 = wr_en; |
| 1659 | rd_data = {28'b0,rdc104}; |
| 1660 | end |
| 1661 | |
| 1662 | 12'h348:begin |
| 1663 | ld_rdc105 = wr_en; |
| 1664 | rd_data = {28'b0,rdc105}; |
| 1665 | end |
| 1666 | |
| 1667 | 12'h350:begin |
| 1668 | ld_rdc106 = wr_en; |
| 1669 | rd_data = {28'b0,rdc106}; |
| 1670 | end |
| 1671 | |
| 1672 | 12'h358:begin |
| 1673 | ld_rdc107 = wr_en; |
| 1674 | rd_data = {28'b0,rdc107}; |
| 1675 | end |
| 1676 | |
| 1677 | 12'h360:begin |
| 1678 | ld_rdc108 = wr_en; |
| 1679 | rd_data = {28'b0,rdc108}; |
| 1680 | end |
| 1681 | |
| 1682 | 12'h368:begin |
| 1683 | ld_rdc109 = wr_en; |
| 1684 | rd_data = {28'b0,rdc109}; |
| 1685 | end |
| 1686 | |
| 1687 | 12'h370:begin |
| 1688 | ld_rdc110 = wr_en; |
| 1689 | rd_data = {28'b0,rdc110}; |
| 1690 | end |
| 1691 | |
| 1692 | 12'h378:begin |
| 1693 | ld_rdc111 = wr_en; |
| 1694 | rd_data = {28'b0,rdc111}; |
| 1695 | end |
| 1696 | |
| 1697 | 12'h380:begin |
| 1698 | ld_rdc112 = wr_en; |
| 1699 | rd_data = {28'b0,rdc112}; |
| 1700 | end |
| 1701 | |
| 1702 | 12'h388:begin |
| 1703 | ld_rdc113 = wr_en; |
| 1704 | rd_data = {28'b0,rdc113}; |
| 1705 | end |
| 1706 | |
| 1707 | 12'h390:begin |
| 1708 | ld_rdc114 = wr_en; |
| 1709 | rd_data = {28'b0,rdc114}; |
| 1710 | end |
| 1711 | |
| 1712 | 12'h398:begin |
| 1713 | ld_rdc115 = wr_en; |
| 1714 | rd_data = {28'b0,rdc115}; |
| 1715 | end |
| 1716 | |
| 1717 | 12'h3a0:begin |
| 1718 | ld_rdc116 = wr_en; |
| 1719 | rd_data = {28'b0,rdc116}; |
| 1720 | end |
| 1721 | |
| 1722 | 12'h3a8:begin |
| 1723 | ld_rdc117 = wr_en; |
| 1724 | rd_data = {28'b0,rdc117}; |
| 1725 | end |
| 1726 | |
| 1727 | 12'h3b0:begin |
| 1728 | ld_rdc118 = wr_en; |
| 1729 | rd_data = {28'b0,rdc118}; |
| 1730 | end |
| 1731 | |
| 1732 | 12'h3b8:begin |
| 1733 | ld_rdc119 = wr_en; |
| 1734 | rd_data = {28'b0,rdc119}; |
| 1735 | end |
| 1736 | |
| 1737 | 12'h3c0:begin |
| 1738 | ld_rdc120 = wr_en; |
| 1739 | rd_data = {28'b0,rdc120}; |
| 1740 | end |
| 1741 | |
| 1742 | 12'h3c8:begin |
| 1743 | ld_rdc121 = wr_en; |
| 1744 | rd_data = {28'b0,rdc121}; |
| 1745 | end |
| 1746 | |
| 1747 | 12'h3d0:begin |
| 1748 | ld_rdc122 = wr_en; |
| 1749 | rd_data = {28'b0,rdc122}; |
| 1750 | end |
| 1751 | |
| 1752 | 12'h3d8:begin |
| 1753 | ld_rdc123 = wr_en; |
| 1754 | rd_data = {28'b0,rdc123}; |
| 1755 | end |
| 1756 | |
| 1757 | 12'h3e0:begin |
| 1758 | ld_rdc124 = wr_en; |
| 1759 | rd_data = {28'b0,rdc124}; |
| 1760 | end |
| 1761 | |
| 1762 | 12'h3e8:begin |
| 1763 | ld_rdc125 = wr_en; |
| 1764 | rd_data = {28'b0,rdc125}; |
| 1765 | end |
| 1766 | |
| 1767 | 12'h3f0:begin |
| 1768 | ld_rdc126 = wr_en; |
| 1769 | rd_data = {28'b0,rdc126}; |
| 1770 | end |
| 1771 | |
| 1772 | 12'h3f8:begin |
| 1773 | ld_rdc127 = wr_en; |
| 1774 | rd_data = {28'b0,rdc127}; |
| 1775 | end |
| 1776 | |
| 1777 | default:begin |
| 1778 | rd_data = 32'hdead_beef; |
| 1779 | non_qualified_addr_err = 1; |
| 1780 | end |
| 1781 | endcase |
| 1782 | |
| 1783 | else begin |
| 1784 | rd_data = 32'hdead_beef; |
| 1785 | non_qualified_addr_err = 1; |
| 1786 | end |
| 1787 | end // always @ (... |
| 1788 | |
| 1789 | |
| 1790 | /* -------------------- config1 Register -------------------- */ |
| 1791 | |
| 1792 | zcp_xREG #(25) config1_xREG (.clk(clk), |
| 1793 | .reset(reset[0]), |
| 1794 | .en(ld_config1), |
| 1795 | .din(wr_data[24:0]), |
| 1796 | .qout(config1[24:0])); |
| 1797 | |
| 1798 | |
| 1799 | wire tt_en = config1[0]; |
| 1800 | wire req_dis = config1[1]; |
| 1801 | wire rsp_dis = config1[2]; |
| 1802 | wire par_chk_dis = config1[3]; // disable parity check |
| 1803 | wire ecc_chk_dis = config1[4]; |
| 1804 | wire [10:0] dmaw_threshold = config1[15:5]; |
| 1805 | wire [7:0] zcp_debug_sel = config1[23:16]; |
| 1806 | wire zcp_32bit_mode = config1[24]; |
| 1807 | assign config1[31:25] = 0; |
| 1808 | |
| 1809 | /* --------------------- Status Register -------------------- */ |
| 1810 | |
| 1811 | zcp_w1c_ff stat0 (.clk(clk),.reset(reset[1]),.set(zcp_dmc_dat_err0),.ld(ld_status),.w1c(w1c_status),.w1c_data(wr_data[0]),.q(zcp_dmc_dat_err0_stat)); |
| 1812 | zcp_w1c_ff stat1 (.clk(clk),.reset(reset[1]),.set(zcp_dmc_dat_err1),.ld(ld_status),.w1c(w1c_status),.w1c_data(wr_data[1]),.q(zcp_dmc_dat_err1_stat)); |
| 1813 | zcp_w1c_ff stat2 (.clk(clk),.reset(reset[1]),.set(zcp_dmc_dat_err2),.ld(ld_status),.w1c(w1c_status),.w1c_data(wr_data[2]),.q(zcp_dmc_dat_err2_stat)); |
| 1814 | zcp_w1c_ff stat3 (.clk(clk),.reset(reset[1]),.set(zcp_dmc_dat_err3),.ld(ld_status),.w1c(w1c_status),.w1c_data(wr_data[3]),.q(zcp_dmc_dat_err3_stat)); |
| 1815 | |
| 1816 | zcp_w1c_ff stat4 (.clk(clk),.reset(reset[1]),.set(zcp_tt_index_err),.ld(ld_status),.w1c(w1c_status),.w1c_data(wr_data[4]),.q(zcp_tt_index_err_stat)); |
| 1817 | zcp_w1c_ff stat5 (.clk(clk),.reset(reset[1]),.set(slv_tt_index_err),.ld(ld_status),.w1c(w1c_status),.w1c_data(wr_data[5]),.q(slv_tt_index_err_stat)); |
| 1818 | zcp_w1c_ff stat6 (.clk(clk),.reset(reset[1]),.set(rsp_tt_index_err),.ld(ld_status),.w1c(w1c_status),.w1c_data(wr_data[6]),.q(rsp_tt_index_err_stat)); |
| 1819 | |
| 1820 | zcp_w1c_ff stat7 (.clk(clk),.reset(reset[1]),.set(set_tt_program_err),.ld(ld_status),.w1c(w1c_status),.w1c_data(wr_data[7]),.q(tt_program_err_stat)); |
| 1821 | |
| 1822 | // vlint flag_null_instance_port off |
| 1823 | // vlint flag_unmatched_port_connect_in_inst off |
| 1824 | zcp_pls_gen2_reg va_ram_perr_pls_gen2(.clk(clk),.sig_in(va_ram_perr),.lead(va_ram_perr_pls),.trail()); |
| 1825 | zcp_pls_gen2_reg dn_ram_perr_pls_gen2(.clk(clk),.sig_in(dn_ram_perr),.lead(dn_ram_perr_pls),.trail()); |
| 1826 | zcp_pls_gen2_reg st_ram_perr_pls_gen2(.clk(clk),.sig_in(st_ram_perr),.lead(st_ram_perr_pls),.trail()); |
| 1827 | // vlint flag_null_instance_port on |
| 1828 | // vlint flag_unmatched_port_connect_in_inst on |
| 1829 | |
| 1830 | zcp_w1c_ff stat8 (.clk(clk),.reset(reset[1]),.set(va_ram_perr_pls),.ld(ld_status),.w1c(w1c_status),.w1c_data(wr_data[8]), .q(va_ram_perr_stat)); |
| 1831 | zcp_w1c_ff stat9 (.clk(clk),.reset(reset[1]),.set(dn_ram_perr_pls),.ld(ld_status),.w1c(w1c_status),.w1c_data(wr_data[9]), .q(dn_ram_perr_stat)); |
| 1832 | zcp_w1c_ff stat10(.clk(clk),.reset(reset[1]),.set(st_ram_perr_pls),.ld(ld_status),.w1c(w1c_status),.w1c_data(wr_data[10]),.q(st_ram_perr_stat)); |
| 1833 | |
| 1834 | zcp_w1c_ff stat11(.clk(clk),.reset(reset[1]),.set(ififo_overrun), .ld(ld_status),.w1c(w1c_status),.w1c_data(wr_data[11]),.q(ififo_overrun_stat)); |
| 1835 | zcp_w1c_ff stat12(.clk(clk),.reset(reset[1]),.set(rspfifo_uncorr_err),.ld(ld_status),.w1c(w1c_status),.w1c_data(wr_data[12]),.q(rspfifo_uncorr_err_stat)); |
| 1836 | |
| 1837 | zcp_w1c_ff stat14(.clk(clk),.reset(reset[1]),.set(rrfifo_overrun), .ld(ld_status),.w1c(w1c_status),.w1c_data(wr_data[14]),.q(rrfifo_overrun_stat)); |
| 1838 | zcp_w1c_ff stat15(.clk(clk),.reset(reset[1]),.set(rrfifo_underrun),.ld(ld_status),.w1c(w1c_status),.w1c_data(wr_data[15]),.q(rrfifo_underrun_stat)); |
| 1839 | |
| 1840 | assign status_dout[0] = zcp_dmc_dat_err0_stat; |
| 1841 | assign status_dout[1] = zcp_dmc_dat_err1_stat; |
| 1842 | assign status_dout[2] = zcp_dmc_dat_err2_stat; |
| 1843 | assign status_dout[3] = zcp_dmc_dat_err3_stat; |
| 1844 | assign status_dout[4] = zcp_tt_index_err_stat; |
| 1845 | assign status_dout[5] = slv_tt_index_err_stat; |
| 1846 | assign status_dout[6] = rsp_tt_index_err_stat; |
| 1847 | assign status_dout[7] = tt_program_err_stat; |
| 1848 | assign status_dout[8] = va_ram_perr_stat; |
| 1849 | assign status_dout[9] = dn_ram_perr_stat; |
| 1850 | assign status_dout[10] = st_ram_perr_stat; |
| 1851 | assign status_dout[11] = ififo_overrun_stat; |
| 1852 | assign status_dout[12] = rspfifo_uncorr_err_stat; |
| 1853 | assign status_dout[13] = 0; |
| 1854 | assign status_dout[14] = rrfifo_overrun_stat; |
| 1855 | assign status_dout[15] = rrfifo_underrun_stat; |
| 1856 | assign status_dout[31:16] = 0; |
| 1857 | |
| 1858 | // Interrupt generation |
| 1859 | |
| 1860 | wire pio_intr = status_dout[0] & mask[0] | |
| 1861 | status_dout[1] & mask[1] | |
| 1862 | status_dout[2] & mask[2] | |
| 1863 | status_dout[3] & mask[3] | |
| 1864 | status_dout[4] & mask[4] | |
| 1865 | status_dout[5] & mask[5] | |
| 1866 | status_dout[6] & mask[6] | |
| 1867 | status_dout[7] & mask[7] | |
| 1868 | status_dout[8] & mask[8] | |
| 1869 | status_dout[9] & mask[9] | |
| 1870 | status_dout[10] & mask[10] | |
| 1871 | status_dout[11] & mask[11] | |
| 1872 | status_dout[12] & mask[12] | |
| 1873 | status_dout[14] & mask[14] | |
| 1874 | status_dout[15] & mask[15] ; |
| 1875 | |
| 1876 | |
| 1877 | always @ (posedge clk) begin zcp_pio_intr <= pio_intr; end |
| 1878 | |
| 1879 | |
| 1880 | /* ---------------------- Mask Register --------------------- */ |
| 1881 | zcp_xREG2 #(16) mask_xREG2( |
| 1882 | .clk(clk), |
| 1883 | .reset(reset[1]), |
| 1884 | .reset_value({16{1'b1}}), |
| 1885 | .load(ld_mask), |
| 1886 | .din(wr_data[15:0]), |
| 1887 | .qout(mask[15:0])); |
| 1888 | |
| 1889 | assign mask[31:16] = 16'b0; |
| 1890 | |
| 1891 | /* ---------------------- 4 buffer region_ctl --------------- */ |
| 1892 | zcp_xREG #(32) buf4_region_ctl_xREG( |
| 1893 | .clk(clk), |
| 1894 | .reset(reset[2]), |
| 1895 | .en(ld_buf4_region_ctl), |
| 1896 | .din(wr_data[31:0]), |
| 1897 | .qout(buf4_region_ctl[31:0])); |
| 1898 | |
| 1899 | wire [7:0] tt_offset0 = buf4_region_ctl[7:0]; |
| 1900 | wire [9:0] tt_index_start0 = buf4_region_ctl[19:10]; |
| 1901 | wire [9:0] tt_index_end0 = buf4_region_ctl[29:20]; |
| 1902 | wire tt_index_chk0 = buf4_region_ctl[30]; |
| 1903 | // vlint flag_dangling_net_within_module off |
| 1904 | // vlint flag_net_has_no_load off |
| 1905 | wire tt_index_rsv0 = buf4_region_ctl[31]; |
| 1906 | // vlint flag_net_has_no_load on |
| 1907 | // vlint flag_dangling_net_within_module on |
| 1908 | |
| 1909 | /* ---------------------- 8 buffer region_ctl --------------- */ |
| 1910 | zcp_xREG #(32) buf8_region_ctl_xREG( |
| 1911 | .clk(clk), |
| 1912 | .reset(reset[2]), |
| 1913 | .en(ld_buf8_region_ctl), |
| 1914 | .din(wr_data[31:0]), |
| 1915 | .qout(buf8_region_ctl[31:0])); |
| 1916 | |
| 1917 | wire [7:0] tt_offset1 = buf8_region_ctl[7:0]; |
| 1918 | wire [9:0] tt_index_start1 = buf8_region_ctl[19:10]; |
| 1919 | wire [9:0] tt_index_end1 = buf8_region_ctl[29:20]; |
| 1920 | wire tt_index_chk1 = buf8_region_ctl[30]; |
| 1921 | // vlint flag_dangling_net_within_module off |
| 1922 | // vlint flag_net_has_no_load off |
| 1923 | wire tt_index_rsv1 = buf8_region_ctl[31]; |
| 1924 | // vlint flag_net_has_no_load on |
| 1925 | // vlint flag_dangling_net_within_module on |
| 1926 | |
| 1927 | /* --------------------- 16 buffer region_ctl --------------- */ |
| 1928 | zcp_xREG #(32) buf16_region_ctl_xREG( |
| 1929 | .clk(clk), |
| 1930 | .reset(reset[3]), |
| 1931 | .en(ld_buf16_region_ctl), |
| 1932 | .din(wr_data[31:0]), |
| 1933 | .qout(buf16_region_ctl[31:0])); |
| 1934 | |
| 1935 | wire [7:0] tt_offset2 = buf16_region_ctl[7:0]; |
| 1936 | wire [9:0] tt_index_start2 = buf16_region_ctl[19:10]; |
| 1937 | wire [9:0] tt_index_end2 = buf16_region_ctl[29:20]; |
| 1938 | wire tt_index_chk2 = buf16_region_ctl[30]; |
| 1939 | // vlint flag_dangling_net_within_module off |
| 1940 | // vlint flag_net_has_no_load off |
| 1941 | wire tt_index_rsv2 = buf16_region_ctl[31]; |
| 1942 | // vlint flag_net_has_no_load on |
| 1943 | // vlint flag_dangling_net_within_module on |
| 1944 | |
| 1945 | /* --------------------- 32 buffer region_ctl --------------- */ |
| 1946 | zcp_xREG #(32) buf32_region_ctl_xREG( |
| 1947 | .clk(clk), |
| 1948 | .reset(reset[3]), |
| 1949 | .en(ld_buf32_region_ctl), |
| 1950 | .din(wr_data[31:0]), |
| 1951 | .qout(buf32_region_ctl[31:0])); |
| 1952 | |
| 1953 | wire [7:0] tt_offset3 = buf32_region_ctl[7:0]; |
| 1954 | wire [9:0] tt_index_start3 = buf32_region_ctl[19:10]; |
| 1955 | wire [9:0] tt_index_end3 = buf32_region_ctl[29:20]; |
| 1956 | wire tt_index_chk3 = buf32_region_ctl[30]; |
| 1957 | // vlint flag_dangling_net_within_module off |
| 1958 | // vlint flag_net_has_no_load off |
| 1959 | wire tt_index_rsv3 = buf32_region_ctl[31]; |
| 1960 | // vlint flag_net_has_no_load on |
| 1961 | // vlint flag_dangling_net_within_module on |
| 1962 | |
| 1963 | // ds stands for dynamic and static table ram. |
| 1964 | /* ------------------- ds 4 buffer region_ctl --------------- */ |
| 1965 | zcp_xREG #(10) ds4_region_ctl_xREG( |
| 1966 | .clk(clk), |
| 1967 | .reset(reset[4]), |
| 1968 | .en(ld_ds4_region_ctl), |
| 1969 | .din(wr_data[9:0]), |
| 1970 | .qout(ds4_region_ctl[9:0])); |
| 1971 | |
| 1972 | wire [9:0] ds_offset0 = ds4_region_ctl[9:0]; |
| 1973 | assign ds4_region_ctl[31:10] = 0; |
| 1974 | |
| 1975 | /* ------------------- ds8 buffer region_ctl --------------- */ |
| 1976 | zcp_xREG #(10) ds8_region_ctl_xREG( |
| 1977 | .clk(clk), |
| 1978 | .reset(reset[4]), |
| 1979 | .en(ld_ds8_region_ctl), |
| 1980 | .din(wr_data[9:0]), |
| 1981 | .qout(ds8_region_ctl[9:0])); |
| 1982 | |
| 1983 | wire [9:0] ds_offset1 = ds8_region_ctl[9:0]; |
| 1984 | assign ds8_region_ctl[31:10] = 0; |
| 1985 | |
| 1986 | /* ------------------- ds16 buffer region_ctl --------------- */ |
| 1987 | zcp_xREG #(10) ds16_region_ctl_xREG( |
| 1988 | .clk(clk), |
| 1989 | .reset(reset[4]), |
| 1990 | .en(ld_ds16_region_ctl), |
| 1991 | .din(wr_data[9:0]), |
| 1992 | .qout(ds16_region_ctl[9:0])); |
| 1993 | |
| 1994 | wire [9:0] ds_offset2 = ds16_region_ctl[9:0]; |
| 1995 | assign ds16_region_ctl[31:10]= 0; |
| 1996 | |
| 1997 | /* ------------------- ds32 buffer region_ctl --------------- */ |
| 1998 | zcp_xREG #(10) ds32_region_ctl_xREG( |
| 1999 | .clk(clk), |
| 2000 | .reset(reset[4]), |
| 2001 | .en(ld_ds32_region_ctl), |
| 2002 | .din(wr_data[9:0]), |
| 2003 | .qout(ds32_region_ctl[9:0])); |
| 2004 | |
| 2005 | wire [9:0] ds_offset3 = ds32_region_ctl[9:0]; |
| 2006 | assign ds32_region_ctl[31:10]= 0; |
| 2007 | |
| 2008 | /* ----- ram access data registers ------ */ |
| 2009 | zcp_RegLd #(32) ram_data0_RegLd( |
| 2010 | .clk(clk), |
| 2011 | .reset(reset[5]), |
| 2012 | .ld(ld_ram2reg), |
| 2013 | .ld_value(ram_rdata[31:0]), |
| 2014 | .we(ld_ram_data0), |
| 2015 | .din(wr_data[31:0]), |
| 2016 | .qout(ram_data0)); |
| 2017 | |
| 2018 | zcp_RegLd #(32) ram_data1_RegLd( |
| 2019 | .clk(clk), |
| 2020 | .reset(reset[5]), |
| 2021 | .ld(ld_ram2reg), |
| 2022 | .ld_value(ram_rdata[63:32]), |
| 2023 | .we(ld_ram_data1), |
| 2024 | .din(wr_data[31:0]), |
| 2025 | .qout(ram_data1)); |
| 2026 | |
| 2027 | zcp_RegLd #(32) ram_data2_RegLd( |
| 2028 | .clk(clk), |
| 2029 | .reset(reset[6]), |
| 2030 | .ld(ld_ram2reg), |
| 2031 | .ld_value(ram_rdata[95:64]), |
| 2032 | .we(ld_ram_data2), |
| 2033 | .din(wr_data[31:0]), |
| 2034 | .qout(ram_data2)); |
| 2035 | zcp_RegLd #(32) ram_data3_RegLd( |
| 2036 | .clk(clk), |
| 2037 | .reset(reset[6]), |
| 2038 | .ld(ld_ram2reg), |
| 2039 | .ld_value(ram_rdata[127:96]), |
| 2040 | .we(ld_ram_data3), |
| 2041 | .din(wr_data[31:0]), |
| 2042 | .qout(ram_data3)); |
| 2043 | |
| 2044 | zcp_RegLd #(8) ram_data4_RegLd( |
| 2045 | .clk(clk), |
| 2046 | .reset(reset[7]), |
| 2047 | .ld(ld_ram2reg), |
| 2048 | .ld_value(ram_rdata[135:128]), |
| 2049 | .we(ld_ram_data4), |
| 2050 | .din(wr_data[7:0]), |
| 2051 | .qout(ram_data4)); |
| 2052 | |
| 2053 | assign ram_data = {ram_data4,ram_data3,ram_data2,ram_data1,ram_data0}; |
| 2054 | |
| 2055 | /* ------ ram access byte enable registers ------ */ |
| 2056 | zcp_xREG #(17) ram_be_xREG( |
| 2057 | .din(wr_data[16:0]), |
| 2058 | .clk(clk), |
| 2059 | .en(ld_ram_be), |
| 2060 | .reset(reset[7]), |
| 2061 | .qout(ram_be[16:0])); |
| 2062 | |
| 2063 | /* ----- ram access address register ------ */ |
| 2064 | zcp_xREG #(31) ram_addr_xREG( |
| 2065 | .din(wr_data[30:0]), |
| 2066 | .clk(clk), |
| 2067 | .en(ld_ram_addr), |
| 2068 | .reset(reset[7]), |
| 2069 | .qout(ram_addr[30:0])); |
| 2070 | |
| 2071 | |
| 2072 | zcp_pls_gen2_reg slv_ram_pls_gen2_reg(.clk(clk),.sig_in(ld_ram_addr),.lead(ld_ram_addr_lead),.trail(ld_ram_addr_trail)); |
| 2073 | |
| 2074 | wire [10:0] slv_ram_addr = ram_addr[10:0]; // For accessing cfifo only. |
| 2075 | wire [4:0] ram_sel = ram_addr[16:12]; |
| 2076 | wire [11:0] slv_tt_index = ram_addr[28:17]; // For accessing va_ram, st_ram, dn_ram. |
| 2077 | wire rw = ram_addr[30]; |
| 2078 | |
| 2079 | assign ram_addr[31] = |ram_access_state; // ram busy |
| 2080 | assign slv_ram_wdata = ram_data; |
| 2081 | assign slv_ram_be = ram_be; |
| 2082 | |
| 2083 | /* -------- par data register ------------------- */ |
| 2084 | zcp_xREG #(17) chk_bit_data_xREG( |
| 2085 | .din(wr_data[16:0]), |
| 2086 | .clk(clk), |
| 2087 | .en(ld_chk_bit_data), |
| 2088 | .reset(reset[8]), |
| 2089 | .qout(chk_bit_data[16:0])); |
| 2090 | |
| 2091 | /* -------- reset cfifo register ---------------- */ |
| 2092 | |
| 2093 | zcp_xREG #(4) reset_cfifo_xREG( |
| 2094 | .din(wr_data[3:0]), |
| 2095 | .clk(clk), |
| 2096 | .en(ld_reset_cfifo), |
| 2097 | .reset(reset[8]), |
| 2098 | .qout({reset_cfifo3,reset_cfifo2,reset_cfifo1,reset_cfifo0})); |
| 2099 | |
| 2100 | /* -------- ecc_err_ctl ------------------------- */ |
| 2101 | wire [5:0] ecc_err_wd = {wr_data[31],wr_data[17:16],wr_data[2:0]}; // 6b |
| 2102 | |
| 2103 | zcp_xREG #(6) ecc_err_ctl0_xREG(.clk(clk),.reset(reset[8]),.en(ld_ecc_err_ctl0),.din(ecc_err_wd[5:0]), |
| 2104 | .qout({ecc_err_ctl0[31],ecc_err_ctl0[17:16],ecc_err_ctl0[2:0]})); |
| 2105 | |
| 2106 | zcp_xREG #(6) ecc_err_ctl1_xREG(.clk(clk),.reset(reset[8]),.en(ld_ecc_err_ctl1),.din(ecc_err_wd[5:0]), |
| 2107 | .qout({ecc_err_ctl1[31],ecc_err_ctl1[17:16],ecc_err_ctl1[2:0]})); |
| 2108 | |
| 2109 | zcp_xREG #(6) ecc_err_ctl2_xREG(.clk(clk),.reset(reset[8]),.en(ld_ecc_err_ctl2),.din(ecc_err_wd[5:0]), |
| 2110 | .qout({ecc_err_ctl2[31],ecc_err_ctl2[17:16],ecc_err_ctl2[2:0]})); |
| 2111 | |
| 2112 | zcp_xREG #(6) ecc_err_ctl3_xREG(.clk(clk),.reset(reset[8]),.en(ld_ecc_err_ctl3),.din(ecc_err_wd[5:0]), |
| 2113 | .qout({ecc_err_ctl3[31],ecc_err_ctl3[17:16],ecc_err_ctl3[2:0]})); |
| 2114 | |
| 2115 | assign ecc_chk_bypass0 = ecc_err_ctl0[31]; // per fifo ecc_chk disable |
| 2116 | assign ecc_err_ctl0[30:18] = 0; |
| 2117 | assign double_bit_err0 = ecc_err_ctl0[17]; |
| 2118 | assign single_bit_err0 = ecc_err_ctl0[16]; |
| 2119 | assign ecc_err_ctl0[15:11] = 0; |
| 2120 | assign ecc_err_ctl0[10] = 1'b1; // all packets |
| 2121 | assign ecc_err_ctl0[9:3] = 0; |
| 2122 | assign last_line_err0 = ecc_err_ctl0[2] ; |
| 2123 | assign second_line_err0 = ecc_err_ctl0[1] ; |
| 2124 | assign first_line_err0 = ecc_err_ctl0[0] ; |
| 2125 | |
| 2126 | assign ecc_err_ctl1[30:18] = 0; |
| 2127 | assign ecc_chk_bypass1 = ecc_err_ctl1[31]; // per fifo ecc_chk disable |
| 2128 | assign double_bit_err1 = ecc_err_ctl1[17]; |
| 2129 | assign single_bit_err1 = ecc_err_ctl1[16]; |
| 2130 | assign ecc_err_ctl1[15:11] = 0; |
| 2131 | assign ecc_err_ctl1[10] = 1'b1; // all packets |
| 2132 | assign ecc_err_ctl1[9:3] = 0; |
| 2133 | assign last_line_err1 = ecc_err_ctl1[2] ; |
| 2134 | assign second_line_err1 = ecc_err_ctl1[1] ; |
| 2135 | assign first_line_err1 = ecc_err_ctl1[0] ; |
| 2136 | |
| 2137 | assign ecc_err_ctl2[30:18] = 0; |
| 2138 | assign ecc_chk_bypass2 = ecc_err_ctl2[31]; // per fifo ecc_chk disable |
| 2139 | assign double_bit_err2 = ecc_err_ctl2[17]; |
| 2140 | assign single_bit_err2 = ecc_err_ctl2[16]; |
| 2141 | assign ecc_err_ctl2[15:11] = 0; |
| 2142 | assign ecc_err_ctl2[10] = 1'b1; // all packets |
| 2143 | assign ecc_err_ctl2[9:3] = 0; |
| 2144 | assign last_line_err2 = ecc_err_ctl2[2] ; |
| 2145 | assign second_line_err2 = ecc_err_ctl2[1] ; |
| 2146 | assign first_line_err2 = ecc_err_ctl2[0] ; |
| 2147 | |
| 2148 | assign ecc_err_ctl3[30:18] = 0; |
| 2149 | assign ecc_chk_bypass3 = ecc_err_ctl3[31]; // per fifo ecc_chk disable |
| 2150 | assign double_bit_err3 = ecc_err_ctl3[17]; |
| 2151 | assign single_bit_err3 = ecc_err_ctl3[16]; |
| 2152 | assign ecc_err_ctl3[15:11] = 0; |
| 2153 | assign ecc_err_ctl3[10] = 1'b1; // all packets |
| 2154 | assign ecc_err_ctl3[9:3] = 0; |
| 2155 | assign last_line_err3 = ecc_err_ctl3[2] ; |
| 2156 | assign second_line_err3 = ecc_err_ctl3[1] ; |
| 2157 | assign first_line_err3 = ecc_err_ctl3[0] ; |
| 2158 | |
| 2159 | /* -------- debug_training_vector --------------- */ |
| 2160 | zcp_xREG #(32) training_vector_xREG(.clk(clk),.reset(reset[9]),.en(ld_training_vector),.din(wr_data[31:0]),.qout(training_vector)); |
| 2161 | |
| 2162 | // vlint flag_empty_block off |
| 2163 | // RAM enable selection MUX |
| 2164 | always @ (posedge clk) |
| 2165 | begin |
| 2166 | // va read or write enable |
| 2167 | va_ram_rwen <= 0; |
| 2168 | va_ram_rwen0 <= 0; |
| 2169 | va_ram_rwen1 <= 0; |
| 2170 | va_ram_rwen2 <= 0; |
| 2171 | va_ram_rwen3 <= 0; |
| 2172 | va_ram_rwen4 <= 0; |
| 2173 | va_ram_rwen5 <= 0; |
| 2174 | va_ram_rwen6 <= 0; |
| 2175 | va_ram_rwen7 <= 0; |
| 2176 | // va read |
| 2177 | va_ram_ren <= 0; |
| 2178 | va_ram_ren0 <= 0; |
| 2179 | va_ram_ren1 <= 0; |
| 2180 | va_ram_ren2 <= 0; |
| 2181 | va_ram_ren3 <= 0; |
| 2182 | va_ram_ren4 <= 0; |
| 2183 | va_ram_ren5 <= 0; |
| 2184 | va_ram_ren6 <= 0; |
| 2185 | va_ram_ren7 <= 0; |
| 2186 | // va write |
| 2187 | va_ram_wen <= 0; |
| 2188 | va_ram_wen0 <= 0; |
| 2189 | va_ram_wen1 <= 0; |
| 2190 | va_ram_wen2 <= 0; |
| 2191 | va_ram_wen3 <= 0; |
| 2192 | va_ram_wen4 <= 0; |
| 2193 | va_ram_wen5 <= 0; |
| 2194 | va_ram_wen6 <= 0; |
| 2195 | va_ram_wen7 <= 0; |
| 2196 | // st ram |
| 2197 | st_ram_ren <= 0; |
| 2198 | st_ram_wen <= 0; |
| 2199 | // dn ram |
| 2200 | dn_ram_ren <= 0; |
| 2201 | dn_ram_wen <= 0; |
| 2202 | // cfifo r/w |
| 2203 | cfifo_ren0 <= 0; |
| 2204 | cfifo_ren1 <= 0; |
| 2205 | cfifo_ren2 <= 0; |
| 2206 | cfifo_ren3 <= 0; |
| 2207 | cfifo_wen0 <= 0; |
| 2208 | cfifo_wen1 <= 0; |
| 2209 | cfifo_wen2 <= 0; |
| 2210 | cfifo_wen3 <= 0; |
| 2211 | |
| 2212 | casex (ram_sel[4:0]) // synopsys parallel_case full_case |
| 2213 | // va_ram |
| 2214 | 5'h00 : begin |
| 2215 | va_ram_rwen <= ram_ren | ram_wen;// r/w enable |
| 2216 | va_ram_rwen0 <= ram_ren | ram_wen;// r/w enable |
| 2217 | va_ram_ren0 <= ram_ren;// ram_ren is a pulse |
| 2218 | va_ram_wen0 <= ram_wen;// ram_wen is a pulse |
| 2219 | va_ram_ren <= ram_ren;// ram_ren is a pulse |
| 2220 | va_ram_wen <= ram_wen;// ram_wen is a pulse |
| 2221 | end |
| 2222 | 5'h01 : begin |
| 2223 | va_ram_rwen <= ram_ren | ram_wen;// r/w enable |
| 2224 | va_ram_rwen1 <= ram_ren | ram_wen;// r/w enable |
| 2225 | va_ram_ren1 <= ram_ren;// ram_ren is a pulse |
| 2226 | va_ram_wen1 <= ram_wen;// ram_wen is a pulse |
| 2227 | va_ram_ren <= ram_ren;// ram_ren is a pulse |
| 2228 | va_ram_wen <= ram_wen;// ram_wen is a pulse |
| 2229 | end |
| 2230 | 5'h02 : begin |
| 2231 | va_ram_rwen <= ram_ren | ram_wen;// r/w enable |
| 2232 | va_ram_rwen2 <= ram_ren | ram_wen;// r/w enable |
| 2233 | va_ram_ren2 <= ram_ren;// ram_ren is a pulse |
| 2234 | va_ram_wen2 <= ram_wen;// ram_wen is a pulse |
| 2235 | va_ram_ren <= ram_ren;// ram_ren is a pulse |
| 2236 | va_ram_wen <= ram_wen;// ram_wen is a pulse |
| 2237 | end |
| 2238 | 5'h03 : begin |
| 2239 | va_ram_rwen <= ram_ren | ram_wen;// r/w enable |
| 2240 | va_ram_rwen3 <= ram_ren | ram_wen;// r/w enable |
| 2241 | va_ram_ren3 <= ram_ren;// ram_ren is a pulse |
| 2242 | va_ram_wen3 <= ram_wen;// ram_wen is a pulse |
| 2243 | va_ram_ren <= ram_ren;// ram_ren is a pulse |
| 2244 | va_ram_wen <= ram_wen;// ram_wen is a pulse |
| 2245 | end |
| 2246 | 5'h04 : begin |
| 2247 | va_ram_rwen <= ram_ren | ram_wen;// r/w enable |
| 2248 | va_ram_rwen4 <= ram_ren | ram_wen;// r/w enable |
| 2249 | va_ram_ren4 <= ram_ren;// ram_ren is a pulse |
| 2250 | va_ram_wen4 <= ram_wen;// ram_wen is a pulse |
| 2251 | va_ram_ren <= ram_ren;// ram_ren is a pulse |
| 2252 | va_ram_wen <= ram_wen;// ram_wen is a pulse |
| 2253 | end |
| 2254 | 5'h05 : begin |
| 2255 | va_ram_rwen <= ram_ren | ram_wen;// r/w enable |
| 2256 | va_ram_rwen5 <= ram_ren | ram_wen;// r/w enable |
| 2257 | va_ram_ren5 <= ram_ren;// ram_ren is a pulse |
| 2258 | va_ram_wen5 <= ram_wen;// ram_wen is a pulse |
| 2259 | va_ram_ren <= ram_ren;// ram_ren is a pulse |
| 2260 | va_ram_wen <= ram_wen;// ram_wen is a pulse |
| 2261 | end |
| 2262 | 5'h06 : begin |
| 2263 | va_ram_rwen <= ram_ren | ram_wen;// r/w enable |
| 2264 | va_ram_rwen6 <= ram_ren | ram_wen;// r/w enable |
| 2265 | va_ram_ren6 <= ram_ren;// ram_ren is a pulse |
| 2266 | va_ram_wen6 <= ram_wen;// ram_wen is a pulse |
| 2267 | va_ram_ren <= ram_ren;// ram_ren is a pulse |
| 2268 | va_ram_wen <= ram_wen;// ram_wen is a pulse |
| 2269 | end |
| 2270 | 5'h07 : begin |
| 2271 | va_ram_rwen <= ram_ren | ram_wen;// r/w enable |
| 2272 | va_ram_rwen7 <= ram_ren | ram_wen;// r/w enable |
| 2273 | va_ram_ren7 <= ram_ren; |
| 2274 | va_ram_wen7 <= ram_wen;// ram_wen is a pulse |
| 2275 | va_ram_ren <= ram_ren;// ram_ren is a pulse |
| 2276 | va_ram_wen <= ram_wen;// ram_wen is a pulse |
| 2277 | end |
| 2278 | 5'h08 : begin // st ram |
| 2279 | st_ram_ren <= ram_ren; |
| 2280 | st_ram_wen <= ram_wen;// ram_wen is a pulse |
| 2281 | end |
| 2282 | 5'h09 : begin // dn ram |
| 2283 | dn_ram_ren <= ram_ren; |
| 2284 | dn_ram_wen <= ram_wen;// ram_wen is a pulse |
| 2285 | end |
| 2286 | 5'h10 : begin //cfifo0 |
| 2287 | cfifo_ren0 <= ram_ren; |
| 2288 | cfifo_wen0 <= ram_wen;// ram_wen is a pulse |
| 2289 | end |
| 2290 | 5'h11 : begin //cfifo1 |
| 2291 | cfifo_ren1 <= ram_ren; |
| 2292 | cfifo_wen1 <= ram_wen;// ram_wen is a pulse |
| 2293 | end |
| 2294 | 5'h12 : begin //cfifo2 |
| 2295 | cfifo_ren2 <= ram_ren; |
| 2296 | cfifo_wen2 <= ram_wen;// ram_wen is a pulse |
| 2297 | end |
| 2298 | 5'h13 : begin //cfifo3 |
| 2299 | cfifo_ren3 <= ram_ren; |
| 2300 | cfifo_wen3 <= ram_wen;// ram_wen is a pulse |
| 2301 | end |
| 2302 | default:begin |
| 2303 | end |
| 2304 | endcase // casex() |
| 2305 | end // always @ (... |
| 2306 | // vlint flag_empty_block on |
| 2307 | |
| 2308 | // ram_rdata selection mux |
| 2309 | always @ ( cfifo_slv_rdata0 or cfifo_slv_rdata1 |
| 2310 | or cfifo_slv_rdata2 or cfifo_slv_rdata3 or dram_slv_rdata |
| 2311 | or ram_sel or sram_slv_rdata or vram_slv_rdata) |
| 2312 | begin |
| 2313 | ram_rdata = `DN_W'h0000_dead_beef; |
| 2314 | casex (ram_sel[4:0]) |
| 2315 | // va_ram |
| 2316 | 5'h00 : ram_rdata = {8'b0,vram_slv_rdata[`W128D0]}; |
| 2317 | 5'h01 : ram_rdata = {8'b0,vram_slv_rdata[`W128D1]}; |
| 2318 | 5'h02 : ram_rdata = {8'b0,vram_slv_rdata[`W128D2]}; |
| 2319 | 5'h03 : ram_rdata = {8'b0,vram_slv_rdata[`W128D3]}; |
| 2320 | 5'h04 : ram_rdata = {8'b0,vram_slv_rdata[`W128D4]}; |
| 2321 | 5'h05 : ram_rdata = {8'b0,vram_slv_rdata[`W128D5]}; |
| 2322 | 5'h06 : ram_rdata = {8'b0,vram_slv_rdata[`W128D6]}; |
| 2323 | 5'h07 : ram_rdata = {8'b0,vram_slv_rdata[`W128D7]}; |
| 2324 | // st_ram |
| 2325 | 5'h08 : ram_rdata = {24'b0,sram_slv_rdata}; |
| 2326 | // dn_ram |
| 2327 | 5'h09 : ram_rdata = dram_slv_rdata; |
| 2328 | // cfifo |
| 2329 | 5'h10 : ram_rdata = {6'b0,cfifo_slv_rdata0}; |
| 2330 | 5'h11 : ram_rdata = {6'b0,cfifo_slv_rdata1}; |
| 2331 | 5'h12 : ram_rdata = {6'b0,cfifo_slv_rdata2}; |
| 2332 | 5'h13 : ram_rdata = {6'b0,cfifo_slv_rdata3}; |
| 2333 | default: ram_rdata = `DN_W'h0000_dead_beef; |
| 2334 | endcase // casex() |
| 2335 | end // always @ (... |
| 2336 | |
| 2337 | |
| 2338 | niu_zcp_ram_access_sm niu_zcp_ram_access_sm |
| 2339 | (/*AUTOINST*/ |
| 2340 | // Outputs |
| 2341 | .ram_ren (ram_ren), |
| 2342 | .ram_wen (ram_wen), |
| 2343 | .slv_request (slv_request), |
| 2344 | .ld_ram2reg (ld_ram2reg), |
| 2345 | .ram_access_state (ram_access_state[2:0]), |
| 2346 | // Inputs |
| 2347 | .clk (clk), |
| 2348 | .reset10 (reset10), |
| 2349 | .ld_ram_addr_trail (ld_ram_addr_trail), |
| 2350 | .slv_accepted (slv_accepted), |
| 2351 | .rw (rw)); |
| 2352 | |
| 2353 | |
| 2354 | //////////////////////////////////////////////////////////////// |
| 2355 | // RDC table |
| 2356 | //////////////////////////////////////////////////////////////// |
| 2357 | |
| 2358 | |
| 2359 | /* -------- rdc Registers ---------------------- */ |
| 2360 | zcp_xREG #(4) rdc0_xREG( .clk(clk),.reset(reset[11]),.en(ld_rdc0),.din(wr_data[3:0]),.qout(rdc0)); |
| 2361 | zcp_xREG #(4) rdc1_xREG( .clk(clk),.reset(reset[11]),.en(ld_rdc1),.din(wr_data[3:0]),.qout(rdc1)); |
| 2362 | zcp_xREG #(4) rdc2_xREG( .clk(clk),.reset(reset[11]),.en(ld_rdc2),.din(wr_data[3:0]),.qout(rdc2)); |
| 2363 | zcp_xREG #(4) rdc3_xREG( .clk(clk),.reset(reset[11]),.en(ld_rdc3),.din(wr_data[3:0]),.qout(rdc3)); |
| 2364 | zcp_xREG #(4) rdc4_xREG( .clk(clk),.reset(reset[11]),.en(ld_rdc4),.din(wr_data[3:0]),.qout(rdc4)); |
| 2365 | zcp_xREG #(4) rdc5_xREG( .clk(clk),.reset(reset[11]),.en(ld_rdc5),.din(wr_data[3:0]),.qout(rdc5)); |
| 2366 | zcp_xREG #(4) rdc6_xREG( .clk(clk),.reset(reset[11]),.en(ld_rdc6),.din(wr_data[3:0]),.qout(rdc6)); |
| 2367 | zcp_xREG #(4) rdc7_xREG( .clk(clk),.reset(reset[11]),.en(ld_rdc7),.din(wr_data[3:0]),.qout(rdc7)); |
| 2368 | zcp_xREG #(4) rdc8_xREG( .clk(clk),.reset(reset[11]),.en(ld_rdc8),.din(wr_data[3:0]),.qout(rdc8)); |
| 2369 | zcp_xREG #(4) rdc9_xREG( .clk(clk),.reset(reset[11]),.en(ld_rdc9),.din(wr_data[3:0]),.qout(rdc9)); |
| 2370 | zcp_xREG #(4) rdc10_xREG(.clk(clk),.reset(reset[11]),.en(ld_rdc10),.din(wr_data[3:0]),.qout(rdc10)); |
| 2371 | zcp_xREG #(4) rdc11_xREG(.clk(clk),.reset(reset[11]),.en(ld_rdc11),.din(wr_data[3:0]),.qout(rdc11)); |
| 2372 | zcp_xREG #(4) rdc12_xREG(.clk(clk),.reset(reset[11]),.en(ld_rdc12),.din(wr_data[3:0]),.qout(rdc12)); |
| 2373 | zcp_xREG #(4) rdc13_xREG(.clk(clk),.reset(reset[12]),.en(ld_rdc13),.din(wr_data[3:0]),.qout(rdc13)); |
| 2374 | zcp_xREG #(4) rdc14_xREG(.clk(clk),.reset(reset[12]),.en(ld_rdc14),.din(wr_data[3:0]),.qout(rdc14)); |
| 2375 | zcp_xREG #(4) rdc15_xREG(.clk(clk),.reset(reset[12]),.en(ld_rdc15),.din(wr_data[3:0]),.qout(rdc15)); |
| 2376 | zcp_xREG #(4) rdc16_xREG(.clk(clk),.reset(reset[12]),.en(ld_rdc16),.din(wr_data[3:0]),.qout(rdc16)); |
| 2377 | zcp_xREG #(4) rdc17_xREG(.clk(clk),.reset(reset[12]),.en(ld_rdc17),.din(wr_data[3:0]),.qout(rdc17)); |
| 2378 | zcp_xREG #(4) rdc18_xREG(.clk(clk),.reset(reset[12]),.en(ld_rdc18),.din(wr_data[3:0]),.qout(rdc18)); |
| 2379 | zcp_xREG #(4) rdc19_xREG(.clk(clk),.reset(reset[12]),.en(ld_rdc19),.din(wr_data[3:0]),.qout(rdc19)); |
| 2380 | zcp_xREG #(4) rdc20_xREG(.clk(clk),.reset(reset[12]),.en(ld_rdc20),.din(wr_data[3:0]),.qout(rdc20)); |
| 2381 | zcp_xREG #(4) rdc21_xREG(.clk(clk),.reset(reset[12]),.en(ld_rdc21),.din(wr_data[3:0]),.qout(rdc21)); |
| 2382 | zcp_xREG #(4) rdc22_xREG(.clk(clk),.reset(reset[12]),.en(ld_rdc22),.din(wr_data[3:0]),.qout(rdc22)); |
| 2383 | zcp_xREG #(4) rdc23_xREG(.clk(clk),.reset(reset[12]),.en(ld_rdc23),.din(wr_data[3:0]),.qout(rdc23)); |
| 2384 | zcp_xREG #(4) rdc24_xREG(.clk(clk),.reset(reset[12]),.en(ld_rdc24),.din(wr_data[3:0]),.qout(rdc24)); |
| 2385 | zcp_xREG #(4) rdc25_xREG(.clk(clk),.reset(reset[13]),.en(ld_rdc25),.din(wr_data[3:0]),.qout(rdc25)); |
| 2386 | zcp_xREG #(4) rdc26_xREG(.clk(clk),.reset(reset[13]),.en(ld_rdc26),.din(wr_data[3:0]),.qout(rdc26)); |
| 2387 | zcp_xREG #(4) rdc27_xREG(.clk(clk),.reset(reset[13]),.en(ld_rdc27),.din(wr_data[3:0]),.qout(rdc27)); |
| 2388 | zcp_xREG #(4) rdc28_xREG(.clk(clk),.reset(reset[13]),.en(ld_rdc28),.din(wr_data[3:0]),.qout(rdc28)); |
| 2389 | zcp_xREG #(4) rdc29_xREG(.clk(clk),.reset(reset[13]),.en(ld_rdc29),.din(wr_data[3:0]),.qout(rdc29)); |
| 2390 | zcp_xREG #(4) rdc30_xREG(.clk(clk),.reset(reset[13]),.en(ld_rdc30),.din(wr_data[3:0]),.qout(rdc30)); |
| 2391 | zcp_xREG #(4) rdc31_xREG(.clk(clk),.reset(reset[13]),.en(ld_rdc31),.din(wr_data[3:0]),.qout(rdc31)); |
| 2392 | zcp_xREG #(4) rdc32_xREG(.clk(clk),.reset(reset[13]),.en(ld_rdc32),.din(wr_data[3:0]),.qout(rdc32)); |
| 2393 | zcp_xREG #(4) rdc33_xREG(.clk(clk),.reset(reset[13]),.en(ld_rdc33),.din(wr_data[3:0]),.qout(rdc33)); |
| 2394 | zcp_xREG #(4) rdc34_xREG(.clk(clk),.reset(reset[13]),.en(ld_rdc34),.din(wr_data[3:0]),.qout(rdc34)); |
| 2395 | zcp_xREG #(4) rdc35_xREG(.clk(clk),.reset(reset[13]),.en(ld_rdc35),.din(wr_data[3:0]),.qout(rdc35)); |
| 2396 | zcp_xREG #(4) rdc36_xREG(.clk(clk),.reset(reset[13]),.en(ld_rdc36),.din(wr_data[3:0]),.qout(rdc36)); |
| 2397 | zcp_xREG #(4) rdc37_xREG(.clk(clk),.reset(reset[14]),.en(ld_rdc37),.din(wr_data[3:0]),.qout(rdc37)); |
| 2398 | zcp_xREG #(4) rdc38_xREG(.clk(clk),.reset(reset[14]),.en(ld_rdc38),.din(wr_data[3:0]),.qout(rdc38)); |
| 2399 | zcp_xREG #(4) rdc39_xREG(.clk(clk),.reset(reset[14]),.en(ld_rdc39),.din(wr_data[3:0]),.qout(rdc39)); |
| 2400 | zcp_xREG #(4) rdc40_xREG(.clk(clk),.reset(reset[14]),.en(ld_rdc40),.din(wr_data[3:0]),.qout(rdc40)); |
| 2401 | zcp_xREG #(4) rdc41_xREG(.clk(clk),.reset(reset[14]),.en(ld_rdc41),.din(wr_data[3:0]),.qout(rdc41)); |
| 2402 | zcp_xREG #(4) rdc42_xREG(.clk(clk),.reset(reset[14]),.en(ld_rdc42),.din(wr_data[3:0]),.qout(rdc42)); |
| 2403 | zcp_xREG #(4) rdc43_xREG(.clk(clk),.reset(reset[14]),.en(ld_rdc43),.din(wr_data[3:0]),.qout(rdc43)); |
| 2404 | zcp_xREG #(4) rdc44_xREG(.clk(clk),.reset(reset[14]),.en(ld_rdc44),.din(wr_data[3:0]),.qout(rdc44)); |
| 2405 | zcp_xREG #(4) rdc45_xREG(.clk(clk),.reset(reset[14]),.en(ld_rdc45),.din(wr_data[3:0]),.qout(rdc45)); |
| 2406 | zcp_xREG #(4) rdc46_xREG(.clk(clk),.reset(reset[14]),.en(ld_rdc46),.din(wr_data[3:0]),.qout(rdc46)); |
| 2407 | zcp_xREG #(4) rdc47_xREG(.clk(clk),.reset(reset[14]),.en(ld_rdc47),.din(wr_data[3:0]),.qout(rdc47)); |
| 2408 | zcp_xREG #(4) rdc48_xREG(.clk(clk),.reset(reset[14]),.en(ld_rdc48),.din(wr_data[3:0]),.qout(rdc48)); |
| 2409 | zcp_xREG #(4) rdc49_xREG(.clk(clk),.reset(reset[15]),.en(ld_rdc49),.din(wr_data[3:0]),.qout(rdc49)); |
| 2410 | zcp_xREG #(4) rdc50_xREG(.clk(clk),.reset(reset[15]),.en(ld_rdc50),.din(wr_data[3:0]),.qout(rdc50)); |
| 2411 | zcp_xREG #(4) rdc51_xREG(.clk(clk),.reset(reset[15]),.en(ld_rdc51),.din(wr_data[3:0]),.qout(rdc51)); |
| 2412 | zcp_xREG #(4) rdc52_xREG(.clk(clk),.reset(reset[15]),.en(ld_rdc52),.din(wr_data[3:0]),.qout(rdc52)); |
| 2413 | zcp_xREG #(4) rdc53_xREG(.clk(clk),.reset(reset[15]),.en(ld_rdc53),.din(wr_data[3:0]),.qout(rdc53)); |
| 2414 | zcp_xREG #(4) rdc54_xREG(.clk(clk),.reset(reset[15]),.en(ld_rdc54),.din(wr_data[3:0]),.qout(rdc54)); |
| 2415 | zcp_xREG #(4) rdc55_xREG(.clk(clk),.reset(reset[15]),.en(ld_rdc55),.din(wr_data[3:0]),.qout(rdc55)); |
| 2416 | zcp_xREG #(4) rdc56_xREG(.clk(clk),.reset(reset[15]),.en(ld_rdc56),.din(wr_data[3:0]),.qout(rdc56)); |
| 2417 | zcp_xREG #(4) rdc57_xREG(.clk(clk),.reset(reset[15]),.en(ld_rdc57),.din(wr_data[3:0]),.qout(rdc57)); |
| 2418 | zcp_xREG #(4) rdc58_xREG(.clk(clk),.reset(reset[15]),.en(ld_rdc58),.din(wr_data[3:0]),.qout(rdc58)); |
| 2419 | zcp_xREG #(4) rdc59_xREG(.clk(clk),.reset(reset[15]),.en(ld_rdc59),.din(wr_data[3:0]),.qout(rdc59)); |
| 2420 | zcp_xREG #(4) rdc60_xREG(.clk(clk),.reset(reset[15]),.en(ld_rdc60),.din(wr_data[3:0]),.qout(rdc60)); |
| 2421 | zcp_xREG #(4) rdc61_xREG(.clk(clk),.reset(reset[16]),.en(ld_rdc61),.din(wr_data[3:0]),.qout(rdc61)); |
| 2422 | zcp_xREG #(4) rdc62_xREG(.clk(clk),.reset(reset[16]),.en(ld_rdc62),.din(wr_data[3:0]),.qout(rdc62)); |
| 2423 | zcp_xREG #(4) rdc63_xREG(.clk(clk),.reset(reset[16]),.en(ld_rdc63),.din(wr_data[3:0]),.qout(rdc63)); |
| 2424 | zcp_xREG #(4) rdc64_xREG(.clk(clk),.reset(reset[16]),.en(ld_rdc64),.din(wr_data[3:0]),.qout(rdc64)); |
| 2425 | zcp_xREG #(4) rdc65_xREG(.clk(clk),.reset(reset[16]),.en(ld_rdc65),.din(wr_data[3:0]),.qout(rdc65)); |
| 2426 | zcp_xREG #(4) rdc66_xREG(.clk(clk),.reset(reset[16]),.en(ld_rdc66),.din(wr_data[3:0]),.qout(rdc66)); |
| 2427 | zcp_xREG #(4) rdc67_xREG(.clk(clk),.reset(reset[16]),.en(ld_rdc67),.din(wr_data[3:0]),.qout(rdc67)); |
| 2428 | zcp_xREG #(4) rdc68_xREG(.clk(clk),.reset(reset[16]),.en(ld_rdc68),.din(wr_data[3:0]),.qout(rdc68)); |
| 2429 | zcp_xREG #(4) rdc69_xREG(.clk(clk),.reset(reset[16]),.en(ld_rdc69),.din(wr_data[3:0]),.qout(rdc69)); |
| 2430 | zcp_xREG #(4) rdc70_xREG(.clk(clk),.reset(reset[16]),.en(ld_rdc70),.din(wr_data[3:0]),.qout(rdc70)); |
| 2431 | zcp_xREG #(4) rdc71_xREG(.clk(clk),.reset(reset[16]),.en(ld_rdc71),.din(wr_data[3:0]),.qout(rdc71)); |
| 2432 | zcp_xREG #(4) rdc72_xREG(.clk(clk),.reset(reset[16]),.en(ld_rdc72),.din(wr_data[3:0]),.qout(rdc72)); |
| 2433 | zcp_xREG #(4) rdc73_xREG(.clk(clk),.reset(reset[17]),.en(ld_rdc73),.din(wr_data[3:0]),.qout(rdc73)); |
| 2434 | zcp_xREG #(4) rdc74_xREG(.clk(clk),.reset(reset[17]),.en(ld_rdc74),.din(wr_data[3:0]),.qout(rdc74)); |
| 2435 | zcp_xREG #(4) rdc75_xREG(.clk(clk),.reset(reset[17]),.en(ld_rdc75),.din(wr_data[3:0]),.qout(rdc75)); |
| 2436 | zcp_xREG #(4) rdc76_xREG(.clk(clk),.reset(reset[17]),.en(ld_rdc76),.din(wr_data[3:0]),.qout(rdc76)); |
| 2437 | zcp_xREG #(4) rdc77_xREG(.clk(clk),.reset(reset[17]),.en(ld_rdc77),.din(wr_data[3:0]),.qout(rdc77)); |
| 2438 | zcp_xREG #(4) rdc78_xREG(.clk(clk),.reset(reset[17]),.en(ld_rdc78),.din(wr_data[3:0]),.qout(rdc78)); |
| 2439 | zcp_xREG #(4) rdc79_xREG(.clk(clk),.reset(reset[17]),.en(ld_rdc79),.din(wr_data[3:0]),.qout(rdc79)); |
| 2440 | zcp_xREG #(4) rdc80_xREG(.clk(clk),.reset(reset[17]),.en(ld_rdc80),.din(wr_data[3:0]),.qout(rdc80)); |
| 2441 | zcp_xREG #(4) rdc81_xREG(.clk(clk),.reset(reset[17]),.en(ld_rdc81),.din(wr_data[3:0]),.qout(rdc81)); |
| 2442 | zcp_xREG #(4) rdc82_xREG(.clk(clk),.reset(reset[17]),.en(ld_rdc82),.din(wr_data[3:0]),.qout(rdc82)); |
| 2443 | zcp_xREG #(4) rdc83_xREG(.clk(clk),.reset(reset[17]),.en(ld_rdc83),.din(wr_data[3:0]),.qout(rdc83)); |
| 2444 | zcp_xREG #(4) rdc84_xREG(.clk(clk),.reset(reset[17]),.en(ld_rdc84),.din(wr_data[3:0]),.qout(rdc84)); |
| 2445 | zcp_xREG #(4) rdc85_xREG(.clk(clk),.reset(reset[18]),.en(ld_rdc85),.din(wr_data[3:0]),.qout(rdc85)); |
| 2446 | zcp_xREG #(4) rdc86_xREG(.clk(clk),.reset(reset[18]),.en(ld_rdc86),.din(wr_data[3:0]),.qout(rdc86)); |
| 2447 | zcp_xREG #(4) rdc87_xREG(.clk(clk),.reset(reset[18]),.en(ld_rdc87),.din(wr_data[3:0]),.qout(rdc87)); |
| 2448 | zcp_xREG #(4) rdc88_xREG(.clk(clk),.reset(reset[18]),.en(ld_rdc88),.din(wr_data[3:0]),.qout(rdc88)); |
| 2449 | zcp_xREG #(4) rdc89_xREG(.clk(clk),.reset(reset[18]),.en(ld_rdc89),.din(wr_data[3:0]),.qout(rdc89)); |
| 2450 | zcp_xREG #(4) rdc90_xREG(.clk(clk),.reset(reset[18]),.en(ld_rdc90),.din(wr_data[3:0]),.qout(rdc90)); |
| 2451 | zcp_xREG #(4) rdc91_xREG(.clk(clk),.reset(reset[18]),.en(ld_rdc91),.din(wr_data[3:0]),.qout(rdc91)); |
| 2452 | zcp_xREG #(4) rdc92_xREG(.clk(clk),.reset(reset[18]),.en(ld_rdc92),.din(wr_data[3:0]),.qout(rdc92)); |
| 2453 | zcp_xREG #(4) rdc93_xREG(.clk(clk),.reset(reset[18]),.en(ld_rdc93),.din(wr_data[3:0]),.qout(rdc93)); |
| 2454 | zcp_xREG #(4) rdc94_xREG(.clk(clk),.reset(reset[18]),.en(ld_rdc94),.din(wr_data[3:0]),.qout(rdc94)); |
| 2455 | zcp_xREG #(4) rdc95_xREG(.clk(clk),.reset(reset[18]),.en(ld_rdc95),.din(wr_data[3:0]),.qout(rdc95)); |
| 2456 | zcp_xREG #(4) rdc96_xREG(.clk(clk),.reset(reset[18]),.en(ld_rdc96),.din(wr_data[3:0]),.qout(rdc96)); |
| 2457 | zcp_xREG #(4) rdc97_xREG(.clk(clk),.reset(reset[19]),.en(ld_rdc97),.din(wr_data[3:0]),.qout(rdc97)); |
| 2458 | zcp_xREG #(4) rdc98_xREG(.clk(clk),.reset(reset[19]),.en(ld_rdc98),.din(wr_data[3:0]),.qout(rdc98)); |
| 2459 | zcp_xREG #(4) rdc99_xREG(.clk(clk),.reset(reset[19]),.en(ld_rdc99),.din(wr_data[3:0]),.qout(rdc99)); |
| 2460 | zcp_xREG #(4) rdc100_xREG(.clk(clk),.reset(reset[19]),.en(ld_rdc100),.din(wr_data[3:0]),.qout(rdc100)); |
| 2461 | zcp_xREG #(4) rdc101_xREG(.clk(clk),.reset(reset[19]),.en(ld_rdc101),.din(wr_data[3:0]),.qout(rdc101)); |
| 2462 | zcp_xREG #(4) rdc102_xREG(.clk(clk),.reset(reset[19]),.en(ld_rdc102),.din(wr_data[3:0]),.qout(rdc102)); |
| 2463 | zcp_xREG #(4) rdc103_xREG(.clk(clk),.reset(reset[19]),.en(ld_rdc103),.din(wr_data[3:0]),.qout(rdc103)); |
| 2464 | zcp_xREG #(4) rdc104_xREG(.clk(clk),.reset(reset[19]),.en(ld_rdc104),.din(wr_data[3:0]),.qout(rdc104)); |
| 2465 | zcp_xREG #(4) rdc105_xREG(.clk(clk),.reset(reset[19]),.en(ld_rdc105),.din(wr_data[3:0]),.qout(rdc105)); |
| 2466 | zcp_xREG #(4) rdc106_xREG(.clk(clk),.reset(reset[19]),.en(ld_rdc106),.din(wr_data[3:0]),.qout(rdc106)); |
| 2467 | zcp_xREG #(4) rdc107_xREG(.clk(clk),.reset(reset[19]),.en(ld_rdc107),.din(wr_data[3:0]),.qout(rdc107)); |
| 2468 | zcp_xREG #(4) rdc108_xREG(.clk(clk),.reset(reset[19]),.en(ld_rdc108),.din(wr_data[3:0]),.qout(rdc108)); |
| 2469 | zcp_xREG #(4) rdc109_xREG(.clk(clk),.reset(reset[20]),.en(ld_rdc109),.din(wr_data[3:0]),.qout(rdc109)); |
| 2470 | zcp_xREG #(4) rdc110_xREG(.clk(clk),.reset(reset[20]),.en(ld_rdc110),.din(wr_data[3:0]),.qout(rdc110)); |
| 2471 | zcp_xREG #(4) rdc111_xREG(.clk(clk),.reset(reset[20]),.en(ld_rdc111),.din(wr_data[3:0]),.qout(rdc111)); |
| 2472 | zcp_xREG #(4) rdc112_xREG(.clk(clk),.reset(reset[20]),.en(ld_rdc112),.din(wr_data[3:0]),.qout(rdc112)); |
| 2473 | zcp_xREG #(4) rdc113_xREG(.clk(clk),.reset(reset[20]),.en(ld_rdc113),.din(wr_data[3:0]),.qout(rdc113)); |
| 2474 | zcp_xREG #(4) rdc114_xREG(.clk(clk),.reset(reset[20]),.en(ld_rdc114),.din(wr_data[3:0]),.qout(rdc114)); |
| 2475 | zcp_xREG #(4) rdc115_xREG(.clk(clk),.reset(reset[20]),.en(ld_rdc115),.din(wr_data[3:0]),.qout(rdc115)); |
| 2476 | zcp_xREG #(4) rdc116_xREG(.clk(clk),.reset(reset[20]),.en(ld_rdc116),.din(wr_data[3:0]),.qout(rdc116)); |
| 2477 | zcp_xREG #(4) rdc117_xREG(.clk(clk),.reset(reset[20]),.en(ld_rdc117),.din(wr_data[3:0]),.qout(rdc117)); |
| 2478 | zcp_xREG #(4) rdc118_xREG(.clk(clk),.reset(reset[20]),.en(ld_rdc118),.din(wr_data[3:0]),.qout(rdc118)); |
| 2479 | zcp_xREG #(4) rdc119_xREG(.clk(clk),.reset(reset[20]),.en(ld_rdc119),.din(wr_data[3:0]),.qout(rdc119)); |
| 2480 | zcp_xREG #(4) rdc120_xREG(.clk(clk),.reset(reset[20]),.en(ld_rdc120),.din(wr_data[3:0]),.qout(rdc120)); |
| 2481 | zcp_xREG #(4) rdc121_xREG(.clk(clk),.reset(reset[21]),.en(ld_rdc121),.din(wr_data[3:0]),.qout(rdc121)); |
| 2482 | zcp_xREG #(4) rdc122_xREG(.clk(clk),.reset(reset[21]),.en(ld_rdc122),.din(wr_data[3:0]),.qout(rdc122)); |
| 2483 | zcp_xREG #(4) rdc123_xREG(.clk(clk),.reset(reset[21]),.en(ld_rdc123),.din(wr_data[3:0]),.qout(rdc123)); |
| 2484 | zcp_xREG #(4) rdc124_xREG(.clk(clk),.reset(reset[21]),.en(ld_rdc124),.din(wr_data[3:0]),.qout(rdc124)); |
| 2485 | zcp_xREG #(4) rdc125_xREG(.clk(clk),.reset(reset[21]),.en(ld_rdc125),.din(wr_data[3:0]),.qout(rdc125)); |
| 2486 | zcp_xREG #(4) rdc126_xREG(.clk(clk),.reset(reset[21]),.en(ld_rdc126),.din(wr_data[3:0]),.qout(rdc126)); |
| 2487 | zcp_xREG #(4) rdc127_xREG(.clk(clk),.reset(reset[21]),.en(ld_rdc127),.din(wr_data[3:0]),.qout(rdc127)); |
| 2488 | |
| 2489 | |
| 2490 | /* --- rdc decoder -------------------------- */ |
| 2491 | |
| 2492 | always @ (/*AUTOSENSE*/rdc0 or rdc1 or rdc10 or rdc100 or rdc101 |
| 2493 | or rdc102 or rdc103 or rdc104 or rdc105 or rdc106 or rdc107 |
| 2494 | or rdc108 or rdc109 or rdc11 or rdc110 or rdc111 or rdc112 |
| 2495 | or rdc113 or rdc114 or rdc115 or rdc116 or rdc117 or rdc118 |
| 2496 | or rdc119 or rdc12 or rdc120 or rdc121 or rdc122 or rdc123 |
| 2497 | or rdc124 or rdc125 or rdc126 or rdc127 or rdc13 or rdc14 |
| 2498 | or rdc15 or rdc16 or rdc17 or rdc18 or rdc19 or rdc2 |
| 2499 | or rdc20 or rdc21 or rdc22 or rdc23 or rdc24 or rdc25 |
| 2500 | or rdc26 or rdc27 or rdc28 or rdc29 or rdc3 or rdc30 |
| 2501 | or rdc31 or rdc32 or rdc33 or rdc34 or rdc35 or rdc36 |
| 2502 | or rdc37 or rdc38 or rdc39 or rdc4 or rdc40 or rdc41 |
| 2503 | or rdc42 or rdc43 or rdc44 or rdc45 or rdc46 or rdc47 |
| 2504 | or rdc48 or rdc49 or rdc5 or rdc50 or rdc51 or rdc52 |
| 2505 | or rdc53 or rdc54 or rdc55 or rdc56 or rdc57 or rdc58 |
| 2506 | or rdc59 or rdc6 or rdc60 or rdc61 or rdc62 or rdc63 |
| 2507 | or rdc64 or rdc65 or rdc66 or rdc67 or rdc68 or rdc69 |
| 2508 | or rdc7 or rdc70 or rdc71 or rdc72 or rdc73 or rdc74 |
| 2509 | or rdc75 or rdc76 or rdc77 or rdc78 or rdc79 or rdc8 |
| 2510 | or rdc80 or rdc81 or rdc82 or rdc83 or rdc84 or rdc85 |
| 2511 | or rdc86 or rdc87 or rdc88 or rdc89 or rdc9 or rdc90 |
| 2512 | or rdc91 or rdc92 or rdc93 or rdc94 or rdc95 or rdc96 |
| 2513 | or rdc97 or rdc98 or rdc99 or sel_rdc) |
| 2514 | begin |
| 2515 | rdc = rdc0; |
| 2516 | casex ({sel_rdc[7:5],sel_rdc[3:0]}) // synopsys parallel_case full_case infer_mux |
| 2517 | 7'd0: rdc = rdc0; |
| 2518 | 7'd1: rdc = rdc1; |
| 2519 | 7'd2: rdc = rdc2; |
| 2520 | 7'd3: rdc = rdc3; |
| 2521 | 7'd4: rdc = rdc4; |
| 2522 | 7'd5: rdc = rdc5; |
| 2523 | 7'd6: rdc = rdc6; |
| 2524 | 7'd7: rdc = rdc7; |
| 2525 | 7'd8: rdc = rdc8; |
| 2526 | 7'd9: rdc = rdc9; |
| 2527 | 7'd10: rdc = rdc10; |
| 2528 | 7'd11: rdc = rdc11; |
| 2529 | 7'd12: rdc = rdc12; |
| 2530 | 7'd13: rdc = rdc13; |
| 2531 | 7'd14: rdc = rdc14; |
| 2532 | 7'd15: rdc = rdc15; |
| 2533 | 7'd16: rdc = rdc16; |
| 2534 | 7'd17: rdc = rdc17; |
| 2535 | 7'd18: rdc = rdc18; |
| 2536 | 7'd19: rdc = rdc19; |
| 2537 | 7'd20: rdc = rdc20; |
| 2538 | 7'd21: rdc = rdc21; |
| 2539 | 7'd22: rdc = rdc22; |
| 2540 | 7'd23: rdc = rdc23; |
| 2541 | 7'd24: rdc = rdc24; |
| 2542 | 7'd25: rdc = rdc25; |
| 2543 | 7'd26: rdc = rdc26; |
| 2544 | 7'd27: rdc = rdc27; |
| 2545 | 7'd28: rdc = rdc28; |
| 2546 | 7'd29: rdc = rdc29; |
| 2547 | 7'd30: rdc = rdc30; |
| 2548 | 7'd31: rdc = rdc31; |
| 2549 | 7'd32: rdc = rdc32; |
| 2550 | 7'd33: rdc = rdc33; |
| 2551 | 7'd34: rdc = rdc34; |
| 2552 | 7'd35: rdc = rdc35; |
| 2553 | 7'd36: rdc = rdc36; |
| 2554 | 7'd37: rdc = rdc37; |
| 2555 | 7'd38: rdc = rdc38; |
| 2556 | 7'd39: rdc = rdc39; |
| 2557 | 7'd40: rdc = rdc40; |
| 2558 | 7'd41: rdc = rdc41; |
| 2559 | 7'd42: rdc = rdc42; |
| 2560 | 7'd43: rdc = rdc43; |
| 2561 | 7'd44: rdc = rdc44; |
| 2562 | 7'd45: rdc = rdc45; |
| 2563 | 7'd46: rdc = rdc46; |
| 2564 | 7'd47: rdc = rdc47; |
| 2565 | 7'd48: rdc = rdc48; |
| 2566 | 7'd49: rdc = rdc49; |
| 2567 | 7'd50: rdc = rdc50; |
| 2568 | 7'd51: rdc = rdc51; |
| 2569 | 7'd52: rdc = rdc52; |
| 2570 | 7'd53: rdc = rdc53; |
| 2571 | 7'd54: rdc = rdc54; |
| 2572 | 7'd55: rdc = rdc55; |
| 2573 | 7'd56: rdc = rdc56; |
| 2574 | 7'd57: rdc = rdc57; |
| 2575 | 7'd58: rdc = rdc58; |
| 2576 | 7'd59: rdc = rdc59; |
| 2577 | 7'd60: rdc = rdc60; |
| 2578 | 7'd61: rdc = rdc61; |
| 2579 | 7'd62: rdc = rdc62; |
| 2580 | 7'd63: rdc = rdc63; |
| 2581 | 7'd64: rdc = rdc64; |
| 2582 | 7'd65: rdc = rdc65; |
| 2583 | 7'd66: rdc = rdc66; |
| 2584 | 7'd67: rdc = rdc67; |
| 2585 | 7'd68: rdc = rdc68; |
| 2586 | 7'd69: rdc = rdc69; |
| 2587 | 7'd70: rdc = rdc70; |
| 2588 | 7'd71: rdc = rdc71; |
| 2589 | 7'd72: rdc = rdc72; |
| 2590 | 7'd73: rdc = rdc73; |
| 2591 | 7'd74: rdc = rdc74; |
| 2592 | 7'd75: rdc = rdc75; |
| 2593 | 7'd76: rdc = rdc76; |
| 2594 | 7'd77: rdc = rdc77; |
| 2595 | 7'd78: rdc = rdc78; |
| 2596 | 7'd79: rdc = rdc79; |
| 2597 | 7'd80: rdc = rdc80; |
| 2598 | 7'd81: rdc = rdc81; |
| 2599 | 7'd82: rdc = rdc82; |
| 2600 | 7'd83: rdc = rdc83; |
| 2601 | 7'd84: rdc = rdc84; |
| 2602 | 7'd85: rdc = rdc85; |
| 2603 | 7'd86: rdc = rdc86; |
| 2604 | 7'd87: rdc = rdc87; |
| 2605 | 7'd88: rdc = rdc88; |
| 2606 | 7'd89: rdc = rdc89; |
| 2607 | 7'd90: rdc = rdc90; |
| 2608 | 7'd91: rdc = rdc91; |
| 2609 | 7'd92: rdc = rdc92; |
| 2610 | 7'd93: rdc = rdc93; |
| 2611 | 7'd94: rdc = rdc94; |
| 2612 | 7'd95: rdc = rdc95; |
| 2613 | 7'd96: rdc = rdc96; |
| 2614 | 7'd97: rdc = rdc97; |
| 2615 | 7'd98: rdc = rdc98; |
| 2616 | 7'd99: rdc = rdc99; |
| 2617 | 7'd100: rdc = rdc100; |
| 2618 | 7'd101: rdc = rdc101; |
| 2619 | 7'd102: rdc = rdc102; |
| 2620 | 7'd103: rdc = rdc103; |
| 2621 | 7'd104: rdc = rdc104; |
| 2622 | 7'd105: rdc = rdc105; |
| 2623 | 7'd106: rdc = rdc106; |
| 2624 | 7'd107: rdc = rdc107; |
| 2625 | 7'd108: rdc = rdc108; |
| 2626 | 7'd109: rdc = rdc109; |
| 2627 | 7'd110: rdc = rdc110; |
| 2628 | 7'd111: rdc = rdc111; |
| 2629 | 7'd112: rdc = rdc112; |
| 2630 | 7'd113: rdc = rdc113; |
| 2631 | 7'd114: rdc = rdc114; |
| 2632 | 7'd115: rdc = rdc115; |
| 2633 | 7'd116: rdc = rdc116; |
| 2634 | 7'd117: rdc = rdc117; |
| 2635 | 7'd118: rdc = rdc118; |
| 2636 | 7'd119: rdc = rdc119; |
| 2637 | 7'd120: rdc = rdc120; |
| 2638 | 7'd121: rdc = rdc121; |
| 2639 | 7'd122: rdc = rdc122; |
| 2640 | 7'd123: rdc = rdc123; |
| 2641 | 7'd124: rdc = rdc124; |
| 2642 | 7'd125: rdc = rdc125; |
| 2643 | 7'd126: rdc = rdc126; |
| 2644 | 7'd127: rdc = rdc127; |
| 2645 | default:rdc = rdc0; |
| 2646 | endcase |
| 2647 | end // always @ (... |
| 2648 | |
| 2649 | |
| 2650 | assign sel_rdc[7:0] = decode_zc_rdc ? tt_rdc_reg[7:0] : |
| 2651 | decode_default_rdc ? fflp_rdc[7:0] : |
| 2652 | {fflp_rdc[7:5],5'b0}; // table_rdc |
| 2653 | |
| 2654 | // default_rdc is abailable @ DLY1 state |
| 2655 | zcp_xREG #(5) default_rdc_xREG(.clk(clk),.reset(reset[21]),.en(decode_default_rdc),.din({1'b0,rdc}),.qout(default_rdc[4:0])); |
| 2656 | |
| 2657 | // table_rdc is abailable @ DLY2 state |
| 2658 | zcp_xREG #(5) table_rdc_xREG (.clk(clk),.reset(reset[21]),.en(decode_table_rdc), .din({1'b0,rdc}),.qout(table_rdc[4:0])); |
| 2659 | |
| 2660 | // zc_rdc is available @ CAL2 state |
| 2661 | zcp_xREG #(5) zc_rdc_xREG (.clk(clk),.reset(reset[21]),.en(decode_zc_rdc), .din({1'b0,rdc}),.qout(zc_rdc[4:0])); |
| 2662 | |
| 2663 | niu_zcp_handle_decoder niu_zcp_handle_decoder |
| 2664 | (/*AUTOINST*/ |
| 2665 | // Outputs |
| 2666 | .fn (fn[1:0]), |
| 2667 | .handle (handle[19:0]), |
| 2668 | // Inputs |
| 2669 | .zc_rdc (zc_rdc[3:0]), |
| 2670 | .rdmc_zcp_func_num (rdmc_zcp_func_num[31:0]), |
| 2671 | .page_handle (page_handle[`PMS15:0])); |
| 2672 | |
| 2673 | /* --------------- spare gates --------------- */ |
| 2674 | `ifdef NEPTUNE |
| 2675 | wire [3:0] do_nad; |
| 2676 | wire [3:0] do_nor; |
| 2677 | wire [3:0] do_inv; |
| 2678 | wire [3:0] do_mux; |
| 2679 | wire [3:0] do_q; |
| 2680 | wire so; |
| 2681 | |
| 2682 | zcp_spare_gates zcp_slv_spare_gates ( |
| 2683 | .di_nd3 ({1'h1, 1'h1, do_q[3]}), |
| 2684 | .di_nd2 ({1'h1, 1'h1, do_q[2]}), |
| 2685 | .di_nd1 ({1'h1, 1'h1, do_q[1]}), |
| 2686 | .di_nd0 ({1'h1, 1'h1, do_q[0]}), |
| 2687 | .di_nr3 ({1'h0, 1'h0}), |
| 2688 | .di_nr2 ({1'h0, 1'h0}), |
| 2689 | .di_nr1 ({1'h0, 1'h0}), |
| 2690 | .di_nr0 ({1'h0, 1'h0}), |
| 2691 | .di_inv (do_nad[3:0]), |
| 2692 | .di_mx3 ({1'h0, 1'h0}), |
| 2693 | .di_mx2 ({1'h0, 1'h0}), |
| 2694 | .di_mx1 ({1'h0, 1'h0}), |
| 2695 | .di_mx0 ({1'h0, 1'h0}), |
| 2696 | .mx_sel (do_nor[3:0]), |
| 2697 | .di_reg (do_inv[3:0]), |
| 2698 | .wt_ena (do_mux[3:0]), |
| 2699 | .rst ({reset[0],reset[0],reset[0],reset[0]}), |
| 2700 | .si (1'h0), |
| 2701 | .se (1'h0), |
| 2702 | .clk (clk), |
| 2703 | .do_nad (do_nad[3:0]), |
| 2704 | .do_nor (do_nor[3:0]), |
| 2705 | .do_inv (do_inv[3:0]), |
| 2706 | .do_mux (do_mux[3:0]), |
| 2707 | .do_q (do_q[3:0]), |
| 2708 | .so (so) |
| 2709 | ); |
| 2710 | |
| 2711 | `else |
| 2712 | `endif |
| 2713 | |
| 2714 | endmodule // niu_zcp_slv |
| 2715 | |