| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_zcp_tt_sm.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
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| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /*%W% %G%*/ |
| 36 | |
| 37 | /*************************************************************** |
| 38 | * |
| 39 | * File Name : niu_zcp_tt_sm.v |
| 40 | * Author Name : John Lo |
| 41 | * Description : |
| 42 | * Parent Module: |
| 43 | * Child Module: |
| 44 | * Interface Mod: |
| 45 | * Date Created : 5/4/04 |
| 46 | * |
| 47 | * Copyright (c) 2020, Sun Microsystems, Inc. |
| 48 | * Sun Proprietary and Confidential |
| 49 | * |
| 50 | * Modification : |
| 51 | * |
| 52 | * Synthesis Notes: |
| 53 | * |
| 54 | * Design Notes: When adding more CAL states DON'T forget to |
| 55 | * modify tt_atomic_op. |
| 56 | * |
| 57 | * |
| 58 | **************************************************************/ |
| 59 | |
| 60 | |
| 61 | module niu_zcp_tt_sm |
| 62 | (/*AUTOARG*/ |
| 63 | // Outputs |
| 64 | tt_rd_en0, tt_rd_en1, tt_rd_en2, tt_rd_en3, tt_rd_en4, wb_tt0, |
| 65 | wb_tt1, decode_default_rdc, decode_table_rdc, decode_zc_rdc, |
| 66 | tt_active, tt_sm_rw, ld_cal_results, tt_fail, buf_req, wr_2words, |
| 67 | wr_4words, tt_state, |
| 68 | // Inputs |
| 69 | clk, reset10, kickoff_tt, tt_ok_reg, tt_en, zc_mode, buf_req_ok |
| 70 | ); |
| 71 | |
| 72 | |
| 73 | input clk; |
| 74 | input reset10; |
| 75 | input kickoff_tt; |
| 76 | input [5:0] tt_ok_reg; |
| 77 | input tt_en; |
| 78 | input zc_mode; |
| 79 | input buf_req_ok; |
| 80 | // outputs |
| 81 | output tt_rd_en0; |
| 82 | output tt_rd_en1; |
| 83 | output tt_rd_en2; |
| 84 | output tt_rd_en3; |
| 85 | output tt_rd_en4; |
| 86 | output wb_tt0; |
| 87 | output wb_tt1; |
| 88 | output decode_default_rdc; |
| 89 | output decode_table_rdc; |
| 90 | output decode_zc_rdc; |
| 91 | output tt_active; |
| 92 | output tt_sm_rw; |
| 93 | output [31:0] ld_cal_results; |
| 94 | output tt_fail; |
| 95 | output buf_req; |
| 96 | output wr_2words; |
| 97 | output wr_4words; |
| 98 | output [3:0] tt_state; |
| 99 | |
| 100 | wire reset = reset10; |
| 101 | wire kickoff_tt; |
| 102 | wire [31:0] ld_cal_results; |
| 103 | wire [3:0] tt_state; |
| 104 | wire tt_rd_en0; |
| 105 | wire tt_rd_en1; |
| 106 | wire tt_rd_en2; |
| 107 | wire tt_rd_en3; |
| 108 | wire tt_rd_en4; |
| 109 | |
| 110 | reg [3:0] nx_tt_state; |
| 111 | reg decode_default_rdc, |
| 112 | decode_table_rdc , |
| 113 | decode_zc_rdc , |
| 114 | p1_ld_cal_results , |
| 115 | tt_active , |
| 116 | tt_sm_rw , |
| 117 | p1_tt_rd_en , |
| 118 | wb_tt0 , |
| 119 | wb_tt1 , |
| 120 | wr_2words , // bypass_mode, tt_fail |
| 121 | wr_4words , // ~tt_fail => do 4 writes to cfifo. |
| 122 | buf_req , |
| 123 | tt_fail ; |
| 124 | |
| 125 | parameter IDLE = 4'b0_000, |
| 126 | BYPASS = 4'b0_001, |
| 127 | DLY1 = 4'b0_010, |
| 128 | DLY2 = 4'b0_011, |
| 129 | DLY3 = 4'b0_100, |
| 130 | DLY4 = 4'b0_101, |
| 131 | |
| 132 | RD_TT = 4'b1_000, |
| 133 | LCH_TT = 4'b1_001, |
| 134 | CAL1 = 4'b1_010, |
| 135 | CAL2 = 4'b1_011, |
| 136 | CAL3 = 4'b1_100, |
| 137 | CAL4 = 4'b1_101, |
| 138 | CHK_RESULT = 4'b1_110; |
| 139 | |
| 140 | // comb part |
| 141 | always @ (/*AUTOSENSE*/buf_req_ok or kickoff_tt or tt_en or tt_ok_reg |
| 142 | or tt_state or zc_mode) |
| 143 | begin |
| 144 | nx_tt_state = IDLE; |
| 145 | decode_default_rdc = 0; |
| 146 | decode_table_rdc = 0; |
| 147 | decode_zc_rdc = 0; |
| 148 | p1_ld_cal_results = 0; |
| 149 | tt_active = 0; |
| 150 | tt_sm_rw = 0; |
| 151 | p1_tt_rd_en = 0; |
| 152 | wb_tt0 = 0; |
| 153 | wb_tt1 = 0; |
| 154 | wr_2words = 0; |
| 155 | wr_4words = 0; |
| 156 | buf_req = 0; |
| 157 | tt_fail = 0; |
| 158 | |
| 159 | casex (tt_state) // synopsys parallel_case full_case |
| 160 | IDLE: |
| 161 | if (kickoff_tt) |
| 162 | begin |
| 163 | if (tt_en & zc_mode) |
| 164 | begin |
| 165 | nx_tt_state = RD_TT; // tt_en and good |
| 166 | p1_tt_rd_en = 1; // tt_rd_en is register to latch va,dn,st ram. |
| 167 | tt_active = 1; |
| 168 | tt_sm_rw = 1; |
| 169 | end |
| 170 | else // bypass mode |
| 171 | begin |
| 172 | nx_tt_state = BYPASS; |
| 173 | end |
| 174 | end |
| 175 | else begin |
| 176 | nx_tt_state = tt_state; // stay |
| 177 | end |
| 178 | |
| 179 | //----- TCP mode and successful tests ----------------- |
| 180 | RD_TT: begin // tt_rd_en = 1 (registered) |
| 181 | nx_tt_state = LCH_TT; |
| 182 | tt_active = 1; |
| 183 | tt_sm_rw = 1; |
| 184 | decode_default_rdc = 1; |
| 185 | end |
| 186 | |
| 187 | LCH_TT:begin |
| 188 | nx_tt_state = CAL1; |
| 189 | tt_active = 1; |
| 190 | decode_table_rdc = 1; |
| 191 | end |
| 192 | |
| 193 | CAL1: begin |
| 194 | nx_tt_state = CAL2; |
| 195 | tt_active = 1; |
| 196 | decode_zc_rdc = 1; |
| 197 | end |
| 198 | |
| 199 | CAL2: begin |
| 200 | nx_tt_state = CAL3; |
| 201 | tt_active = 1; |
| 202 | end |
| 203 | |
| 204 | CAL3: begin |
| 205 | nx_tt_state = CAL4; |
| 206 | p1_ld_cal_results = 1; |
| 207 | tt_active = 1; |
| 208 | end |
| 209 | |
| 210 | CAL4: begin |
| 211 | nx_tt_state = CHK_RESULT; |
| 212 | tt_active = 1; |
| 213 | tt_sm_rw = 1; |
| 214 | end |
| 215 | |
| 216 | CHK_RESULT: // handle is ready |
| 217 | begin |
| 218 | nx_tt_state = IDLE; |
| 219 | tt_fail = ~tt_ok_reg[0]; |
| 220 | buf_req = tt_ok_reg[1] & buf_req_ok; |
| 221 | wr_4words = tt_ok_reg[2]; |
| 222 | wr_2words = ~tt_ok_reg[3]; |
| 223 | wb_tt0 = tt_ok_reg[4]; |
| 224 | wb_tt1 = tt_ok_reg[5]; |
| 225 | tt_active = 1; |
| 226 | tt_sm_rw = 1; |
| 227 | end |
| 228 | |
| 229 | //----- BYPASS mode tests ------------------- |
| 230 | BYPASS:begin |
| 231 | nx_tt_state = DLY1; |
| 232 | decode_default_rdc = 1; |
| 233 | end |
| 234 | DLY1: begin |
| 235 | nx_tt_state = DLY2; |
| 236 | decode_table_rdc = 1; |
| 237 | end |
| 238 | DLY2: begin |
| 239 | nx_tt_state = DLY3; |
| 240 | p1_ld_cal_results = 1; |
| 241 | end |
| 242 | DLY3: begin |
| 243 | nx_tt_state = DLY4; |
| 244 | // ld_cal_result = 1; |
| 245 | end |
| 246 | DLY4: begin |
| 247 | nx_tt_state = IDLE; |
| 248 | wr_2words = 1; |
| 249 | end |
| 250 | |
| 251 | //----- default stuff ---------------------------------------- |
| 252 | default: |
| 253 | begin |
| 254 | nx_tt_state = IDLE; |
| 255 | // synopsys translate_off |
| 256 | $display("(* ERROR: at sim time = %d, niu_zcp_tt_sm is in forbidden state *) \n", $time); |
| 257 | // synopsys translate_on |
| 258 | end // case: default |
| 259 | endcase // casex(tt_state) |
| 260 | end // always @ (... |
| 261 | |
| 262 | |
| 263 | |
| 264 | // seq part |
| 265 | zcp_RegRst #(4) tt_state_RegRst(.din(nx_tt_state[3:0]), |
| 266 | .clk(clk), |
| 267 | .reset(reset), |
| 268 | .qout(tt_state[3:0])); |
| 269 | |
| 270 | |
| 271 | // glue logic |
| 272 | zcp_RegDff #(5) tt_rd_en_RegDff(.din({5{p1_tt_rd_en}}),.clk(clk),.qout({tt_rd_en4,tt_rd_en3,tt_rd_en2,tt_rd_en1,tt_rd_en0})); |
| 273 | |
| 274 | zcp_RegDff #(32) tt_state_RegDff(.din({32{p1_ld_cal_results}}),.clk(clk),.qout(ld_cal_results[31:0])); |
| 275 | |
| 276 | |
| 277 | endmodule // niu_zcp_tt_sm |
| 278 | |
| 279 | |