| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: pcs.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | // @(#)pcs.v 1.10G |
| 36 | /**********************************************************************/ |
| 37 | /* Project Name : CASSINI */ |
| 38 | /* Module Name : PCS Top Module */ |
| 39 | /* Description : The PCS top module hooks together the rx datapath,*/ |
| 40 | /* which contains the encoder, running disparity and */ |
| 41 | /* pipeline stages; the tx_datapath which contains */ |
| 42 | /* decoder and pipeline stages; link configuration */ |
| 43 | /* block; word synchronization block, and sequence */ |
| 44 | /* detection block. */ |
| 45 | /* */ |
| 46 | /* The function of the PCS block is to encode 8 bit */ |
| 47 | /* transmit data into 10 bit codes, decode 10 bit */ |
| 48 | /* receive data coes into 8 bit codes, perform word */ |
| 49 | /* synchronization on the incoming codes, detect */ |
| 50 | /* coding errors, detect disparity errors, perform */ |
| 51 | /* link configuration and adhere to the 802.3 */ |
| 52 | /* standard on register definitions and behavior. */ |
| 53 | /* */ |
| 54 | /* Assumptions : none. */ |
| 55 | /* */ |
| 56 | /* Parent module : gem_core.v */ |
| 57 | /* Child modules : none. */ |
| 58 | /* Author Name : Linda Chen */ |
| 59 | /* Date Created : 10/25/96 */ |
| 60 | /* */ |
| 61 | /* Copyright (c) 1994, Sun Microsystems, Inc. */ |
| 62 | /* Sun Proprietary and Confidential */ |
| 63 | /* */ |
| 64 | /* Modifications : */ |
| 65 | /* 7-30-97 : update ports to submodules for rev2 pcs update */ |
| 66 | /* Synthesis Notes : none yet */ |
| 67 | /**********************************************************************/ |
| 68 | |
| 69 | `include "pcs_define.h" |
| 70 | |
| 71 | module pcs ( |
| 72 | rxclk,rx_10bdata, // pcs_rx_dpath |
| 73 | rxd, |
| 74 | |
| 75 | rx_dv,rx_er, // pcs_rx_ctrl |
| 76 | |
| 77 | odd_rx,signal_detect, // pcs_sequence_detect |
| 78 | an_loss_sync, |
| 79 | |
| 80 | serdes_rdy, // pcs_link_configuration |
| 81 | link_up_tx, |
| 82 | |
| 83 | txclk,tx_en,tx_er, // pcs_tx_ctrl |
| 84 | crs,col, |
| 85 | |
| 86 | txd, // pcs_tx_dpath |
| 87 | tx_10bdata, |
| 88 | |
| 89 | clk,pio_core_reset, // pcs_slave |
| 90 | pio_core_sel,pio_rd_wr,pio_addr, |
| 91 | pio_wr_data,slink_state, |
| 92 | |
| 93 | pio_err,pio_core_ack,pio_rd_data, |
| 94 | sw_ensyncdet,sw_lockref,phy_mode, |
| 95 | shared_sel,pcs_int,ewrap); |
| 96 | |
| 97 | |
| 98 | /* |
| 99 | ** Inputs and Outputs from Rx Datapath |
| 100 | */ |
| 101 | input rxclk; // 125 MHz rx clock |
| 102 | input [9:0] rx_10bdata; // incoming 10 bits from link |
| 103 | output [7:0] rxd; // data going onto GMII |
| 104 | |
| 105 | /* |
| 106 | ** Inputs and Outputs from Rx Control |
| 107 | */ |
| 108 | output rx_dv; // receive data valid, GMII interface |
| 109 | output rx_er; // receive error, GMII interface |
| 110 | |
| 111 | /* |
| 112 | ** Output from Link Configuration |
| 113 | */ |
| 114 | input serdes_rdy; // from slink control block, serdes initialized |
| 115 | output link_up_tx; // signal to on-board LED, low pulse elongated |
| 116 | |
| 117 | /* |
| 118 | ** Inputs from Sequence Detect |
| 119 | */ |
| 120 | input odd_rx; // indicates alignment to word boundary |
| 121 | input signal_detect; // input from optics which indicates light ok |
| 122 | output an_loss_sync; // loss of word synchronization in rxclk domain |
| 123 | |
| 124 | /* |
| 125 | ** Inputs and Outputs from Tx Control |
| 126 | */ |
| 127 | input txclk; // Tx Clk 125 MHz |
| 128 | input tx_en; // GMII transmit enable from Mac |
| 129 | input tx_er; // GMII transmit error from Mac |
| 130 | output crs; // async carrier sense signal over GMII |
| 131 | output col; // async collision signal over GMII |
| 132 | |
| 133 | /* |
| 134 | ** Input and Output from Tx Datapath |
| 135 | */ |
| 136 | input [7:0] txd; // byte from MAC over GMII |
| 137 | output [9:0] tx_10bdata; // symbol to send over link |
| 138 | |
| 139 | /* |
| 140 | ** Outputs from Slave |
| 141 | */ |
| 142 | input clk; // PCI clock 33 or 66 MHz |
| 143 | input pio_core_reset; // global hw reset, synchronous to pci clock |
| 144 | input pio_core_sel; // pio select for pcs |
| 145 | input pio_rd_wr; // pio read signal |
| 146 | input [6:0] pio_addr; // pio address - register memory map |
| 147 | input [17:0] pio_wr_data; // pio data in, don't need all 32 bits |
| 148 | input [1:0] slink_state; // serdes control state register |
| 149 | |
| 150 | output pio_err; |
| 151 | output pio_core_ack; // pio acknowledge |
| 152 | output [31:0] pio_rd_data; // pio read data out |
| 153 | output sw_ensyncdet; // sw override for ensyncdet, to slink_ctrl |
| 154 | output sw_lockref; // sw override for lockref, to slink_ctrl |
| 155 | output phy_mode; // selects network i/f, to phy dpath block |
| 156 | output [2:0] shared_sel; // used as a select for shared output pins |
| 157 | output pcs_int; // pcs link down interrupt, secondary interrupt |
| 158 | output ewrap; // to external serdes for loopback enable |
| 159 | |
| 160 | wire tx_er_d,tx_en_d,got3_config0_rx,enable_rx; |
| 161 | |
| 162 | /* |
| 163 | ** Internal Outputs from Rx datapath |
| 164 | */ |
| 165 | wire [7:0] rx_8bdata, // data from decoder |
| 166 | rx_8bdata_p, // data from decoder previous stage |
| 167 | rx_8bdata_pp; |
| 168 | wire kchar, |
| 169 | kchar_p, |
| 170 | kchar_pp; |
| 171 | wire disp_err, // disparity error flag for rx_8bdata |
| 172 | disp_err_p; |
| 173 | wire dec_err, // decoder error flag for rx_8bdata |
| 174 | dec_err_p; |
| 175 | wire got_d_linkconf_p; // flags special data character detected |
| 176 | |
| 177 | /* |
| 178 | ** Internal output from Rx Control |
| 179 | */ |
| 180 | wire [2:0] rx_d_sel; // receive data mux select |
| 181 | wire [2:0] rx_state_rx; // receive control state bits to slave |
| 182 | wire link_up_rx; // link up signal synchronized to rxclk |
| 183 | wire nxt_crs_mask; // mask crs_rx for early deassert |
| 184 | // for IPG count start |
| 185 | wire [10:0] rx_pkt_cnt_rx; // rx packet counter |
| 186 | |
| 187 | /* |
| 188 | ** Internal outputs from Sequence Detector/Word Synchronizer |
| 189 | */ |
| 190 | wire good3_Cnack_rx; // flag to link config, got 3 C's |
| 191 | wire good3_CorData_rx; // flag to link config, got 3 C's or data |
| 192 | wire got_C_rx; // flag to indicate currently receiving C chars |
| 193 | wire CorData_err_rx; // flag to indicate not receiving C or data |
| 194 | wire loss_sync_rx; // flag which indicates word synchronization |
| 195 | wire reset_rx; // synchronized here, to be used by rx_ctrl |
| 196 | wire [15:0] link_partner_rx; // link partner ability register to slave |
| 197 | wire [1:0] seq_state_rx; // sequence state machine bits to slave |
| 198 | wire [2:0] word_state_rx; // word synchronization state machine bits |
| 199 | wire crs_rx; // post-masked crs_rx due out with rx_dv |
| 200 | wire nxt_crs_rx; // unmasked crs_rx, used with rx_8bdata |
| 201 | |
| 202 | /* |
| 203 | ** Internal outputs from Link Configuration |
| 204 | */ |
| 205 | wire link_up_tx; // a signal to the MII status register |
| 206 | wire link_up_loc; // a local signal to the Tx datapath |
| 207 | wire [3:0] tx_enc_conf_sel; // encoder control lines |
| 208 | wire [1:0] txd_sel; // select for tx data mux |
| 209 | wire reset_tx; // synchronous reset to txclk |
| 210 | wire ack; // used in configuration register sent |
| 211 | wire odd_tx; // polarity for byte alignment on Tx side |
| 212 | wire [3:0] link_state_tx; // link configuration state bits to slave |
| 213 | wire res_auto_tx; // restart autonegotiation clr for MII config |
| 214 | wire lost_link_tx; // used to set link_status flag |
| 215 | wire set_lol_from_los_tx; // used for loss of link diag |
| 216 | wire set_lol_from_c_tx; // used for loss of link diag |
| 217 | wire [5:0] link_not_up_diag_tx; // used for link not up diag |
| 218 | wire link_up_filter_en; |
| 219 | |
| 220 | /* |
| 221 | ** Internal output from Tx Control |
| 222 | */ |
| 223 | wire [3:0] tx_enc_ctrl_sel; // control inputs for encoder |
| 224 | wire [3:0] tx_state_tx; // tx control state bits for slave |
| 225 | wire [10:0] tx_pkt_cnt_tx; // tx packet counter |
| 226 | |
| 227 | /* |
| 228 | ** Internal output from Tx Datapath |
| 229 | */ |
| 230 | wire pos_disp_tx_p; // positive disparity flag, last data |
| 231 | wire txd_eq_crs_ext; // incoming txd maps to crs ext code |
| 232 | |
| 233 | /* |
| 234 | ** Internal outputs from Slave |
| 235 | */ |
| 236 | wire res_auto_pci; // restart link configuration |
| 237 | wire col_test_pci; // collision test, pci clock domain |
| 238 | wire [12:0] adver_reg; // advertisement of capabilities |
| 239 | wire enable_pci; // PCS enable, otherwise looks like link down |
| 240 | wire autoneg_ena_pci;// enable for autonegotiation |
| 241 | wire reset_pci; // hw and sw reset to pci clock |
| 242 | wire signal_detect_pci; // processed version of signal_detect_optic |
| 243 | wire [1:0] jitter_study_pci; // select for tx data output mux |
| 244 | wire timer_override_pci; // used by aneg to shorten length of bringup |
| 245 | wire lost_link_pci; // used to clear lost_link_tx flag |
| 246 | wire set_lol_from_los_pci; // used for loss of link diag |
| 247 | wire set_lol_from_c_pci; // used for loss of link diag |
| 248 | wire comma_p; |
| 249 | wire k285w1_p; |
| 250 | |
| 251 | // vlint flag_non_name_based_inst off |
| 252 | pcs_rx_dpath pcs_rx_dpath (rxclk,reset_rx,enable_pci, // inputs |
| 253 | {rx_10bdata[0],rx_10bdata[1],rx_10bdata[2], |
| 254 | rx_10bdata[3],rx_10bdata[4],rx_10bdata[5], |
| 255 | rx_10bdata[6],rx_10bdata[7],rx_10bdata[8], |
| 256 | rx_10bdata[9]},rx_d_sel,link_up_rx, |
| 257 | |
| 258 | rxd, |
| 259 | rx_8bdata,kchar,disp_err,dec_err, // outputs |
| 260 | rx_8bdata_p,kchar_p,disp_err_p,dec_err_p, |
| 261 | rx_8bdata_pp,kchar_pp, |
| 262 | got_d_linkconf_p,comma_p,k285w1_p,enable_rx); |
| 263 | // vlint flag_non_name_based_inst on |
| 264 | |
| 265 | // vlint flag_non_name_based_inst off |
| 266 | pcs_rx_ctrl pcs_rx_ctrl (rxclk,reset_rx,enable_rx,link_up_tx, // inputs |
| 267 | kchar,rx_8bdata,kchar_p,rx_8bdata_p,kchar_pp, |
| 268 | rx_8bdata_pp,disp_err,dec_err,nxt_crs_rx, |
| 269 | got_d_linkconf_p,loss_sync_rx,odd_rx, |
| 270 | |
| 271 | rx_dv,rx_er,rx_d_sel,rx_state_rx,link_up_rx, // outputs |
| 272 | nxt_crs_mask, rx_pkt_cnt_rx); |
| 273 | // vlint flag_non_name_based_inst on |
| 274 | |
| 275 | // vlint flag_non_name_based_inst off |
| 276 | pcs_sequence_detect pcs_sequence_detect ( |
| 277 | rxclk,reset_pci, // inputs |
| 278 | kchar_p,disp_err_p,dec_err_p,rx_8bdata_p, |
| 279 | odd_rx,signal_detect_pci, |
| 280 | got_d_linkconf_p, |
| 281 | nxt_crs_mask,link_up_tx,comma_p,k285w1_p, |
| 282 | |
| 283 | good3_Cnack_rx,good3_CorData_rx, // outputs |
| 284 | got_C_rx,CorData_err_rx,nxt_crs_rx,crs_rx, |
| 285 | loss_sync_rx,reset_rx,link_partner_rx, |
| 286 | seq_state_rx,word_state_rx,got3_config0_rx); |
| 287 | // vlint flag_non_name_based_inst on |
| 288 | |
| 289 | // vlint flag_non_name_based_inst off |
| 290 | pcs_link_config pcs_link_config ( |
| 291 | txclk,reset_pci,res_auto_pci, // inputs |
| 292 | loss_sync_rx,pos_disp_tx_p, |
| 293 | good3_Cnack_rx,good3_CorData_rx, |
| 294 | got_C_rx,CorData_err_rx, |
| 295 | autoneg_ena_pci,serdes_rdy, |
| 296 | got3_config0_rx,timer_override_pci, |
| 297 | lost_link_pci,set_lol_from_los_pci, |
| 298 | set_lol_from_c_pci, |
| 299 | link_up_filter_en, |
| 300 | link_up_loc,link_up_tx, // outputs |
| 301 | tx_enc_conf_sel,txd_sel,reset_tx, |
| 302 | ack,odd_tx,res_auto_tx, |
| 303 | link_state_tx,an_loss_sync, |
| 304 | lost_link_tx,set_lol_from_los_tx, |
| 305 | set_lol_from_c_tx,link_not_up_diag_tx); |
| 306 | // vlint flag_non_name_based_inst on |
| 307 | |
| 308 | // vlint flag_non_name_based_inst off |
| 309 | pcs_tx_ctrl pcs_tx_ctrl (txclk,reset_tx,enable_pci, // inputs |
| 310 | odd_tx,tx_en_d,tx_er_d,pos_disp_tx_p, |
| 311 | crs_rx,txd_eq_crs_ext, |
| 312 | col_test_pci,link_up_tx, // outputs |
| 313 | |
| 314 | tx_enc_ctrl_sel,crs,col,tx_state_tx, |
| 315 | tx_pkt_cnt_tx); |
| 316 | // vlint flag_non_name_based_inst on |
| 317 | |
| 318 | // vlint flag_non_name_based_inst off |
| 319 | pcs_tx_dpath pcs_tx_dpath (txclk,reset_tx,txd,tx_en,tx_er, // inputs |
| 320 | adver_reg,ack,txd_sel, |
| 321 | tx_enc_ctrl_sel,tx_enc_conf_sel,link_up_loc, |
| 322 | jitter_study_pci, |
| 323 | |
| 324 | {tx_10bdata[0],tx_10bdata[1],tx_10bdata[2], // outputs |
| 325 | tx_10bdata[3],tx_10bdata[4],tx_10bdata[5], |
| 326 | tx_10bdata[6],tx_10bdata[7],tx_10bdata[8], |
| 327 | tx_10bdata[9]},tx_en_d,tx_er_d,txd_eq_crs_ext, |
| 328 | pos_disp_tx_p); |
| 329 | // vlint flag_non_name_based_inst on |
| 330 | |
| 331 | // vlint flag_non_name_based_inst off |
| 332 | pcs_slave pcs_slave ( |
| 333 | clk,pio_core_reset,pio_core_sel,pio_rd_wr, // inputs |
| 334 | pio_addr,pio_wr_data,link_up_tx,link_partner_rx, |
| 335 | rx_state_rx,tx_state_tx,word_state_rx,seq_state_rx, |
| 336 | link_state_tx,reset_tx,reset_rx, |
| 337 | res_auto_tx,slink_state, |
| 338 | signal_detect,lost_link_tx, |
| 339 | set_lol_from_los_tx,set_lol_from_c_tx, |
| 340 | rx_pkt_cnt_rx,tx_pkt_cnt_tx,link_not_up_diag_tx, |
| 341 | ack, |
| 342 | |
| 343 | link_up_filter_en,pio_err,pio_core_ack,pio_rd_data,// outputs |
| 344 | res_auto_pci,col_test_pci, |
| 345 | adver_reg,reset_pci,enable_pci, |
| 346 | autoneg_ena_pci,sw_ensyncdet,sw_lockref, |
| 347 | phy_mode,shared_sel, |
| 348 | pcs_int,ewrap,signal_detect_pci,jitter_study_pci, |
| 349 | timer_override_pci,lost_link_pci, |
| 350 | set_lol_from_los_pci,set_lol_from_c_pci); |
| 351 | // vlint flag_non_name_based_inst on |
| 352 | |
| 353 | endmodule |