| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: pcs_slave.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
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| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | // @(#)pcs_slave.v 1.10G |
| 36 | /**********************************************************************/ |
| 37 | /* Project Name : CASSINI */ |
| 38 | /* Module Name : PCS Slave Interface */ |
| 39 | /* Description : This module contains the decoder for the registers*/ |
| 40 | /* programmable through the PCI slave interface. */ |
| 41 | /* The configuration register, the state machine */ |
| 42 | /* register, the PCS MII Configuration register, */ |
| 43 | /* the PCS MII Status register, the PCS MII */ |
| 44 | /* Advertisement register, the PCS MII Link Partner */ |
| 45 | /* Ability register, the PHY Datapath Mode register */ |
| 46 | /* the Serialink Control register, and the Shared */ |
| 47 | /* Output Select register are stored in this module. */ |
| 48 | /* */ |
| 49 | /* The PHY Datapath Mode, Serialink Control, and */ |
| 50 | /* Shared Output Select registers are not used by */ |
| 51 | /* the PCS, but pass on to the PHY Datapath block */ |
| 52 | /* Serialink Control blocks. They are not affected */ |
| 53 | /* by PCS SW reset. */ |
| 54 | /* */ |
| 55 | /* The Advertisement registers should not be written */ |
| 56 | /* unless PCS is disabled. */ |
| 57 | /* */ |
| 58 | /* Read/Write Registers available through PIO are: */ |
| 59 | /* o PCS Configuration Register */ |
| 60 | /* o PCS MII Configuration Register */ |
| 61 | /* o PCS MII Advertisement Register */ |
| 62 | /* o PHY Datapath Mode Register */ |
| 63 | /* o Serialink Control Register */ |
| 64 | /* o Shared Output Select Register */ |
| 65 | /* Read Only Registers available through PIO are: */ |
| 66 | /* o PCS State Machine Register */ |
| 67 | /* o PCS MII Status Register */ |
| 68 | /* o PCS MII Link Partner Ability Register */ |
| 69 | /* o SERDES control state Register */ |
| 70 | /* o Packet Counter */ |
| 71 | /* */ |
| 72 | /* Assumptions : A PCS PIO select is going to come from the SEB */ |
| 73 | /* block. This does the initial decode to determine */ |
| 74 | /* that the PIO access falls into the Rx register */ |
| 75 | /* space. */ |
| 76 | /* */ |
| 77 | /* Parent module : pcs.v */ |
| 78 | /* Child modules : none */ |
| 79 | /* Author Name : Linda Chen */ |
| 80 | /* Date Created : 10/25/96 */ |
| 81 | /* */ |
| 82 | /* Copyright (c) 1994, Sun Microsystems, Inc. */ |
| 83 | /* Sun Proprietary and Confidential */ |
| 84 | /* */ |
| 85 | /* Modifications : 4/21/98 - added link_not_up_diag_tx bits, added */ |
| 86 | /* rx and tx packet counters. */ |
| 87 | /* 8/6/98 */ |
| 88 | /* - addition of 5 link diagnostic bits for */ |
| 89 | /* why link is not coming up. */ |
| 90 | /* - addition of packets transmitted and received */ |
| 91 | /* counters, available to read through PIO */ |
| 92 | /* - make the ack bit readable from the Advertisement */ |
| 93 | /* register */ |
| 94 | /* - remove the Serialink specific control bits */ |
| 95 | /* - make the loopback bit to external serdes active high*/ |
| 96 | /* - remove the wrapback bit from MII Config */ |
| 97 | /* - make the signal_detect override bit non-resettable */ |
| 98 | /* - remove the tx output enable bit and serialink */ |
| 99 | /* enable bit from the phy_dpath register */ |
| 100 | /* */ |
| 101 | /* Synthesis Notes : none yet */ |
| 102 | /**********************************************************************/ |
| 103 | |
| 104 | `include "pcs_define.h" |
| 105 | |
| 106 | module pcs_slave ( |
| 107 | clk,pio_core_reset,pio_core_sel,pio_rd_wr, // inputs |
| 108 | pio_addr,pio_wr_data,link_up_tx,link_partner_rx, |
| 109 | rx_state_rx,tx_state_tx,word_state_rx,seq_state_rx, |
| 110 | link_state_tx,reset_tx,reset_rx, |
| 111 | res_auto_tx,slink_state, |
| 112 | signal_detect_optic,lost_link_tx, |
| 113 | set_lol_from_los_tx,set_lol_from_c_tx, |
| 114 | rx_pkt_cnt_rx,tx_pkt_cnt_tx,link_not_up_diag_tx, |
| 115 | ack, |
| 116 | |
| 117 | link_up_filter_en,pio_err,pio_core_ack,pio_rd_data,// outputs |
| 118 | res_auto_pci,col_test_pci, |
| 119 | adver_reg,reset_pci,enable_pci, |
| 120 | autoneg_ena_pci,sw_ensyncdet,sw_lockref, |
| 121 | phy_mode,shared_sel, |
| 122 | pcs_int,ewrap,signal_detect_pci,jitter_study_pci, |
| 123 | timer_override_pci,lost_link_pci, |
| 124 | set_lol_from_los_pci,set_lol_from_c_pci); |
| 125 | |
| 126 | |
| 127 | input clk; // PCI clock 33 or 66 MHz |
| 128 | input pio_core_reset; // global hw reset, synchronous to pci clock |
| 129 | input pio_core_sel; // pio select for pcs |
| 130 | input pio_rd_wr; // pio read signal |
| 131 | input [6:0] pio_addr; // pio address - register memory map |
| 132 | input [17:0] pio_wr_data; // pio data in |
| 133 | |
| 134 | input link_up_tx; // link status from tx clock domain |
| 135 | input [15:0] link_partner_rx;// link partner ability from rx clock |
| 136 | input [2:0] rx_state_rx; // rx control state in rx clock domain |
| 137 | input [3:0] tx_state_tx; // tx control state in tx clock domain |
| 138 | input [2:0] word_state_rx; // word synchronizatoin state, rx clock domain |
| 139 | input [1:0] seq_state_rx; // sequencer state , rx clock domain |
| 140 | input [3:0] link_state_tx; // Link Configuration state, tx clock domain |
| 141 | input reset_tx; // used to clear reset bit |
| 142 | input reset_rx; // used to clear reset bit |
| 143 | input res_auto_tx; // used to clear restart autonegotiation bit |
| 144 | input [1:0] slink_state; // serdes control block state bits |
| 145 | input signal_detect_optic; // signal detect raw from the optic |
| 146 | input lost_link_tx; // used to set link_status |
| 147 | input set_lol_from_los_tx; // sets diag bit for why link was lost |
| 148 | input set_lol_from_c_tx; // sets diag bit for why link was lost |
| 149 | input [10:0] rx_pkt_cnt_rx; // receive packet count |
| 150 | input [10:0] tx_pkt_cnt_tx; // transmit packet count |
| 151 | input [5:0] link_not_up_diag_tx; // diagnostic bits |
| 152 | input ack; // ack bit for adver reg |
| 153 | |
| 154 | output link_up_filter_en; |
| 155 | output pio_err; |
| 156 | output pio_core_ack; // pio acknowledge |
| 157 | output [31:0] pio_rd_data; // pio read data out |
| 158 | |
| 159 | output res_auto_pci; // restart link configuration |
| 160 | output col_test_pci; // collision test, pci clock domain |
| 161 | output [12:0] adver_reg; // advertisement of capabilities |
| 162 | output reset_pci; // hw and sw reset |
| 163 | output enable_pci; // PCS enable, otherwise looks like link down |
| 164 | output autoneg_ena_pci;// autonegotiation enable |
| 165 | output sw_lockref; // sw override for lockref |
| 166 | output sw_ensyncdet; // sw override for ensyncdet |
| 167 | output ewrap; // loopback enable for external serdes |
| 168 | output phy_mode; // selects network i/f, to phy dpath block |
| 169 | output [2:0] shared_sel; // used as a select for shared output pins |
| 170 | output pcs_int; // pcs link up interrupt |
| 171 | output signal_detect_pci; // active high post processed version of |
| 172 | // signal_detect_optic |
| 173 | output [1:0] jitter_study_pci;// select for tx datapath output mux |
| 174 | output timer_override_pci;// to autoneg to shorten length of bringup |
| 175 | output lost_link_pci; // used to clear lost_link_tx flag |
| 176 | output set_lol_from_los_pci; // used to clear set in link config |
| 177 | output set_lol_from_c_pci; // used to clear set in link config |
| 178 | |
| 179 | wire hw_reset ; // register version of pio_core_reset. -loj 4/4/02 |
| 180 | wire write_pulse; // decoded the event of pio write,no err |
| 181 | wire read_pulse; // decoded the event of pio read |
| 182 | wire link_up_pci; // synchronized version of link_up_tx |
| 183 | wire link_up_pci_d; // synchronized version of link_up_tx, delayed |
| 184 | wire sw_reset; // software reset from MII config register |
| 185 | wire nxt_sw_reset; // stays high until reset comes back from tx/rx |
| 186 | wire set_reset; // set software reset |
| 187 | wire our_fault; // remote fault (partner sees no light) |
| 188 | wire set_our_fault; // set our remote fault bit for MII status |
| 189 | wire nxt_our_fault; // remote fault (partner sees no light) |
| 190 | wire [1:0] link_partner_bit1312; // our rem fault bit, partner sees no lt. |
| 191 | wire clr_status; // read of status by pio |
| 192 | wire set_link_status;// detect condition of link down |
| 193 | wire link_status; // part of MII status register (link is down) |
| 194 | wire nxt_link_status;// part of MII status register (link is down) |
| 195 | wire set_res_auto; // pulse for restart autonegotiation |
| 196 | wire clr_res_auto; // clr upon read for autonegotiation restart |
| 197 | wire res_auto_pci; // restart autoneg signal, to link config |
| 198 | wire nxt_res_auto_pci;// restart autoneg signal, to link config |
| 199 | wire [16:0] state_bits_pci; // state bits synchronized |
| 200 | wire auto_complete; // autonegotiation complete |
| 201 | reg reset_pci; // hw and sw reset for PCS |
| 202 | wire core_sel_d; // delayed version of core sel, wait for |
| 203 | wire core_sel_dd; // arrival of perr_slv to generate write pulse |
| 204 | wire clr_reset_t; // synchronized from tx to pci time domain |
| 205 | wire clr_reset_r; // synchronized from rx to pci time domain |
| 206 | wire set_pcs_int; // pcs set upon link change |
| 207 | wire clr_pcs_int; // pcs clear upon read of register |
| 208 | wire nxt_pcs_int; // pcs link change interrupt |
| 209 | wire pcs_mask; // pcs global interrupt mask bit. |
| 210 | wire pio_core_sel_d; // delayed one cycle for timing |
| 211 | wire [1:0] slink_state_pci;// synchronized version of serdes control state |
| 212 | wire [15:0] link_partner_pci;// synchronized version of link_partner_rx |
| 213 | wire sig_det_polarity_change; // if high indicates signal_detect_optic |
| 214 | // should be interpreted as active low |
| 215 | wire sig_det_override;// indicates that signal_detect should not affect |
| 216 | // the link |
| 217 | wire signal_detect_optic_pci; // signal_detect raw from optic |
| 218 | // synchronized to pci clock domain |
| 219 | wire autoneg_ena_pci_d; // to detect change |
| 220 | wire an_ena_change; // to detect changein autonegotiation enable |
| 221 | wire read_state; // read pulse for state machine register, |
| 222 | // clears 3 diag bits |
| 223 | wire nxt_lost_sig_det; // used for loss of link diag |
| 224 | wire nxt_lol_from_los; // used for loss of link diag |
| 225 | wire nxt_lol_from_c; // used for loss of link diag |
| 226 | wire lost_sig_det; // used for loss of link diag |
| 227 | wire lol_from_los; // used for loss of link diag |
| 228 | wire lol_from_c; // used for loss of link diag |
| 229 | wire set_lost_sig_det; // used for loss of link diag |
| 230 | wire signal_detect_pci_d;// used for loss of link diag |
| 231 | wire [21:0] pkt_cnt; // used for link not up diag |
| 232 | wire [5:0] link_not_up_diag_pci;// synchronized to pci clock domain |
| 233 | wire [6:0] pio_addr_d; // for timing |
| 234 | wire pio_rd_wr_d; // for timing |
| 235 | wire [31:0] pio_rd_data; // to SEB |
| 236 | wire [17:0] pio_wr_data; |
| 237 | // vlint flag_net_has_no_load off |
| 238 | // vlint flag_dangling_net_within_module off |
| 239 | wire [17:0] slv_write_data; |
| 240 | // vlint flag_dangling_net_within_module on |
| 241 | // vlint flag_net_has_no_load on |
| 242 | reg [31:0] rd_data; |
| 243 | reg [12:0] adver_reg; // advertisement config reg |
| 244 | reg autoneg_ena_pci;// autnegotation enable bit in MII config |
| 245 | reg ewrap; // ser_ctrl to serdes directly for loopback |
| 246 | reg sw_lockref; // ser_ctrl to slink_ctrl |
| 247 | reg sw_ensyncdet; // ser_ctrl to slink_ctrl |
| 248 | reg pio_err; |
| 249 | wire pio_core_ack; |
| 250 | wire pio_core_ack_p1; |
| 251 | |
| 252 | |
| 253 | /* |
| 254 | ** PIO generic decode |
| 255 | ** The decode is same for read and write |
| 256 | ** These signals are used to control the output mux for pio_rd_data |
| 257 | */ |
| 258 | wire gen_sel_MII_conf = pio_core_sel_d & (pio_addr_d == `PHY_PIO_MII_CONF); |
| 259 | wire gen_sel_MII_status = pio_core_sel_d & (pio_addr_d == `PHY_PIO_MII_STAT); |
| 260 | wire gen_sel_MII_adver = pio_core_sel_d & (pio_addr_d == `PHY_PIO_MII_ADVER); |
| 261 | wire gen_sel_MII_partn = pio_core_sel_d & (pio_addr_d == `PHY_PIO_MII_PARTNER); |
| 262 | wire gen_sel_conf = pio_core_sel_d & (pio_addr_d == `PHY_PIO_CONF_REG); |
| 263 | wire gen_sel_state = pio_core_sel_d & (pio_addr_d == `PHY_PIO_STATE); |
| 264 | wire gen_sel_dpath = pio_core_sel_d & (pio_addr_d == `PHY_PIO_DPATH_MODE); |
| 265 | wire gen_sel_serctrl = pio_core_sel_d & (pio_addr_d == `PHY_PIO_SER_CTRL); |
| 266 | wire gen_sel_shared = pio_core_sel_d & (pio_addr_d == `PHY_PIO_SHARED); |
| 267 | wire gen_sel_pcs_int = pio_core_sel_d & (pio_addr_d == `PHY_PIO_INTERRUPT); |
| 268 | wire gen_sel_ser_state = pio_core_sel_d & (pio_addr_d == `PHY_PIO_SER_STATE); |
| 269 | wire gen_sel_pkt_cnt = pio_core_sel_d & (pio_addr_d == `PHY_PIO_PKT_CNT); |
| 270 | |
| 271 | // register pio_err |
| 272 | always @ (posedge clk) |
| 273 | begin |
| 274 | pio_err <= pio_core_ack_p1 & // equivalent of addr_err = non_qualified_addr_err & pio_core_sel_d |
| 275 | ~(gen_sel_MII_conf | |
| 276 | gen_sel_MII_status | |
| 277 | gen_sel_MII_adver | |
| 278 | gen_sel_MII_partn | |
| 279 | gen_sel_conf | |
| 280 | gen_sel_state | |
| 281 | gen_sel_dpath | |
| 282 | gen_sel_serctrl | |
| 283 | gen_sel_shared | |
| 284 | gen_sel_pcs_int | |
| 285 | gen_sel_ser_state | |
| 286 | gen_sel_pkt_cnt); |
| 287 | end |
| 288 | |
| 289 | |
| 290 | /* |
| 291 | ** PIO write selects |
| 292 | */ |
| 293 | wire pio_sel_MII_conf = gen_sel_MII_conf & write_pulse; |
| 294 | wire pio_sel_MII_adver = gen_sel_MII_adver & write_pulse; |
| 295 | wire pio_sel_conf = gen_sel_conf & write_pulse; |
| 296 | wire pio_sel_dpath = gen_sel_dpath & write_pulse; |
| 297 | wire pio_sel_serctrl = gen_sel_serctrl & write_pulse; |
| 298 | wire pio_sel_shared = gen_sel_shared & write_pulse; |
| 299 | wire [1:0] phy_mode_ext; // all bits of the phy mode so sw can read it back |
| 300 | |
| 301 | RegDff #(1) hpio_core_ack_RegDff (.din(pio_core_ack_p1),.clk(clk), |
| 302 | .qout(pio_core_ack)); |
| 303 | |
| 304 | assign pio_core_ack_p1 = core_sel_d & ~core_sel_dd, |
| 305 | write_pulse = pio_core_ack_p1 & ~pio_rd_wr_d, |
| 306 | read_pulse = pio_core_ack_p1 & pio_rd_wr_d, |
| 307 | |
| 308 | set_reset = pio_sel_MII_conf & slv_write_data[15], |
| 309 | nxt_sw_reset = (hw_reset|set_reset) ? 1'h1 : |
| 310 | (clr_reset_t & clr_reset_r) ? 1'h0 : sw_reset, |
| 311 | set_res_auto = pio_sel_MII_conf & slv_write_data[9], |
| 312 | /* |
| 313 | ** Standard specifies that restart an should occur |
| 314 | ** upon change of autoneg enable, or when restart |
| 315 | ** autoneg is set along with autoneg enable. |
| 316 | */ |
| 317 | nxt_res_auto_pci = (reset_pci) ? 1'b0 : |
| 318 | ((set_res_auto & autoneg_ena_pci)|(an_ena_change)) ? 1'b1 : |
| 319 | (clr_res_auto) ? 1'b0 : res_auto_pci, |
| 320 | an_ena_change = (autoneg_ena_pci & ~autoneg_ena_pci_d) | |
| 321 | (~autoneg_ena_pci & autoneg_ena_pci_d ), |
| 322 | set_link_status = (lost_link_pci | res_auto_pci), // detect link down |
| 323 | clr_status = read_pulse & gen_sel_MII_status, |
| 324 | set_pcs_int = (~link_up_pci & link_up_pci_d) | // link going down |
| 325 | (link_up_pci & ~link_up_pci_d), // link going up |
| 326 | clr_pcs_int = read_pulse & gen_sel_pcs_int, |
| 327 | nxt_pcs_int = (set_pcs_int) ? 1'h1 : |
| 328 | (clr_pcs_int) ? 1'h0 : pcs_int, |
| 329 | nxt_link_status = (set_link_status)? 1'h0 : |
| 330 | (reset_pci | clr_status) ? link_up_pci : link_status, |
| 331 | auto_complete = link_up_pci & autoneg_ena_pci, |
| 332 | set_our_fault = (|link_partner_bit1312) & link_up_pci, |
| 333 | nxt_our_fault = (reset_pci)? 1'h0 : (set_our_fault)? 1'h1 : |
| 334 | (clr_status)? 1'h0 : our_fault, |
| 335 | phy_mode = phy_mode_ext[1], // don't need to pass lsb |
| 336 | link_up_filter_en = phy_mode_ext[0], |
| 337 | /* |
| 338 | ** Signal_detect needs to be held at 1 during loopback since |
| 339 | ** the optic is not operational during those modes. |
| 340 | ** In external serdes mode, the sig_det_override should be programmed |
| 341 | ** to "1". For slink mode loopbacks automatically override sig_det. |
| 342 | */ |
| 343 | signal_detect_pci = (sig_det_override|ewrap)? 1'h1 : |
| 344 | (sig_det_polarity_change) ? ~signal_detect_optic_pci : |
| 345 | signal_detect_optic_pci, |
| 346 | set_lost_sig_det = ~signal_detect_pci & signal_detect_pci_d, |
| 347 | read_state = read_pulse & gen_sel_state, |
| 348 | nxt_lost_sig_det = (reset_pci) ? 1'h0 : (set_lost_sig_det)? 1'h1: |
| 349 | (read_state)? 1'h0 : lost_sig_det, |
| 350 | nxt_lol_from_los = (reset_pci) ? 1'h0 : (set_lol_from_los_pci)? 1'h1: |
| 351 | (read_state)? 1'h0 : lol_from_los, |
| 352 | nxt_lol_from_c = (reset_pci) ? 1'h0 : (set_lol_from_c_pci)? 1'h1: |
| 353 | (read_state)? 1'h0 : lol_from_c; |
| 354 | |
| 355 | always @ (posedge clk) |
| 356 | reset_pci <= hw_reset | sw_reset; |
| 357 | |
| 358 | |
| 359 | always@(posedge clk) |
| 360 | begin |
| 361 | if (reset_pci) |
| 362 | autoneg_ena_pci <= 1'h1; // default is one |
| 363 | else if (pio_sel_MII_conf) |
| 364 | autoneg_ena_pci <= slv_write_data[12]; |
| 365 | else |
| 366 | autoneg_ena_pci <= autoneg_ena_pci; |
| 367 | end |
| 368 | |
| 369 | /* |
| 370 | ** Advertisement Register (what we advertise) |
| 371 | */ |
| 372 | always @(posedge clk) |
| 373 | begin |
| 374 | if (reset_pci) |
| 375 | adver_reg <= 13'he0; // pause bits, duplex bits on |
| 376 | else if (pio_sel_MII_adver) |
| 377 | adver_reg <= {slv_write_data[13],slv_write_data[11:0]}; |
| 378 | else |
| 379 | adver_reg <= adver_reg; |
| 380 | end |
| 381 | |
| 382 | /* |
| 383 | ** Serdes Control Register |
| 384 | */ |
| 385 | |
| 386 | //summit modcovoff -bpe |
| 387 | always @(posedge clk) |
| 388 | begin |
| 389 | if (hw_reset) |
| 390 | begin |
| 391 | ewrap <= 1'h0; |
| 392 | sw_lockref <= 1'h0; |
| 393 | sw_ensyncdet <= 1'h0; |
| 394 | end |
| 395 | else if (pio_sel_serctrl) |
| 396 | begin |
| 397 | ewrap <= slv_write_data[0]; |
| 398 | sw_ensyncdet <= slv_write_data[1]; |
| 399 | sw_lockref <= slv_write_data[2]; |
| 400 | end |
| 401 | else |
| 402 | begin |
| 403 | ewrap <= ewrap; |
| 404 | sw_ensyncdet <= sw_ensyncdet; |
| 405 | sw_lockref <= sw_lockref; |
| 406 | end |
| 407 | end |
| 408 | //summit modcovon -bpe |
| 409 | |
| 410 | /* |
| 411 | ** PIO Data out Muxd register |
| 412 | */ |
| 413 | always @(ack or adver_reg or auto_complete |
| 414 | or autoneg_ena_pci or col_test_pci or enable_pci or ewrap |
| 415 | or gen_sel_MII_adver or gen_sel_MII_conf or gen_sel_MII_partn |
| 416 | or gen_sel_MII_status or gen_sel_conf or gen_sel_dpath |
| 417 | or gen_sel_pcs_int or gen_sel_pkt_cnt or gen_sel_ser_state |
| 418 | or gen_sel_serctrl or gen_sel_shared or gen_sel_state |
| 419 | or jitter_study_pci or link_not_up_diag_pci |
| 420 | or link_partner_pci or link_status or lol_from_c |
| 421 | or lol_from_los or lost_sig_det or our_fault or pcs_int |
| 422 | or pcs_mask or phy_mode_ext or pkt_cnt or res_auto_pci |
| 423 | or shared_sel or sig_det_override or sig_det_polarity_change |
| 424 | or slink_state_pci or state_bits_pci or sw_ensyncdet |
| 425 | or sw_lockref or sw_reset or timer_override_pci) |
| 426 | begin |
| 427 | casez({gen_sel_pkt_cnt,gen_sel_ser_state,gen_sel_pcs_int, |
| 428 | gen_sel_MII_conf,gen_sel_MII_status,gen_sel_MII_adver, |
| 429 | gen_sel_MII_partn,gen_sel_conf,gen_sel_state, |
| 430 | gen_sel_dpath,gen_sel_serctrl,gen_sel_shared}) |
| 431 | 12'b1???_????_????: // Packet counter |
| 432 | rd_data = {5'b0,pkt_cnt[21:11],5'b0,pkt_cnt[10:0]}; |
| 433 | 12'b01??_????_????: // Serdes Control State/home/ Register |
| 434 | rd_data = {30'b0,slink_state_pci}; |
| 435 | 12'b001?_????_????: // Interrupt Register |
| 436 | rd_data = {29'b0,pcs_int,2'b0}; |
| 437 | 12'b0001_????_????: // MII configuration |
| 438 | rd_data = {16'b0,sw_reset,2'b0,autoneg_ena_pci, |
| 439 | 2'h0,res_auto_pci,1'b0,col_test_pci,1'h1,6'h0}; |
| 440 | 12'b0000_1???_????: // MII status |
| 441 | rd_data = {23'h0,1'h1,2'h0,auto_complete,our_fault,1'b1, |
| 442 | link_status,2'b0}; |
| 443 | 12'b0000_01??_????: // MII advertisement |
| 444 | rd_data = {17'h0,ack,adver_reg[12],1'b0, |
| 445 | adver_reg[11:0]}; |
| 446 | 12'b0000_001?_????: // MII link partner ability |
| 447 | rd_data = {16'h0,link_partner_pci}; |
| 448 | 12'b0000_0001_????: // Configuration |
| 449 | rd_data = {25'h0,pcs_mask,timer_override_pci,jitter_study_pci, |
| 450 | sig_det_polarity_change,sig_det_override,enable_pci}; |
| 451 | 12'b0000_0000_1???: // State & Diag |
| 452 | rd_data = {2'b0,link_not_up_diag_pci,1'h0,lost_sig_det, |
| 453 | lol_from_los,lol_from_c,3'h0,state_bits_pci}; |
| 454 | 12'b0000_0000_01??: // Datapath mode |
| 455 | rd_data = {30'h0,phy_mode_ext}; |
| 456 | 12'b0000_0000_001?: // Serialink Control |
| 457 | rd_data = {29'h0,sw_lockref,sw_ensyncdet,ewrap}; |
| 458 | 12'b0000_0000_0001: // Shared output |
| 459 | rd_data = {29'h0,shared_sel}; |
| 460 | 12'b0000_0000_0000: // default |
| 461 | rd_data = {32'hdead_beef}; |
| 462 | default:rd_data = {32'hdead_beef}; |
| 463 | endcase |
| 464 | end // always @ (... |
| 465 | |
| 466 | |
| 467 | // register pio outputs |
| 468 | RegDff #(32) pio_rd_data_RegDff (.din(rd_data[31:0]),.clk(clk),.qout(pio_rd_data[31:0])); |
| 469 | /* |
| 470 | ** Registers |
| 471 | */ |
| 472 | // register pio inputs |
| 473 | RegDff #(18) slv_write_data_RegDff (.din(pio_wr_data[17:0]),.clk(clk),.qout(slv_write_data[17:0])); |
| 474 | RegDff #(1) hw_reset_RegDff (.din(pio_core_reset),.clk(clk),.qout(hw_reset)); |
| 475 | REG #(1) r_core_sel_d (core_sel_d, clk,pio_core_sel);// wait a cycle for wrst |
| 476 | REG #(1) r_core_sel_dd (core_sel_dd,clk,core_sel_d ); // case perror arrival |
| 477 | REG #(1) r_pio_core_sel_d (pio_core_sel_d,clk,pio_core_sel); // for timing |
| 478 | REG #(1) r_lost_sig_det (lost_sig_det,clk,nxt_lost_sig_det); |
| 479 | REG #(1) r_lol_from_los (lol_from_los,clk,nxt_lol_from_los); |
| 480 | REG #(1) r_lol_from_c (lol_from_c,clk,nxt_lol_from_c); |
| 481 | REG #(1) r_sd_d (signal_detect_pci_d,clk,signal_detect_pci); |
| 482 | REG #(1) r_pio_rd_wr_d (pio_rd_wr_d,clk,pio_rd_wr); |
| 483 | REG #(7) r_pio_addr_d (pio_addr_d,clk,pio_addr); |
| 484 | |
| 485 | // SYNCREG (qout, clk, din); |
| 486 | SYNCREG r_link_up_pci(link_up_pci,clk,link_up_tx); |
| 487 | SYNCREG17 r_state_bits (state_bits_pci,clk, {link_state_tx, |
| 488 | seq_state_rx,word_state_rx,1'b0,rx_state_rx,tx_state_tx}); |
| 489 | SYNCREG r_rem_fault13(link_partner_bit1312[1],clk,link_partner_rx[13]); |
| 490 | SYNCREG r_rem_fault12(link_partner_bit1312[0],clk,link_partner_rx[12]); |
| 491 | SYNCREG r_clr_reset_t(clr_reset_t,clk,reset_tx); |
| 492 | SYNCREG r_clr_reset_r(clr_reset_r,clk,reset_rx); |
| 493 | SYNCREG16 r_link_part_pci(link_partner_pci,clk,link_partner_rx); |
| 494 | SYNCREG r_ser_state1(slink_state_pci[1],clk,slink_state[1]); |
| 495 | SYNCREG r_ser_state0(slink_state_pci[0],clk,slink_state[0]); |
| 496 | SYNCREG r_lost_link(lost_link_pci,clk,lost_link_tx); |
| 497 | SYNCREG22 r_pkt_cnt(pkt_cnt,clk,{rx_pkt_cnt_rx,tx_pkt_cnt_tx}); |
| 498 | |
| 499 | SRREG #(1) r_col_test (col_test_pci,clk,pio_sel_MII_conf,reset_pci, |
| 500 | slv_write_data[7]); |
| 501 | |
| 502 | //SRREG #(6) r_pcs_config ({pcs_mask,timer_override_pci,jitter_study_pci, |
| 503 | // sig_det_polarity_change,enable_pci}, |
| 504 | // clk,pio_sel_conf,reset_pci,{slv_write_data[6:2],slv_write_data[0]}); |
| 505 | // vlint flag_net_has_no_load off |
| 506 | // vlint flag_dangling_net_within_module off |
| 507 | wire reserve1; |
| 508 | // vlint flag_dangling_net_within_module on |
| 509 | // vlint flag_net_has_no_load on |
| 510 | |
| 511 | xREG2 #(7) pcs_config_xREG2 (.clk(clk), |
| 512 | .reset(reset_pci), |
| 513 | .reset_value(7'b100_0000), |
| 514 | .load(pio_sel_conf), |
| 515 | .din(slv_write_data[6:0]), |
| 516 | .qout({pcs_mask,timer_override_pci,jitter_study_pci[1:0], |
| 517 | sig_det_polarity_change,reserve1,enable_pci})); |
| 518 | |
| 519 | EREG #(1) r_sig_det_override (sig_det_override,clk,pio_sel_conf, |
| 520 | slv_write_data[1]); // non-resetable |
| 521 | |
| 522 | //EREG (qout, clk, en, din); |
| 523 | //EREG #(2) r_phymode (phy_mode_ext,clk,pio_sel_dpath, |
| 524 | // slv_write_data[1:0]); |
| 525 | |
| 526 | xREG2 #(2) phy_mode_ext_xREG2(.clk(clk), |
| 527 | .reset(hw_reset), |
| 528 | .reset_value(2'b10), |
| 529 | .load(pio_sel_dpath), |
| 530 | .din(slv_write_data[1:0]), |
| 531 | .qout(phy_mode_ext)); |
| 532 | |
| 533 | SRREG #(3) r_shared (shared_sel,clk,pio_sel_shared,hw_reset, |
| 534 | slv_write_data[2:0]); |
| 535 | |
| 536 | SYNCREG r_clr_res_auto(clr_res_auto,clk,res_auto_tx); |
| 537 | SYNCREG r_sigdet_optic_pci(signal_detect_optic_pci,clk,signal_detect_optic); |
| 538 | |
| 539 | SYNCREG r_set_lol_from_los(set_lol_from_los_pci,clk,set_lol_from_los_tx); |
| 540 | SYNCREG r_set_lol_from_c(set_lol_from_c_pci,clk,set_lol_from_c_tx); |
| 541 | SYNCREG6 r_link_not_up(link_not_up_diag_pci,clk,link_not_up_diag_tx); |
| 542 | |
| 543 | // REG (qout, clk, din); |
| 544 | REG #(1) r_sw_reset(sw_reset,clk,nxt_sw_reset); |
| 545 | REG #(1) r_our_fault(our_fault,clk,nxt_our_fault); |
| 546 | REG #(1) r_link_status(link_status,clk,nxt_link_status); |
| 547 | REG #(1) r_res_auto(res_auto_pci,clk,nxt_res_auto_pci); |
| 548 | REG #(1) r_link_up_pci_d(link_up_pci_d,clk,link_up_pci); |
| 549 | REG #(1) r_an_ena_d(autoneg_ena_pci_d,clk,autoneg_ena_pci); |
| 550 | RREG #(1) r_pcs_int (pcs_int,clk,reset_pci | pcs_mask,nxt_pcs_int); |
| 551 | |
| 552 | endmodule |
| 553 | |