| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: pcs_tx_ctrl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | // @(#)pcs_tx_ctrl.v 1.5G |
| 36 | /**********************************************************************/ |
| 37 | /* Project Name : GEM */ |
| 38 | /* Module Name : PCS Tx Control Block */ |
| 39 | /* Description : This block sends control signals to the Encoder */ |
| 40 | /* block which indicates which characters should go */ |
| 41 | /* on the media. When link is down, the link config */ |
| 42 | /* block takes control over the media so the Tx */ |
| 43 | /* Control block controls are irrelevant at that */ |
| 44 | /* time. The controls are deasserted. */ |
| 45 | /* If the disparity is positive at the end of the */ |
| 46 | /* packet, disparity is flipped to negative. The */ |
| 47 | /* Start of Frame character always resides in an */ |
| 48 | /* even byte location. One or two bytes of the */ |
| 49 | /* preamble are replaced by the Tx Control block */ |
| 50 | /* depending on if the last character of Idle needs */ |
| 51 | /* to be sent out. One byte may be replaced with */ |
| 52 | /* the last portion of Idle, and one byte replaced */ |
| 53 | /* with the Start of Frame character. */ |
| 54 | /* */ |
| 55 | /* CRS and COL of the GMII interface are generated */ |
| 56 | /* here. They are asynchronous because they are *//* generated in part from crs_rx from the rx clock */ |
| 57 | /* domain. */ |
| 58 | /* */ |
| 59 | /* Assumptions : none. */ |
| 60 | /* */ |
| 61 | /* Parent module : pcs.v */ |
| 62 | /* Child modules : none. */ |
| 63 | /* Author Name : Linda Chen */ |
| 64 | /* Date Created : 10/18/96 */ |
| 65 | /* */ |
| 66 | /* Copyright (c) 1994, Sun Microsystems, Inc. */ |
| 67 | /* Sun Proprietary and Confidential */ |
| 68 | /* */ |
| 69 | /* Modifications : */ |
| 70 | /* 11/17/97 : removed tx_eq_crs_err signal */ |
| 71 | /* : deassert transmitting two bytes before idle */ |
| 72 | /* conditionally with odd lookahead */ |
| 73 | /* 12/9/98 : disabled crs upon ~enable_tx */ |
| 74 | /* Synthesis Notes : none yet */ |
| 75 | /**********************************************************************/ |
| 76 | |
| 77 | `include "pcs_define.h" |
| 78 | |
| 79 | module pcs_tx_ctrl (txclk,reset_tx,enable_pci, // inputs |
| 80 | odd_tx,tx_en_d,tx_er_d,pos_disp_tx_p, |
| 81 | crs_rx,txd_eq_crs_ext, |
| 82 | col_test_pci,link_up_tx, |
| 83 | |
| 84 | tx_enc_ctrl_sel,crs,col,tx_state_tx, |
| 85 | tx_pkt_cnt_tx); // outputs |
| 86 | |
| 87 | input txclk; // Tx Clk 125 MHz |
| 88 | input reset_tx; // hw and sw reset OR'ed |
| 89 | input enable_pci; // enable for PCS |
| 90 | input odd_tx; // byte polarity on media |
| 91 | input tx_en_d; // GMII transmit enable from Mac |
| 92 | input tx_er_d; // GMII transmit error from Mac |
| 93 | input pos_disp_tx_p; // disparity of data tx_8b_enc_in |
| 94 | input crs_rx; // activity on receive media |
| 95 | input txd_eq_crs_ext; // incoming txd maps to crs extension code |
| 96 | input col_test_pci; // collision test enable |
| 97 | input link_up_tx; // used to disable gmii inputs |
| 98 | |
| 99 | output [3:0] tx_enc_ctrl_sel; // control inputs for encoder |
| 100 | output crs; // async carrier sense signal over GMII |
| 101 | output col; // async collision signal over GMII |
| 102 | output [3:0] tx_state_tx; // tx control state bits to slave |
| 103 | output [10:0] tx_pkt_cnt_tx; // packet counter |
| 104 | |
| 105 | wire tx_err; // |
| 106 | wire crs, col; // GMII signals to MAC |
| 107 | wire [10:0] nxt_pkt_cnt; // next packet count value |
| 108 | wire enable_tx; // enable for PCS in tx clock domain |
| 109 | wire [3:0] tx_state_tx; // tx control state bits to slave |
| 110 | reg transmitting; // tx is actively transmitting |
| 111 | reg [3:0] tx_enc_ctrl_sel;// tx mux control |
| 112 | reg inc_pkt_cnt; // increment packet count |
| 113 | reg [3:0] nxt_tx_state_tx;// next state |
| 114 | reg tx_err_at_sop; |
| 115 | |
| 116 | wire tx_err_at_sop_d1; |
| 117 | |
| 118 | parameter K285 = 4'h0, |
| 119 | D_IDLE = 4'h1, |
| 120 | START_OF_STREAM = 4'h2, |
| 121 | TRANSMIT_STREAM = 4'h3, |
| 122 | CRS_EXT = 4'h4, |
| 123 | END_R = 4'h7, |
| 124 | CHECK_DISP = 4'h9, |
| 125 | FLIP_DISP = 4'hA; |
| 126 | |
| 127 | assign crs = enable_tx & (crs_rx | transmitting), |
| 128 | col = (col_test_pci | crs_rx) & transmitting, |
| 129 | nxt_pkt_cnt = (inc_pkt_cnt)? tx_pkt_cnt_tx + 1'h1 : tx_pkt_cnt_tx; |
| 130 | |
| 131 | FD1 tx_err_at_sop_d1_FD1(.CP(txclk), .D(tx_err_at_sop), .Q(tx_err_at_sop_d1)); |
| 132 | |
| 133 | assign tx_err = tx_err_at_sop_d1 | tx_er_d; |
| 134 | |
| 135 | /* Tx Control state machine */ |
| 136 | |
| 137 | |
| 138 | always @ (tx_state_tx or reset_tx or odd_tx or |
| 139 | tx_en_d or link_up_tx or enable_tx or |
| 140 | tx_err or tx_er_d or txd_eq_crs_ext or pos_disp_tx_p) |
| 141 | begin |
| 142 | transmitting = 1'h0; |
| 143 | tx_enc_ctrl_sel = `PCS_ENC_K285; |
| 144 | inc_pkt_cnt = 1'h0; |
| 145 | tx_err_at_sop = 1'b0; |
| 146 | nxt_tx_state_tx = K285; |
| 147 | |
| 148 | case (tx_state_tx) // synopsys parallel_case full_case |
| 149 | K285 : // 0 |
| 150 | if (reset_tx | odd_tx) |
| 151 | nxt_tx_state_tx = K285; |
| 152 | else if (tx_en_d & link_up_tx & enable_tx) |
| 153 | begin |
| 154 | transmitting = 1'h1; |
| 155 | tx_enc_ctrl_sel = `PCS_ENC_SOP; |
| 156 | tx_err_at_sop = tx_er_d; // loj |
| 157 | nxt_tx_state_tx = TRANSMIT_STREAM; |
| 158 | inc_pkt_cnt = 1'h1; |
| 159 | end |
| 160 | else |
| 161 | nxt_tx_state_tx = D_IDLE; |
| 162 | D_IDLE : // 1 |
| 163 | begin |
| 164 | tx_enc_ctrl_sel = `PCS_ENC_IDLE2; |
| 165 | if (tx_en_d & link_up_tx) |
| 166 | begin |
| 167 | inc_pkt_cnt = 1'h1; |
| 168 | nxt_tx_state_tx = START_OF_STREAM; |
| 169 | end |
| 170 | else |
| 171 | nxt_tx_state_tx = K285; |
| 172 | end |
| 173 | START_OF_STREAM : // 2 |
| 174 | begin |
| 175 | transmitting = 1'h1; |
| 176 | tx_enc_ctrl_sel = `PCS_ENC_SOP; |
| 177 | tx_err_at_sop = tx_er_d; // loj |
| 178 | nxt_tx_state_tx = TRANSMIT_STREAM; |
| 179 | end |
| 180 | TRANSMIT_STREAM : // 3 |
| 181 | if (tx_en_d) |
| 182 | begin |
| 183 | transmitting = 1'h1; |
| 184 | if (tx_err) |
| 185 | tx_enc_ctrl_sel = `PCS_ENC_H_CHAR; |
| 186 | else |
| 187 | tx_enc_ctrl_sel = `PCS_ENC_DATA; |
| 188 | nxt_tx_state_tx = TRANSMIT_STREAM; |
| 189 | end |
| 190 | else |
| 191 | begin |
| 192 | transmitting = 1'h1; |
| 193 | tx_enc_ctrl_sel = `PCS_ENC_T_CHAR; |
| 194 | nxt_tx_state_tx = TRANSMIT_STREAM; |
| 195 | if (txd_eq_crs_ext) |
| 196 | nxt_tx_state_tx = CRS_EXT; |
| 197 | else if (tx_err) |
| 198 | begin |
| 199 | tx_enc_ctrl_sel = `PCS_ENC_H_CHAR; |
| 200 | nxt_tx_state_tx = CRS_EXT; |
| 201 | end |
| 202 | else |
| 203 | begin |
| 204 | nxt_tx_state_tx = END_R; |
| 205 | transmitting = odd_tx; // if odd, 3rd byte from end |
| 206 | end |
| 207 | end |
| 208 | CRS_EXT : // 4 |
| 209 | begin // add extra R's |
| 210 | transmitting = 1'h1; |
| 211 | tx_enc_ctrl_sel = `PCS_ENC_R_CHAR; |
| 212 | if (txd_eq_crs_ext) |
| 213 | nxt_tx_state_tx = CRS_EXT; |
| 214 | else if (tx_err) // includes carrier extension error |
| 215 | begin |
| 216 | nxt_tx_state_tx = CRS_EXT; |
| 217 | tx_enc_ctrl_sel = `PCS_ENC_H_CHAR; |
| 218 | end |
| 219 | else if (tx_en_d) |
| 220 | begin |
| 221 | tx_enc_ctrl_sel = `PCS_ENC_SOP; |
| 222 | nxt_tx_state_tx = TRANSMIT_STREAM; |
| 223 | end |
| 224 | else |
| 225 | nxt_tx_state_tx = END_R; |
| 226 | end |
| 227 | END_R : // 7 |
| 228 | begin |
| 229 | tx_enc_ctrl_sel = `PCS_ENC_R_CHAR; |
| 230 | if (!odd_tx) |
| 231 | nxt_tx_state_tx = END_R; |
| 232 | else |
| 233 | nxt_tx_state_tx = CHECK_DISP; |
| 234 | end |
| 235 | CHECK_DISP : // 9 |
| 236 | |
| 237 | if (pos_disp_tx_p) |
| 238 | nxt_tx_state_tx = FLIP_DISP; |
| 239 | else |
| 240 | nxt_tx_state_tx = D_IDLE; |
| 241 | FLIP_DISP : // A |
| 242 | begin |
| 243 | tx_enc_ctrl_sel = `PCS_ENC_IDLE1; |
| 244 | nxt_tx_state_tx = K285; |
| 245 | end // case: FLIP_DISP |
| 246 | default:nxt_tx_state_tx = K285; |
| 247 | endcase |
| 248 | end |
| 249 | |
| 250 | // state registers |
| 251 | RREG #(4) tx_state_tx_RREG (tx_state_tx, txclk, reset_tx, nxt_tx_state_tx); |
| 252 | |
| 253 | RREG #(11) pkt_cnt_tx_RREG(tx_pkt_cnt_tx, txclk, reset_tx, nxt_pkt_cnt); |
| 254 | |
| 255 | SYNCREG enable_tx_SYNCREG(enable_tx,txclk,enable_pci); |
| 256 | |
| 257 | |
| 258 | endmodule // pcs_tx_ctrl |
| 259 | |
| 260 | |