| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: pcs_tx_dpath.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
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| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | // @(#)pcs_tx_dpath.v 1.2G |
| 36 | /**********************************************************************/ |
| 37 | /* Project Name : CASSINI */ |
| 38 | /* Module Name : PCS Tx Datapath Block */ |
| 39 | /* Description : The PCS Tx datapath contains the configuration */ |
| 40 | /* registers to be sent during link configuration, */ |
| 41 | /* the mux for encoder control between the Link */ |
| 42 | /* config block and Tx control block, the mux for */ |
| 43 | /* the data going into the Encoder block, Encoder */ |
| 44 | /* block, and registers on either side of the */ |
| 45 | /* Encoder block. These exist because the critical */ |
| 46 | /* path is in the Encoder. */ |
| 47 | /* */ |
| 48 | /* Running disparity is calculated on txd on a per */ |
| 49 | /* clock basis and passed onto Encoder. */ |
| 50 | /* */ |
| 51 | /* Assumptions : none. */ |
| 52 | /* */ |
| 53 | /* Parent module : pcs.v */ |
| 54 | /* Child modules : pcs_encoder.v pcs_rx_disparity.v */ |
| 55 | /* Author Name : Linda Chen */ |
| 56 | /* Date Created : 10/24/96 */ |
| 57 | /* */ |
| 58 | /* Copyright (c) 1994, Sun Microsystems, Inc. */ |
| 59 | /* Sun Proprietary and Confidential */ |
| 60 | /* */ |
| 61 | /* Modifications : */ |
| 62 | /* 11/3/97 : removed unnecessary flag for txd_eq_crs_err */ |
| 63 | /* 11/3/97 : set remote fault as long as signal_detect is FAIL */ |
| 64 | /* 10/2/98 : removed their fault bit to improve interoperability*/ |
| 65 | /* Synthesis Notes : none yet */ |
| 66 | /**********************************************************************/ |
| 67 | |
| 68 | `include "pcs_define.h" |
| 69 | |
| 70 | module pcs_tx_dpath (txclk,reset_tx,txd,tx_en,tx_er, // inputs |
| 71 | adver_reg,ack,txd_sel, |
| 72 | tx_enc_ctrl_sel,tx_enc_conf_sel,link_up_loc, |
| 73 | jitter_study_pci, |
| 74 | |
| 75 | tx_10bdata,tx_en_d,tx_er_d,txd_eq_crs_ext, // outputs |
| 76 | pos_disp_tx_p); |
| 77 | |
| 78 | input txclk; // 125 MHz clock |
| 79 | input reset_tx; // reset synchronized to txclk |
| 80 | input [7:0] txd; // byte from MAC over GMII |
| 81 | input tx_en; // control signal from MAC over GMII |
| 82 | input tx_er; // control signal from MAC over GMII |
| 83 | input [12:0] adver_reg; // reg to be used for configuration |
| 84 | // from PCI clock domain, but should |
| 85 | // never change when PCS enabled |
| 86 | input ack; // from link configuration state mach. |
| 87 | //input signal_detect; // from optics, light ok |
| 88 | input [1:0] txd_sel; // select between data and config regs |
| 89 | input [3:0] tx_enc_ctrl_sel; // encoder control from tx ctrl |
| 90 | input [3:0] tx_enc_conf_sel; // encoder control from link config |
| 91 | input link_up_loc; // select for tx_enc_sel mux |
| 92 | //input config_done; // clear for remote their fault |
| 93 | input [1:0] jitter_study_pci; // select for 10 bit data output mux |
| 94 | |
| 95 | output [9:0] tx_10bdata; // symbol to send over link |
| 96 | output tx_en_d; // to be used by tx_ctrl |
| 97 | output tx_er_d; // to be used by tx_ctrl |
| 98 | output txd_eq_crs_ext; // incoming txd maps to crs ext code |
| 99 | //output txd_eq_crs_err; // incoming txd maps to crs err code |
| 100 | output pos_disp_tx_p; // positive disparity flag, last data |
| 101 | //output their_fault_tx; // remote their fault, advertisement |
| 102 | |
| 103 | wire [7:0] txd_d; // input from MAC delayed one |
| 104 | wire [7:0] tx_8bdata_conf; // muxed MAC data and config regs |
| 105 | wire [7:0] tx_8b_enc_in; // bus which inputs to encoder |
| 106 | wire [9:0] tx_10b_enc_out; // bus which outputs from encoder |
| 107 | wire [3:0] tx_enc_sel; // encoder control, one cycle early |
| 108 | wire [3:0] encoder_sel; // encoder control, input to encoder |
| 109 | wire special_char; // special code, one cycle early |
| 110 | wire special_enc_in; // special code, for tx_8b_enc_in |
| 111 | wire [15:0] config_reg; // used for advertisement |
| 112 | wire pos_disp_tx_p; // running disparity for tx_8b_enc_in |
| 113 | //wire set_their_fault; // signal detect negedge |
| 114 | //wire nxt_their_fault; // used for latching remote their fault |
| 115 | //wire signal_detect_tx; // used for negedge detect of signal |
| 116 | wire [9:0] tx_10bdata_predel; // for hold time to Serialink |
| 117 | wire [9:0] tx_10bdata_todiag; // 10b data to diagnostic mux |
| 118 | wire [1:0] jitter_study_tx; // to select mux for tx 10b data |
| 119 | |
| 120 | wire pos_disp_tx; |
| 121 | |
| 122 | /* |
| 123 | ** Creation of flag to facilitate fast encoding of regular data |
| 124 | */ |
| 125 | assign special_char =((tx_enc_sel == `PCS_ENC_K285) | |
| 126 | (tx_enc_sel == `PCS_ENC_IDLE2) | |
| 127 | (tx_enc_sel == `PCS_ENC_SOP) | |
| 128 | (tx_enc_sel == `PCS_ENC_T_CHAR) | |
| 129 | (tx_enc_sel == `PCS_ENC_R_CHAR) | |
| 130 | (tx_enc_sel == `PCS_ENC_H_CHAR) | |
| 131 | (tx_enc_sel == `PCS_ENC_IDLE1) | |
| 132 | (tx_enc_sel == `PCS_ENC_LINK_CONFA) | |
| 133 | (tx_enc_sel == `PCS_ENC_LINK_CONFB)), |
| 134 | |
| 135 | config_reg = {1'b0,ack,adver_reg[12],1'b0,adver_reg[11:0]}, |
| 136 | txd_eq_crs_ext = tx_er_d & (txd_d == 8'h0F); |
| 137 | // txd_eq_crs_err = tx_er_d & (txd_d == 8'h1F), |
| 138 | // for pcs_tx_ctrl.v |
| 139 | /* old:set_their_fault = ~signal_detect_tx & signal_detect_tx_d, |
| 140 | ** this will indicate remote fault as long as signal_detect is failed |
| 141 | ** it gives management better visibility of signal_detect |
| 142 | ** loss of sync should occur if signal_detect indicates fail |
| 143 | */ |
| 144 | // set_their_fault = ~signal_detect_tx, |
| 145 | // nxt_their_fault = (reset_tx) ? 1'h0 : (set_their_fault) ? |
| 146 | // 1'h1 : (config_done) ? 1'h0 : their_fault_tx; |
| 147 | |
| 148 | /* |
| 149 | ** Input Reg for TXD |
| 150 | */ |
| 151 | RREG #(8) r_txd_d (.qout(txd_d),.clk(txclk),.rst(reset_tx),.din(txd)); |
| 152 | |
| 153 | /* |
| 154 | ** Mux between incoming GMII data, config reg lsb, and config reg msb |
| 155 | ** The default is the GMII data from MAC. Select is generated by |
| 156 | ** the Link Config state machine. Output feeds into pre encoder register. |
| 157 | */ |
| 158 | MUX4TO1 #(8) r_pre_enc_data_mux (.dout(tx_8bdata_conf),.sel(txd_sel), |
| 159 | .data0(txd_d),.data1(config_reg[7:0]),.data2(config_reg[15:8]), |
| 160 | .data3(8'h0)); |
| 161 | |
| 162 | /* |
| 163 | ** Pre Encoder Data Reg. Provides maximum time for encoder to encode 8b to 10b |
| 164 | */ |
| 165 | REG #(8) r_tx_8bdata_p (.qout(tx_8b_enc_in),.clk(txclk),.din(tx_8bdata_conf)); |
| 166 | |
| 167 | /* |
| 168 | ** Registered Control Signals from MAC (same level as Pre Encoder Data Reg |
| 169 | */ |
| 170 | RREG #(1) r_tx_en_d (.qout(tx_en_d),.clk(txclk),.rst(reset_tx),.din(tx_en)); |
| 171 | RREG #(1) r_tx_er_d (.qout(tx_er_d),.clk(txclk),.rst(reset_tx),.din(tx_er)); |
| 172 | |
| 173 | /* |
| 174 | ** Encoder - takes control inputs and data to create encoded 10b output |
| 175 | ** Outputs disparity for incoming data for link config (so it knows |
| 176 | ** whether to generate Idle1 or Idle2 next. |
| 177 | */ |
| 178 | pcs_encoder pcs_encoder (tx_8b_enc_in,encoder_sel, |
| 179 | special_enc_in,pos_disp_tx, |
| 180 | |
| 181 | tx_10b_enc_out); |
| 182 | |
| 183 | /* |
| 184 | ** Tx running disparity calculator |
| 185 | */ |
| 186 | pcs_tx_disparity pcs_tx_disparity (.reset_tx(reset_tx), // inputs |
| 187 | .txclk(txclk), .special_char(special_enc_in), |
| 188 | .tx_enc_sel(encoder_sel),.data(tx_8b_enc_in), |
| 189 | .RDreg(pos_disp_tx), |
| 190 | |
| 191 | .RD(pos_disp_tx_p)); // outputs |
| 192 | /* |
| 193 | ** Register to store running disparity |
| 194 | */ |
| 195 | RREG #(1) r_pos_disp_tx (.qout(pos_disp_tx), .din(pos_disp_tx_p), .clk(txclk), |
| 196 | .rst(reset_tx)); |
| 197 | |
| 198 | /* |
| 199 | ** Post Encoder Register. Provides maximum time for encoder to encode |
| 200 | ** Also provides plenty of setup time on the SERDES interface. |
| 201 | */ |
| 202 | REG #(10) r_tx_10bdata (.qout(tx_10bdata_todiag),.clk(txclk), |
| 203 | .din(tx_10b_enc_out)); |
| 204 | |
| 205 | /* |
| 206 | ** For jitter study, a high frequency pattern D21.5 and low frequency |
| 207 | ** pattern K28.7 are provided. |
| 208 | */ |
| 209 | MUX3TO1 #(10) r_tx_10b_diag (.dout(tx_10bdata_predel),.sel(jitter_study_tx), |
| 210 | .data0(tx_10bdata_todiag),.data1(10'h2aa),.data2(10'h0f8)); |
| 211 | |
| 212 | REG #(10) tx_10bdata_REG (.qout(tx_10bdata),.clk(txclk),.din(tx_10bdata_predel)); |
| 213 | |
| 214 | /* |
| 215 | ** 2:1 MUX for encoder select information |
| 216 | ** If link is down, encoder is controlled by link configuration state |
| 217 | ** machine. If link is up, encoder is controlled by tx control state machine |
| 218 | */ |
| 219 | MUX2TO1 #(4) r_tx_enc_sel(.dout(tx_enc_sel),.sel(link_up_loc), |
| 220 | .data0(tx_enc_conf_sel),.data1(tx_enc_ctrl_sel)); |
| 221 | |
| 222 | /* |
| 223 | ** Pre Encoder Register for Encoder controls. |
| 224 | */ |
| 225 | REG #(4) r_encoder_sel (.qout(encoder_sel),.clk(txclk),.din(tx_enc_sel)); |
| 226 | REG #(1) r_spec_enc (.qout(special_enc_in),.clk(txclk),.din(special_char)); |
| 227 | |
| 228 | /* |
| 229 | ** Registers for Remote "Their" Fault |
| 230 | */ |
| 231 | //SYNCREG r_signal_detect_tx(signal_detect_tx,txclk,signal_detect); |
| 232 | //REG #(1) r_their_fault (their_fault_tx, txclk, nxt_their_fault); |
| 233 | |
| 234 | SYNCREG r_jitter_study1(jitter_study_tx[1],txclk,jitter_study_pci[1]); |
| 235 | SYNCREG r_jitter_study0(jitter_study_tx[0],txclk,jitter_study_pci[0]); |
| 236 | |
| 237 | |
| 238 | endmodule |
| 239 | |