| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: rx_xmac.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
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| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /*%W% %G%*/ |
| 36 | |
| 37 | /************************************************************************* |
| 38 | * |
| 39 | * File Name : rx_xmac.v |
| 40 | * Author Name : John Lo |
| 41 | * Description : receive mac main block. In rx_clk domain |
| 42 | * Parent Module: xmac |
| 43 | * Child Module: many. |
| 44 | * Interface Mod: many. |
| 45 | * Date Created : 5/9/00 |
| 46 | * |
| 47 | * Copyright (c) 2008, Sun Microsystems, Inc. |
| 48 | * Sun Proprietary and Confidential |
| 49 | * |
| 50 | * Modification : major redesign for 64 bit xpcs interface. |
| 51 | * |
| 52 | * In Feb. 10th, 2004, the rxfifo overflow bug shows up again. |
| 53 | * It is caused by adding one more layer of pipeline register |
| 54 | * to add the strip_crc function. |
| 55 | * For this reason, the rxfifo_afull signal has to be extended 1 more. |
| 56 | * |
| 57 | * Design Notes: In 10G mode, when "E" happened in PA time the |
| 58 | * xmac behavior is different from 1G/100M/10M mode |
| 59 | * which will set the abort_bit. |
| 60 | * |
| 61 | * Here is the difference: |
| 62 | * ----------------------- |
| 63 | * When E happened in PA time, the S won't be |
| 64 | * detected and the packet will be filterred out |
| 65 | * on the spot. |
| 66 | * No abort_bit will be set since the packet did not even enter rx_xmac. |
| 67 | * |
| 68 | * Common Notes: "_a" represents column 0~3. |
| 69 | * "_b" represents column 4~7. |
| 70 | * |
| 71 | * Synthesis Notes: |
| 72 | * |
| 73 | * Static Timing Analysis Notes: |
| 74 | * 1. txd_image and txc_image are signals corssing |
| 75 | * different clock domain. Do STA check carefully. |
| 76 | * |
| 77 | *************************************************************************/ |
| 78 | |
| 79 | `include "xmac.h" |
| 80 | |
| 81 | module rx_xmac |
| 82 | (/*AUTOARG*/ |
| 83 | // Outputs |
| 84 | rxfifo_dout, rxfifo_g_wr_ptr_rxclk, rxfifo_full_rxclk_reg, |
| 85 | rxfifo_overrun_rxclk, srfifo_dout, srfifo_g_wr_ptr_rxclk, |
| 86 | rx_good_pkt, rx_fc_pkt_ok, pause_time, toggle_rx_bcount, |
| 87 | inc_bcast_count, inc_mcast_count, inc_code_viol_count, |
| 88 | inc_crc_err_count, inc_min_pkt_err_count, inc_max_pkt_err_count, |
| 89 | rx_data_valid_gmux_reg, rx_pa_data, link_fault, |
| 90 | inc_link_fault_count, remote_fault_oc_reg, local_fault_oc_reg, |
| 91 | lfs_state, xrlm_state, sop_state, S_detected_reg, |
| 92 | T_E_detected_at_modified_pkt_reg, |
| 93 | END_PKT_ERR_detected_a_at_modified_pkt_reg, |
| 94 | END_PKT_ERR_detected_b_at_modified_pkt_reg, S_D_reg, S_I_reg, |
| 95 | D_S_reg, I_S_reg, abort_bit_reg, rx_err_reg, crc_error_reg, |
| 96 | kill_data_ready_reg, kill_crc_reg, rx_sel_reg, |
| 97 | // Inputs |
| 98 | rx_clk, rx_reset, warning_msg_en, xgmii_rxc, xgmii_rxd, xpcs_rxc, |
| 99 | xpcs_rxd, txc_image, txd_image, hold_rxd, hold_rx_dv, hold_rx_err, |
| 100 | xpcs_bypass, mii_or_gmii_mode, loopback, rx_enable_rxclk, |
| 101 | code_viol_chk_dis, crc_chk_dis, promisc_all, promisc_group, |
| 102 | err_chk_dis, rx_pause_en, pass_fc, reserve_multicast, |
| 103 | mac_unique_addr, no_rx_min_pkt_size_chk, rx_min_pkt_size, |
| 104 | max_pkt_size, lfs_disable_rxclk, rxfifo_g_rd_ptr_sync, |
| 105 | rxfifo_rd_ptr_clk, srfifo_rd_ptr_clk, strip_crc, addr_filter_en, |
| 106 | hash_filter_en, alt_addr_comp_en, mac_alt_addr0, mac_alt_addr1, |
| 107 | mac_alt_addr2, mac_alt_addr3, mac_alt_addr4, mac_alt_addr5, |
| 108 | mac_alt_addr6, mac_alt_addr7, mac_alt_addr8, mac_alt_addr9, |
| 109 | mac_alt_addr10, mac_alt_addr11, mac_alt_addr12, mac_alt_addr13, |
| 110 | mac_alt_addr14, mac_alt_addr15, addr_filter, addr_filter_mask_msb, |
| 111 | addr_filter_mask_lsb, hash_table, mac_host_info0, mac_host_info1, |
| 112 | mac_host_info2, mac_host_info3, mac_host_info4, mac_host_info5, |
| 113 | mac_host_info6, mac_host_info7, mac_host_info8, mac_host_info9, |
| 114 | mac_host_info10, mac_host_info11, mac_host_info12, |
| 115 | mac_host_info13, mac_host_info14, mac_host_info15, |
| 116 | mac_host_info16, mac_host_info17, mac_host_info18, |
| 117 | mac_host_info19 |
| 118 | ); |
| 119 | |
| 120 | /* ------------------------------------------------------------------- */ |
| 121 | input rx_clk; |
| 122 | input rx_reset; |
| 123 | input warning_msg_en; |
| 124 | // xgmii interface |
| 125 | input [3:0] xgmii_rxc; |
| 126 | input [31:0] xgmii_rxd; |
| 127 | // xpcs interface |
| 128 | input [7:0] xpcs_rxc; |
| 129 | input [63:0] xpcs_rxd; |
| 130 | // loopback path |
| 131 | input [7:0] txc_image; // loopback path |
| 132 | input [63:0] txd_image; // loopback path |
| 133 | // gmii/mii path |
| 134 | input [63:0] hold_rxd; |
| 135 | input [7:0] hold_rx_dv; |
| 136 | input hold_rx_err; |
| 137 | // static signals from sys_clk domain |
| 138 | input xpcs_bypass; |
| 139 | input mii_or_gmii_mode; |
| 140 | input loopback; |
| 141 | input rx_enable_rxclk; |
| 142 | input code_viol_chk_dis; |
| 143 | input crc_chk_dis; |
| 144 | input promisc_all; |
| 145 | input promisc_group; |
| 146 | input err_chk_dis; |
| 147 | input rx_pause_en; |
| 148 | input pass_fc; |
| 149 | input reserve_multicast; |
| 150 | input [47:0] mac_unique_addr; |
| 151 | input no_rx_min_pkt_size_chk; |
| 152 | input [9:0] rx_min_pkt_size; |
| 153 | input [13:0] max_pkt_size; |
| 154 | input lfs_disable_rxclk; |
| 155 | // inter module signals |
| 156 | input [4:0] rxfifo_g_rd_ptr_sync; // ***** signal crossing different clock domain. ***** |
| 157 | input [3:0] rxfifo_rd_ptr_clk; // ***** signal crossing different clock domain. ***** |
| 158 | input [4:0] srfifo_rd_ptr_clk; // ***** signal crossing different clock domain. ***** |
| 159 | // start of ALT_ADDR_AND_HASH_FUNC specific signals |
| 160 | input strip_crc; |
| 161 | input addr_filter_en; |
| 162 | input hash_filter_en; |
| 163 | input [15:0] alt_addr_comp_en; |
| 164 | input [47:0] mac_alt_addr0; |
| 165 | input [47:0] mac_alt_addr1; |
| 166 | input [47:0] mac_alt_addr2; |
| 167 | input [47:0] mac_alt_addr3; |
| 168 | input [47:0] mac_alt_addr4; |
| 169 | input [47:0] mac_alt_addr5; |
| 170 | input [47:0] mac_alt_addr6; |
| 171 | input [47:0] mac_alt_addr7; |
| 172 | input [47:0] mac_alt_addr8; |
| 173 | input [47:0] mac_alt_addr9; |
| 174 | input [47:0] mac_alt_addr10; |
| 175 | input [47:0] mac_alt_addr11; |
| 176 | input [47:0] mac_alt_addr12; |
| 177 | input [47:0] mac_alt_addr13; |
| 178 | input [47:0] mac_alt_addr14; |
| 179 | input [47:0] mac_alt_addr15; |
| 180 | input [47:0] addr_filter; |
| 181 | input [7:0] addr_filter_mask_msb; |
| 182 | input [15:0] addr_filter_mask_lsb; |
| 183 | input [255:0] hash_table; |
| 184 | input [`H_INFO] mac_host_info0 ; |
| 185 | input [`H_INFO] mac_host_info1 ; |
| 186 | input [`H_INFO] mac_host_info2 ; |
| 187 | input [`H_INFO] mac_host_info3 ; |
| 188 | input [`H_INFO] mac_host_info4 ; |
| 189 | input [`H_INFO] mac_host_info5 ; |
| 190 | input [`H_INFO] mac_host_info6 ; |
| 191 | input [`H_INFO] mac_host_info7 ; |
| 192 | input [`H_INFO] mac_host_info8 ; |
| 193 | input [`H_INFO] mac_host_info9 ; |
| 194 | input [`H_INFO] mac_host_info10; |
| 195 | input [`H_INFO] mac_host_info11; |
| 196 | input [`H_INFO] mac_host_info12; |
| 197 | input [`H_INFO] mac_host_info13; |
| 198 | input [`H_INFO] mac_host_info14; |
| 199 | input [`H_INFO] mac_host_info15; |
| 200 | input [`H_INFO] mac_host_info16; |
| 201 | input [`H_INFO] mac_host_info17; |
| 202 | input [`H_INFO] mac_host_info18; |
| 203 | input [`H_INFO] mac_host_info19; |
| 204 | // end of ALT_ADDR_AND_HASH_FUNC specific signals |
| 205 | // output signals |
| 206 | // rxfifo |
| 207 | output [65:0] rxfifo_dout; // {mac_ctrl_word,tag,64bit data} |
| 208 | output [4:0] rxfifo_g_wr_ptr_rxclk; // ***** signal crossing different clock domain. ***** |
| 209 | output rxfifo_full_rxclk_reg; |
| 210 | output rxfifo_overrun_rxclk; |
| 211 | // srfifo |
| 212 | output [`TBITS] srfifo_dout; |
| 213 | output [4:0] srfifo_g_wr_ptr_rxclk; // ***** signal crossing different clock domain. ***** |
| 214 | // |
| 215 | output rx_good_pkt; |
| 216 | output rx_fc_pkt_ok; // ***** signal crossing different clock domain. ***** |
| 217 | output [15:0] pause_time; // ***** signal crossing different clock domain. ***** |
| 218 | output toggle_rx_bcount; // ***** signal crossing different clock domain. ***** |
| 219 | output inc_bcast_count; // ***** signal crossing different clock domain. ***** |
| 220 | output inc_mcast_count; // ***** signal crossing different clock domain. ***** |
| 221 | output inc_code_viol_count;// ***** signal crossing different clock domain. ***** |
| 222 | output inc_crc_err_count;// ***** signal crossing different clock domain. ***** |
| 223 | output inc_min_pkt_err_count;// ***** signal crossing different clock domain. ***** |
| 224 | output inc_max_pkt_err_count;// ***** signal crossing different clock domain. ***** |
| 225 | output rx_data_valid_gmux_reg; |
| 226 | output [63:0] rx_pa_data; |
| 227 | // |
| 228 | output link_fault; // to both xmac_sync then to xmac_slv |
| 229 | output inc_link_fault_count; // to xmac_sync.v |
| 230 | output remote_fault_oc_reg; // to xmac_slv. sw does RAC |
| 231 | output local_fault_oc_reg; // to xmac_slv. sw does RAC |
| 232 | output [1:0] lfs_state; // dynamic signal |
| 233 | // state machine outputs |
| 234 | output xrlm_state; |
| 235 | output sop_state; |
| 236 | // signal observation |
| 237 | output S_detected_reg; |
| 238 | output T_E_detected_at_modified_pkt_reg; |
| 239 | output END_PKT_ERR_detected_a_at_modified_pkt_reg; |
| 240 | output END_PKT_ERR_detected_b_at_modified_pkt_reg; |
| 241 | output S_D_reg; |
| 242 | output S_I_reg; |
| 243 | output D_S_reg; |
| 244 | output I_S_reg; |
| 245 | output abort_bit_reg; |
| 246 | output rx_err_reg; |
| 247 | output crc_error_reg; |
| 248 | output kill_data_ready_reg; |
| 249 | output kill_crc_reg; |
| 250 | output [1:0] rx_sel_reg; |
| 251 | |
| 252 | /*AUTOWIRE*/ |
| 253 | // Beginning of automatic wires (for undeclared instantiated-module outputs) |
| 254 | wire abort_bit; // From rx_xdecap of rx_xdecap.v |
| 255 | wire bad_pkt_bit; // From rx_xdecap of rx_xdecap.v |
| 256 | wire hash_hit_match; // From address_decoder of address_decoder.v |
| 257 | wire local_fault_oc; // From lfs of lfs.v |
| 258 | wire max_pkt_size_limit; // From rx_xdecap of rx_xdecap.v |
| 259 | wire remote_fault_oc; // From lfs of lfs.v |
| 260 | wire rst_data_ready; // From sop_sm of sop_sm.v |
| 261 | wire rx_fc_pkt; // From address_decoder of address_decoder.v |
| 262 | wire rx_ok; // From xrlm_sm of xrlm_sm.v |
| 263 | wire set_data_ready; // From sop_sm of sop_sm.v |
| 264 | wire valid_data; // From xrlm_sm of xrlm_sm.v |
| 265 | // End of automatics |
| 266 | |
| 267 | /* --- wire definition --- */ |
| 268 | wire rx_data_valid_gmux; |
| 269 | wire rx_data_valid_gmux_p1; |
| 270 | wire rx_data_valid; |
| 271 | wire mod_rx_dv; |
| 272 | wire rx_dv; |
| 273 | wire [7:0] rx_dv_8bit; |
| 274 | wire [7:0] rx_dv_8bit_reg0; |
| 275 | wire [7:0] rx_dv_8bit_reg0_gmux; |
| 276 | wire [7:0] rx_dv_8bit_reg0_gmux_p1; |
| 277 | wire [7:0] rx_dv_8bit_reg1; |
| 278 | wire [63:0] rx_data_64bit; |
| 279 | wire [63:0] rx_data_64bit_reg0; |
| 280 | wire [63:0] rx_data_64bit_reg0_gmux; |
| 281 | wire [63:0] rx_data_64bit_reg0_gmux_p1; |
| 282 | wire [63:0] rx_data_64bit_reg1; |
| 283 | wire [63:0] rx_data_64bit_reg2; |
| 284 | wire [47:0] mac_unique_addr; |
| 285 | wire [9:0] rx_min_pkt_size; |
| 286 | wire [13:0] max_pkt_size; |
| 287 | wire xrlm_state; |
| 288 | wire sop_state; |
| 289 | wire [15:0] pause_time; |
| 290 | // |
| 291 | wire [65:0] rxfifo_din; |
| 292 | wire [65:0] rxfifo_dout; |
| 293 | wire [4:0] srfifo_g_wr_ptr_rxclk; |
| 294 | wire [`TBITS] rx_status; |
| 295 | reg [`TBITS] rx_stat; |
| 296 | wire [`TBITS] srfifo_din; |
| 297 | wire [`TBITS] srfifo_dout; |
| 298 | wire eop,rx_eop,mod_eop,eop_wen; |
| 299 | wire rxfifo_full_rxclk; |
| 300 | wire rxfifo_afull_rxclk; // rxfifo almost full |
| 301 | wire rx_err; // = rx_err_det | rx_err_hold; |
| 302 | wire rx_err_det; |
| 303 | wire rx_err_det_pls; |
| 304 | wire rx_err_gmux; // = gmii ? g2x_rx_err : xgmii_rx_err; |
| 305 | wire rx_err_gmux_p1; // = gmii ? g2x_rx_err : xgmii_rx_err; |
| 306 | wire xgmii_rx_err; // xgmii mode rx_err |
| 307 | wire [63:0] g2x_rxd_64bit; |
| 308 | wire [7:0] g2x_rx_dv_8bit; |
| 309 | wire g2x_rx_err; |
| 310 | wire T_showup_a; |
| 311 | wire T_showup_b; |
| 312 | wire code_viol_a; |
| 313 | wire code_viol_b; |
| 314 | wire [`MAC_CTRL]mac_ctrl_word; // mac_ctrl_word goes with mac_ctrl_word_wr_en |
| 315 | wire mac_ctrl_word_wr_en; // mac_ctrl_word goes with mac_ctrl_word_wr_en |
| 316 | wire mac_ctrl_word_wen; // one clock delay of mac_ctrl_word_wr_en. It goes with rx_stat |
| 317 | // data path |
| 318 | wire [7:0] xgmii_rxc_8b; |
| 319 | wire [63:0] xgmii_rxd_64b; |
| 320 | wire [7:0] xpcs_rxc; |
| 321 | wire [7:0] xpcs_rxc_reg; |
| 322 | wire [63:0] xpcs_rxd; |
| 323 | wire [63:0] xpcs_rxd_reg; |
| 324 | wire [7:0] txc_image; |
| 325 | wire [7:0] txc_image_rx_clk; |
| 326 | wire [63:0] txd_image; |
| 327 | wire [63:0] txd_image_rx_clk; |
| 328 | // positive control |
| 329 | wire [7:0] xrc; |
| 330 | wire [3:0] xrc_a_p1; |
| 331 | wire [3:0] xrc_b_p1; |
| 332 | wire [3:0] xrc_a; |
| 333 | wire [3:0] xrc_b; |
| 334 | // positive data |
| 335 | wire [63:0] xrd; |
| 336 | wire [31:0] xrd_a_p1; |
| 337 | wire [31:0] xrd_b_p1; |
| 338 | wire [31:0] xrd_a; |
| 339 | wire [31:0] xrd_b; |
| 340 | // |
| 341 | wire [1:0] set_sel; |
| 342 | wire [1:0] rst_sel; |
| 343 | wire [1:0] rx_sel; |
| 344 | // |
| 345 | wire [3:0] rxc_a,rxc_b; |
| 346 | wire [31:0] rxd_a,rxd_b; |
| 347 | wire [31:0] rxd_aa,rxd_bb; // valid only at S_detected. It is used for latching rx_pa_data. |
| 348 | // |
| 349 | wire S_detected; |
| 350 | wire S_detected_at_modified_pkt; |
| 351 | wire T_detected_at_modified_pkt; |
| 352 | wire MID_PKT_ERR_detected_at_modified_pkt; |
| 353 | wire T_E_detected_at_modified_pkt; |
| 354 | wire S_D; |
| 355 | wire S_I; |
| 356 | wire D_S; |
| 357 | wire I_S; |
| 358 | wire kill_data_ready; |
| 359 | wire data_ok; |
| 360 | wire min_pkt_size_limit; |
| 361 | wire [63:0] rx_pa_data; |
| 362 | wire srfifo_wr_en; |
| 363 | wire kill_crc; |
| 364 | wire data_ready; |
| 365 | wire rx_data_valid_gmux_lead; |
| 366 | wire rxfifo_wen; |
| 367 | wire rx_err_hold; |
| 368 | wire crc_error; |
| 369 | // vlint flag_net_has_no_load off |
| 370 | // vlint flag_dangling_net_within_module off |
| 371 | wire [31:0] rx_crc_result; |
| 372 | wire [13:0] rx_byte_count; // for observation. |
| 373 | wire [13:0] mod_rx_byte_count; // for observation. |
| 374 | wire da_match; |
| 375 | wire da_match_err; |
| 376 | wire mac_own_da_match; |
| 377 | wire [4:0] rxfifo_wr_ptr_rxclk; |
| 378 | wire [15:0] hash_value; |
| 379 | wire [6:0] alt_addr_filter_value; |
| 380 | wire [31:0] new_crc5_result; |
| 381 | wire I_detected; |
| 382 | wire E_detected; |
| 383 | wire T_detected; |
| 384 | wire rx_data_valid_trail; |
| 385 | wire err_cond; |
| 386 | wire set_err_time; |
| 387 | wire rxfifo_empty_rxclk; |
| 388 | // vlint flag_dangling_net_within_module on |
| 389 | // vlint flag_net_has_no_load on |
| 390 | |
| 391 | RegDff #(1) rxfifo_full_rxclk_reg_RegDff (.din(rxfifo_full_rxclk),.clk(rx_clk),.qout(rxfifo_full_rxclk_reg)); |
| 392 | RegDff #(1) remote_fault_oc_reg_RegDff (.din(remote_fault_oc), .clk(rx_clk),.qout(remote_fault_oc_reg)); |
| 393 | RegDff #(1) local_fault_oc_reg_RegDff (.din(local_fault_oc), .clk(rx_clk),.qout(local_fault_oc_reg)); |
| 394 | |
| 395 | |
| 396 | /* ------------------ data path ------------------------------- */ |
| 397 | // 1st stage interface mux: mux in loopback and xgmii data path. |
| 398 | // |
| 399 | // Reason to place mux before register: |
| 400 | // For xgmii interface mode:The entire xgmii_intf can be placed |
| 401 | // right next to IO pad. |
| 402 | // From xgmii_intf register out to |
| 403 | // this 1st stage mux can have whole |
| 404 | // 6.4ns for layout trace. |
| 405 | // It can also provid some hold time to |
| 406 | // compensate rx_clk insertion delay. |
| 407 | // Good for both rtl and gate sim. |
| 408 | // |
| 409 | // For xpcs interface mode: The xpcs_rxc and xpcs_rxd are |
| 410 | // registered output. The mux provides |
| 411 | // some hold time to compensate rx_clk |
| 412 | // insertion delay. |
| 413 | // Good for both rtl and gate sim. |
| 414 | |
| 415 | // 1st stage interface register: register in |
| 416 | RegDff #(8) xpcs_rxc_reg_RegDff (.din(xpcs_rxc),.clk(rx_clk),.qout(xpcs_rxc_reg)); |
| 417 | RegDff #(64) xpcs_rxd_reg_RegDff (.din(xpcs_rxd),.clk(rx_clk),.qout(xpcs_rxd_reg)); |
| 418 | RegDff #(8) txc_image_rx_clk_RegDff(.din(txc_image),.clk(rx_clk),.qout(txc_image_rx_clk)); |
| 419 | RegDff #(64) txd_image_rx_clk_RegDff(.din(txd_image),.clk(rx_clk),.qout(txd_image_rx_clk)); |
| 420 | |
| 421 | xMUX_3to1 #(8) xrc_MUX_3to1( |
| 422 | .din0(xpcs_rxc_reg), |
| 423 | .din1(xgmii_rxc_8b), |
| 424 | .din2(txc_image_rx_clk), |
| 425 | .sel({loopback,xpcs_bypass}), |
| 426 | .dout(xrc)); |
| 427 | |
| 428 | xMUX_3to1 #(64) xrd_MUX_3to1( |
| 429 | .din0(xpcs_rxd_reg), |
| 430 | .din1(xgmii_rxd_64b), |
| 431 | .din2(txd_image_rx_clk), |
| 432 | .sel({loopback,xpcs_bypass}), |
| 433 | .dout(xrd)); |
| 434 | |
| 435 | assign xrc_a_p1 = xrc[3:0]; |
| 436 | assign xrc_b_p1 = xrc[7:4]; |
| 437 | assign xrd_a_p1 = xrd[31:0]; |
| 438 | assign xrd_b_p1 = xrd[63:32]; |
| 439 | |
| 440 | // 2nd stage interface register: |
| 441 | RegDff #(4) xrc_a_RegDff(.din(xrc_a_p1),.clk(rx_clk),.qout(xrc_a)); |
| 442 | RegDff #(4) xrc_b_RegDff(.din(xrc_b_p1),.clk(rx_clk),.qout(xrc_b)); |
| 443 | RegDff #(32) xrd_a_RegDff(.din(xrd_a_p1),.clk(rx_clk),.qout(xrd_a)); |
| 444 | RegDff #(32) xrd_b_RegDff(.din(xrd_b_p1),.clk(rx_clk),.qout(xrd_b)); |
| 445 | |
| 446 | // 2nd stage interface mux: |
| 447 | // for control rxc |
| 448 | xMUX_2to1 #(4) rxc_a_MUX_2to1(.din0(xrc_a), |
| 449 | .din1(xrc_b), |
| 450 | .sel(rx_sel[1]), |
| 451 | .dout(rxc_a)); |
| 452 | |
| 453 | xMUX_4to1 #(4) rxc_b_MUX_4to1(.din0(xrc_b), |
| 454 | .din1(xrc_b_p1), |
| 455 | .din2(xrc_a), |
| 456 | .din3(xrc_a_p1), |
| 457 | .sel(rx_sel[1:0]), |
| 458 | .dout(rxc_b)); |
| 459 | // for data rxd |
| 460 | xMUX_2to1 #(32) rxd_a_MUX_2to1(.din0(xrd_a), |
| 461 | .din1(xrd_b), |
| 462 | .sel(rx_sel[1]), |
| 463 | .dout(rxd_a)); |
| 464 | |
| 465 | xMUX_4to1 #(32) rxd_b_MUX_4to1(.din0(xrd_b), |
| 466 | .din1(xrd_b_p1), |
| 467 | .din2(xrd_a), |
| 468 | .din3(xrd_a_p1), |
| 469 | .sel(rx_sel[1:0]), |
| 470 | .dout(rxd_b)); |
| 471 | // for rx_pa_data |
| 472 | xMUX_2to1 #(32) rxd_aa_MUX_2to1(.din0(xrd_a), |
| 473 | .din1(xrd_b), |
| 474 | .sel(set_sel[1]), |
| 475 | .dout(rxd_aa)); |
| 476 | |
| 477 | xMUX_4to1 #(32) rxd_bb_MUX_4to1(.din0(xrd_b), |
| 478 | .din1(xrd_b_p1), |
| 479 | .din2(xrd_a), |
| 480 | .din3(xrd_a_p1), |
| 481 | .sel(set_sel[1:0]), |
| 482 | .dout(rxd_bb)); |
| 483 | |
| 484 | // If set and reset happened at the same time, |
| 485 | // set gets higher priority. |
| 486 | // The reset part is taken care of by kill_data_ready to |
| 487 | // lower data_ok. |
| 488 | SR_FF data_ready_SR_FF(.set(set_data_ready), |
| 489 | .rst(rst_data_ready), |
| 490 | .clk(rx_clk), |
| 491 | .reset(rx_reset), |
| 492 | .qout(data_ready)); |
| 493 | // rx_sel[1] is equivalent to rx_swap. |
| 494 | RS_FF sel1_RS_FF (.set(set_sel[1]), |
| 495 | .rst(rst_sel[1]), |
| 496 | .clk(rx_clk), |
| 497 | .reset(rx_reset), |
| 498 | .qout(rx_sel[1])); |
| 499 | |
| 500 | RS_FF sel0_RS_FF (.set(set_sel[0]), |
| 501 | .rst(rst_sel[0]), |
| 502 | .clk(rx_clk), |
| 503 | .reset(rx_reset), |
| 504 | .qout(rx_sel[0])); |
| 505 | |
| 506 | // T_E_detected_at_modified_pkt is used to chop the pkt so that forcing bad CRC to happen and abort bit set. |
| 507 | assign kill_data_ready = (T_detected_at_modified_pkt & S_detected_at_modified_pkt) | T_E_detected_at_modified_pkt; |
| 508 | |
| 509 | assign data_ok = data_ready & ~(rxfifo_full_rxclk | rxfifo_afull_rxclk) & ~kill_data_ready; |
| 510 | |
| 511 | assign rx_dv_8bit[`BYTE]={(data_ok & ~rxc_b[3]), |
| 512 | (data_ok & ~rxc_b[2]), |
| 513 | (data_ok & ~rxc_b[1]), |
| 514 | (data_ok & ~rxc_b[0]), |
| 515 | (data_ok & ~rxc_a[3]), |
| 516 | (data_ok & ~rxc_a[2]), |
| 517 | (data_ok & ~rxc_a[1]), |
| 518 | (data_ok & ~rxc_a[0]) |
| 519 | }; |
| 520 | |
| 521 | assign rx_data_64bit = {rxd_b[31:0],rxd_a[31:0]}; |
| 522 | |
| 523 | /* ------------------ 0th statge registers -------------------- */ |
| 524 | |
| 525 | // RegDff #(8) rx_dv_8bit_reg0_RegDff (.din(rx_dv_8bit), .clk(rx_clk),.qout(rx_dv_8bit_reg0)); |
| 526 | // RegDff #(64) rx_data_64bit_reg0_RegDff (.din(rx_data_64bit),.clk(rx_clk),.qout(rx_data_64bit_reg0)); |
| 527 | // RegDff #(1) rx_data_valid_RegDff (.din(|rx_dv_8bit), .clk(rx_clk),.qout(rx_data_valid)); |
| 528 | |
| 529 | assign rx_dv_8bit_reg0 = rx_dv_8bit; |
| 530 | assign rx_data_64bit_reg0 = rx_data_64bit; |
| 531 | assign rx_data_valid = |rx_dv_8bit; |
| 532 | |
| 533 | /* ------------------ 0th stage muxes ------------------------- */ |
| 534 | /******************************************************* |
| 535 | * This is where gmii and xgmii data path come together. |
| 536 | * "gmux" is used as surfix to designated that this |
| 537 | * is the merger of gmii and xgmii data path mux. |
| 538 | *******************************************************/ |
| 539 | wire reset_g2x_regs = rx_reset | rxfifo_full_rxclk; |
| 540 | |
| 541 | RegRst #(64) g2x_rxd_64bit_RegRst (.clk(rx_clk), |
| 542 | .reset(reset_g2x_regs), |
| 543 | .din(hold_rxd[63:0]), |
| 544 | .qout(g2x_rxd_64bit[63:0])); |
| 545 | |
| 546 | RegRst #(8) g2x_rx_dv_8bit_RegRst (.clk(rx_clk), |
| 547 | .reset(reset_g2x_regs), |
| 548 | .din(hold_rx_dv[7:0]), |
| 549 | .qout(g2x_rx_dv_8bit[7:0])); |
| 550 | |
| 551 | RegRst #(1) g2x_rx_err_8bit_RegRst(.clk(rx_clk), |
| 552 | .reset(reset_g2x_regs), |
| 553 | .din(hold_rx_err), |
| 554 | .qout(g2x_rx_err)); |
| 555 | |
| 556 | xMUX_2to1 #(64) rx_data_64bit_reg0_gmux_xMUX_2to1(.din0(rx_data_64bit_reg0),.din1(g2x_rxd_64bit), .sel(mii_or_gmii_mode),.dout(rx_data_64bit_reg0_gmux_p1)); |
| 557 | xMUX_2to1 #(8) rx_dv_8bit_reg0_gmux_xMUX_2to1 (.din0(rx_dv_8bit_reg0), .din1(g2x_rx_dv_8bit), .sel(mii_or_gmii_mode),.dout(rx_dv_8bit_reg0_gmux_p1)); |
| 558 | xMUX_2to1 #(1) rx_data_valid_gmux_xMUX_2to1 (.din0(rx_data_valid), .din1(|g2x_rx_dv_8bit),.sel(mii_or_gmii_mode),.dout(rx_data_valid_gmux_p1)); |
| 559 | |
| 560 | /* ----- add this stage to improve crc timing ----------------- */ |
| 561 | RegDff #(64) rx_data_64bit_reg0_gmux_RegDff (.din(rx_data_64bit_reg0_gmux_p1), .clk(rx_clk),.qout(rx_data_64bit_reg0_gmux)); |
| 562 | RegDff #(8) rx_dv_8bit_reg0_gmux_p1_RegDff (.din(rx_dv_8bit_reg0_gmux_p1), .clk(rx_clk),.qout(rx_dv_8bit_reg0_gmux)); |
| 563 | RegDff #(1) rx_data_valid_gmux_RegDff (.din(rx_data_valid_gmux_p1), .clk(rx_clk),.qout(rx_data_valid_gmux)); |
| 564 | |
| 565 | PlsGen2 rx_data_valid_PlsGen2 (.sig_in(rx_data_valid_gmux),.clk(rx_clk), |
| 566 | .lead (rx_data_valid_gmux_lead), |
| 567 | .trail(rx_data_valid_trail));// not used |
| 568 | |
| 569 | FD1 rx_data_valid_gmux_reg_FD1 (.D(rx_data_valid_gmux),.CP(rx_clk),.Q(rx_data_valid_gmux_reg)); |
| 570 | |
| 571 | /* ----------------- 1st statge registers --------------------- */ |
| 572 | // xrlm_sm convert rx_data_valid_gmux to valid_data in real time. |
| 573 | FD1 rx_dv_FD1 (.D(valid_data),.CP(rx_clk),.Q(rx_dv)); |
| 574 | RegDff #(64) rx_data_64bit_reg1_RegDff (.din(rx_data_64bit_reg0_gmux),.clk(rx_clk),.qout(rx_data_64bit_reg1)); |
| 575 | RegDff #(8) rx_dv_8bit_reg1_RegDff (.din(rx_dv_8bit_reg0_gmux), .clk(rx_clk),.qout(rx_dv_8bit_reg1)); |
| 576 | |
| 577 | /* ----------------- 2nd statge registers --------------------- */ |
| 578 | RegDff #(64) rx_data_64bit_reg2_RegDff (.din(rx_data_64bit_reg1),.clk(rx_clk),.qout(rx_data_64bit_reg2)); |
| 579 | |
| 580 | always @ (posedge rx_clk) // rx_status has the same timing as eop. // loj |
| 581 | rx_stat <= rx_status; |
| 582 | |
| 583 | // rxfifo related logic |
| 584 | /* ------------------ rxfifo_din mux logic -------------------- */ |
| 585 | // mac_ctrl_word_wen,eop_wen should behave the same way. |
| 586 | assign mod_rx_dv = rx_dv & (~kill_crc); |
| 587 | FD1 rxfifo_wen_FD1(.D(mod_rx_dv),.CP(rx_clk),.Q(rxfifo_wen)); |
| 588 | assign rxfifo_din = {mac_ctrl_word_wen,eop_wen,rx_data_64bit_reg2}; |
| 589 | // ^ ^ |
| 590 | // | | |
| 591 | // rxmac_ipp_ctrl rxmac_ipp_tag |
| 592 | // srfifo related logic |
| 593 | FD1 mac_ctrl_word_wen_FD1(.D(mac_ctrl_word_wr_en),.CP(rx_clk),.Q(mac_ctrl_word_wen)); |
| 594 | |
| 595 | // eop is a lookahead signal. |
| 596 | // eop is used in reg1 time. |
| 597 | // rx_eop is used in reg2 time. |
| 598 | assign mod_eop = eop & (~kill_crc); |
| 599 | FD1 rx_eop_FD1 (.D(mod_eop),.CP(rx_clk),.Q(rx_eop)); |
| 600 | assign srfifo_wr_en = eop_wen | mac_ctrl_word_wen; |
| 601 | // eop goes with rx_status. |
| 602 | // rx_eop goes with rx_stat. |
| 603 | // kill_crc only happens in eop time. |
| 604 | // implicit eop time; eop delay by one clk; |
| 605 | // | | |
| 606 | // v v |
| 607 | assign eop_wen = kill_crc ? 1'b1 : rx_eop; |
| 608 | // ^ ^ |
| 609 | // | | |
| 610 | // v v |
| 611 | assign srfifo_din = kill_crc ? rx_status: rx_stat; |
| 612 | |
| 613 | /* ---------- start of strip_crc modification logic ----------- */ |
| 614 | // The ~min_pkt_size_limit is to take care of the runt pkt that is less or equal 8 bytes. |
| 615 | |
| 616 | //The following two equations performs the same results. |
| 617 | // |
| 618 | //always @ (eop or strip_crc or min_pkt_size_limit or rx_dv_8bit_reg1) |
| 619 | // if (eop & strip_crc & (~min_pkt_size_limit)) |
| 620 | // case(rx_dv_8bit_reg1) // synopsys parallel_case full_case |
| 621 | // /* -- below this line kill_crc == 1 -> kill crc at current and previous lanes -- */ |
| 622 | // 8'b00000001: kill_crc = 1; |
| 623 | // 8'b00000011: kill_crc = 1; |
| 624 | // 8'b00000111: kill_crc = 1; |
| 625 | // 8'b00001111: kill_crc = 1; |
| 626 | // /* -- below this line kill_crc == 0 -> kill crc at current lanes -- */ |
| 627 | // 8'b00011111: kill_crc = 0; |
| 628 | // 8'b00111111: kill_crc = 0; |
| 629 | // 8'b01111111: kill_crc = 0; |
| 630 | // 8'b11111111: kill_crc = 0; |
| 631 | // default : kill_crc = 0; |
| 632 | // endcase // case(rx_dv_8bit_reg1) |
| 633 | // else kill_crc = 0; |
| 634 | |
| 635 | assign kill_crc = ((rx_dv_8bit_reg1 == 8'b00000001) | |
| 636 | (rx_dv_8bit_reg1 == 8'b00000011) | |
| 637 | (rx_dv_8bit_reg1 == 8'b00000111) | |
| 638 | (rx_dv_8bit_reg1 == 8'b00001111)) & |
| 639 | (eop & strip_crc & (~min_pkt_size_limit)); |
| 640 | |
| 641 | |
| 642 | /************************ control logic ************************/ |
| 643 | |
| 644 | parameter THREE_0 = 3'b000 , |
| 645 | FOUR_0 = 4'b0000, |
| 646 | // THREE_1 = 3'b111 , // not used |
| 647 | FOUR_1 = 4'b1111; |
| 648 | |
| 649 | /* ---------- detect S (sop) logic ---------------------------- */ |
| 650 | // S = 8'hFB, T = 8'hFD, E = 8'hFE, I = 8'h07 |
| 651 | // in 802.3z pp-36A.2 shows PA => FB 55 55 55 55 55 55 D5 |
| 652 | // |
| 653 | // detect SOP logic |
| 654 | // D: pre amble |
| 655 | // I: can be T or I or mixture of T&I&D or I&D; |
| 656 | // S: sop |
| 657 | // |
| 658 | // LSB MSB |
| 659 | // \ / |
| 660 | // a b <--------- Big Endian format |
| 661 | // | | |
| 662 | // v v |
| 663 | assign S_D = ((xrc_a[0] & (xrd_a[`BYTE0] == `S)) & (xrc_a[3:1] == THREE_0)) & (xrc_b == FOUR_0) ; //normal |
| 664 | |
| 665 | //abnormal |
| 666 | assign S_I = ((xrc_a[0] & (xrd_a[`BYTE0] == `S)) & (xrc_a[3:1] == THREE_0)) & (xrc_b == FOUR_1) & (xrc_b_p1 == FOUR_0); |
| 667 | |
| 668 | //abnormal |
| 669 | assign D_S = (xrc_a == FOUR_0) & ((xrc_b[0] & (xrd_b[`BYTE0] == `S)) & (xrc_b[3:1] == THREE_0)) ; |
| 670 | |
| 671 | //normal |
| 672 | assign I_S = (xrc_a == FOUR_1) & ((xrc_b[0] & (xrd_b[`BYTE0] == `S)) & (xrc_b[3:1] == THREE_0)) & (xrc_a_p1 == FOUR_0); |
| 673 | |
| 674 | |
| 675 | assign S_detected = S_D | S_I | D_S | I_S; |
| 676 | |
| 677 | assign S_detected_at_modified_pkt = (rxc_a[0] & (rxd_a[`BYTE0] == `S)) | (rxc_b[0] & (rxd_b[`BYTE0] == `S)); // lane0 |
| 678 | |
| 679 | // ------------------------------------------------ |
| 680 | // truth talbe |
| 681 | // -------------------------- -------------------- |
| 682 | // xrc_a xrc_b encode comments |
| 683 | // ------- ------- ---------- -------------------- |
| 684 | // S D 2'b00 no action |
| 685 | // |
| 686 | // S I 2'b01 pull b (abnormal) |
| 687 | // |
| 688 | // D S 2'b10 swap a&b (abnormal) |
| 689 | // |
| 690 | // I S 2'b11 swap a&b + pull a |
| 691 | // ------------------------------------------------ |
| 692 | // |
| 693 | // comments: |
| 694 | // 1. whenever the I is detected, |
| 695 | // the rxc_a_p1/rxc_b_p1 is used. |
| 696 | // 2. sel[1]: is the swap enable bit |
| 697 | // sel[0]: is the delay bit. |
| 698 | |
| 699 | /* ---------- detect T logic ---------------------------------- */ |
| 700 | assign T_detected = // not used |
| 701 | xrc_a[0] & (xrd_a[`BYTE0] == `T) | // lane0 |
| 702 | xrc_a[1] & (xrd_a[`BYTE1] == `T) | // lane1 |
| 703 | xrc_a[2] & (xrd_a[`BYTE2] == `T) | // lane2 |
| 704 | xrc_a[3] & (xrd_a[`BYTE3] == `T) | // lane3 |
| 705 | xrc_b[0] & (xrd_b[`BYTE0] == `T) | // lane4 |
| 706 | xrc_b[1] & (xrd_b[`BYTE1] == `T) | // lane5 |
| 707 | xrc_b[2] & (xrd_b[`BYTE2] == `T) | // lane6 |
| 708 | xrc_b[3] & (xrd_b[`BYTE3] == `T) ; // lane7 |
| 709 | |
| 710 | wire T_detected_a_at_modified_pkt = |
| 711 | rxc_a[0] & (rxd_a[`BYTE0] == `T) | // lane0 |
| 712 | rxc_a[1] & (rxd_a[`BYTE1] == `T) | // lane1 |
| 713 | rxc_a[2] & (rxd_a[`BYTE2] == `T) | // lane2 |
| 714 | rxc_a[3] & (rxd_a[`BYTE3] == `T) ; // lane3 |
| 715 | |
| 716 | |
| 717 | |
| 718 | wire T_detected_b_at_modified_pkt = |
| 719 | rxc_b[0] & (rxd_b[`BYTE0] == `T) | // lane4 |
| 720 | rxc_b[1] & (rxd_b[`BYTE1] == `T) | // lane5 |
| 721 | rxc_b[2] & (rxd_b[`BYTE2] == `T) | // lane6 |
| 722 | rxc_b[3] & (rxd_b[`BYTE3] == `T) ; // lane7 |
| 723 | |
| 724 | assign T_detected_at_modified_pkt = |
| 725 | T_detected_a_at_modified_pkt | T_detected_b_at_modified_pkt; |
| 726 | |
| 727 | /* ---------- detect I CHAR ----------------------------------- */ |
| 728 | assign I_detected = // not used |
| 729 | xrc_a[0] & (xrd_a[`BYTE0] == `I) | // lane0 |
| 730 | xrc_a[1] & (xrd_a[`BYTE1] == `I) | // lane1 |
| 731 | xrc_a[2] & (xrd_a[`BYTE2] == `I) | // lane2 |
| 732 | xrc_a[3] & (xrd_a[`BYTE3] == `I) | // lane3 |
| 733 | xrc_b[0] & (xrd_b[`BYTE0] == `I) | // lane4 |
| 734 | xrc_b[1] & (xrd_b[`BYTE1] == `I) | // lane5 |
| 735 | xrc_b[2] & (xrd_b[`BYTE2] == `I) | // lane6 |
| 736 | xrc_b[3] & (xrd_b[`BYTE3] == `I) ; // lane7 |
| 737 | |
| 738 | /* ---------- detect E CHAR ----------------------------------- */ |
| 739 | assign E_detected = // not used |
| 740 | xrc_a[0] & (xrd_a[`BYTE0] == `E) | // lane0 |
| 741 | xrc_a[1] & (xrd_a[`BYTE1] == `E) | // lane1 |
| 742 | xrc_a[2] & (xrd_a[`BYTE2] == `E) | // lane2 |
| 743 | xrc_a[3] & (xrd_a[`BYTE3] == `E) | // lane3 |
| 744 | xrc_b[0] & (xrd_b[`BYTE0] == `E) | // lane4 |
| 745 | xrc_b[1] & (xrd_b[`BYTE1] == `E) | // lane5 |
| 746 | xrc_b[2] & (xrd_b[`BYTE2] == `E) | // lane6 |
| 747 | xrc_b[3] & (xrd_b[`BYTE3] == `E) ; // lane7 |
| 748 | |
| 749 | /* ---------- detect ERR in the middle of pkt ----------------- */ |
| 750 | assign MID_PKT_ERR_detected_at_modified_pkt = (|rxc_a) | (|rxc_b); |
| 751 | |
| 752 | /* ---------- detect ERR at the end of pkt -------------------- */ |
| 753 | wire END_PKT_ERR_detected_a_at_modified_pkt = |
| 754 | rxc_a[0] & (rxd_a[`BYTE0] == `E) | // lane0 |
| 755 | rxc_a[1] & (rxd_a[`BYTE1] == `E) | // lane1 |
| 756 | rxc_a[2] & (rxd_a[`BYTE2] == `E) | // lane2 |
| 757 | rxc_a[3] & (rxd_a[`BYTE3] == `E) ; // lane3 |
| 758 | |
| 759 | wire END_PKT_ERR_detected_b_at_modified_pkt = |
| 760 | rxc_b[0] & (rxd_b[`BYTE0] == `E) | // lane4 |
| 761 | rxc_b[1] & (rxd_b[`BYTE1] == `E) | // lane5 |
| 762 | rxc_b[2] & (rxd_b[`BYTE2] == `E) | // lane6 |
| 763 | rxc_b[3] & (rxd_b[`BYTE3] == `E) ; // lane7 |
| 764 | |
| 765 | assign T_E_detected_at_modified_pkt = (T_detected_a_at_modified_pkt & END_PKT_ERR_detected_a_at_modified_pkt) | |
| 766 | (T_detected_b_at_modified_pkt & END_PKT_ERR_detected_b_at_modified_pkt) ; |
| 767 | |
| 768 | /* ---------- rx pre-amble data (8 bytes) --------------------- */ |
| 769 | xREG #(64) rx_pa_data_xREG(.din({rxd_bb,rxd_aa}), |
| 770 | .clk(rx_clk), |
| 771 | .en(S_detected), |
| 772 | .reset(rx_reset), |
| 773 | .qout(rx_pa_data)); |
| 774 | |
| 775 | /* ---------- detect E logic @ reg0 time ---------------------- */ |
| 776 | // please refer to July 2000, La Jolla meeting. |
| 777 | // XAUI/XGXS Proposal : slide 20 |
| 778 | assign T_showup_a = |
| 779 | (~rx_dv_8bit_reg0[0] & (rx_data_64bit_reg0[`BYTE0] == `T) | |
| 780 | ~rx_dv_8bit_reg0[1] & (rx_data_64bit_reg0[`BYTE1] == `T) | |
| 781 | ~rx_dv_8bit_reg0[2] & (rx_data_64bit_reg0[`BYTE2] == `T) | |
| 782 | ~rx_dv_8bit_reg0[3] & (rx_data_64bit_reg0[`BYTE3] == `T) ); |
| 783 | |
| 784 | assign T_showup_b = |
| 785 | (~rx_dv_8bit_reg0[4] & (rx_data_64bit_reg0[`BYTE4] == `T) | |
| 786 | ~rx_dv_8bit_reg0[5] & (rx_data_64bit_reg0[`BYTE5] == `T) | |
| 787 | ~rx_dv_8bit_reg0[6] & (rx_data_64bit_reg0[`BYTE6] == `T) | |
| 788 | ~rx_dv_8bit_reg0[7] & (rx_data_64bit_reg0[`BYTE7] == `T) ); |
| 789 | |
| 790 | assign code_viol_a = |
| 791 | (~rx_dv_8bit_reg0[0] & (rx_data_64bit_reg0[`BYTE0] == `E) | |
| 792 | ~rx_dv_8bit_reg0[1] & (rx_data_64bit_reg0[`BYTE1] == `E) | |
| 793 | ~rx_dv_8bit_reg0[2] & (rx_data_64bit_reg0[`BYTE2] == `E) | |
| 794 | ~rx_dv_8bit_reg0[3] & (rx_data_64bit_reg0[`BYTE3] == `E)); |
| 795 | |
| 796 | assign code_viol_b = |
| 797 | (~rx_dv_8bit_reg0[4] & (rx_data_64bit_reg0[`BYTE4] == `E) | |
| 798 | ~rx_dv_8bit_reg0[5] & (rx_data_64bit_reg0[`BYTE5] == `E) | |
| 799 | ~rx_dv_8bit_reg0[6] & (rx_data_64bit_reg0[`BYTE6] == `E) | |
| 800 | ~rx_dv_8bit_reg0[7] & (rx_data_64bit_reg0[`BYTE7] == `E)); |
| 801 | |
| 802 | assign xgmii_rx_err = ( |
| 803 | ( ~(T_showup_a | T_showup_b) & (code_viol_a | code_viol_b) ) | |
| 804 | (T_showup_a & code_viol_a) | |
| 805 | (T_showup_b & (code_viol_a | code_viol_b) ) |
| 806 | ); |
| 807 | |
| 808 | |
| 809 | assign rx_err_gmux_p1 = (mii_or_gmii_mode) ? g2x_rx_err : xgmii_rx_err; |
| 810 | RegDff #(1) rx_err_gmux_RegDff (.din(rx_err_gmux_p1),.clk(rx_clk),.qout(rx_err_gmux)); |
| 811 | |
| 812 | assign rx_err_det = ~code_viol_chk_dis & rx_data_valid_gmux & rx_err_gmux; |
| 813 | |
| 814 | PlsGen rx_err_det_pls_PlsGen(.reset(rx_reset),.clk(rx_clk),.iSigIn(rx_err_det),.oPlsOut(rx_err_det_pls)); |
| 815 | |
| 816 | RS_FF rx_err_hold_RS_FF(.set(rx_err_det_pls),.rst(eop),.clk(rx_clk), |
| 817 | .reset(rx_reset),.qout(rx_err_hold)); |
| 818 | |
| 819 | assign rx_err = rx_err_det | rx_err_hold; |
| 820 | |
| 821 | /* ------------------ xgmii interface instantiation ----------- */ |
| 822 | rx_xgmii_intf rx_xgmii_intf |
| 823 | (/*AUTOINST*/ |
| 824 | // Outputs |
| 825 | .xgmii_rxc_8b (xgmii_rxc_8b[7:0]), |
| 826 | .xgmii_rxd_64b (xgmii_rxd_64b[63:0]), |
| 827 | // Inputs |
| 828 | .rx_clk (rx_clk), |
| 829 | .xgmii_rxc (xgmii_rxc[3:0]), |
| 830 | .xgmii_rxd (xgmii_rxd[31:0])); |
| 831 | |
| 832 | /* ------------------ address_decoder instantiation ----------- */ |
| 833 | address_decoder address_decoder |
| 834 | (/*AUTOINST*/ |
| 835 | // Outputs |
| 836 | .alt_addr_filter_value (alt_addr_filter_value[6:0]), |
| 837 | .hash_hit_match (hash_hit_match), |
| 838 | .hash_value (hash_value[15:0]), |
| 839 | .mac_ctrl_word (mac_ctrl_word[`MAC_CTRL]), |
| 840 | .mac_ctrl_word_wr_en (mac_ctrl_word_wr_en), |
| 841 | .rx_fc_pkt (rx_fc_pkt), |
| 842 | .rx_fc_pkt_ok (rx_fc_pkt_ok), |
| 843 | .pause_time (pause_time[15:0]), |
| 844 | .da_match (da_match), |
| 845 | .da_match_err (da_match_err), |
| 846 | .mac_own_da_match (mac_own_da_match), |
| 847 | .inc_bcast_count (inc_bcast_count), |
| 848 | .inc_mcast_count (inc_mcast_count), |
| 849 | // Inputs |
| 850 | .rx_clk (rx_clk), |
| 851 | .rx_reset (rx_reset), |
| 852 | .eop (eop), |
| 853 | .bad_pkt_bit (bad_pkt_bit), |
| 854 | .promisc_all (promisc_all), |
| 855 | .promisc_group (promisc_group), |
| 856 | .reserve_multicast (reserve_multicast), |
| 857 | .rx_pause_en (rx_pause_en), |
| 858 | .rx_data_64bit_reg0_gmux (rx_data_64bit_reg0_gmux[63:0]), |
| 859 | .rx_data_valid_gmux_lead (rx_data_valid_gmux_lead), |
| 860 | .mac_unique_addr (mac_unique_addr[47:0]), |
| 861 | .new_crc5_result (new_crc5_result[15:0]), |
| 862 | .addr_filter_en (addr_filter_en), |
| 863 | .hash_filter_en (hash_filter_en), |
| 864 | .alt_addr_comp_en (alt_addr_comp_en[15:0]), |
| 865 | .mac_alt_addr0 (mac_alt_addr0[47:0]), |
| 866 | .mac_alt_addr1 (mac_alt_addr1[47:0]), |
| 867 | .mac_alt_addr2 (mac_alt_addr2[47:0]), |
| 868 | .mac_alt_addr3 (mac_alt_addr3[47:0]), |
| 869 | .mac_alt_addr4 (mac_alt_addr4[47:0]), |
| 870 | .mac_alt_addr5 (mac_alt_addr5[47:0]), |
| 871 | .mac_alt_addr6 (mac_alt_addr6[47:0]), |
| 872 | .mac_alt_addr7 (mac_alt_addr7[47:0]), |
| 873 | .mac_alt_addr8 (mac_alt_addr8[47:0]), |
| 874 | .mac_alt_addr9 (mac_alt_addr9[47:0]), |
| 875 | .mac_alt_addr10 (mac_alt_addr10[47:0]), |
| 876 | .mac_alt_addr11 (mac_alt_addr11[47:0]), |
| 877 | .mac_alt_addr12 (mac_alt_addr12[47:0]), |
| 878 | .mac_alt_addr13 (mac_alt_addr13[47:0]), |
| 879 | .mac_alt_addr14 (mac_alt_addr14[47:0]), |
| 880 | .mac_alt_addr15 (mac_alt_addr15[47:0]), |
| 881 | .addr_filter (addr_filter[47:0]), |
| 882 | .addr_filter_mask_msb (addr_filter_mask_msb[7:0]), |
| 883 | .addr_filter_mask_lsb (addr_filter_mask_lsb[15:0]), |
| 884 | .hash_table (hash_table[255:0]), |
| 885 | .mac_host_info0 (mac_host_info0[`H_INFO]), |
| 886 | .mac_host_info1 (mac_host_info1[`H_INFO]), |
| 887 | .mac_host_info2 (mac_host_info2[`H_INFO]), |
| 888 | .mac_host_info3 (mac_host_info3[`H_INFO]), |
| 889 | .mac_host_info4 (mac_host_info4[`H_INFO]), |
| 890 | .mac_host_info5 (mac_host_info5[`H_INFO]), |
| 891 | .mac_host_info6 (mac_host_info6[`H_INFO]), |
| 892 | .mac_host_info7 (mac_host_info7[`H_INFO]), |
| 893 | .mac_host_info8 (mac_host_info8[`H_INFO]), |
| 894 | .mac_host_info9 (mac_host_info9[`H_INFO]), |
| 895 | .mac_host_info10 (mac_host_info10[`H_INFO]), |
| 896 | .mac_host_info11 (mac_host_info11[`H_INFO]), |
| 897 | .mac_host_info12 (mac_host_info12[`H_INFO]), |
| 898 | .mac_host_info13 (mac_host_info13[`H_INFO]), |
| 899 | .mac_host_info14 (mac_host_info14[`H_INFO]), |
| 900 | .mac_host_info15 (mac_host_info15[`H_INFO]), |
| 901 | .mac_host_info16 (mac_host_info16[`H_INFO]), |
| 902 | .mac_host_info17 (mac_host_info17[`H_INFO]), |
| 903 | .mac_host_info18 (mac_host_info18[`H_INFO]), |
| 904 | .mac_host_info19 (mac_host_info19[`H_INFO]), |
| 905 | .rx_ok (rx_ok)); |
| 906 | |
| 907 | |
| 908 | /* ------------------- rx_xdecap instantiation ---------------- */ |
| 909 | rx_xdecap rx_xdecap |
| 910 | (/*AUTOINST*/ |
| 911 | // Outputs |
| 912 | .min_pkt_size_limit (min_pkt_size_limit), |
| 913 | .max_pkt_size_limit (max_pkt_size_limit), |
| 914 | .rx_good_pkt (rx_good_pkt), |
| 915 | .inc_code_viol_count (inc_code_viol_count), |
| 916 | .inc_crc_err_count (inc_crc_err_count), |
| 917 | .inc_min_pkt_err_count (inc_min_pkt_err_count), |
| 918 | .inc_max_pkt_err_count (inc_max_pkt_err_count), |
| 919 | .toggle_rx_bcount (toggle_rx_bcount), |
| 920 | .abort_bit (abort_bit), |
| 921 | .bad_pkt_bit (bad_pkt_bit), |
| 922 | .rx_byte_count (rx_byte_count[13:0]), |
| 923 | .mod_rx_byte_count (mod_rx_byte_count[13:0]), |
| 924 | .rx_status (rx_status[`TBITS]), |
| 925 | // Inputs |
| 926 | .rx_clk (rx_clk), |
| 927 | .rx_reset (rx_reset), |
| 928 | .warning_msg_en (warning_msg_en), |
| 929 | .strip_crc (strip_crc), |
| 930 | .err_chk_dis (err_chk_dis), |
| 931 | .pass_fc (pass_fc), |
| 932 | .crc_error (crc_error), |
| 933 | .rxfifo_full_rxclk (rxfifo_full_rxclk), |
| 934 | .rxfifo_afull_rxclk (rxfifo_afull_rxclk), |
| 935 | .rx_fc_pkt (rx_fc_pkt), |
| 936 | .no_rx_min_pkt_size_chk (no_rx_min_pkt_size_chk), |
| 937 | .rx_min_pkt_size (rx_min_pkt_size[9:0]), |
| 938 | .max_pkt_size (max_pkt_size[13:0]), |
| 939 | .valid_data (valid_data), |
| 940 | .rx_dv (rx_dv), |
| 941 | .rx_err (rx_err), |
| 942 | .rx_dv_8bit_reg0_gmux (rx_dv_8bit_reg0_gmux[7:0]), |
| 943 | .eop (eop), |
| 944 | .hash_hit_match (hash_hit_match), |
| 945 | .hash_value (hash_value[5:0]), |
| 946 | .mac_ctrl_word (mac_ctrl_word[`MAC_CTRL]), |
| 947 | .mac_ctrl_word_wr_en (mac_ctrl_word_wr_en)); |
| 948 | |
| 949 | /* ------------------- rxfifo_load instantiation -------------- */ |
| 950 | rxfifo_load rxfifo_load |
| 951 | (/*AUTOINST*/ |
| 952 | // Outputs |
| 953 | .rxfifo_dout (rxfifo_dout[65:0]), |
| 954 | .rxfifo_g_wr_ptr_rxclk (rxfifo_g_wr_ptr_rxclk[4:0]), |
| 955 | .rxfifo_full_rxclk (rxfifo_full_rxclk), |
| 956 | .rxfifo_afull_rxclk (rxfifo_afull_rxclk), |
| 957 | .rxfifo_wr_ptr_rxclk (rxfifo_wr_ptr_rxclk[4:0]), |
| 958 | .rxfifo_empty_rxclk (rxfifo_empty_rxclk), |
| 959 | .rxfifo_overrun_rxclk (rxfifo_overrun_rxclk), |
| 960 | // Inputs |
| 961 | .rx_clk (rx_clk), |
| 962 | .rx_reset (rx_reset), |
| 963 | .rxfifo_wen (rxfifo_wen), |
| 964 | .rxfifo_g_rd_ptr_sync (rxfifo_g_rd_ptr_sync[4:0]), |
| 965 | .rxfifo_rd_ptr_clk (rxfifo_rd_ptr_clk[3:0]), |
| 966 | .rxfifo_din (rxfifo_din[65:0]));// this should never happen. |
| 967 | |
| 968 | /* ------------------- srfifo_load instantiation -------------- */ |
| 969 | srfifo_load srfifo_load |
| 970 | (/*AUTOINST*/ |
| 971 | // Outputs |
| 972 | .srfifo_dout (srfifo_dout[`TBITS]), |
| 973 | .srfifo_g_wr_ptr_rxclk (srfifo_g_wr_ptr_rxclk[4:0]), |
| 974 | // Inputs |
| 975 | .rx_clk (rx_clk), |
| 976 | .rx_reset (rx_reset), |
| 977 | .srfifo_wr_en (srfifo_wr_en), |
| 978 | .srfifo_rd_ptr_clk (srfifo_rd_ptr_clk[4:0]), |
| 979 | .srfifo_din (srfifo_din[`TBITS])); |
| 980 | |
| 981 | /* ------------------- sop_sm instantiation ------------------- */ |
| 982 | sop_sm sop_sm |
| 983 | (/*AUTOINST*/ |
| 984 | // Outputs |
| 985 | .set_data_ready (set_data_ready), |
| 986 | .rst_data_ready (rst_data_ready), |
| 987 | .set_sel (set_sel[1:0]), |
| 988 | .rst_sel (rst_sel[1:0]), |
| 989 | .sop_state (sop_state), |
| 990 | // Inputs |
| 991 | .rx_clk (rx_clk), |
| 992 | .rx_reset (rx_reset), |
| 993 | .S_D (S_D), |
| 994 | .S_I (S_I), |
| 995 | .D_S (D_S), |
| 996 | .I_S (I_S), |
| 997 | .S_detected (S_detected), |
| 998 | .T_detected_at_modified_pkt (T_detected_at_modified_pkt), |
| 999 | .MID_PKT_ERR_detected_at_modified_pkt (MID_PKT_ERR_detected_at_modified_pkt), |
| 1000 | .rxfifo_full_rxclk (rxfifo_full_rxclk), |
| 1001 | .rxfifo_afull_rxclk (rxfifo_afull_rxclk), |
| 1002 | .link_fault (link_fault)); |
| 1003 | |
| 1004 | /* ------------------- xmac_fcs instantiation ----------------- */ |
| 1005 | wire initialize_rx_crc = rx_reset | !rx_data_valid_gmux; |
| 1006 | xmac_fcs xmac_fcs |
| 1007 | (/*Do Not use AUTOINST since the clk, reset, compute_en, etc won't be correct*/ |
| 1008 | .clk(rx_clk), |
| 1009 | .initialize_crc(initialize_rx_crc), |
| 1010 | .compute_en(~initialize_rx_crc), |
| 1011 | .crc_chk_dis(crc_chk_dis), |
| 1012 | .data_valid(rx_data_valid_gmux), |
| 1013 | .dv_8bit(rx_dv_8bit_reg0_gmux), |
| 1014 | .data_64bit(rx_data_64bit_reg0_gmux), |
| 1015 | // outputs |
| 1016 | .new_crc5_result(new_crc5_result[31:0]), |
| 1017 | .crc_result(rx_crc_result[31:0]), |
| 1018 | .crc_error(crc_error)); |
| 1019 | |
| 1020 | |
| 1021 | /* ------------------- xrlm_sm instantiation ----------------- */ |
| 1022 | xrlm_sm xrlm_sm |
| 1023 | (/*AUTOINST*/ |
| 1024 | // Outputs |
| 1025 | .valid_data (valid_data), |
| 1026 | .set_err_time (set_err_time), |
| 1027 | .eop (eop), |
| 1028 | .rx_ok (rx_ok), |
| 1029 | .err_cond (err_cond), |
| 1030 | .xrlm_state (xrlm_state), |
| 1031 | // Inputs |
| 1032 | .rx_clk (rx_clk), |
| 1033 | .rx_reset (rx_reset), |
| 1034 | .rx_enable_rxclk (rx_enable_rxclk), |
| 1035 | .rx_data_valid_gmux (rx_data_valid_gmux), |
| 1036 | .rx_data_valid_gmux_lead (rx_data_valid_gmux_lead), |
| 1037 | .da_match_err (da_match_err), |
| 1038 | .rxfifo_full_rxclk (rxfifo_full_rxclk), |
| 1039 | .rxfifo_afull_rxclk (rxfifo_afull_rxclk), |
| 1040 | .max_pkt_size_limit (max_pkt_size_limit), |
| 1041 | .err_chk_dis (err_chk_dis), |
| 1042 | .link_fault (link_fault)); |
| 1043 | |
| 1044 | /* ------------------- lfs instantiation ---------------------- */ |
| 1045 | lfs lfs |
| 1046 | (/*AUTOINST*/ |
| 1047 | // Outputs |
| 1048 | .link_fault (link_fault), |
| 1049 | .inc_link_fault_count (inc_link_fault_count), |
| 1050 | .remote_fault_oc (remote_fault_oc), |
| 1051 | .local_fault_oc (local_fault_oc), |
| 1052 | .lfs_state (lfs_state[1:0]), |
| 1053 | // Inputs |
| 1054 | .rx_clk (rx_clk), |
| 1055 | .rx_reset (rx_reset), |
| 1056 | .lfs_disable_rxclk (lfs_disable_rxclk), |
| 1057 | .rxc_a (rxc_a[3:0]), |
| 1058 | .rxc_b (rxc_b[3:0]), |
| 1059 | .rx_data_64bit_reg0 (rx_data_64bit_reg0[63:0])); |
| 1060 | |
| 1061 | |
| 1062 | |
| 1063 | /* ------------------- debug support -------------------------- */ |
| 1064 | RegDff #(1) S_detected_RegDff (.din(S_detected),.clk(rx_clk),.qout(S_detected_reg)); |
| 1065 | RegDff #(1) T_E_detected_at_modified_pkt_RegDff (.din(T_E_detected_at_modified_pkt),.clk(rx_clk),.qout(T_E_detected_at_modified_pkt_reg)); |
| 1066 | RegDff #(1) END_PKT_ERR_detected_a_at_modified_pkt_RegDff (.din(END_PKT_ERR_detected_a_at_modified_pkt),.clk(rx_clk),.qout(END_PKT_ERR_detected_a_at_modified_pkt_reg)); |
| 1067 | RegDff #(1) END_PKT_ERR_detected_b_at_modified_pkt_RegDff (.din(END_PKT_ERR_detected_b_at_modified_pkt),.clk(rx_clk),.qout(END_PKT_ERR_detected_b_at_modified_pkt_reg)); |
| 1068 | RegDff #(1) S_D_RegDff (.din(S_D),.clk(rx_clk),.qout(S_D_reg)); |
| 1069 | RegDff #(1) S_I_RegDff (.din(S_I),.clk(rx_clk),.qout(S_I_reg)); |
| 1070 | RegDff #(1) D_S_RegDff (.din(D_S),.clk(rx_clk),.qout(D_S_reg)); |
| 1071 | RegDff #(1) I_S_RegDff (.din(I_S),.clk(rx_clk),.qout(I_S_reg)); |
| 1072 | RegDff #(1) abort_bit_RegDff (.din(abort_bit),.clk(rx_clk),.qout(abort_bit_reg)); |
| 1073 | RegDff #(1) rx_err_RegDff (.din(rx_err),.clk(rx_clk),.qout(rx_err_reg)); |
| 1074 | RegDff #(1) crc_error_reg_RegDff (.din(crc_error),.clk(rx_clk),.qout(crc_error_reg)); |
| 1075 | RegDff #(1) kill_data_ready_RegDff (.din(kill_data_ready),.clk(rx_clk),.qout(kill_data_ready_reg)); |
| 1076 | RegDff #(1) kill_crc_RegDff (.din(kill_crc),.clk(rx_clk),.qout(kill_crc_reg)); |
| 1077 | RegDff #(2) rx_sel_RegDff (.din(rx_sel[1:0]),.clk(rx_clk),.qout(rx_sel_reg[1:0])); |
| 1078 | |
| 1079 | endmodule // rx_xmac |
| 1080 | |
| 1081 | |