| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: sop_sm.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
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| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /*%W% %G%*/ |
| 36 | |
| 37 | /************************************************************************* |
| 38 | * |
| 39 | * File Name : sop_sm |
| 40 | * Author Name : John Lo |
| 41 | * Description : start of frame deliminter detection state machine. |
| 42 | * It looks at two different data point at different time. |
| 43 | * |
| 44 | * In the initial state CHK_SOP sop_sm looks at |
| 45 | * xrc_a, xrc_b, xrd_a, xrd_b. |
| 46 | * S_detected is used at this state. |
| 47 | * |
| 48 | * After S is verify, sop_sm is in CHK_T_E state and looks at |
| 49 | * rxc_a, rxc_b, rxd_a, rxd_b. |
| 50 | * T_detected_at_modified_pkt and RR_detected_at_modified_pkt |
| 51 | * are used at this state. |
| 52 | * |
| 53 | * Parent Module: rx_xmac |
| 54 | * Child Module: |
| 55 | * Interface Mod: |
| 56 | * Date Created : 7/19/00 |
| 57 | * |
| 58 | * Copyright (c) 2002, Sun Microsystems, Inc. |
| 59 | * Sun Proprietary and Confidential |
| 60 | * |
| 61 | * Modification : complete redesign on 5/29/03 to take care of |
| 62 | * 64 bit xpcs intf. |
| 63 | * |
| 64 | * Synthesis Notes: |
| 65 | * |
| 66 | *************************************************************************/ |
| 67 | |
| 68 | module sop_sm ( |
| 69 | rx_clk, |
| 70 | rx_reset, |
| 71 | S_D, |
| 72 | S_I, |
| 73 | D_S, |
| 74 | I_S, |
| 75 | S_detected, |
| 76 | T_detected_at_modified_pkt, |
| 77 | MID_PKT_ERR_detected_at_modified_pkt, |
| 78 | rxfifo_full_rxclk, |
| 79 | rxfifo_afull_rxclk, |
| 80 | link_fault, |
| 81 | // outputs |
| 82 | set_data_ready, |
| 83 | rst_data_ready, |
| 84 | set_sel, |
| 85 | rst_sel, |
| 86 | sop_state |
| 87 | ); |
| 88 | |
| 89 | |
| 90 | input rx_clk; |
| 91 | input rx_reset; |
| 92 | input S_D; |
| 93 | input S_I; |
| 94 | input D_S; |
| 95 | input I_S; |
| 96 | input S_detected; |
| 97 | input T_detected_at_modified_pkt; |
| 98 | input MID_PKT_ERR_detected_at_modified_pkt; |
| 99 | input rxfifo_full_rxclk; |
| 100 | input rxfifo_afull_rxclk; |
| 101 | input link_fault; |
| 102 | // outputs |
| 103 | output set_data_ready; |
| 104 | output rst_data_ready; |
| 105 | output [1:0] set_sel; |
| 106 | output [1:0] rst_sel; |
| 107 | output sop_state; |
| 108 | |
| 109 | reg set_data_ready; |
| 110 | reg rst_data_ready; |
| 111 | reg [1:0] set_sel; |
| 112 | reg [1:0] rst_sel; |
| 113 | reg nx_sop_state;// next state |
| 114 | wire sop_state; // current state |
| 115 | wire S_D,S_I,D_S,I_S; |
| 116 | |
| 117 | // ------------------------------------------------ |
| 118 | // truth talbe |
| 119 | // -------------------------- -------------------- |
| 120 | // xrc_a xrc_b encode comments |
| 121 | // ------- ------- ---------- -------------------- |
| 122 | // S D 2'b00 no action |
| 123 | // |
| 124 | // S I 2'b01 pull b (abnormal) |
| 125 | // |
| 126 | // D S 2'b10 swap a&b (abnormal) |
| 127 | // |
| 128 | // I S 2'b11 swap a&b + pull a |
| 129 | // ------------------------------------------------ |
| 130 | // |
| 131 | // comments: |
| 132 | // 1. whenever the I is detected, |
| 133 | // the rxc_a_p1/rxc_b_p1 is used. |
| 134 | // 2. sel[1]: is the swap enable bit |
| 135 | // sel[0]: is the delay bit. |
| 136 | |
| 137 | parameter CHK_SOP = 1'b0, |
| 138 | CHK_T_E = 1'b1; |
| 139 | |
| 140 | /* ----------------------- com part ----------------------- */ |
| 141 | always @ (sop_state or rxfifo_full_rxclk or rxfifo_afull_rxclk or |
| 142 | link_fault or S_detected or S_D or S_I or D_S or I_S or |
| 143 | T_detected_at_modified_pkt or MID_PKT_ERR_detected_at_modified_pkt) |
| 144 | begin |
| 145 | nx_sop_state = CHK_SOP; |
| 146 | set_data_ready = 0; |
| 147 | rst_data_ready = 0; |
| 148 | set_sel = 0; |
| 149 | rst_sel = 0; |
| 150 | case (sop_state) // synopsys parallel_case full_case |
| 151 | CHK_SOP: if (rxfifo_full_rxclk | rxfifo_afull_rxclk | |
| 152 | link_fault | ~S_detected) |
| 153 | begin |
| 154 | nx_sop_state = sop_state; // stay |
| 155 | rst_data_ready = 1; |
| 156 | end |
| 157 | else |
| 158 | begin |
| 159 | nx_sop_state = CHK_T_E; |
| 160 | set_data_ready = 1; |
| 161 | case({S_D,S_I,D_S,I_S}) |
| 162 | 4'b1000: begin |
| 163 | set_sel= 2'b00; |
| 164 | rst_sel= 2'b11; |
| 165 | end |
| 166 | 4'b0100: begin |
| 167 | set_sel= 2'b01; |
| 168 | rst_sel= 2'b10; |
| 169 | end |
| 170 | 4'b0010: begin |
| 171 | set_sel= 2'b10; |
| 172 | rst_sel= 2'b01; |
| 173 | end |
| 174 | 4'b0001: begin |
| 175 | set_sel= 2'b11; |
| 176 | rst_sel= 2'b00; |
| 177 | end |
| 178 | default: begin |
| 179 | set_sel= 2'b00; |
| 180 | rst_sel= 2'b00; |
| 181 | end |
| 182 | endcase |
| 183 | end |
| 184 | |
| 185 | CHK_T_E: if (rxfifo_full_rxclk | rxfifo_afull_rxclk | |
| 186 | link_fault | T_detected_at_modified_pkt | (~T_detected_at_modified_pkt & MID_PKT_ERR_detected_at_modified_pkt)) |
| 187 | begin |
| 188 | nx_sop_state = CHK_SOP; |
| 189 | rst_data_ready = 1; |
| 190 | end |
| 191 | else nx_sop_state = sop_state; // stay |
| 192 | |
| 193 | default: begin |
| 194 | nx_sop_state = CHK_SOP; |
| 195 | set_data_ready = 0; |
| 196 | rst_data_ready = 0; |
| 197 | set_sel = 0; |
| 198 | rst_sel = 0; |
| 199 | end |
| 200 | endcase // case(sop_state) |
| 201 | end // always @ (sop_state or S_detected_R or S_detected_F or... |
| 202 | |
| 203 | |
| 204 | |
| 205 | // seq part |
| 206 | RegRst #(1) sop_state_RegRst(.clk(rx_clk),.reset(rx_reset),.din(nx_sop_state),.qout(sop_state)); |
| 207 | |
| 208 | endmodule // sop_sm |
| 209 | |