| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: xpcs.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /************************************************************************* |
| 36 | * File Name : xpcs |
| 37 | * Author Name : Carlos Castil |
| 38 | * Description : This module performs 802.3ae 10Gbps pcs function |
| 39 | * Refer to 802.3ae Clause 36, 46, and 48 |
| 40 | * Parent Module: xmac_2pcs_core |
| 41 | * Date Created : 9/19/02 |
| 42 | * |
| 43 | * Copyright (c) 2003, Sun Microsystems, Inc. |
| 44 | * Sun Proprietary and Confidential |
| 45 | * |
| 46 | * Modification : |
| 47 | * |
| 48 | * Synthesis Notes: |
| 49 | * |
| 50 | *************************************************************************/ |
| 51 | |
| 52 | |
| 53 | module xpcs ( |
| 54 | |
| 55 | |
| 56 | clk, // System input clock |
| 57 | |
| 58 | tx_clk, // MAC TX input Clk 312 MHz (tx_clk div 2) |
| 59 | |
| 60 | rbc0_a, // chan a input clock from Serdes 312 Mhz rx clock <===== NEW CLOCK |
| 61 | rbc0_b, // chan b input clock form Serdes 312 Mhz rx clock |
| 62 | rbc0_c, // chan c input clock form Serdes 312 Mhz rx clock |
| 63 | rbc0_d, // chan d input clock form Serdes 312 Mhz rx clock |
| 64 | |
| 65 | xpcs_loopback, |
| 66 | |
| 67 | xrx_code_group, // Serdes to xpcs receive symbols |
| 68 | xtx_code_group, // xpcs to Serdes transmit symbols |
| 69 | |
| 70 | xlink_up_tx, // signal to on-board LED, low pulse elongated |
| 71 | xsignal_detect, // input from optics which indicates light ok. Inputs from Sequence Detect. |
| 72 | xserdes_rdy, // input from serdes to indicate that the serdes pll is locked |
| 73 | |
| 74 | xpcs_rxd, // XGMII data going onto xGMII |
| 75 | xpcs_rxc, // XGMII receive data valid, GMII interface |
| 76 | |
| 77 | xpcs_txd, // XGMII byte from MAC over GMII |
| 78 | xpcs_txc, // XGMII transmit enable from Mac |
| 79 | |
| 80 | xpcs_debug, |
| 81 | |
| 82 | pio_core_reset, // pio signals |
| 83 | sel_xpcs, |
| 84 | ack_xpcs, |
| 85 | pio_addr, |
| 86 | pio_rd, |
| 87 | pio_wdata, |
| 88 | pio_err_xpcs, |
| 89 | rdata_xpcs, |
| 90 | xpcs_interrupt ); |
| 91 | |
| 92 | input tx_clk; // 312 Mhz reference from serdes |
| 93 | |
| 94 | input clk; // core clock |
| 95 | |
| 96 | input rbc0_a; // 312 Mhz rx clock from serdes |
| 97 | input rbc0_b; // 312 Mhz rx clock from serdes |
| 98 | input rbc0_c; // 312 Mhz rx clock from serdes |
| 99 | input rbc0_d; // 312 Mhz rx clock from serdes |
| 100 | |
| 101 | input [79:0] xrx_code_group; // symbol to send over link |
| 102 | output [79:0] xtx_code_group; // symbol to send over link |
| 103 | |
| 104 | input [3:0] xsignal_detect; // Input from optics which indicates light ok. |
| 105 | input xserdes_rdy; // Input from Serdes to indicate pll lock |
| 106 | |
| 107 | output xlink_up_tx; // signal to on-board LED, low pulse elongated |
| 108 | |
| 109 | output [63:0] xpcs_rxd; // data going onto xGMII |
| 110 | output [7:0] xpcs_rxc; // receive data valid, xGMII interface |
| 111 | |
| 112 | output [31:0] xpcs_debug; |
| 113 | |
| 114 | |
| 115 | input [63:0] xpcs_txd; // 4 bytes from MAC over xGMII |
| 116 | input [7:0] xpcs_txc; // xGMII transmit enable from Mac |
| 117 | |
| 118 | output xpcs_loopback; |
| 119 | |
| 120 | |
| 121 | input pio_core_reset; // hw_reset |
| 122 | input sel_xpcs; |
| 123 | output ack_xpcs; |
| 124 | output pio_err_xpcs; |
| 125 | input [8:0] pio_addr; |
| 126 | input pio_rd; |
| 127 | input [31:0] pio_wdata; |
| 128 | output [31:0] rdata_xpcs; |
| 129 | output xpcs_interrupt; |
| 130 | |
| 131 | wire reset; |
| 132 | |
| 133 | wire [8:0] pio_addr; |
| 134 | wire [31:0] pio_wdata; |
| 135 | wire [31:0] rdata_xpcs; |
| 136 | |
| 137 | wire csr_xpcs_enable; |
| 138 | wire csr_link_status; |
| 139 | wire csr_pulse_deskew_error; |
| 140 | wire [7:0] csr_ebuffer_state; |
| 141 | wire csr_receive_state; |
| 142 | wire csr_bypass_signal_detect; |
| 143 | |
| 144 | wire [3:0] csr_lane_sync_status; |
| 145 | |
| 146 | wire [79:0] xrx_code_group; // symbol to send over link |
| 147 | wire [79:0] xtx_code_group; // symbol to send over link |
| 148 | |
| 149 | wire [39:0] xtx_code_group_mux; |
| 150 | wire [39:0] xrx_code_group_muxout; |
| 151 | |
| 152 | wire [3:0] csr_lane_sync_state0; |
| 153 | wire [3:0] csr_lane_sync_state1; |
| 154 | wire [3:0] csr_lane_sync_state2; |
| 155 | wire [3:0] csr_lane_sync_state3; |
| 156 | |
| 157 | wire csr_loopback; |
| 158 | // vlint flag_dangling_net_within_module off |
| 159 | // vlint flag_net_has_no_load off |
| 160 | wire csr_low_power; |
| 161 | // vlint flag_dangling_net_within_module on |
| 162 | // vlint flag_net_has_no_load on |
| 163 | |
| 164 | wire tx_clk; |
| 165 | wire [63:0] xpcs_txd; |
| 166 | wire [7:0] xpcs_txc; |
| 167 | |
| 168 | wire inc_tx_pkt_count; |
| 169 | wire inc_rx_pkt_count; |
| 170 | |
| 171 | wire inc_tx_pkt_count_ref; |
| 172 | wire inc_rx_pkt_count_ref; |
| 173 | |
| 174 | wire csr_enable_tx_buffers; |
| 175 | |
| 176 | wire csr_trigger_transmit_fault; |
| 177 | wire csr_trigger_receive_fault; |
| 178 | |
| 179 | wire csr_tx_test_enable; |
| 180 | wire [1:0] csr_test_pattern_sel; |
| 181 | |
| 182 | |
| 183 | wire xpcs_loopback; |
| 184 | |
| 185 | wire [7:0] rx_byte_0; |
| 186 | wire [7:0] rx_byte_1; |
| 187 | wire [7:0] rx_byte_2; |
| 188 | wire [7:0] rx_byte_3; |
| 189 | |
| 190 | wire rx_special_0; |
| 191 | wire rx_special_1; |
| 192 | wire rx_special_2; |
| 193 | wire rx_special_3; |
| 194 | |
| 195 | wire rx_error_0; |
| 196 | wire rx_error_1; |
| 197 | wire rx_error_2; |
| 198 | wire rx_error_3; |
| 199 | |
| 200 | wire [7:0] tx_byte_0_enc; |
| 201 | wire [7:0] tx_byte_1_enc; |
| 202 | wire [7:0] tx_byte_2_enc; |
| 203 | wire [7:0] tx_byte_3_enc; |
| 204 | |
| 205 | wire tx_special_0_enc; |
| 206 | wire tx_special_1_enc; |
| 207 | wire tx_special_2_enc; |
| 208 | wire tx_special_3_enc; |
| 209 | |
| 210 | wire [7:0] tx_xgmii_byte_0; |
| 211 | wire [7:0] tx_xgmii_byte_1; |
| 212 | wire [7:0] tx_xgmii_byte_2; |
| 213 | wire [7:0] tx_xgmii_byte_3; |
| 214 | |
| 215 | wire tx_xgmii_special_0; |
| 216 | wire tx_xgmii_special_1; |
| 217 | wire tx_xgmii_special_2; |
| 218 | wire tx_xgmii_special_3; |
| 219 | |
| 220 | wire [7:0] rx_xgmii_byte_0; |
| 221 | wire [7:0] rx_xgmii_byte_1; |
| 222 | wire [7:0] rx_xgmii_byte_2; |
| 223 | wire [7:0] rx_xgmii_byte_3; |
| 224 | |
| 225 | wire rx_xgmii_special_0; |
| 226 | wire rx_xgmii_special_1; |
| 227 | wire rx_xgmii_special_2; |
| 228 | wire rx_xgmii_special_3; |
| 229 | |
| 230 | wire [3:0] csr_tx_state; |
| 231 | |
| 232 | wire sw_reset; |
| 233 | |
| 234 | wire reset_rxclk; |
| 235 | wire reset_txclk; |
| 236 | |
| 237 | wire inc_deskew_error; |
| 238 | |
| 239 | wire csr_transmit_fault_ref; |
| 240 | wire csr_receive_fault_ref; |
| 241 | |
| 242 | wire hw_reset; |
| 243 | |
| 244 | wire clr_sw_reset; |
| 245 | |
| 246 | wire [3:0] csr_vendor_debug_sel; |
| 247 | wire csr_vendor_debug_io_test; |
| 248 | wire [31:0] training_vector; |
| 249 | |
| 250 | wire [31:0] xpcs_debug; |
| 251 | |
| 252 | wire [31:0] rx0_debug; |
| 253 | wire [31:0] rx1_debug; |
| 254 | wire [31:0] rx2_debug; |
| 255 | wire [31:0] rx3_debug; |
| 256 | |
| 257 | wire [31:0] tx0_debug; |
| 258 | wire [31:0] tx1_debug; |
| 259 | wire [31:0] tx2_debug; |
| 260 | wire [31:0] tx3_debug; |
| 261 | |
| 262 | wire rx_symbols_dft_dummy; |
| 263 | |
| 264 | wire debug_io_test_0; |
| 265 | wire debug_io_test_1; |
| 266 | |
| 267 | wire csr_link_status_rx; |
| 268 | |
| 269 | wire trigger_symbol_err_cnt0; |
| 270 | wire trigger_symbol_err_cnt1; |
| 271 | wire trigger_symbol_err_cnt2; |
| 272 | wire trigger_symbol_err_cnt3; |
| 273 | |
| 274 | assign xpcs_loopback = csr_loopback; |
| 275 | assign xlink_up_tx = csr_link_status; |
| 276 | |
| 277 | xpcs_pio xpcs_pio ( |
| 278 | |
| 279 | .core_clk(clk), |
| 280 | |
| 281 | .reset(reset), |
| 282 | .clr_sw_reset(clr_sw_reset), |
| 283 | .sw_reset(sw_reset), |
| 284 | .hw_reset(hw_reset), |
| 285 | |
| 286 | .sel_xpcs(sel_xpcs), |
| 287 | .pio_rd(pio_rd), |
| 288 | .pio_addr(pio_addr), |
| 289 | .pio_wdata(pio_wdata), |
| 290 | |
| 291 | .rdata_xpcs(rdata_xpcs), |
| 292 | .ack_xpcs(ack_xpcs), |
| 293 | .pio_err_xpcs(pio_err_xpcs), |
| 294 | |
| 295 | .xpcs_interrupt(xpcs_interrupt), |
| 296 | |
| 297 | .csr_vendor_debug_sel (csr_vendor_debug_sel), |
| 298 | .csr_vendor_debug_io_test(csr_vendor_debug_io_test), |
| 299 | .training_vector (training_vector), |
| 300 | |
| 301 | .csr_xpcs_enable(csr_xpcs_enable), |
| 302 | .csr_link_status(csr_link_status), |
| 303 | .csr_ebuffer_state(csr_ebuffer_state), |
| 304 | .csr_receive_state(csr_receive_state), |
| 305 | .csr_bypass_signal_detect(csr_bypass_signal_detect), |
| 306 | |
| 307 | .csr_tx_test_enable(csr_tx_test_enable), |
| 308 | .csr_test_pattern_sel(csr_test_pattern_sel), |
| 309 | |
| 310 | .inc_deskew_error(inc_deskew_error), |
| 311 | .inc_tx_pkt_count(inc_tx_pkt_count), |
| 312 | .inc_rx_pkt_count(inc_rx_pkt_count), |
| 313 | |
| 314 | .csr_trigger_transmit_fault(csr_trigger_transmit_fault), |
| 315 | .csr_trigger_receive_fault(csr_trigger_receive_fault), |
| 316 | |
| 317 | .csr_lane_sync_status(csr_lane_sync_status), |
| 318 | |
| 319 | .csr_loopback(csr_loopback), |
| 320 | .csr_low_power(csr_low_power), |
| 321 | .csr_enable_tx_buffers(csr_enable_tx_buffers), |
| 322 | |
| 323 | .csr_tx_state(csr_tx_state), |
| 324 | |
| 325 | .csr_lane_sync_state0(csr_lane_sync_state0), |
| 326 | .csr_lane_sync_state1(csr_lane_sync_state1), |
| 327 | .csr_lane_sync_state2(csr_lane_sync_state2), |
| 328 | .csr_lane_sync_state3(csr_lane_sync_state3), |
| 329 | |
| 330 | .trigger_symbol_err_cnt0(trigger_symbol_err_cnt0), |
| 331 | .trigger_symbol_err_cnt1(trigger_symbol_err_cnt1), |
| 332 | .trigger_symbol_err_cnt2(trigger_symbol_err_cnt2), |
| 333 | .trigger_symbol_err_cnt3(trigger_symbol_err_cnt3) |
| 334 | ); |
| 335 | |
| 336 | xpcs_rxio xpcs_rxio ( |
| 337 | |
| 338 | .reset_rxclk(reset_rxclk), |
| 339 | |
| 340 | .core_clk(clk), |
| 341 | |
| 342 | .rx_signal_detect(xsignal_detect), |
| 343 | |
| 344 | .rx_byte_0(rx_byte_0), |
| 345 | .rx_byte_1(rx_byte_1), |
| 346 | .rx_byte_2(rx_byte_2), |
| 347 | .rx_byte_3(rx_byte_3), |
| 348 | |
| 349 | .rx_special_0(rx_special_0), |
| 350 | .rx_special_1(rx_special_1), |
| 351 | .rx_special_2(rx_special_2), |
| 352 | .rx_special_3(rx_special_3), |
| 353 | |
| 354 | .rx_error_0(rx_error_0), |
| 355 | .rx_error_1(rx_error_1), |
| 356 | .rx_error_2(rx_error_2), |
| 357 | .rx_error_3(rx_error_3), |
| 358 | |
| 359 | .rx_wclk_a(rbc0_a), |
| 360 | .rx_symbol_a(xrx_code_group_muxout[9:0]), |
| 361 | |
| 362 | .rx_wclk_b(rbc0_b), |
| 363 | .rx_symbol_b(xrx_code_group_muxout[19:10]), |
| 364 | |
| 365 | .rx_wclk_c(rbc0_c), |
| 366 | .rx_symbol_c(xrx_code_group_muxout[29:20]), |
| 367 | |
| 368 | .rx_wclk_d(rbc0_d), |
| 369 | .rx_symbol_d(xrx_code_group_muxout[39:30]), |
| 370 | |
| 371 | .csr_lane_sync_status(csr_lane_sync_status), |
| 372 | |
| 373 | .csr_lane_sync_state0(csr_lane_sync_state0), |
| 374 | .csr_lane_sync_state1(csr_lane_sync_state1), |
| 375 | .csr_lane_sync_state2(csr_lane_sync_state2), |
| 376 | .csr_lane_sync_state3(csr_lane_sync_state3), |
| 377 | |
| 378 | .csr_link_status(csr_link_status), |
| 379 | .csr_link_status_rx(csr_link_status_rx), |
| 380 | .csr_pulse_deskew_error(csr_pulse_deskew_error), |
| 381 | .csr_ebuffer_state(csr_ebuffer_state) ); |
| 382 | |
| 383 | |
| 384 | |
| 385 | xpcs_rx xpcs_rx ( |
| 386 | |
| 387 | .rx_clk(rbc0_a), |
| 388 | .reset_rxclk(reset_rxclk), |
| 389 | |
| 390 | .state(csr_receive_state), |
| 391 | .csr_xpcs_enable(csr_xpcs_enable), |
| 392 | .csr_link_status_rx(csr_link_status_rx), |
| 393 | .csr_tx_test_enable(csr_tx_test_enable), |
| 394 | .csr_receive_fault_ref(csr_receive_fault_ref), |
| 395 | |
| 396 | .inc_rx_pkt_count_ref(inc_rx_pkt_count_ref), |
| 397 | |
| 398 | .xserdes_rdy(xserdes_rdy), |
| 399 | |
| 400 | .rx_xgmii_byte_0(rx_xgmii_byte_0), |
| 401 | .rx_xgmii_byte_1(rx_xgmii_byte_1), |
| 402 | .rx_xgmii_byte_2(rx_xgmii_byte_2), |
| 403 | .rx_xgmii_byte_3(rx_xgmii_byte_3), |
| 404 | |
| 405 | .rx_xgmii_special_0(rx_xgmii_special_0), |
| 406 | .rx_xgmii_special_1(rx_xgmii_special_1), |
| 407 | .rx_xgmii_special_2(rx_xgmii_special_2), |
| 408 | .rx_xgmii_special_3(rx_xgmii_special_3), |
| 409 | |
| 410 | .rx_byte_0(rx_byte_0), |
| 411 | .rx_byte_1(rx_byte_1), |
| 412 | .rx_byte_2(rx_byte_2), |
| 413 | .rx_byte_3(rx_byte_3), |
| 414 | |
| 415 | .rx_special_0(rx_special_0), |
| 416 | .rx_special_1(rx_special_1), |
| 417 | .rx_special_2(rx_special_2), |
| 418 | .rx_special_3(rx_special_3), |
| 419 | |
| 420 | .rx_error_0(rx_error_0), |
| 421 | .rx_error_1(rx_error_1), |
| 422 | .rx_error_2(rx_error_2), |
| 423 | .rx_error_3(rx_error_3) |
| 424 | |
| 425 | ); |
| 426 | |
| 427 | xpcs_xgmii_dpath xpcs_xgmii_dpath ( |
| 428 | |
| 429 | .reset_txclk (reset_txclk), |
| 430 | .reset_rxclk (reset_rxclk), |
| 431 | |
| 432 | .tx_clk (tx_clk), // 312 mhz tx clk |
| 433 | |
| 434 | .rbc0_a (rbc0_a), // 312 mhz rx clk |
| 435 | |
| 436 | .xpcs_rxd(xpcs_rxd), // outputs to XMAC receive |
| 437 | .xpcs_rxc(xpcs_rxc), |
| 438 | |
| 439 | .xpcs_txd(xpcs_txd), // inputs from XMAC transmit |
| 440 | .xpcs_txc(xpcs_txc), |
| 441 | |
| 442 | // inputs from XPCS receive |
| 443 | |
| 444 | .rx_xgmii_byte_0(rx_xgmii_byte_0), |
| 445 | .rx_xgmii_byte_1(rx_xgmii_byte_1), |
| 446 | .rx_xgmii_byte_2(rx_xgmii_byte_2), |
| 447 | .rx_xgmii_byte_3(rx_xgmii_byte_3), |
| 448 | |
| 449 | .rx_xgmii_special_0(rx_xgmii_special_0), |
| 450 | .rx_xgmii_special_1(rx_xgmii_special_1), |
| 451 | .rx_xgmii_special_2(rx_xgmii_special_2), |
| 452 | .rx_xgmii_special_3(rx_xgmii_special_3), |
| 453 | |
| 454 | // outputs to XPCS transmit |
| 455 | |
| 456 | .tx_xgmii_byte_0(tx_xgmii_byte_0), |
| 457 | .tx_xgmii_byte_1(tx_xgmii_byte_1), |
| 458 | .tx_xgmii_byte_2(tx_xgmii_byte_2), |
| 459 | .tx_xgmii_byte_3(tx_xgmii_byte_3), |
| 460 | |
| 461 | .tx_xgmii_special_0(tx_xgmii_special_0), |
| 462 | .tx_xgmii_special_1(tx_xgmii_special_1), |
| 463 | .tx_xgmii_special_2(tx_xgmii_special_2), |
| 464 | .tx_xgmii_special_3(tx_xgmii_special_3) |
| 465 | |
| 466 | ); |
| 467 | |
| 468 | xpcs_dpath xpcs_dpath ( |
| 469 | .tx_clk(tx_clk), |
| 470 | |
| 471 | .rx_clk(rbc0_a), |
| 472 | .rbc0_b(rbc0_b), |
| 473 | .rbc0_c(rbc0_c), |
| 474 | .rbc0_d(rbc0_d), |
| 475 | |
| 476 | .csr_loopback(csr_loopback), |
| 477 | .csr_enable_tx_buffers(csr_enable_tx_buffers), |
| 478 | |
| 479 | .rx_symbols_dft_dummy (rx_symbols_dft_dummy), |
| 480 | |
| 481 | .tx_symbols_mux(xtx_code_group_mux), |
| 482 | |
| 483 | .rx_symbols_mux({xrx_code_group[69:60], // receive in from serdes |
| 484 | xrx_code_group[49:40], |
| 485 | xrx_code_group[29:20], |
| 486 | xrx_code_group[9:0]}), |
| 487 | |
| 488 | .rx_symbols_dft({xrx_code_group[79:70], // receive in from serdes |
| 489 | xrx_code_group[59:50], |
| 490 | xrx_code_group[39:30], |
| 491 | xrx_code_group[19:10]}), |
| 492 | |
| 493 | .tx_symbols_dft({xtx_code_group[79:70], |
| 494 | xtx_code_group[59:50], |
| 495 | xtx_code_group[39:30], |
| 496 | xtx_code_group[19:10]}), |
| 497 | |
| 498 | .xrx_code_group_muxout(xrx_code_group_muxout), |
| 499 | |
| 500 | .xtx_code_group({xtx_code_group[69:60], // transmit out to serdes |
| 501 | xtx_code_group[49:40], |
| 502 | xtx_code_group[29:20], |
| 503 | xtx_code_group[9:0]}) |
| 504 | ); |
| 505 | |
| 506 | |
| 507 | xpcs_tx xpcs_tx (.tx_clk(tx_clk), |
| 508 | .reset(reset_txclk), |
| 509 | |
| 510 | .csr_link_status(csr_link_status), |
| 511 | .csr_tx_test_enable(csr_tx_test_enable), |
| 512 | .csr_test_pattern_sel(csr_test_pattern_sel), |
| 513 | |
| 514 | .csr_transmit_fault_ref(csr_transmit_fault_ref), |
| 515 | |
| 516 | .inc_tx_pkt_count_ref(inc_tx_pkt_count_ref), |
| 517 | |
| 518 | .tx_byte_0(tx_xgmii_byte_0), |
| 519 | .tx_byte_1(tx_xgmii_byte_1), |
| 520 | .tx_byte_2(tx_xgmii_byte_2), |
| 521 | .tx_byte_3(tx_xgmii_byte_3), |
| 522 | |
| 523 | .tx_special_0(tx_xgmii_special_0), |
| 524 | .tx_special_1(tx_xgmii_special_1), |
| 525 | .tx_special_2(tx_xgmii_special_2), |
| 526 | .tx_special_3(tx_xgmii_special_3), |
| 527 | |
| 528 | .tx_byte_0_enc(tx_byte_0_enc), |
| 529 | .tx_byte_1_enc(tx_byte_1_enc), |
| 530 | .tx_byte_2_enc(tx_byte_2_enc), |
| 531 | .tx_byte_3_enc(tx_byte_3_enc), |
| 532 | |
| 533 | .tx_special_0_enc(tx_special_0_enc), |
| 534 | .tx_special_1_enc(tx_special_1_enc), |
| 535 | .tx_special_2_enc(tx_special_2_enc), |
| 536 | .tx_special_3_enc(tx_special_3_enc), |
| 537 | |
| 538 | .state(csr_tx_state) ); |
| 539 | |
| 540 | |
| 541 | xpcs_txio xpcs_txio ( |
| 542 | .reset(reset_txclk), |
| 543 | .tx_clk(tx_clk), |
| 544 | |
| 545 | .tx_byte_0(tx_byte_0_enc), |
| 546 | .tx_byte_1(tx_byte_1_enc), |
| 547 | .tx_byte_2(tx_byte_2_enc), |
| 548 | .tx_byte_3(tx_byte_3_enc), |
| 549 | |
| 550 | .tx_special_0(tx_special_0_enc), |
| 551 | .tx_special_1(tx_special_1_enc), |
| 552 | .tx_special_2(tx_special_2_enc), |
| 553 | .tx_special_3(tx_special_3_enc), |
| 554 | |
| 555 | .tx_symbol_0(xtx_code_group_mux[9:0]), |
| 556 | .tx_symbol_1(xtx_code_group_mux[19:10]), |
| 557 | .tx_symbol_2(xtx_code_group_mux[29:20]), |
| 558 | .tx_symbol_3(xtx_code_group_mux[39:30]) |
| 559 | |
| 560 | ); |
| 561 | |
| 562 | xpcs_sync xpcs_sync ( |
| 563 | .core_clk(clk), |
| 564 | .tx_clk(tx_clk), // 312 Mhz reference from serdes |
| 565 | |
| 566 | .rbc0_a(rbc0_a), |
| 567 | |
| 568 | .csr_transmit_fault_ref(csr_transmit_fault_ref), |
| 569 | .csr_receive_fault_ref(csr_receive_fault_ref), |
| 570 | |
| 571 | .csr_trigger_transmit_fault(csr_trigger_transmit_fault), |
| 572 | .csr_trigger_receive_fault(csr_trigger_receive_fault), |
| 573 | |
| 574 | .inc_tx_pkt_count_ref(inc_tx_pkt_count_ref), |
| 575 | .inc_rx_pkt_count_ref(inc_rx_pkt_count_ref), |
| 576 | |
| 577 | .inc_tx_pkt_count(inc_tx_pkt_count), |
| 578 | .inc_rx_pkt_count(inc_rx_pkt_count), |
| 579 | |
| 580 | .csr_pulse_deskew_error(csr_pulse_deskew_error), |
| 581 | .inc_deskew_error(inc_deskew_error), |
| 582 | |
| 583 | .sw_reset(sw_reset), |
| 584 | .pio_core_reset(pio_core_reset), |
| 585 | |
| 586 | .reset_txclk(reset_txclk), |
| 587 | .reset_rxclk(reset_rxclk), |
| 588 | |
| 589 | .clr_sw_reset(clr_sw_reset), |
| 590 | |
| 591 | .rx_error_0(rx_error_0), |
| 592 | .rx_error_1(rx_error_1), |
| 593 | .rx_error_2(rx_error_2), |
| 594 | .rx_error_3(rx_error_3), |
| 595 | |
| 596 | .trigger_symbol_err_cnt0(trigger_symbol_err_cnt0), |
| 597 | .trigger_symbol_err_cnt1(trigger_symbol_err_cnt1), |
| 598 | .trigger_symbol_err_cnt2(trigger_symbol_err_cnt2), |
| 599 | .trigger_symbol_err_cnt3(trigger_symbol_err_cnt3), |
| 600 | |
| 601 | .hw_reset(hw_reset), |
| 602 | .reset(reset) ); |
| 603 | |
| 604 | |
| 605 | // ***************************************************** |
| 606 | // Debug MUX |
| 607 | // ***************************************************** |
| 608 | |
| 609 | assign debug_io_test_0 = csr_bypass_signal_detect; |
| 610 | assign debug_io_test_1 = csr_enable_tx_buffers; |
| 611 | |
| 612 | reg [39:0] xrx_code_group_muxout_dbg; |
| 613 | always @ (posedge rbc0_a) xrx_code_group_muxout_dbg[9:0] <= xrx_code_group_muxout[9:0]; |
| 614 | always @ (posedge rbc0_b) xrx_code_group_muxout_dbg[19:10] <= xrx_code_group_muxout[19:10]; |
| 615 | always @ (posedge rbc0_c) xrx_code_group_muxout_dbg[29:20] <= xrx_code_group_muxout[29:20]; |
| 616 | always @ (posedge rbc0_d) xrx_code_group_muxout_dbg[39:30] <= xrx_code_group_muxout[39:30]; |
| 617 | |
| 618 | |
| 619 | assign rx0_debug = csr_vendor_debug_io_test ? |
| 620 | {debug_io_test_0, debug_io_test_1, |
| 621 | debug_io_test_0, debug_io_test_1, |
| 622 | debug_io_test_0, debug_io_test_1, |
| 623 | debug_io_test_0, debug_io_test_1, |
| 624 | debug_io_test_0, debug_io_test_1, |
| 625 | debug_io_test_0, debug_io_test_1, |
| 626 | debug_io_test_0, debug_io_test_1, |
| 627 | debug_io_test_0, debug_io_test_1, |
| 628 | debug_io_test_0, debug_io_test_1, |
| 629 | debug_io_test_0, debug_io_test_1, |
| 630 | debug_io_test_0, debug_io_test_1, |
| 631 | debug_io_test_0, debug_io_test_1, |
| 632 | debug_io_test_0, debug_io_test_1, |
| 633 | debug_io_test_0, debug_io_test_1, |
| 634 | debug_io_test_0, debug_io_test_1, |
| 635 | debug_io_test_0, debug_io_test_1} |
| 636 | : {rx_symbols_dft_dummy, |
| 637 | 2'b0, |
| 638 | rx_xgmii_byte_0, |
| 639 | rx_xgmii_special_0, |
| 640 | rx_byte_0, |
| 641 | rx_special_0, |
| 642 | rx_error_0, |
| 643 | xrx_code_group_muxout_dbg[9:0]}; |
| 644 | |
| 645 | assign rx1_debug = {3'b000, |
| 646 | rx_xgmii_byte_1, |
| 647 | rx_xgmii_special_1, |
| 648 | rx_byte_1, |
| 649 | rx_special_1, |
| 650 | rx_error_1, |
| 651 | xrx_code_group_muxout_dbg[19:10]}; |
| 652 | |
| 653 | assign rx2_debug = {3'b000, |
| 654 | rx_xgmii_byte_2, |
| 655 | rx_xgmii_special_2, |
| 656 | rx_byte_2, |
| 657 | rx_special_2, |
| 658 | rx_error_2, |
| 659 | xrx_code_group_muxout_dbg[29:20]}; |
| 660 | |
| 661 | assign rx3_debug = {3'b000, |
| 662 | rx_xgmii_byte_3, |
| 663 | rx_xgmii_special_3, |
| 664 | rx_byte_3, |
| 665 | rx_special_3, |
| 666 | rx_error_3, |
| 667 | xrx_code_group_muxout_dbg[39:30]}; |
| 668 | |
| 669 | assign tx0_debug = {4'b0000, |
| 670 | tx_xgmii_byte_0, |
| 671 | tx_xgmii_special_0, |
| 672 | tx_byte_0_enc, |
| 673 | tx_special_0_enc, |
| 674 | xtx_code_group_mux[9:0]}; |
| 675 | |
| 676 | assign tx1_debug = {4'b0000, |
| 677 | tx_xgmii_byte_1, |
| 678 | tx_xgmii_special_1, |
| 679 | tx_byte_1_enc, |
| 680 | tx_special_1_enc, |
| 681 | xtx_code_group_mux[19:10]}; |
| 682 | |
| 683 | assign tx2_debug = {4'b0000, |
| 684 | tx_xgmii_byte_2, |
| 685 | tx_xgmii_special_2, |
| 686 | tx_byte_2_enc, |
| 687 | tx_special_2_enc, |
| 688 | xtx_code_group_mux[29:20]}; |
| 689 | |
| 690 | assign tx3_debug = {4'b0000, |
| 691 | tx_xgmii_byte_3, |
| 692 | tx_xgmii_special_3, |
| 693 | tx_byte_3_enc, |
| 694 | tx_special_3_enc, |
| 695 | xtx_code_group_mux[39:30]}; |
| 696 | |
| 697 | |
| 698 | xpcs_dbg xpcs_dbg (.csr_vendor_debug_sel (csr_vendor_debug_sel), |
| 699 | .training_vector (training_vector), |
| 700 | .rx0_debug (rx0_debug), |
| 701 | .rx1_debug (rx1_debug), |
| 702 | .rx2_debug (rx2_debug), |
| 703 | .rx3_debug (rx3_debug), |
| 704 | |
| 705 | .tx0_debug (tx0_debug), |
| 706 | .tx1_debug (tx1_debug), |
| 707 | .tx2_debug (tx2_debug), |
| 708 | .tx3_debug (tx3_debug), |
| 709 | .xpcs_debug (xpcs_debug) ); |
| 710 | |
| 711 | |
| 712 | endmodule // xpcs |