| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: pcie_common_dcd.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module pcie_common_dcd |
| 36 | ( |
| 37 | clk, // destination clock |
| 38 | rst_l, // reset |
| 39 | csr_pkt_data, // packet data |
| 40 | csr_pkt_req, // packet request |
| 41 | csr_pkt_ack, // packet acknowledge |
| 42 | csr_rng_data // ring data |
| 43 | ); |
| 44 | |
| 45 | // ---------------------------------------------------------------------------- |
| 46 | // Parameters |
| 47 | // ---------------------------------------------------------------------------- |
| 48 | parameter IDLE = 2'b00, // state machine states |
| 49 | LDMS = 2'b01, |
| 50 | LDLS = 2'b10; |
| 51 | |
| 52 | // ---------------------------------------------------------------------------- |
| 53 | // Ports |
| 54 | // ---------------------------------------------------------------------------- |
| 55 | input clk; |
| 56 | input rst_l; |
| 57 | input [`FIRE_CSR_PCKT_BITS] csr_pkt_data; |
| 58 | input csr_pkt_req; |
| 59 | |
| 60 | output csr_pkt_ack; |
| 61 | output [`FIRE_CSR_RING_BITS] csr_rng_data; |
| 62 | |
| 63 | // ---------------------------------------------------------------------------- |
| 64 | // Variables |
| 65 | // ---------------------------------------------------------------------------- |
| 66 | wire req; |
| 67 | |
| 68 | reg [`FIRE_CSR_RING_BITS] csr_rng_data, nxt_rng; |
| 69 | reg [1:0] state, nxt_state; |
| 70 | reg [1:0] sel; |
| 71 | reg ack, nxt_ack; |
| 72 | |
| 73 | // ---------------------------------------------------------------------------- |
| 74 | // Zero In Checkers |
| 75 | // ---------------------------------------------------------------------------- |
| 76 | |
| 77 | // 0in known_driven -var ack -active rst_l |
| 78 | // 0in known_driven -var state -active rst_l |
| 79 | // 0in state_transition -var state -val IDLE -next LDMS |
| 80 | // 0in state_transition -var state -val LDMS -next LDLS |
| 81 | // 0in state_transition -var state -val LDLS -next IDLE |
| 82 | |
| 83 | // ---------------------------------------------------------------------------- |
| 84 | // Instantiations |
| 85 | // ---------------------------------------------------------------------------- |
| 86 | /* N2- AT 03/04/05: |
| 87 | pcie_common_sync_flop #(1'b1) sff |
| 88 | ( |
| 89 | .clk (clk), |
| 90 | .din (csr_pkt_req), |
| 91 | .dout (req) |
| 92 | ); |
| 93 | END N2- AT 03/04/05 */ |
| 94 | |
| 95 | // N2+ AT 03/04/05: repalce pcie_common_sync_flop w/ sync cells from N2 lib. |
| 96 | cl_a1_clksyncff_4x sff( |
| 97 | .siclk (1'b0), |
| 98 | .soclk (1'b0), |
| 99 | .si (1'b0), |
| 100 | .so (), |
| 101 | .l1clk (clk), |
| 102 | .d (csr_pkt_req), |
| 103 | .q (req) |
| 104 | ); |
| 105 | // END N2+ AT 03/04/05 |
| 106 | |
| 107 | // ---------------------------------------------------------------------------- |
| 108 | // Combinational |
| 109 | // ---------------------------------------------------------------------------- |
| 110 | wire csr_pkt_ack = ack; |
| 111 | |
| 112 | // next state |
| 113 | always @ (state or req or ack) begin |
| 114 | case (state) // synopsys parallel_case |
| 115 | IDLE : begin |
| 116 | if (req ^ ack) nxt_state = LDMS; |
| 117 | else nxt_state = IDLE; |
| 118 | end |
| 119 | LDMS : nxt_state = LDLS; |
| 120 | LDLS : nxt_state = IDLE; |
| 121 | default : nxt_state = IDLE; |
| 122 | endcase |
| 123 | end |
| 124 | |
| 125 | // state outputs |
| 126 | always @ (state or nxt_state or ack) begin |
| 127 | case (state) // synopsys parallel_case |
| 128 | IDLE : begin |
| 129 | case (nxt_state) // synopsys parallel_case |
| 130 | LDMS : begin |
| 131 | nxt_ack = ack; |
| 132 | sel = 2'b01; |
| 133 | end |
| 134 | default : begin |
| 135 | nxt_ack = ack; |
| 136 | sel = 2'b00; |
| 137 | end |
| 138 | endcase |
| 139 | end |
| 140 | LDMS : begin |
| 141 | nxt_ack = ack; |
| 142 | sel = 2'b10; |
| 143 | end |
| 144 | LDLS : begin |
| 145 | nxt_ack = ~ack; |
| 146 | sel = 2'b11; |
| 147 | end |
| 148 | default : begin |
| 149 | nxt_ack = ack; |
| 150 | sel = 2'b00; |
| 151 | end |
| 152 | endcase |
| 153 | end |
| 154 | |
| 155 | // next ring |
| 156 | always @ (sel or csr_pkt_data) begin |
| 157 | case (sel) // synopsys infer_mux |
| 158 | 2'b00 : nxt_rng = 0; |
| 159 | 2'b01 : nxt_rng = csr_pkt_data[`FIRE_CSR_PCKT_ADDR_BITS]; |
| 160 | 2'b10 : nxt_rng = csr_pkt_data[`FIRE_CSR_PCKT_RDMS_BITS]; |
| 161 | 2'b11 : nxt_rng = csr_pkt_data[`FIRE_CSR_PCKT_RDLS_BITS]; |
| 162 | endcase |
| 163 | end |
| 164 | |
| 165 | // ---------------------------------------------------------------------------- |
| 166 | // Sequential |
| 167 | // ---------------------------------------------------------------------------- |
| 168 | always @ (posedge clk) begin |
| 169 | if (!rst_l) begin |
| 170 | ack <= 0; |
| 171 | state <= IDLE; |
| 172 | end |
| 173 | else begin |
| 174 | ack <= nxt_ack; |
| 175 | state <= nxt_state; |
| 176 | end |
| 177 | end |
| 178 | |
| 179 | always @ (posedge clk) |
| 180 | if (!rst_l) begin |
| 181 | csr_rng_data <= {32{1'b0}}; |
| 182 | end |
| 183 | else begin |
| 184 | csr_rng_data <= nxt_rng; |
| 185 | end |
| 186 | |
| 187 | endmodule // pcie_common_dcd |