| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: pcie_common_dcs_ism.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
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| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
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| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module pcie_common_dcs_ism |
| 36 | ( |
| 37 | clk, // source clock |
| 38 | rst_l, // reset |
| 39 | csr_rng_cmd, // csr ring command |
| 40 | osm2ism_deq, // osm dequeue |
| 41 | ism2osm_vld, // osm valid |
| 42 | ism2sdp_ds, // sdp data select |
| 43 | ism2sdp_ld // sdp load |
| 44 | ); |
| 45 | |
| 46 | // ---------------------------------------------------------------------------- |
| 47 | // Parameters |
| 48 | // ---------------------------------------------------------------------------- |
| 49 | parameter QD = 3; // queue depth |
| 50 | |
| 51 | parameter IDLE = 2'b00, // state machine states |
| 52 | LDMS = 2'b01, |
| 53 | LDLS = 2'b10; |
| 54 | |
| 55 | // ---------------------------------------------------------------------------- |
| 56 | // Ports |
| 57 | // ---------------------------------------------------------------------------- |
| 58 | input clk; |
| 59 | input rst_l; |
| 60 | input [`FIRE_CSR_CMND_BITS] csr_rng_cmd; |
| 61 | input osm2ism_deq; |
| 62 | |
| 63 | output ism2osm_vld; |
| 64 | output [QD-2:0] ism2sdp_ds; |
| 65 | output [QD-1:0] ism2sdp_ld; |
| 66 | |
| 67 | // ---------------------------------------------------------------------------- |
| 68 | // Variables |
| 69 | // ---------------------------------------------------------------------------- |
| 70 | wire ism2osm_vld, deq; |
| 71 | |
| 72 | reg [QD-2:0] ism2sdp_ds; |
| 73 | reg [QD-1:0] ism2sdp_ld; |
| 74 | reg [QD-1:0] vld, nxt_vld; |
| 75 | reg [1:0] state, nxt_state; |
| 76 | reg enq; |
| 77 | |
| 78 | integer i; |
| 79 | |
| 80 | // ---------------------------------------------------------------------------- |
| 81 | // Zero In Checkers |
| 82 | // ---------------------------------------------------------------------------- |
| 83 | |
| 84 | // 0in fifo -enq enq -deq deq -depth QD |
| 85 | // 0in known_driven -var vld -active rst_l |
| 86 | // 0in known_driven -var state -active rst_l |
| 87 | // 0in state_transition -var state -val IDLE -next LDMS |
| 88 | // 0in state_transition -var state -val LDMS -next LDLS |
| 89 | // 0in state_transition -var state -val LDLS -next IDLE |
| 90 | |
| 91 | // ---------------------------------------------------------------------------- |
| 92 | // Combinational |
| 93 | // ---------------------------------------------------------------------------- |
| 94 | |
| 95 | // valid command |
| 96 | wire rng_vld = |csr_rng_cmd; |
| 97 | |
| 98 | // next state |
| 99 | always @ (state or rng_vld) begin |
| 100 | case (state) // synopsys parallel_case |
| 101 | IDLE : begin |
| 102 | if (rng_vld) nxt_state = LDMS; |
| 103 | else nxt_state = IDLE; |
| 104 | end |
| 105 | LDMS : nxt_state = LDLS; |
| 106 | LDLS : nxt_state = IDLE; |
| 107 | default : nxt_state = IDLE; |
| 108 | endcase |
| 109 | end |
| 110 | |
| 111 | // state outputs |
| 112 | always @ (state or rng_vld) begin |
| 113 | case (state) // synopsys parallel_case |
| 114 | IDLE : enq = rng_vld; |
| 115 | LDMS : enq = 1'b1; |
| 116 | LDLS : enq = 1'b1; |
| 117 | default : enq = 1'b0; |
| 118 | endcase |
| 119 | end |
| 120 | |
| 121 | // osm valid |
| 122 | assign ism2osm_vld = vld[0]; |
| 123 | |
| 124 | // dequeue |
| 125 | assign deq = osm2ism_deq; |
| 126 | |
| 127 | // queue controls |
| 128 | always @ (rst_l or enq or deq or vld) begin |
| 129 | for (i = 0; i < QD - 1; i = i + 1) ism2sdp_ds[i] = vld[i+1]; |
| 130 | case ({enq, deq}) |
| 131 | 2'b00 : ism2sdp_ld = ~{ QD { rst_l } }; |
| 132 | 2'b01 : ism2sdp_ld = vld; |
| 133 | 2'b10 : ism2sdp_ld = ~vld; |
| 134 | 2'b11 : ism2sdp_ld = vld; |
| 135 | endcase |
| 136 | case ({enq, deq}) |
| 137 | 2'b00 : nxt_vld = vld; |
| 138 | 2'b01 : nxt_vld = { 1'b0, vld[QD-1:1] }; |
| 139 | 2'b10 : nxt_vld = { vld[QD-2:0], 1'b1 }; |
| 140 | 2'b11 : nxt_vld = vld; |
| 141 | endcase |
| 142 | end |
| 143 | |
| 144 | // ---------------------------------------------------------------------------- |
| 145 | // Sequential |
| 146 | // ---------------------------------------------------------------------------- |
| 147 | always @ (posedge clk) begin |
| 148 | if (!rst_l) begin |
| 149 | vld <= 0; |
| 150 | state <= IDLE; |
| 151 | end |
| 152 | else begin |
| 153 | vld <= nxt_vld; |
| 154 | state <= nxt_state; |
| 155 | end |
| 156 | end |
| 157 | |
| 158 | endmodule // pcie_common_dcs_ism |