| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: pcie_common_srq_qcp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module pcie_common_srq_qcp ( |
| 36 | clk, |
| 37 | rst_l, |
| 38 | enq, |
| 39 | deq, |
| 40 | ld, |
| 41 | ds, |
| 42 | vld ); |
| 43 | |
| 44 | // ---------------------------------------------------------------------------- |
| 45 | // Parameters |
| 46 | // ---------------------------------------------------------------------------- |
| 47 | parameter QD = 4; // queue depth |
| 48 | |
| 49 | // ---------------------------------------------------------------------------- |
| 50 | // Ports |
| 51 | // ---------------------------------------------------------------------------- |
| 52 | input clk; // clock |
| 53 | input rst_l; // reset |
| 54 | |
| 55 | input enq; // enqueue |
| 56 | input deq; // dequeue |
| 57 | |
| 58 | output [QD-1:0] ld; // load |
| 59 | output [QD-2:0] ds; // data select |
| 60 | output [QD-1:0] vld; // valid bits |
| 61 | |
| 62 | // ---------------------------------------------------------------------------- |
| 63 | // Variables |
| 64 | // ---------------------------------------------------------------------------- |
| 65 | reg [QD-1:0] ld; |
| 66 | reg [QD-2:0] ds; |
| 67 | reg [QD-1:0] vld, nxt_vld; |
| 68 | |
| 69 | integer i; |
| 70 | |
| 71 | // ---------------------------------------------------------------------------- |
| 72 | // Combinational |
| 73 | // ---------------------------------------------------------------------------- |
| 74 | |
| 75 | // data selects |
| 76 | always @ (vld) begin |
| 77 | for (i = 0; i < QD - 1; i = i + 1) ds[i] = vld[i+1]; |
| 78 | end |
| 79 | |
| 80 | // loads |
| 81 | always @ (rst_l or enq or deq or vld) begin |
| 82 | case ({enq, deq}) |
| 83 | 2'b00 : ld = ~{ QD { rst_l } }; |
| 84 | 2'b01 : ld = vld; |
| 85 | 2'b10 : ld = ~vld; |
| 86 | 2'b11 : ld = vld; |
| 87 | endcase |
| 88 | end |
| 89 | |
| 90 | // next valid bits |
| 91 | always @ (enq or deq or vld) begin |
| 92 | case ({enq, deq}) |
| 93 | 2'b00 : nxt_vld = vld; |
| 94 | 2'b01 : nxt_vld = { 1'b0, vld[QD-1:1] }; |
| 95 | 2'b10 : nxt_vld = { vld[QD-2:0], 1'b1 }; |
| 96 | 2'b11 : nxt_vld = vld; |
| 97 | endcase |
| 98 | end |
| 99 | |
| 100 | // ---------------------------------------------------------------------------- |
| 101 | // Sequential |
| 102 | // ---------------------------------------------------------------------------- |
| 103 | |
| 104 | // valid bits |
| 105 | always @ (posedge clk) begin |
| 106 | if (!rst_l) begin |
| 107 | vld <= 0; |
| 108 | end |
| 109 | else begin |
| 110 | vld <= nxt_vld; |
| 111 | end |
| 112 | end |
| 113 | |
| 114 | endmodule // pcie_common_srq_qcp |
| 115 | |