| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: sii_ilc_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module sii_ilc_ctl ( |
| 36 | l2t_sii_iq_dequeue, |
| 37 | l2t_sii_wib_dequeue, |
| 38 | sii_l2t_req_vld, |
| 39 | sii_dbg_l2t_req, |
| 40 | sio_sii_olc_ilc_dequeue_r, |
| 41 | ilc_ipcc_stop, |
| 42 | ilc_ipcc_dmu_wrm_dq, |
| 43 | ilc_ipcc_niu_wrm_dq, |
| 44 | ilc_ipcc_dmu_wrm, |
| 45 | ilc_ipcc_niu_wrm, |
| 46 | ilc_ild_de_sel, |
| 47 | ilc_ild_hdr_sel, |
| 48 | ilc_ild_cyc_sel, |
| 49 | ilc_ild_newhdr, |
| 50 | ilc_ild_ldhdr, |
| 51 | ilc_ild_addr_h, |
| 52 | ilc_ild_addr_lo, |
| 53 | ipcc_data_58_56, |
| 54 | ilc_ildq_rd_addr_m, |
| 55 | ilc_ildq_rd_en_m, |
| 56 | ipcc_ildq_wr_addr, |
| 57 | ipcc_ildq_wr_en, |
| 58 | ipcc_ilc_be, |
| 59 | ipcc_ilc_cmd, |
| 60 | ild_ilc_curhdr, |
| 61 | sii_mb0_run, |
| 62 | sii_mb0_rd_en, |
| 63 | sii_mb0_addr, |
| 64 | l2clk, |
| 65 | scan_in, |
| 66 | scan_out, |
| 67 | tcu_scan_en, |
| 68 | tcu_aclk, |
| 69 | tcu_bclk, |
| 70 | tcu_pce_ov, |
| 71 | tcu_clk_stop); |
| 72 | wire se; |
| 73 | wire siclk; |
| 74 | wire soclk; |
| 75 | wire pce_ov; |
| 76 | wire stop; |
| 77 | wire l1clk; |
| 78 | wire spares_scanin; |
| 79 | wire spares_scanout; |
| 80 | wire ilc_ildq_rd_en_r_unused; |
| 81 | wire ilc_ildq_rd_en_r; |
| 82 | wire [5:0] cstate_r; |
| 83 | wire sii_l2t_req_vld_l; |
| 84 | wire arc_start_hdr1; |
| 85 | wire wrm; |
| 86 | wire wrm_drop; |
| 87 | wire [1:0] sii_dbg_l2t_req_l; |
| 88 | wire [1:0] req_en; |
| 89 | wire hdr_full; |
| 90 | wire [63:0] wrm_hdr; |
| 91 | wire jtag; |
| 92 | wire ilc_ipcc_dmu_wrm_l; |
| 93 | wire wrm_end_r; |
| 94 | wire ilc_ipcc_dmu_wrm_r; |
| 95 | wire ilc_ipcc_niu_wrm_l; |
| 96 | wire ilc_ipcc_niu_wrm_r; |
| 97 | wire wri; |
| 98 | wire [3:0] wri_cnt_l; |
| 99 | wire arc_hdr1_hdr2; |
| 100 | wire wrm_pre; |
| 101 | wire [4:0] curhdr_58_56; |
| 102 | wire [2:0] wrm_cnt_r; |
| 103 | wire [4:0] be_addr; |
| 104 | wire [1:0] cur_hdr_wr_ptr; |
| 105 | wire [2:0] hdr_wr_ptr_r; |
| 106 | wire be_en; |
| 107 | wire be00; |
| 108 | wire be01; |
| 109 | wire be02; |
| 110 | wire be03; |
| 111 | wire be04; |
| 112 | wire be05; |
| 113 | wire be06; |
| 114 | wire be07; |
| 115 | wire be10; |
| 116 | wire be11; |
| 117 | wire be12; |
| 118 | wire be13; |
| 119 | wire be14; |
| 120 | wire be15; |
| 121 | wire be16; |
| 122 | wire be17; |
| 123 | wire be20; |
| 124 | wire be21; |
| 125 | wire be22; |
| 126 | wire be23; |
| 127 | wire be24; |
| 128 | wire be25; |
| 129 | wire be26; |
| 130 | wire be27; |
| 131 | wire be30; |
| 132 | wire be31; |
| 133 | wire be32; |
| 134 | wire be33; |
| 135 | wire be34; |
| 136 | wire be35; |
| 137 | wire be36; |
| 138 | wire be37; |
| 139 | wire [63:0] full_be0; |
| 140 | wire [7:0] be07_r; |
| 141 | wire [7:0] be06_r; |
| 142 | wire [7:0] be05_r; |
| 143 | wire [7:0] be04_r; |
| 144 | wire [7:0] be03_r; |
| 145 | wire [7:0] be02_r; |
| 146 | wire [7:0] be01_r; |
| 147 | wire [7:0] be00_r; |
| 148 | wire [63:0] full_be1; |
| 149 | wire [7:0] be17_r; |
| 150 | wire [7:0] be16_r; |
| 151 | wire [7:0] be15_r; |
| 152 | wire [7:0] be14_r; |
| 153 | wire [7:0] be13_r; |
| 154 | wire [7:0] be12_r; |
| 155 | wire [7:0] be11_r; |
| 156 | wire [7:0] be10_r; |
| 157 | wire [63:0] full_be2; |
| 158 | wire [7:0] be27_r; |
| 159 | wire [7:0] be26_r; |
| 160 | wire [7:0] be25_r; |
| 161 | wire [7:0] be24_r; |
| 162 | wire [7:0] be23_r; |
| 163 | wire [7:0] be22_r; |
| 164 | wire [7:0] be21_r; |
| 165 | wire [7:0] be20_r; |
| 166 | wire [63:0] full_be3; |
| 167 | wire [7:0] be37_r; |
| 168 | wire [7:0] be36_r; |
| 169 | wire [7:0] be35_r; |
| 170 | wire [7:0] be34_r; |
| 171 | wire [7:0] be33_r; |
| 172 | wire [7:0] be32_r; |
| 173 | wire [7:0] be31_r; |
| 174 | wire [7:0] be30_r; |
| 175 | wire [2:0] hdr_rd_ptr_l; |
| 176 | wire [7:0] bem; |
| 177 | wire [2:0] wrm_cnt_l; |
| 178 | wire [5:0] ilc_ildq_rd_addr; |
| 179 | wire hdr_empty; |
| 180 | wire rrd; |
| 181 | wire wri_end; |
| 182 | wire [5:0] ilc_ildq_rd_addr_r; |
| 183 | wire sii_mb0_run_r; |
| 184 | wire [4:0] sii_mb0_addr_r; |
| 185 | wire sii_mb0_rd_en_r; |
| 186 | wire ilc_ildq_rd_en; |
| 187 | wire turn_off_rden; |
| 188 | wire [2:0] hdr_rd_ptr_r; |
| 189 | wire wri_end_pre; |
| 190 | wire [2:0] hdr_wr_ptr_l; |
| 191 | wire [1:0] l2iq_cnt_l; |
| 192 | wire [1:0] l2iq_cnt_r; |
| 193 | wire [2:0] l2wib_cnt_l; |
| 194 | wire [2:0] l2wib_cnt_r; |
| 195 | wire [2:0] sio_cnt_l; |
| 196 | wire posted; |
| 197 | wire [2:0] sio_cnt_r; |
| 198 | wire arc_hdr2_data1; |
| 199 | wire [3:0] wri_cnt_r; |
| 200 | wire arc_data2_start; |
| 201 | wire make_request; |
| 202 | wire l2ok; |
| 203 | wire wrdata_rdy; |
| 204 | wire [2:0] cmd; |
| 205 | wire [2:0] cmd_r; |
| 206 | wire wrm_end_l; |
| 207 | wire arc_data1_data2; |
| 208 | wire arc_data2_data2; |
| 209 | wire arc_data3_start; |
| 210 | wire [4:0] pre_curhdr; |
| 211 | wire [4:0] pre_curhdr0_mux; |
| 212 | wire [4:0] pre_curhdr1_mux; |
| 213 | wire [4:0] pre_curhdr2_mux; |
| 214 | wire [4:0] pre_curhdr3_mux; |
| 215 | wire [4:0] pre_curhdr0; |
| 216 | wire [4:0] pre_curhdr1; |
| 217 | wire [4:0] pre_curhdr2; |
| 218 | wire [4:0] pre_curhdr3; |
| 219 | wire [4:0] pre_curhdr0_r; |
| 220 | wire [4:0] pre_curhdr1_r; |
| 221 | wire [4:0] pre_curhdr2_r; |
| 222 | wire [4:0] pre_curhdr3_r; |
| 223 | wire reg_curhdr_58_56_scanin; |
| 224 | wire reg_curhdr_58_56_scanout; |
| 225 | wire reg_pre_curhdr0_scanin; |
| 226 | wire reg_pre_curhdr0_scanout; |
| 227 | wire reg_pre_curhdr1_scanin; |
| 228 | wire reg_pre_curhdr1_scanout; |
| 229 | wire reg_pre_curhdr2_scanin; |
| 230 | wire reg_pre_curhdr2_scanout; |
| 231 | wire reg_pre_curhdr3_scanin; |
| 232 | wire reg_pre_curhdr3_scanout; |
| 233 | wire reg_sii_l2t_req_vld_scanin; |
| 234 | wire reg_sii_l2t_req_vld_scanout; |
| 235 | wire reg_sii_dbg_l2t_req_scanin; |
| 236 | wire reg_sii_dbg_l2t_req_scanout; |
| 237 | wire reg_cstate_scanin; |
| 238 | wire reg_cstate_scanout; |
| 239 | wire reg_sio_cnt_scanin; |
| 240 | wire reg_sio_cnt_scanout; |
| 241 | wire reg_wri_cnt_scanin; |
| 242 | wire reg_wri_cnt_scanout; |
| 243 | wire reg_wrm_cnt_scanin; |
| 244 | wire reg_wrm_cnt_scanout; |
| 245 | wire reg_l2iq_cnt_r_scanin; |
| 246 | wire reg_l2iq_cnt_r_scanout; |
| 247 | wire reg_l2wib_cnt_r_scanin; |
| 248 | wire reg_l2wib_cnt_r_scanout; |
| 249 | wire reg_hdr_rd_ptr_scanin; |
| 250 | wire reg_hdr_rd_ptr_scanout; |
| 251 | wire reg_hdr_wr_ptr_scanin; |
| 252 | wire reg_hdr_wr_ptr_scanout; |
| 253 | wire reg_ilc_ildq_rd_addr_scanin; |
| 254 | wire reg_ilc_ildq_rd_addr_scanout; |
| 255 | wire reg_ilc_ildq_rd_en_scanin; |
| 256 | wire reg_ilc_ildq_rd_en_scanout; |
| 257 | wire reg_wrm_end_scanin; |
| 258 | wire reg_wrm_end_scanout; |
| 259 | wire reg_cmd_scanin; |
| 260 | wire reg_cmd_scanout; |
| 261 | wire reg_dmu_wrm_scanin; |
| 262 | wire reg_dmu_wrm_scanout; |
| 263 | wire reg_niu_wrm_scanin; |
| 264 | wire reg_niu_wrm_scanout; |
| 265 | wire reg_be00_scanin; |
| 266 | wire reg_be00_scanout; |
| 267 | wire reg_be01_scanin; |
| 268 | wire reg_be01_scanout; |
| 269 | wire reg_be02_scanin; |
| 270 | wire reg_be02_scanout; |
| 271 | wire reg_be03_scanin; |
| 272 | wire reg_be03_scanout; |
| 273 | wire reg_be04_scanin; |
| 274 | wire reg_be04_scanout; |
| 275 | wire reg_be05_scanin; |
| 276 | wire reg_be05_scanout; |
| 277 | wire reg_be06_scanin; |
| 278 | wire reg_be06_scanout; |
| 279 | wire reg_be07_scanin; |
| 280 | wire reg_be07_scanout; |
| 281 | wire reg_be10_scanin; |
| 282 | wire reg_be10_scanout; |
| 283 | wire reg_be11_scanin; |
| 284 | wire reg_be11_scanout; |
| 285 | wire reg_be12_scanin; |
| 286 | wire reg_be12_scanout; |
| 287 | wire reg_be13_scanin; |
| 288 | wire reg_be13_scanout; |
| 289 | wire reg_be14_scanin; |
| 290 | wire reg_be14_scanout; |
| 291 | wire reg_be15_scanin; |
| 292 | wire reg_be15_scanout; |
| 293 | wire reg_be16_scanin; |
| 294 | wire reg_be16_scanout; |
| 295 | wire reg_be17_scanin; |
| 296 | wire reg_be17_scanout; |
| 297 | wire reg_be20_scanin; |
| 298 | wire reg_be20_scanout; |
| 299 | wire reg_be21_scanin; |
| 300 | wire reg_be21_scanout; |
| 301 | wire reg_be22_scanin; |
| 302 | wire reg_be22_scanout; |
| 303 | wire reg_be23_scanin; |
| 304 | wire reg_be23_scanout; |
| 305 | wire reg_be24_scanin; |
| 306 | wire reg_be24_scanout; |
| 307 | wire reg_be25_scanin; |
| 308 | wire reg_be25_scanout; |
| 309 | wire reg_be26_scanin; |
| 310 | wire reg_be26_scanout; |
| 311 | wire reg_be27_scanin; |
| 312 | wire reg_be27_scanout; |
| 313 | wire reg_be30_scanin; |
| 314 | wire reg_be30_scanout; |
| 315 | wire reg_be31_scanin; |
| 316 | wire reg_be31_scanout; |
| 317 | wire reg_be32_scanin; |
| 318 | wire reg_be32_scanout; |
| 319 | wire reg_be33_scanin; |
| 320 | wire reg_be33_scanout; |
| 321 | wire reg_be34_scanin; |
| 322 | wire reg_be34_scanout; |
| 323 | wire reg_be35_scanin; |
| 324 | wire reg_be35_scanout; |
| 325 | wire reg_be36_scanin; |
| 326 | wire reg_be36_scanout; |
| 327 | wire reg_be37_scanin; |
| 328 | wire reg_be37_scanout; |
| 329 | wire reg_sii_mb0_run_scanin; |
| 330 | wire reg_sii_mb0_run_scanout; |
| 331 | wire reg_sii_mb0_rd_en_scanin; |
| 332 | wire reg_sii_mb0_rd_en_scanout; |
| 333 | wire reg_sii_mb0_addr_scanin; |
| 334 | wire reg_sii_mb0_addr_scanout; |
| 335 | wire reg_ilc_ild_addr_h_scanin; |
| 336 | wire reg_ilc_ild_addr_h_scanout; |
| 337 | wire reg_ilc_ild_addr_lo_scanin; |
| 338 | wire reg_ilc_ild_addr_lo_scanout; |
| 339 | |
| 340 | |
| 341 | input l2t_sii_iq_dequeue; |
| 342 | input l2t_sii_wib_dequeue; |
| 343 | output sii_l2t_req_vld; |
| 344 | output [1:0] sii_dbg_l2t_req; |
| 345 | |
| 346 | input sio_sii_olc_ilc_dequeue_r; |
| 347 | //------inter-submodule signals------- |
| 348 | |
| 349 | output ilc_ipcc_stop; //cmp_clk |
| 350 | output ilc_ipcc_dmu_wrm_dq; //cmp_clk |
| 351 | output ilc_ipcc_niu_wrm_dq; //cmp_clk |
| 352 | output ilc_ipcc_dmu_wrm; //cmp_clk |
| 353 | output ilc_ipcc_niu_wrm; //cmp_clk |
| 354 | output [1:0] ilc_ild_de_sel; |
| 355 | output [1:0] ilc_ild_hdr_sel; // select hdr cycle 1 or 2 |
| 356 | output [1:0] ilc_ild_cyc_sel; |
| 357 | output [63:0] ilc_ild_newhdr; |
| 358 | output [3:0] ilc_ild_ldhdr; // load into the hdr register |
| 359 | output [3:0] ilc_ild_addr_h; // select the header register |
| 360 | output [3:0] ilc_ild_addr_lo; // select the header register |
| 361 | |
| 362 | input [4:0] ipcc_data_58_56; |
| 363 | //------going to register file ildq------- |
| 364 | output [4:0] ilc_ildq_rd_addr_m; |
| 365 | output ilc_ildq_rd_en_m; |
| 366 | input [4:0] ipcc_ildq_wr_addr; // for data |
| 367 | input ipcc_ildq_wr_en; // for data |
| 368 | |
| 369 | input [7:0] ipcc_ilc_be; // from ilc |
| 370 | input ipcc_ilc_cmd; // active 1 cyc to indicate header on bus |
| 371 | input [63:0] ild_ilc_curhdr; // current transaction header |
| 372 | |
| 373 | //------ mbist related signals ----------- |
| 374 | input sii_mb0_run; |
| 375 | input sii_mb0_rd_en; |
| 376 | input [4:0] sii_mb0_addr; |
| 377 | |
| 378 | //------ test related signals ----------- |
| 379 | input l2clk; |
| 380 | input scan_in ; |
| 381 | output scan_out; |
| 382 | input tcu_scan_en; |
| 383 | input tcu_aclk; |
| 384 | input tcu_bclk; |
| 385 | input tcu_pce_ov; |
| 386 | input tcu_clk_stop; |
| 387 | |
| 388 | reg [63:0] cur_be; |
| 389 | reg be_on; |
| 390 | reg [3:0] ilc_ild_addr_l; |
| 391 | reg [3:0] ilc_ild_ldhdr; |
| 392 | |
| 393 | assign se = tcu_scan_en; |
| 394 | assign siclk = tcu_aclk; |
| 395 | assign soclk = tcu_bclk; |
| 396 | assign pce_ov = tcu_pce_ov; |
| 397 | assign stop = tcu_clk_stop; |
| 398 | |
| 399 | // Clock header |
| 400 | sii_ilc_ctll1clkhdr_ctl_macro clkgen ( |
| 401 | .l2clk (l2clk ), |
| 402 | .l1en (1'b1 ), |
| 403 | .l1clk (l1clk ), |
| 404 | .pce_ov(pce_ov), |
| 405 | .stop(stop), |
| 406 | .se(se) |
| 407 | ); |
| 408 | // Spare gates |
| 409 | sii_ilc_ctlspare_ctl_macro__num_6 spares ( |
| 410 | .scan_in(spares_scanin), |
| 411 | .scan_out(spares_scanout), |
| 412 | .l1clk (l1clk), |
| 413 | .siclk(siclk), |
| 414 | .soclk(soclk) |
| 415 | ); |
| 416 | |
| 417 | //************************************************************************ |
| 418 | // UNUSED CONNECTIONS |
| 419 | //************************************************************************ |
| 420 | assign ilc_ildq_rd_en_r_unused = ilc_ildq_rd_en_r; |
| 421 | |
| 422 | |
| 423 | //************************************************************************ |
| 424 | // STATE DEFINITION |
| 425 | //************************************************************************ |
| 426 | |
| 427 | `define START_ST 6'b000001 |
| 428 | `define HDR1_ST 6'b000010 |
| 429 | `define HDR2_ST 6'b000100 |
| 430 | `define DATA1_ST 6'b001000 |
| 431 | `define DATA2_ST 6'b010000 |
| 432 | `define DATA3_ST 6'b100000 |
| 433 | |
| 434 | `define START 0 |
| 435 | `define HDR1 1 |
| 436 | `define HDR2 2 |
| 437 | `define DATA1 3 |
| 438 | `define DATA2 4 |
| 439 | `define DATA3 5 |
| 440 | |
| 441 | `define RDD 3'b001 |
| 442 | `define WRM 3'b010 |
| 443 | `define WRI 3'b100 |
| 444 | |
| 445 | reg [5:0] nstate_r; |
| 446 | //reg [5:0] cstate_r; |
| 447 | |
| 448 | wire [5:0] nstate; |
| 449 | wire [5:0] cstate; |
| 450 | |
| 451 | // ------- internal signals -------- |
| 452 | reg [7:0] be; |
| 453 | |
| 454 | assign nstate = {nstate_r[5:1], ~nstate_r[0]}; |
| 455 | assign cstate = {cstate_r[5:1], ~cstate_r[0]}; |
| 456 | //0in one_hot -var cstate[5:0] |
| 457 | //0in one_hot -var nstate_r[5:0] |
| 458 | |
| 459 | |
| 460 | //************************************************************************ |
| 461 | // OUTPUT LOGICS |
| 462 | //************************************************************************ |
| 463 | |
| 464 | assign sii_l2t_req_vld_l = arc_start_hdr1 && ~(wrm && ~be_on && ~wrm_drop); |
| 465 | assign sii_dbg_l2t_req_l[1:0] = sii_l2t_req_vld_l ? req_en[1:0] : 2'b00; |
| 466 | |
| 467 | assign ilc_ipcc_stop = hdr_full; //??? ipcc check 4 data space as well |
| 468 | assign ilc_ipcc_dmu_wrm_dq = sii_l2t_req_vld && wrm && wrm_hdr[59] && ~jtag; |
| 469 | assign ilc_ipcc_niu_wrm_dq = sii_l2t_req_vld && wrm && ~wrm_hdr[59] && ~jtag; |
| 470 | assign ilc_ipcc_dmu_wrm_l = ilc_ipcc_dmu_wrm_dq ? 1'b1 : (wrm_end_r && wrm_hdr[59]) |
| 471 | ? 1'b0 : ilc_ipcc_dmu_wrm ; |
| 472 | assign ilc_ipcc_dmu_wrm = (wrm_end_r && wrm_hdr[59] && ~jtag) || ilc_ipcc_dmu_wrm_r; |
| 473 | assign ilc_ipcc_niu_wrm_l = ilc_ipcc_niu_wrm_dq ? 1'b1 : (wrm_end_r && ~wrm_hdr[59]) |
| 474 | ? 1'b0 : ilc_ipcc_niu_wrm ; |
| 475 | assign ilc_ipcc_niu_wrm = (wrm_end_r && ~wrm_hdr[59] && ~jtag) || ilc_ipcc_niu_wrm_r; |
| 476 | |
| 477 | assign ilc_ild_de_sel[0] = cstate[`DATA1] || (wri ? ~wri_cnt_l[0] : 1'b0); |
| 478 | assign ilc_ild_de_sel[1] = ~ilc_ild_de_sel[0]; |
| 479 | |
| 480 | // select hdr cycle 1 or 2 |
| 481 | assign ilc_ild_hdr_sel[0] = arc_hdr1_hdr2; // select hdr cycle 1 or 2 |
| 482 | assign ilc_ild_hdr_sel[1] = arc_start_hdr1 ; |
| 483 | |
| 484 | assign ilc_ild_cyc_sel[0] = arc_start_hdr1 || arc_hdr1_hdr2 ; |
| 485 | assign ilc_ild_cyc_sel[1] = ~ilc_ild_cyc_sel[0]; |
| 486 | assign ilc_ild_newhdr[63:0] = ((wrm && ~wrm_drop) || wrm_pre) ? wrm_hdr[63:0] : ild_ilc_curhdr[63:0]; |
| 487 | |
| 488 | assign wrm_hdr = {curhdr_58_56[4], ild_ilc_curhdr[62:60], curhdr_58_56[3:0], ild_ilc_curhdr[55:48], be[7:0], |
| 489 | ild_ilc_curhdr[39:6], wrm_cnt_r[2:0], ild_ilc_curhdr[2:0]}; |
| 490 | assign req_en = ild_ilc_curhdr[56] ? 2'b01 : ild_ilc_curhdr[57] ? 2'b11 : 2'b10 ; |
| 491 | //------------ BYTE ENABLE SECTION ---------------- |
| 492 | |
| 493 | assign jtag = wrm_hdr[63]; |
| 494 | assign be_addr[4:0] = {cur_hdr_wr_ptr[1:0],ipcc_ildq_wr_addr[2:0]} ; |
| 495 | assign cur_hdr_wr_ptr[1:0] = hdr_wr_ptr_r[1:0] - 2'b01; |
| 496 | assign be_en = ipcc_ildq_wr_en; |
| 497 | |
| 498 | assign be00 = (be_addr[4:0] == 5'b00000) ? 1'b1 && be_en: 1'b0; |
| 499 | assign be01 = (be_addr[4:0] == 5'b00001) ? 1'b1 && be_en: 1'b0; |
| 500 | assign be02 = (be_addr[4:0] == 5'b00010) ? 1'b1 && be_en: 1'b0; |
| 501 | assign be03 = (be_addr[4:0] == 5'b00011) ? 1'b1 && be_en: 1'b0; |
| 502 | assign be04 = (be_addr[4:0] == 5'b00100) ? 1'b1 && be_en: 1'b0; |
| 503 | assign be05 = (be_addr[4:0] == 5'b00101) ? 1'b1 && be_en: 1'b0; |
| 504 | assign be06 = (be_addr[4:0] == 5'b00110) ? 1'b1 && be_en: 1'b0; |
| 505 | assign be07 = (be_addr[4:0] == 5'b00111) ? 1'b1 && be_en: 1'b0; |
| 506 | assign be10 = (be_addr[4:0] == 5'b01000) ? 1'b1 && be_en: 1'b0; |
| 507 | assign be11 = (be_addr[4:0] == 5'b01001) ? 1'b1 && be_en: 1'b0; |
| 508 | assign be12 = (be_addr[4:0] == 5'b01010) ? 1'b1 && be_en: 1'b0; |
| 509 | assign be13 = (be_addr[4:0] == 5'b01011) ? 1'b1 && be_en: 1'b0; |
| 510 | assign be14 = (be_addr[4:0] == 5'b01100) ? 1'b1 && be_en: 1'b0; |
| 511 | assign be15 = (be_addr[4:0] == 5'b01101) ? 1'b1 && be_en: 1'b0; |
| 512 | assign be16 = (be_addr[4:0] == 5'b01110) ? 1'b1 && be_en: 1'b0; |
| 513 | assign be17 = (be_addr[4:0] == 5'b01111) ? 1'b1 && be_en: 1'b0; |
| 514 | assign be20 = (be_addr[4:0] == 5'b10000) ? 1'b1 && be_en: 1'b0; |
| 515 | assign be21 = (be_addr[4:0] == 5'b10001) ? 1'b1 && be_en: 1'b0; |
| 516 | assign be22 = (be_addr[4:0] == 5'b10010) ? 1'b1 && be_en: 1'b0; |
| 517 | assign be23 = (be_addr[4:0] == 5'b10011) ? 1'b1 && be_en: 1'b0; |
| 518 | assign be24 = (be_addr[4:0] == 5'b10100) ? 1'b1 && be_en: 1'b0; |
| 519 | assign be25 = (be_addr[4:0] == 5'b10101) ? 1'b1 && be_en: 1'b0; |
| 520 | assign be26 = (be_addr[4:0] == 5'b10110) ? 1'b1 && be_en: 1'b0; |
| 521 | assign be27 = (be_addr[4:0] == 5'b10111) ? 1'b1 && be_en: 1'b0; |
| 522 | assign be30 = (be_addr[4:0] == 5'b11000) ? 1'b1 && be_en: 1'b0; |
| 523 | assign be31 = (be_addr[4:0] == 5'b11001) ? 1'b1 && be_en: 1'b0; |
| 524 | assign be32 = (be_addr[4:0] == 5'b11010) ? 1'b1 && be_en: 1'b0; |
| 525 | assign be33 = (be_addr[4:0] == 5'b11011) ? 1'b1 && be_en: 1'b0; |
| 526 | assign be34 = (be_addr[4:0] == 5'b11100) ? 1'b1 && be_en: 1'b0; |
| 527 | assign be35 = (be_addr[4:0] == 5'b11101) ? 1'b1 && be_en: 1'b0; |
| 528 | assign be36 = (be_addr[4:0] == 5'b11110) ? 1'b1 && be_en: 1'b0; |
| 529 | assign be37 = (be_addr[4:0] == 5'b11111) ? 1'b1 && be_en: 1'b0; |
| 530 | |
| 531 | assign full_be0[63:0] = {be07_r[7:0], be06_r[7:0], be05_r[7:0], be04_r[7:0], |
| 532 | be03_r[7:0], be02_r[7:0], be01_r[7:0], be00_r[7:0]}; |
| 533 | assign full_be1[63:0] = {be17_r[7:0], be16_r[7:0], be15_r[7:0], be14_r[7:0], |
| 534 | be13_r[7:0], be12_r[7:0], be11_r[7:0], be10_r[7:0]}; |
| 535 | assign full_be2[63:0] = {be27_r[7:0], be26_r[7:0], be25_r[7:0], be24_r[7:0], |
| 536 | be23_r[7:0], be22_r[7:0], be21_r[7:0], be20_r[7:0]}; |
| 537 | assign full_be3[63:0] = {be37_r[7:0], be36_r[7:0], be35_r[7:0], be34_r[7:0], |
| 538 | be33_r[7:0], be32_r[7:0], be31_r[7:0], be30_r[7:0]}; |
| 539 | always @ (hdr_rd_ptr_l[1:0] or full_be0[63:0] or full_be1[63:0] |
| 540 | or full_be2[63:0] or full_be3[63:0]) |
| 541 | case (hdr_rd_ptr_l[1:0]) //synopsys parallel_case full_case |
| 542 | 2'b00 : cur_be[63:0] = full_be0[63:0]; |
| 543 | 2'b01 : cur_be[63:0] = full_be1[63:0]; |
| 544 | 2'b10 : cur_be[63:0] = full_be2[63:0]; |
| 545 | 2'b11 : cur_be[63:0] = full_be3[63:0]; |
| 546 | default : cur_be[63:0] = 64'h0000000000000000; // 0in < fire -message "ERROR: sii_ilc cur_be default case" |
| 547 | endcase |
| 548 | assign bem[7:0] = {|cur_be[63:56], |cur_be[55:48], |cur_be[47:40], |cur_be[39:32], |
| 549 | |cur_be[31:24], |cur_be[23:16], |cur_be[15:8], |cur_be[7:0]}; |
| 550 | |
| 551 | always @ (wrm_cnt_l[2:0] or bem[7:0] or cur_be[63:0]) |
| 552 | case (wrm_cnt_l[2:0]) //synopsys parallel_case full_case |
| 553 | 3'b000 : begin |
| 554 | be = cur_be[7:0]; |
| 555 | be_on = bem[0]; |
| 556 | end |
| 557 | 3'b001 : begin |
| 558 | be = cur_be[15:8]; |
| 559 | be_on = bem[1]; |
| 560 | end |
| 561 | 3'b010 : begin |
| 562 | be = cur_be[23:16]; |
| 563 | be_on = bem[2]; |
| 564 | end |
| 565 | 3'b011 : begin |
| 566 | be = cur_be[31:24]; |
| 567 | be_on = bem[3]; |
| 568 | end |
| 569 | 3'b100 : begin |
| 570 | be = cur_be[39:32]; |
| 571 | be_on = bem[4]; |
| 572 | end |
| 573 | 3'b101 : begin |
| 574 | be = cur_be[47:40]; |
| 575 | be_on = bem[5]; |
| 576 | end |
| 577 | 3'b110 : begin |
| 578 | be = cur_be[55:48]; |
| 579 | be_on = bem[6]; |
| 580 | end |
| 581 | 3'b111 : begin |
| 582 | be = cur_be[63:56]; |
| 583 | be_on = bem[7]; |
| 584 | end |
| 585 | default : begin |
| 586 | // 0in < fire -message "ERROR: sii_ilc be_on, be default case" |
| 587 | be = 8'b00000000; |
| 588 | be_on = 1'b0; |
| 589 | end |
| 590 | endcase |
| 591 | //------------ READ/WRITE POINTER OF HEADERS ---------------- |
| 592 | always @ (hdr_rd_ptr_l[1:0] ) |
| 593 | case (hdr_rd_ptr_l[1:0]) //synopsys parallel_case full_case |
| 594 | 2'b00 : ilc_ild_addr_l[3:0] = 4'b0001; |
| 595 | 2'b01 : ilc_ild_addr_l[3:0] = 4'b0010; |
| 596 | 2'b10 : ilc_ild_addr_l[3:0] = 4'b0100; |
| 597 | 2'b11 : ilc_ild_addr_l[3:0] = 4'b1000; |
| 598 | default : ilc_ild_addr_l[3:0] = 4'b0000; // 0in < fire -message "ERROR :sii_ilc hdr_rd_ptr default case" |
| 599 | endcase |
| 600 | |
| 601 | always @ (hdr_wr_ptr_r[1:0] or ipcc_ilc_cmd) |
| 602 | if (~ipcc_ilc_cmd) |
| 603 | ilc_ild_ldhdr[3:0] = 4'b0000; |
| 604 | else |
| 605 | case (hdr_wr_ptr_r[1:0]) //synopsys parallel_case full_case |
| 606 | 2'b00 : ilc_ild_ldhdr[3:0] = 4'b0001; |
| 607 | 2'b01 : ilc_ild_ldhdr[3:0] = 4'b0010; |
| 608 | 2'b10 : ilc_ild_ldhdr[3:0] = 4'b0100; |
| 609 | 2'b11 : ilc_ild_ldhdr[3:0] = 4'b1000; |
| 610 | default : ilc_ild_ldhdr[3:0] = 4'b0000; // 0in < fire -message "ERROR :sii_ilc hdr_wr_ptr default case" |
| 611 | endcase |
| 612 | |
| 613 | assign ilc_ildq_rd_addr[5:0] = ~hdr_empty && ((cstate[`HDR2] && ~rrd )|| cstate[`DATA2] && wri |
| 614 | || cstate[`DATA3] && wri_cnt_l[0] && ~wri_end ) ? |
| 615 | (ilc_ildq_rd_addr_r[5:0] + 6'd1) : ilc_ildq_rd_addr_r[5:0]; |
| 616 | |
| 617 | assign ilc_ildq_rd_addr_m[4:0] = sii_mb0_run_r ? sii_mb0_addr_r[4:0] : ilc_ildq_rd_addr[4:0]; |
| 618 | assign ilc_ildq_rd_en_m = sii_mb0_run_r ? sii_mb0_rd_en_r : ilc_ildq_rd_en; |
| 619 | |
| 620 | assign ilc_ildq_rd_en = ~turn_off_rden ; |
| 621 | |
| 622 | //************************************************************************ |
| 623 | // internal wires assignment |
| 624 | //************************************************************************ |
| 625 | |
| 626 | //------------ header empty/full ---------------- |
| 627 | assign hdr_empty = (hdr_rd_ptr_r[1:0] == hdr_wr_ptr_r[1:0]) && |
| 628 | (hdr_rd_ptr_r[2] == hdr_wr_ptr_r[2]); |
| 629 | |
| 630 | assign hdr_full = (hdr_rd_ptr_r[1:0] == hdr_wr_ptr_r[1:0]) && |
| 631 | (hdr_rd_ptr_r[2] != hdr_wr_ptr_r[2]); |
| 632 | |
| 633 | assign hdr_rd_ptr_l[2:0] = ((cstate[`DATA1] && rrd) || (wrm_end_r && wrm ) || |
| 634 | (wri && wri_end_pre)) |
| 635 | ? (hdr_rd_ptr_r[2:0] + 3'b001) |
| 636 | : hdr_rd_ptr_r[2:0]; |
| 637 | assign hdr_wr_ptr_l[2:0] = ipcc_ilc_cmd ? (hdr_wr_ptr_r[2:0] + 3'b001) |
| 638 | : hdr_wr_ptr_r[2:0]; |
| 639 | |
| 640 | |
| 641 | |
| 642 | //------------------l2 transaction counters--------------- |
| 643 | assign l2iq_cnt_l[1:0] = (sii_l2t_req_vld && ~ l2t_sii_iq_dequeue )? (l2iq_cnt_r[1:0]+2'b01) : |
| 644 | (l2t_sii_iq_dequeue && ~sii_l2t_req_vld )? (l2iq_cnt_r[1:0] - 2'b01): |
| 645 | l2iq_cnt_r[1:0]; |
| 646 | |
| 647 | assign l2wib_cnt_l[2:0] = ((sii_l2t_req_vld && wri) && ~l2t_sii_wib_dequeue )? |
| 648 | (l2wib_cnt_r[2:0]+3'b001) : |
| 649 | (l2t_sii_wib_dequeue && ~(sii_l2t_req_vld && wri) ) ? |
| 650 | (l2wib_cnt_r[2:0] - 3'b001): |
| 651 | l2wib_cnt_r[2:0]; |
| 652 | |
| 653 | assign sio_cnt_l[2:0] = (sii_l2t_req_vld && ~posted && ~jtag && ~sio_sii_olc_ilc_dequeue_r )? |
| 654 | (sio_cnt_r[2:0]+3'b001) : |
| 655 | (sio_sii_olc_ilc_dequeue_r && ~(sii_l2t_req_vld && ~posted))? (sio_cnt_r[2:0] - 3'b001): |
| 656 | sio_cnt_r[2:0]; |
| 657 | |
| 658 | //------------------Count WRI cycles --------------- |
| 659 | assign wri_cnt_l[3:0] = cstate[`HDR1] ? 4'b0000 : |
| 660 | ((arc_hdr2_data1 && wri ) || cstate[`DATA3]) ? |
| 661 | (wri_cnt_r[3:0] + 4'b0001) : wri_cnt_r[3:0]; |
| 662 | |
| 663 | //------------------Count WRM cycles --------------- |
| 664 | assign wrm_cnt_l[2:0] = (& wrm_cnt_r[2:0] && arc_data2_start ) ? |
| 665 | 3'b000 : (wrm && cstate[`DATA2] && make_request) ? |
| 666 | (wrm_cnt_r[2:0] + 3'b001) : wrm_cnt_r[2:0]; |
| 667 | |
| 668 | |
| 669 | assign l2ok = (l2iq_cnt_r != 2'b10) & (l2wib_cnt_r != 3'b100) |
| 670 | & (sio_cnt_r[2:0] != 3'b100); |
| 671 | assign turn_off_rden = (ilc_ildq_rd_addr[4:0] == ipcc_ildq_wr_addr[4:0]) && ipcc_ildq_wr_en; |
| 672 | assign make_request = l2ok && ~hdr_empty && wrdata_rdy; |
| 673 | assign wrdata_rdy = (cmd[2:0] == `RDD) ? 1'b1 : (hdr_full || (ilc_ildq_rd_addr_r[4:0] != ipcc_ildq_wr_addr[4:0])); |
| 674 | assign posted = ild_ilc_curhdr[61]; |
| 675 | assign cmd[2:0] = curhdr_58_56[2:0]; |
| 676 | assign wri = (cmd_r[2:0] == `WRI) ? 1'b1 : 1'b0; |
| 677 | assign rrd = (cmd_r[2:0] == `RDD) ? 1'b1 : 1'b0; |
| 678 | assign wrm = (cmd_r[2:0] == `WRM) ? 1'b1 : 1'b0; |
| 679 | assign wri_end = &wri_cnt_l[3:0]; |
| 680 | //assign wri_going = |wri_cnt_r[3:0]; |
| 681 | assign wri_end_pre = (wri_cnt_l[3:0] == 4'b1110); |
| 682 | assign wrm_end_l = &wrm_cnt_l[2:0] && cstate[`DATA1]; |
| 683 | assign wrm_drop = (cmd[2:0] == `WRM) ? 1'b0 : 1'b1; |
| 684 | assign wrm_pre = (cmd[2:0] == `WRM) ? 1'b1 : 1'b0; |
| 685 | |
| 686 | //************************************************************************ |
| 687 | // STATE TRANSITION SECTION |
| 688 | //************************************************************************ |
| 689 | |
| 690 | assign arc_start_hdr1 = cstate[`START] && make_request ; |
| 691 | assign arc_hdr1_hdr2 = cstate[`HDR1] ; |
| 692 | assign arc_hdr2_data1 = cstate[`HDR2] ; |
| 693 | assign arc_data1_data2 = cstate[`DATA1] ; |
| 694 | //assign arc_data2_start = cstate[`DATA2] && ~make_request && ~(wri && wri_going); |
| 695 | //assign arc_data2_hdr1 = cstate[`DATA2] && make_request && ~wri && ~wrm_end_r && ~rrd; |
| 696 | assign arc_data2_start = cstate[`DATA2] && ~wri ; |
| 697 | //in the middle of wrm, l2 not gnt |
| 698 | assign arc_data2_data2 = cstate[`DATA2] && (~l2ok && ~wrm_end_r) && wrm ; |
| 699 | assign arc_data3_start = cstate[`DATA3] && wri_end; |
| 700 | |
| 701 | always @ (arc_start_hdr1 or arc_hdr1_hdr2 or arc_hdr2_data1 or |
| 702 | arc_data1_data2 or arc_data2_start or |
| 703 | arc_data2_data2 or arc_data3_start or cstate ) |
| 704 | |
| 705 | begin |
| 706 | case (1'b1) //synopsys parallel_case full_case |
| 707 | cstate[`START] : if (arc_start_hdr1) |
| 708 | nstate_r = `HDR1_ST; |
| 709 | else |
| 710 | nstate_r = `START_ST; |
| 711 | cstate[`HDR1] : if (arc_hdr1_hdr2) |
| 712 | nstate_r = `HDR2_ST; |
| 713 | else |
| 714 | nstate_r = `START_ST; |
| 715 | cstate[`HDR2] : if (arc_hdr2_data1) |
| 716 | nstate_r = `DATA1_ST; |
| 717 | else |
| 718 | nstate_r = `START_ST; |
| 719 | cstate[`DATA1] : if (arc_data1_data2) |
| 720 | nstate_r = `DATA2_ST; |
| 721 | else |
| 722 | nstate_r = `START_ST; |
| 723 | cstate[`DATA2] : if (arc_data2_data2) |
| 724 | nstate_r = `DATA2_ST; |
| 725 | else if (arc_data2_start) |
| 726 | nstate_r = `START_ST; |
| 727 | else |
| 728 | nstate_r = `DATA3_ST; |
| 729 | cstate[`DATA3] : if (arc_data3_start) |
| 730 | nstate_r = `START_ST; |
| 731 | else |
| 732 | nstate_r = `DATA3_ST; |
| 733 | default : begin |
| 734 | nstate_r = `START_ST; |
| 735 | // 0in < fire -message "ERROR: SIU_ILC state machine default case" |
| 736 | end |
| 737 | |
| 738 | endcase |
| 739 | end |
| 740 | |
| 741 | //************************************************************************ |
| 742 | // REGISTERS section for timing fix |
| 743 | //************************************************************************ |
| 744 | // Make a copy of the curhdr[58:56] inside ilc for timing critical paths |
| 745 | |
| 746 | //{ precurhdr[4:0] = 63, 59-56} |
| 747 | assign pre_curhdr[4:0] = pre_curhdr0_mux[4:0] | pre_curhdr1_mux[4:0] | |
| 748 | pre_curhdr2_mux[4:0] | pre_curhdr3_mux[4:0]; |
| 749 | |
| 750 | assign pre_curhdr0_mux[4:0] = {5{ilc_ild_addr_l[0]}} & pre_curhdr0[4:0]; |
| 751 | assign pre_curhdr1_mux[4:0] = {5{ilc_ild_addr_l[1]}} & pre_curhdr1[4:0]; |
| 752 | assign pre_curhdr2_mux[4:0] = {5{ilc_ild_addr_l[2]}} & pre_curhdr2[4:0]; |
| 753 | assign pre_curhdr3_mux[4:0] = {5{ilc_ild_addr_l[3]}} & pre_curhdr3[4:0]; |
| 754 | |
| 755 | assign pre_curhdr0[4:0] = ilc_ild_ldhdr[0] ? ipcc_data_58_56[4:0] : pre_curhdr0_r[4:0]; |
| 756 | assign pre_curhdr1[4:0] = ilc_ild_ldhdr[1] ? ipcc_data_58_56[4:0] : pre_curhdr1_r[4:0]; |
| 757 | assign pre_curhdr2[4:0] = ilc_ild_ldhdr[2] ? ipcc_data_58_56[4:0] : pre_curhdr2_r[4:0]; |
| 758 | assign pre_curhdr3[4:0] = ilc_ild_ldhdr[3] ? ipcc_data_58_56[4:0] : pre_curhdr3_r[4:0]; |
| 759 | |
| 760 | sii_ilc_ctlmsff_ctl_macro__width_5 reg_curhdr_58_56 |
| 761 | ( |
| 762 | .scan_in(reg_curhdr_58_56_scanin), |
| 763 | .scan_out(reg_curhdr_58_56_scanout), |
| 764 | .din (pre_curhdr[4:0]), |
| 765 | .l1clk (l1clk), |
| 766 | .dout (curhdr_58_56[4:0]), |
| 767 | .siclk(siclk), |
| 768 | .soclk(soclk) |
| 769 | ) ; |
| 770 | |
| 771 | sii_ilc_ctlmsff_ctl_macro__width_5 reg_pre_curhdr0 |
| 772 | ( |
| 773 | .scan_in(reg_pre_curhdr0_scanin), |
| 774 | .scan_out(reg_pre_curhdr0_scanout), |
| 775 | .din (pre_curhdr0[4:0]), |
| 776 | .l1clk (l1clk), |
| 777 | .dout (pre_curhdr0_r[4:0]), |
| 778 | .siclk(siclk), |
| 779 | .soclk(soclk) |
| 780 | ) ; |
| 781 | |
| 782 | sii_ilc_ctlmsff_ctl_macro__width_5 reg_pre_curhdr1 |
| 783 | ( |
| 784 | .scan_in(reg_pre_curhdr1_scanin), |
| 785 | .scan_out(reg_pre_curhdr1_scanout), |
| 786 | .din (pre_curhdr1[4:0]), |
| 787 | .l1clk (l1clk), |
| 788 | .dout (pre_curhdr1_r[4:0]), |
| 789 | .siclk(siclk), |
| 790 | .soclk(soclk) |
| 791 | ) ; |
| 792 | |
| 793 | sii_ilc_ctlmsff_ctl_macro__width_5 reg_pre_curhdr2 |
| 794 | ( |
| 795 | .scan_in(reg_pre_curhdr2_scanin), |
| 796 | .scan_out(reg_pre_curhdr2_scanout), |
| 797 | .din (pre_curhdr2[4:0]), |
| 798 | .l1clk (l1clk), |
| 799 | .dout (pre_curhdr2_r[4:0]), |
| 800 | .siclk(siclk), |
| 801 | .soclk(soclk) |
| 802 | ) ; |
| 803 | |
| 804 | sii_ilc_ctlmsff_ctl_macro__width_5 reg_pre_curhdr3 |
| 805 | ( |
| 806 | .scan_in(reg_pre_curhdr3_scanin), |
| 807 | .scan_out(reg_pre_curhdr3_scanout), |
| 808 | .din (pre_curhdr3[4:0]), |
| 809 | .l1clk (l1clk), |
| 810 | .dout (pre_curhdr3_r[4:0]), |
| 811 | .siclk(siclk), |
| 812 | .soclk(soclk) |
| 813 | ) ; |
| 814 | |
| 815 | //************************************************************************ |
| 816 | // REGISTERS section |
| 817 | //************************************************************************ |
| 818 | sii_ilc_ctlmsff_ctl_macro__width_1 reg_sii_l2t_req_vld // ASYNC reset active low |
| 819 | ( |
| 820 | .scan_in(reg_sii_l2t_req_vld_scanin), |
| 821 | .scan_out(reg_sii_l2t_req_vld_scanout), |
| 822 | .dout(sii_l2t_req_vld), |
| 823 | .l1clk(l1clk), |
| 824 | .din(sii_l2t_req_vld_l), |
| 825 | .siclk(siclk), |
| 826 | .soclk(soclk) |
| 827 | ); |
| 828 | |
| 829 | sii_ilc_ctlmsff_ctl_macro__width_2 reg_sii_dbg_l2t_req // ASYNC reset active low |
| 830 | ( |
| 831 | .scan_in(reg_sii_dbg_l2t_req_scanin), |
| 832 | .scan_out(reg_sii_dbg_l2t_req_scanout), |
| 833 | .dout(sii_dbg_l2t_req), |
| 834 | .l1clk(l1clk), |
| 835 | .din(sii_dbg_l2t_req_l), |
| 836 | .siclk(siclk), |
| 837 | .soclk(soclk) |
| 838 | ); |
| 839 | |
| 840 | sii_ilc_ctlmsff_ctl_macro__width_6 reg_cstate // ASYNC reset active low |
| 841 | ( |
| 842 | .scan_in(reg_cstate_scanin), |
| 843 | .scan_out(reg_cstate_scanout), |
| 844 | .dout(cstate_r[5:0]), |
| 845 | .l1clk(l1clk), |
| 846 | .din(nstate[5:0]), |
| 847 | .siclk(siclk), |
| 848 | .soclk(soclk) |
| 849 | ); |
| 850 | |
| 851 | sii_ilc_ctlmsff_ctl_macro__width_3 reg_sio_cnt // ASYNC reset active low |
| 852 | ( |
| 853 | .scan_in(reg_sio_cnt_scanin), |
| 854 | .scan_out(reg_sio_cnt_scanout), |
| 855 | .dout(sio_cnt_r[2:0]), |
| 856 | .l1clk(l1clk), |
| 857 | .din(sio_cnt_l[2:0]), |
| 858 | .siclk(siclk), |
| 859 | .soclk(soclk) |
| 860 | ); |
| 861 | |
| 862 | sii_ilc_ctlmsff_ctl_macro__width_4 reg_wri_cnt // ASYNC reset active low |
| 863 | ( |
| 864 | .scan_in(reg_wri_cnt_scanin), |
| 865 | .scan_out(reg_wri_cnt_scanout), |
| 866 | .dout(wri_cnt_r[3:0]), |
| 867 | .l1clk(l1clk), |
| 868 | .din(wri_cnt_l[3:0]), |
| 869 | .siclk(siclk), |
| 870 | .soclk(soclk) |
| 871 | ); |
| 872 | |
| 873 | sii_ilc_ctlmsff_ctl_macro__width_3 reg_wrm_cnt // ASYNC reset active low |
| 874 | ( |
| 875 | .scan_in(reg_wrm_cnt_scanin), |
| 876 | .scan_out(reg_wrm_cnt_scanout), |
| 877 | .dout(wrm_cnt_r[2:0]), |
| 878 | .l1clk(l1clk), |
| 879 | .din(wrm_cnt_l[2:0]), |
| 880 | .siclk(siclk), |
| 881 | .soclk(soclk) |
| 882 | ); |
| 883 | |
| 884 | |
| 885 | sii_ilc_ctlmsff_ctl_macro__width_2 reg_l2iq_cnt_r // ASYNC reset active low |
| 886 | ( |
| 887 | .scan_in(reg_l2iq_cnt_r_scanin), |
| 888 | .scan_out(reg_l2iq_cnt_r_scanout), |
| 889 | .dout(l2iq_cnt_r[1:0]), |
| 890 | .l1clk(l1clk), |
| 891 | .din(l2iq_cnt_l[1:0]), |
| 892 | .siclk(siclk), |
| 893 | .soclk(soclk) |
| 894 | ); |
| 895 | |
| 896 | sii_ilc_ctlmsff_ctl_macro__width_3 reg_l2wib_cnt_r // ASYNC reset active low |
| 897 | ( |
| 898 | .scan_in(reg_l2wib_cnt_r_scanin), |
| 899 | .scan_out(reg_l2wib_cnt_r_scanout), |
| 900 | .dout(l2wib_cnt_r[2:0]), |
| 901 | .l1clk(l1clk), |
| 902 | .din(l2wib_cnt_l[2:0]), |
| 903 | .siclk(siclk), |
| 904 | .soclk(soclk) |
| 905 | ); |
| 906 | |
| 907 | sii_ilc_ctlmsff_ctl_macro__width_3 reg_hdr_rd_ptr // ASYNC reset active low |
| 908 | ( |
| 909 | .scan_in(reg_hdr_rd_ptr_scanin), |
| 910 | .scan_out(reg_hdr_rd_ptr_scanout), |
| 911 | .dout(hdr_rd_ptr_r[2:0]), |
| 912 | .l1clk(l1clk), |
| 913 | .din(hdr_rd_ptr_l[2:0]), |
| 914 | .siclk(siclk), |
| 915 | .soclk(soclk) |
| 916 | ); |
| 917 | |
| 918 | sii_ilc_ctlmsff_ctl_macro__width_3 reg_hdr_wr_ptr // ASYNC reset active low |
| 919 | ( |
| 920 | .scan_in(reg_hdr_wr_ptr_scanin), |
| 921 | .scan_out(reg_hdr_wr_ptr_scanout), |
| 922 | .dout(hdr_wr_ptr_r[2:0]), |
| 923 | .l1clk(l1clk), |
| 924 | .din(hdr_wr_ptr_l[2:0]), |
| 925 | .siclk(siclk), |
| 926 | .soclk(soclk) |
| 927 | ); |
| 928 | |
| 929 | sii_ilc_ctlmsff_ctl_macro__width_6 reg_ilc_ildq_rd_addr // ASYNC reset active low |
| 930 | ( |
| 931 | .scan_in(reg_ilc_ildq_rd_addr_scanin), |
| 932 | .scan_out(reg_ilc_ildq_rd_addr_scanout), |
| 933 | .dout(ilc_ildq_rd_addr_r[5:0]), |
| 934 | .l1clk(l1clk), |
| 935 | .din(ilc_ildq_rd_addr[5:0]), |
| 936 | .siclk(siclk), |
| 937 | .soclk(soclk) |
| 938 | ); |
| 939 | |
| 940 | sii_ilc_ctlmsff_ctl_macro__width_1 reg_ilc_ildq_rd_en // ASYNC reset active low |
| 941 | ( |
| 942 | .scan_in(reg_ilc_ildq_rd_en_scanin), |
| 943 | .scan_out(reg_ilc_ildq_rd_en_scanout), |
| 944 | .dout(ilc_ildq_rd_en_r), |
| 945 | .l1clk(l1clk), |
| 946 | .din(ilc_ildq_rd_en), |
| 947 | .siclk(siclk), |
| 948 | .soclk(soclk) |
| 949 | ); |
| 950 | |
| 951 | sii_ilc_ctlmsff_ctl_macro__width_1 reg_wrm_end // ASYNC reset active low |
| 952 | ( |
| 953 | .scan_in(reg_wrm_end_scanin), |
| 954 | .scan_out(reg_wrm_end_scanout), |
| 955 | .dout(wrm_end_r), |
| 956 | .l1clk(l1clk), |
| 957 | .din(wrm_end_l), |
| 958 | .siclk(siclk), |
| 959 | .soclk(soclk) |
| 960 | ); |
| 961 | |
| 962 | sii_ilc_ctlmsff_ctl_macro__width_3 reg_cmd // ASYNC reset active low |
| 963 | ( |
| 964 | .scan_in(reg_cmd_scanin), |
| 965 | .scan_out(reg_cmd_scanout), |
| 966 | .dout(cmd_r[2:0]), |
| 967 | .l1clk(l1clk), |
| 968 | .din(cmd[2:0]), |
| 969 | .siclk(siclk), |
| 970 | .soclk(soclk) |
| 971 | ); |
| 972 | |
| 973 | sii_ilc_ctlmsff_ctl_macro__width_1 reg_dmu_wrm // ASYNC reset active low |
| 974 | ( |
| 975 | .scan_in(reg_dmu_wrm_scanin), |
| 976 | .scan_out(reg_dmu_wrm_scanout), |
| 977 | .dout(ilc_ipcc_dmu_wrm_r), |
| 978 | .l1clk(l1clk), |
| 979 | .din(ilc_ipcc_dmu_wrm_l), |
| 980 | .siclk(siclk), |
| 981 | .soclk(soclk) |
| 982 | ); |
| 983 | |
| 984 | sii_ilc_ctlmsff_ctl_macro__width_1 reg_niu_wrm // ASYNC reset active low |
| 985 | ( |
| 986 | .scan_in(reg_niu_wrm_scanin), |
| 987 | .scan_out(reg_niu_wrm_scanout), |
| 988 | .dout(ilc_ipcc_niu_wrm_r), |
| 989 | .l1clk(l1clk), |
| 990 | .din(ilc_ipcc_niu_wrm_l), |
| 991 | .siclk(siclk), |
| 992 | .soclk(soclk) |
| 993 | ); |
| 994 | |
| 995 | //****************************************************************** |
| 996 | // BE REGISTERS |
| 997 | //****************************************************************** |
| 998 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be00 // ASYNC reset active low |
| 999 | ( |
| 1000 | .scan_in(reg_be00_scanin), |
| 1001 | .scan_out(reg_be00_scanout), |
| 1002 | .dout(be00_r[7:0]), |
| 1003 | .l1clk(l1clk), |
| 1004 | .en(be00), |
| 1005 | .din(ipcc_ilc_be[7:0]), |
| 1006 | .siclk(siclk), |
| 1007 | .soclk(soclk) |
| 1008 | ); |
| 1009 | |
| 1010 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be01 // ASYNC reset active low |
| 1011 | ( |
| 1012 | .scan_in(reg_be01_scanin), |
| 1013 | .scan_out(reg_be01_scanout), |
| 1014 | .dout(be01_r[7:0]), |
| 1015 | .l1clk(l1clk), |
| 1016 | .en(be01), |
| 1017 | .din(ipcc_ilc_be[7:0]), |
| 1018 | .siclk(siclk), |
| 1019 | .soclk(soclk) |
| 1020 | ); |
| 1021 | |
| 1022 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be02 // ASYNC reset active low |
| 1023 | ( |
| 1024 | .scan_in(reg_be02_scanin), |
| 1025 | .scan_out(reg_be02_scanout), |
| 1026 | .dout(be02_r[7:0]), |
| 1027 | .l1clk(l1clk), |
| 1028 | .en(be02), |
| 1029 | .din(ipcc_ilc_be[7:0]), |
| 1030 | .siclk(siclk), |
| 1031 | .soclk(soclk) |
| 1032 | ); |
| 1033 | |
| 1034 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be03 // ASYNC reset active low |
| 1035 | ( |
| 1036 | .scan_in(reg_be03_scanin), |
| 1037 | .scan_out(reg_be03_scanout), |
| 1038 | .dout(be03_r[7:0]), |
| 1039 | .l1clk(l1clk), |
| 1040 | .en(be03), |
| 1041 | .din(ipcc_ilc_be[7:0]), |
| 1042 | .siclk(siclk), |
| 1043 | .soclk(soclk) |
| 1044 | ); |
| 1045 | |
| 1046 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be04 // ASYNC reset active low |
| 1047 | ( |
| 1048 | .scan_in(reg_be04_scanin), |
| 1049 | .scan_out(reg_be04_scanout), |
| 1050 | .dout(be04_r[7:0]), |
| 1051 | .l1clk(l1clk), |
| 1052 | .en(be04), |
| 1053 | .din(ipcc_ilc_be[7:0]), |
| 1054 | .siclk(siclk), |
| 1055 | .soclk(soclk) |
| 1056 | ); |
| 1057 | |
| 1058 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be05 // ASYNC reset active low |
| 1059 | ( |
| 1060 | .scan_in(reg_be05_scanin), |
| 1061 | .scan_out(reg_be05_scanout), |
| 1062 | .dout(be05_r[7:0]), |
| 1063 | .l1clk(l1clk), |
| 1064 | .en(be05), |
| 1065 | .din(ipcc_ilc_be[7:0]), |
| 1066 | .siclk(siclk), |
| 1067 | .soclk(soclk) |
| 1068 | ); |
| 1069 | |
| 1070 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be06 // ASYNC reset active low |
| 1071 | ( |
| 1072 | .scan_in(reg_be06_scanin), |
| 1073 | .scan_out(reg_be06_scanout), |
| 1074 | .dout(be06_r[7:0]), |
| 1075 | .l1clk(l1clk), |
| 1076 | .en(be06), |
| 1077 | .din(ipcc_ilc_be[7:0]), |
| 1078 | .siclk(siclk), |
| 1079 | .soclk(soclk) |
| 1080 | ); |
| 1081 | |
| 1082 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be07 // ASYNC reset active low |
| 1083 | ( |
| 1084 | .scan_in(reg_be07_scanin), |
| 1085 | .scan_out(reg_be07_scanout), |
| 1086 | .dout(be07_r[7:0]), |
| 1087 | .l1clk(l1clk), |
| 1088 | .en(be07), |
| 1089 | .din(ipcc_ilc_be[7:0]), |
| 1090 | .siclk(siclk), |
| 1091 | .soclk(soclk) |
| 1092 | ); |
| 1093 | |
| 1094 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be10 // ASYNC reset active low |
| 1095 | ( |
| 1096 | .scan_in(reg_be10_scanin), |
| 1097 | .scan_out(reg_be10_scanout), |
| 1098 | .dout(be10_r[7:0]), |
| 1099 | .l1clk(l1clk), |
| 1100 | .en(be10), |
| 1101 | .din(ipcc_ilc_be[7:0]), |
| 1102 | .siclk(siclk), |
| 1103 | .soclk(soclk) |
| 1104 | ); |
| 1105 | |
| 1106 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be11 // ASYNC reset active low |
| 1107 | ( |
| 1108 | .scan_in(reg_be11_scanin), |
| 1109 | .scan_out(reg_be11_scanout), |
| 1110 | .dout(be11_r[7:0]), |
| 1111 | .l1clk(l1clk), |
| 1112 | .en(be11), |
| 1113 | .din(ipcc_ilc_be[7:0]), |
| 1114 | .siclk(siclk), |
| 1115 | .soclk(soclk) |
| 1116 | ); |
| 1117 | |
| 1118 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be12 // ASYNC reset active low |
| 1119 | ( |
| 1120 | .scan_in(reg_be12_scanin), |
| 1121 | .scan_out(reg_be12_scanout), |
| 1122 | .dout(be12_r[7:0]), |
| 1123 | .l1clk(l1clk), |
| 1124 | .en(be12), |
| 1125 | .din(ipcc_ilc_be[7:0]), |
| 1126 | .siclk(siclk), |
| 1127 | .soclk(soclk) |
| 1128 | ); |
| 1129 | |
| 1130 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be13 // ASYNC reset active low |
| 1131 | ( |
| 1132 | .scan_in(reg_be13_scanin), |
| 1133 | .scan_out(reg_be13_scanout), |
| 1134 | .dout(be13_r[7:0]), |
| 1135 | .l1clk(l1clk), |
| 1136 | .en(be13), |
| 1137 | .din(ipcc_ilc_be[7:0]), |
| 1138 | .siclk(siclk), |
| 1139 | .soclk(soclk) |
| 1140 | ); |
| 1141 | |
| 1142 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be14 // ASYNC reset active low |
| 1143 | ( |
| 1144 | .scan_in(reg_be14_scanin), |
| 1145 | .scan_out(reg_be14_scanout), |
| 1146 | .dout(be14_r[7:0]), |
| 1147 | .l1clk(l1clk), |
| 1148 | .en(be14), |
| 1149 | .din(ipcc_ilc_be[7:0]), |
| 1150 | .siclk(siclk), |
| 1151 | .soclk(soclk) |
| 1152 | ); |
| 1153 | |
| 1154 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be15 // ASYNC reset active low |
| 1155 | ( |
| 1156 | .scan_in(reg_be15_scanin), |
| 1157 | .scan_out(reg_be15_scanout), |
| 1158 | .dout(be15_r[7:0]), |
| 1159 | .l1clk(l1clk), |
| 1160 | .en(be15), |
| 1161 | .din(ipcc_ilc_be[7:0]), |
| 1162 | .siclk(siclk), |
| 1163 | .soclk(soclk) |
| 1164 | ); |
| 1165 | |
| 1166 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be16 // ASYNC reset active low |
| 1167 | ( |
| 1168 | .scan_in(reg_be16_scanin), |
| 1169 | .scan_out(reg_be16_scanout), |
| 1170 | .dout(be16_r[7:0]), |
| 1171 | .l1clk(l1clk), |
| 1172 | .en(be16), |
| 1173 | .din(ipcc_ilc_be[7:0]), |
| 1174 | .siclk(siclk), |
| 1175 | .soclk(soclk) |
| 1176 | ); |
| 1177 | |
| 1178 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be17 // ASYNC reset active low |
| 1179 | ( |
| 1180 | .scan_in(reg_be17_scanin), |
| 1181 | .scan_out(reg_be17_scanout), |
| 1182 | .dout(be17_r[7:0]), |
| 1183 | .l1clk(l1clk), |
| 1184 | .en(be17), |
| 1185 | .din(ipcc_ilc_be[7:0]), |
| 1186 | .siclk(siclk), |
| 1187 | .soclk(soclk) |
| 1188 | ); |
| 1189 | |
| 1190 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be20 // ASYNC reset active low |
| 1191 | ( |
| 1192 | .scan_in(reg_be20_scanin), |
| 1193 | .scan_out(reg_be20_scanout), |
| 1194 | .dout(be20_r[7:0]), |
| 1195 | .l1clk(l1clk), |
| 1196 | .en(be20), |
| 1197 | .din(ipcc_ilc_be[7:0]), |
| 1198 | .siclk(siclk), |
| 1199 | .soclk(soclk) |
| 1200 | ); |
| 1201 | |
| 1202 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be21 // ASYNC reset active low |
| 1203 | ( |
| 1204 | .scan_in(reg_be21_scanin), |
| 1205 | .scan_out(reg_be21_scanout), |
| 1206 | .dout(be21_r[7:0]), |
| 1207 | .l1clk(l1clk), |
| 1208 | .en(be21), |
| 1209 | .din(ipcc_ilc_be[7:0]), |
| 1210 | .siclk(siclk), |
| 1211 | .soclk(soclk) |
| 1212 | ); |
| 1213 | |
| 1214 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be22 // ASYNC reset active low |
| 1215 | ( |
| 1216 | .scan_in(reg_be22_scanin), |
| 1217 | .scan_out(reg_be22_scanout), |
| 1218 | .dout(be22_r[7:0]), |
| 1219 | .l1clk(l1clk), |
| 1220 | .en(be22), |
| 1221 | .din(ipcc_ilc_be[7:0]), |
| 1222 | .siclk(siclk), |
| 1223 | .soclk(soclk) |
| 1224 | ); |
| 1225 | |
| 1226 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be23 // ASYNC reset active low |
| 1227 | ( |
| 1228 | .scan_in(reg_be23_scanin), |
| 1229 | .scan_out(reg_be23_scanout), |
| 1230 | .dout(be23_r[7:0]), |
| 1231 | .l1clk(l1clk), |
| 1232 | .en(be23), |
| 1233 | .din(ipcc_ilc_be[7:0]), |
| 1234 | .siclk(siclk), |
| 1235 | .soclk(soclk) |
| 1236 | ); |
| 1237 | |
| 1238 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be24 // ASYNC reset active low |
| 1239 | ( |
| 1240 | .scan_in(reg_be24_scanin), |
| 1241 | .scan_out(reg_be24_scanout), |
| 1242 | .dout(be24_r[7:0]), |
| 1243 | .l1clk(l1clk), |
| 1244 | .en(be24), |
| 1245 | .din(ipcc_ilc_be[7:0]), |
| 1246 | .siclk(siclk), |
| 1247 | .soclk(soclk) |
| 1248 | ); |
| 1249 | |
| 1250 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be25 // ASYNC reset active low |
| 1251 | ( |
| 1252 | .scan_in(reg_be25_scanin), |
| 1253 | .scan_out(reg_be25_scanout), |
| 1254 | .dout(be25_r[7:0]), |
| 1255 | .l1clk(l1clk), |
| 1256 | .en(be25), |
| 1257 | .din(ipcc_ilc_be[7:0]), |
| 1258 | .siclk(siclk), |
| 1259 | .soclk(soclk) |
| 1260 | ); |
| 1261 | |
| 1262 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be26 // ASYNC reset active low |
| 1263 | ( |
| 1264 | .scan_in(reg_be26_scanin), |
| 1265 | .scan_out(reg_be26_scanout), |
| 1266 | .dout(be26_r[7:0]), |
| 1267 | .l1clk(l1clk), |
| 1268 | .en(be26), |
| 1269 | .din(ipcc_ilc_be[7:0]), |
| 1270 | .siclk(siclk), |
| 1271 | .soclk(soclk) |
| 1272 | ); |
| 1273 | |
| 1274 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be27 // ASYNC reset active low |
| 1275 | ( |
| 1276 | .scan_in(reg_be27_scanin), |
| 1277 | .scan_out(reg_be27_scanout), |
| 1278 | .dout(be27_r[7:0]), |
| 1279 | .l1clk(l1clk), |
| 1280 | .en(be27), |
| 1281 | .din(ipcc_ilc_be[7:0]), |
| 1282 | .siclk(siclk), |
| 1283 | .soclk(soclk) |
| 1284 | ); |
| 1285 | |
| 1286 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be30 // ASYNC reset active low |
| 1287 | ( |
| 1288 | .scan_in(reg_be30_scanin), |
| 1289 | .scan_out(reg_be30_scanout), |
| 1290 | .dout(be30_r[7:0]), |
| 1291 | .l1clk(l1clk), |
| 1292 | .en(be30), |
| 1293 | .din(ipcc_ilc_be[7:0]), |
| 1294 | .siclk(siclk), |
| 1295 | .soclk(soclk) |
| 1296 | ); |
| 1297 | |
| 1298 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be31 // ASYNC reset active low |
| 1299 | ( |
| 1300 | .scan_in(reg_be31_scanin), |
| 1301 | .scan_out(reg_be31_scanout), |
| 1302 | .dout(be31_r[7:0]), |
| 1303 | .l1clk(l1clk), |
| 1304 | .en(be31), |
| 1305 | .din(ipcc_ilc_be[7:0]), |
| 1306 | .siclk(siclk), |
| 1307 | .soclk(soclk) |
| 1308 | ); |
| 1309 | |
| 1310 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be32 // ASYNC reset active low |
| 1311 | ( |
| 1312 | .scan_in(reg_be32_scanin), |
| 1313 | .scan_out(reg_be32_scanout), |
| 1314 | .dout(be32_r[7:0]), |
| 1315 | .l1clk(l1clk), |
| 1316 | .en(be32), |
| 1317 | .din(ipcc_ilc_be[7:0]), |
| 1318 | .siclk(siclk), |
| 1319 | .soclk(soclk) |
| 1320 | ); |
| 1321 | |
| 1322 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be33 // ASYNC reset active low |
| 1323 | ( |
| 1324 | .scan_in(reg_be33_scanin), |
| 1325 | .scan_out(reg_be33_scanout), |
| 1326 | .dout(be33_r[7:0]), |
| 1327 | .l1clk(l1clk), |
| 1328 | .en(be33), |
| 1329 | .din(ipcc_ilc_be[7:0]), |
| 1330 | .siclk(siclk), |
| 1331 | .soclk(soclk) |
| 1332 | ); |
| 1333 | |
| 1334 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be34 // ASYNC reset active low |
| 1335 | ( |
| 1336 | .scan_in(reg_be34_scanin), |
| 1337 | .scan_out(reg_be34_scanout), |
| 1338 | .dout(be34_r[7:0]), |
| 1339 | .l1clk(l1clk), |
| 1340 | .en(be34), |
| 1341 | .din(ipcc_ilc_be[7:0]), |
| 1342 | .siclk(siclk), |
| 1343 | .soclk(soclk) |
| 1344 | ); |
| 1345 | |
| 1346 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be35 // ASYNC reset active low |
| 1347 | ( |
| 1348 | .scan_in(reg_be35_scanin), |
| 1349 | .scan_out(reg_be35_scanout), |
| 1350 | .dout(be35_r[7:0]), |
| 1351 | .l1clk(l1clk), |
| 1352 | .en(be35), |
| 1353 | .din(ipcc_ilc_be[7:0]), |
| 1354 | .siclk(siclk), |
| 1355 | .soclk(soclk) |
| 1356 | ); |
| 1357 | |
| 1358 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be36 // ASYNC reset active low |
| 1359 | ( |
| 1360 | .scan_in(reg_be36_scanin), |
| 1361 | .scan_out(reg_be36_scanout), |
| 1362 | .dout(be36_r[7:0]), |
| 1363 | .l1clk(l1clk), |
| 1364 | .en(be36), |
| 1365 | .din(ipcc_ilc_be[7:0]), |
| 1366 | .siclk(siclk), |
| 1367 | .soclk(soclk) |
| 1368 | ); |
| 1369 | |
| 1370 | sii_ilc_ctlmsff_ctl_macro__en_1__width_8 reg_be37 // ASYNC reset active low |
| 1371 | ( |
| 1372 | .scan_in(reg_be37_scanin), |
| 1373 | .scan_out(reg_be37_scanout), |
| 1374 | .dout(be37_r[7:0]), |
| 1375 | .l1clk(l1clk), |
| 1376 | .en(be37), |
| 1377 | .din(ipcc_ilc_be[7:0]), |
| 1378 | .siclk(siclk), |
| 1379 | .soclk(soclk) |
| 1380 | ); |
| 1381 | |
| 1382 | sii_ilc_ctlmsff_ctl_macro__width_1 reg_sii_mb0_run // ASYNC reset active low |
| 1383 | ( |
| 1384 | .scan_in(reg_sii_mb0_run_scanin), |
| 1385 | .scan_out(reg_sii_mb0_run_scanout), |
| 1386 | .dout(sii_mb0_run_r), |
| 1387 | .l1clk(l1clk), |
| 1388 | .din(sii_mb0_run), |
| 1389 | .siclk(siclk), |
| 1390 | .soclk(soclk) |
| 1391 | ); |
| 1392 | |
| 1393 | sii_ilc_ctlmsff_ctl_macro__width_1 reg_sii_mb0_rd_en // ASYNC reset active low |
| 1394 | ( |
| 1395 | .scan_in(reg_sii_mb0_rd_en_scanin), |
| 1396 | .scan_out(reg_sii_mb0_rd_en_scanout), |
| 1397 | .dout(sii_mb0_rd_en_r), |
| 1398 | .l1clk(l1clk), |
| 1399 | .din(sii_mb0_rd_en), |
| 1400 | .siclk(siclk), |
| 1401 | .soclk(soclk) |
| 1402 | ); |
| 1403 | |
| 1404 | sii_ilc_ctlmsff_ctl_macro__width_5 reg_sii_mb0_addr // ASYNC reset active low |
| 1405 | ( |
| 1406 | .scan_in(reg_sii_mb0_addr_scanin), |
| 1407 | .scan_out(reg_sii_mb0_addr_scanout), |
| 1408 | .dout(sii_mb0_addr_r[4:0]), |
| 1409 | .l1clk(l1clk), |
| 1410 | .din(sii_mb0_addr[4:0]), |
| 1411 | .siclk(siclk), |
| 1412 | .soclk(soclk) |
| 1413 | ); |
| 1414 | |
| 1415 | sii_ilc_ctlmsff_ctl_macro__width_4 reg_ilc_ild_addr_h // ASYNC reset active low |
| 1416 | ( |
| 1417 | .scan_in(reg_ilc_ild_addr_h_scanin), |
| 1418 | .scan_out(reg_ilc_ild_addr_h_scanout), |
| 1419 | .dout(ilc_ild_addr_h[3:0]), |
| 1420 | .l1clk(l1clk), |
| 1421 | .din(ilc_ild_addr_l[3:0]), |
| 1422 | .siclk(siclk), |
| 1423 | .soclk(soclk) |
| 1424 | ); |
| 1425 | |
| 1426 | sii_ilc_ctlmsff_ctl_macro__width_4 reg_ilc_ild_addr_lo // ASYNC reset active low |
| 1427 | ( |
| 1428 | .scan_in(reg_ilc_ild_addr_lo_scanin), |
| 1429 | .scan_out(reg_ilc_ild_addr_lo_scanout), |
| 1430 | .dout(ilc_ild_addr_lo[3:0]), |
| 1431 | .l1clk(l1clk), |
| 1432 | .din(ilc_ild_addr_l[3:0]), |
| 1433 | .siclk(siclk), |
| 1434 | .soclk(soclk) |
| 1435 | ); |
| 1436 | |
| 1437 | // fixscan start: |
| 1438 | assign spares_scanin = scan_in ; |
| 1439 | assign reg_curhdr_58_56_scanin = spares_scanout ; |
| 1440 | assign reg_pre_curhdr0_scanin = reg_curhdr_58_56_scanout ; |
| 1441 | assign reg_pre_curhdr1_scanin = reg_pre_curhdr0_scanout ; |
| 1442 | assign reg_pre_curhdr2_scanin = reg_pre_curhdr1_scanout ; |
| 1443 | assign reg_pre_curhdr3_scanin = reg_pre_curhdr2_scanout ; |
| 1444 | assign reg_sii_l2t_req_vld_scanin = reg_pre_curhdr3_scanout ; |
| 1445 | assign reg_sii_dbg_l2t_req_scanin = reg_sii_l2t_req_vld_scanout; |
| 1446 | assign reg_cstate_scanin = reg_sii_dbg_l2t_req_scanout; |
| 1447 | assign reg_sio_cnt_scanin = reg_cstate_scanout ; |
| 1448 | assign reg_wri_cnt_scanin = reg_sio_cnt_scanout ; |
| 1449 | assign reg_wrm_cnt_scanin = reg_wri_cnt_scanout ; |
| 1450 | assign reg_l2iq_cnt_r_scanin = reg_wrm_cnt_scanout ; |
| 1451 | assign reg_l2wib_cnt_r_scanin = reg_l2iq_cnt_r_scanout ; |
| 1452 | assign reg_hdr_rd_ptr_scanin = reg_l2wib_cnt_r_scanout ; |
| 1453 | assign reg_hdr_wr_ptr_scanin = reg_hdr_rd_ptr_scanout ; |
| 1454 | assign reg_ilc_ildq_rd_addr_scanin = reg_hdr_wr_ptr_scanout ; |
| 1455 | assign reg_ilc_ildq_rd_en_scanin = reg_ilc_ildq_rd_addr_scanout; |
| 1456 | assign reg_wrm_end_scanin = reg_ilc_ildq_rd_en_scanout; |
| 1457 | assign reg_cmd_scanin = reg_wrm_end_scanout ; |
| 1458 | assign reg_dmu_wrm_scanin = reg_cmd_scanout ; |
| 1459 | assign reg_niu_wrm_scanin = reg_dmu_wrm_scanout ; |
| 1460 | assign reg_be00_scanin = reg_niu_wrm_scanout ; |
| 1461 | assign reg_be01_scanin = reg_be00_scanout ; |
| 1462 | assign reg_be02_scanin = reg_be01_scanout ; |
| 1463 | assign reg_be03_scanin = reg_be02_scanout ; |
| 1464 | assign reg_be04_scanin = reg_be03_scanout ; |
| 1465 | assign reg_be05_scanin = reg_be04_scanout ; |
| 1466 | assign reg_be06_scanin = reg_be05_scanout ; |
| 1467 | assign reg_be07_scanin = reg_be06_scanout ; |
| 1468 | assign reg_be10_scanin = reg_be07_scanout ; |
| 1469 | assign reg_be11_scanin = reg_be10_scanout ; |
| 1470 | assign reg_be12_scanin = reg_be11_scanout ; |
| 1471 | assign reg_be13_scanin = reg_be12_scanout ; |
| 1472 | assign reg_be14_scanin = reg_be13_scanout ; |
| 1473 | assign reg_be15_scanin = reg_be14_scanout ; |
| 1474 | assign reg_be16_scanin = reg_be15_scanout ; |
| 1475 | assign reg_be17_scanin = reg_be16_scanout ; |
| 1476 | assign reg_be20_scanin = reg_be17_scanout ; |
| 1477 | assign reg_be21_scanin = reg_be20_scanout ; |
| 1478 | assign reg_be22_scanin = reg_be21_scanout ; |
| 1479 | assign reg_be23_scanin = reg_be22_scanout ; |
| 1480 | assign reg_be24_scanin = reg_be23_scanout ; |
| 1481 | assign reg_be25_scanin = reg_be24_scanout ; |
| 1482 | assign reg_be26_scanin = reg_be25_scanout ; |
| 1483 | assign reg_be27_scanin = reg_be26_scanout ; |
| 1484 | assign reg_be30_scanin = reg_be27_scanout ; |
| 1485 | assign reg_be31_scanin = reg_be30_scanout ; |
| 1486 | assign reg_be32_scanin = reg_be31_scanout ; |
| 1487 | assign reg_be33_scanin = reg_be32_scanout ; |
| 1488 | assign reg_be34_scanin = reg_be33_scanout ; |
| 1489 | assign reg_be35_scanin = reg_be34_scanout ; |
| 1490 | assign reg_be36_scanin = reg_be35_scanout ; |
| 1491 | assign reg_be37_scanin = reg_be36_scanout ; |
| 1492 | assign reg_sii_mb0_run_scanin = reg_be37_scanout ; |
| 1493 | assign reg_sii_mb0_rd_en_scanin = reg_sii_mb0_run_scanout ; |
| 1494 | assign reg_sii_mb0_addr_scanin = reg_sii_mb0_rd_en_scanout; |
| 1495 | assign reg_ilc_ild_addr_h_scanin = reg_sii_mb0_addr_scanout ; |
| 1496 | assign reg_ilc_ild_addr_lo_scanin = reg_ilc_ild_addr_h_scanout; |
| 1497 | assign scan_out = reg_ilc_ild_addr_lo_scanout; |
| 1498 | // fixscan end: |
| 1499 | endmodule |
| 1500 | |
| 1501 | |
| 1502 | |
| 1503 | |
| 1504 | |
| 1505 | |
| 1506 | // any PARAMS parms go into naming of macro |
| 1507 | |
| 1508 | module sii_ilc_ctll1clkhdr_ctl_macro ( |
| 1509 | l2clk, |
| 1510 | l1en, |
| 1511 | pce_ov, |
| 1512 | stop, |
| 1513 | se, |
| 1514 | l1clk); |
| 1515 | |
| 1516 | |
| 1517 | input l2clk; |
| 1518 | input l1en; |
| 1519 | input pce_ov; |
| 1520 | input stop; |
| 1521 | input se; |
| 1522 | output l1clk; |
| 1523 | |
| 1524 | |
| 1525 | |
| 1526 | |
| 1527 | |
| 1528 | cl_sc1_l1hdr_8x c_0 ( |
| 1529 | |
| 1530 | |
| 1531 | .l2clk(l2clk), |
| 1532 | .pce(l1en), |
| 1533 | .l1clk(l1clk), |
| 1534 | .se(se), |
| 1535 | .pce_ov(pce_ov), |
| 1536 | .stop(stop) |
| 1537 | ); |
| 1538 | |
| 1539 | |
| 1540 | |
| 1541 | endmodule |
| 1542 | |
| 1543 | |
| 1544 | |
| 1545 | |
| 1546 | |
| 1547 | |
| 1548 | |
| 1549 | |
| 1550 | |
| 1551 | // Description: Spare gate macro for control blocks |
| 1552 | // |
| 1553 | // Param num controls the number of times the macro is added |
| 1554 | // flops=0 can be used to use only combination spare logic |
| 1555 | |
| 1556 | |
| 1557 | module sii_ilc_ctlspare_ctl_macro__num_6 ( |
| 1558 | l1clk, |
| 1559 | scan_in, |
| 1560 | siclk, |
| 1561 | soclk, |
| 1562 | scan_out); |
| 1563 | wire si_0; |
| 1564 | wire so_0; |
| 1565 | wire spare0_flop_unused; |
| 1566 | wire spare0_buf_32x_unused; |
| 1567 | wire spare0_nand3_8x_unused; |
| 1568 | wire spare0_inv_8x_unused; |
| 1569 | wire spare0_aoi22_4x_unused; |
| 1570 | wire spare0_buf_8x_unused; |
| 1571 | wire spare0_oai22_4x_unused; |
| 1572 | wire spare0_inv_16x_unused; |
| 1573 | wire spare0_nand2_16x_unused; |
| 1574 | wire spare0_nor3_4x_unused; |
| 1575 | wire spare0_nand2_8x_unused; |
| 1576 | wire spare0_buf_16x_unused; |
| 1577 | wire spare0_nor2_16x_unused; |
| 1578 | wire spare0_inv_32x_unused; |
| 1579 | wire si_1; |
| 1580 | wire so_1; |
| 1581 | wire spare1_flop_unused; |
| 1582 | wire spare1_buf_32x_unused; |
| 1583 | wire spare1_nand3_8x_unused; |
| 1584 | wire spare1_inv_8x_unused; |
| 1585 | wire spare1_aoi22_4x_unused; |
| 1586 | wire spare1_buf_8x_unused; |
| 1587 | wire spare1_oai22_4x_unused; |
| 1588 | wire spare1_inv_16x_unused; |
| 1589 | wire spare1_nand2_16x_unused; |
| 1590 | wire spare1_nor3_4x_unused; |
| 1591 | wire spare1_nand2_8x_unused; |
| 1592 | wire spare1_buf_16x_unused; |
| 1593 | wire spare1_nor2_16x_unused; |
| 1594 | wire spare1_inv_32x_unused; |
| 1595 | wire si_2; |
| 1596 | wire so_2; |
| 1597 | wire spare2_flop_unused; |
| 1598 | wire spare2_buf_32x_unused; |
| 1599 | wire spare2_nand3_8x_unused; |
| 1600 | wire spare2_inv_8x_unused; |
| 1601 | wire spare2_aoi22_4x_unused; |
| 1602 | wire spare2_buf_8x_unused; |
| 1603 | wire spare2_oai22_4x_unused; |
| 1604 | wire spare2_inv_16x_unused; |
| 1605 | wire spare2_nand2_16x_unused; |
| 1606 | wire spare2_nor3_4x_unused; |
| 1607 | wire spare2_nand2_8x_unused; |
| 1608 | wire spare2_buf_16x_unused; |
| 1609 | wire spare2_nor2_16x_unused; |
| 1610 | wire spare2_inv_32x_unused; |
| 1611 | wire si_3; |
| 1612 | wire so_3; |
| 1613 | wire spare3_flop_unused; |
| 1614 | wire spare3_buf_32x_unused; |
| 1615 | wire spare3_nand3_8x_unused; |
| 1616 | wire spare3_inv_8x_unused; |
| 1617 | wire spare3_aoi22_4x_unused; |
| 1618 | wire spare3_buf_8x_unused; |
| 1619 | wire spare3_oai22_4x_unused; |
| 1620 | wire spare3_inv_16x_unused; |
| 1621 | wire spare3_nand2_16x_unused; |
| 1622 | wire spare3_nor3_4x_unused; |
| 1623 | wire spare3_nand2_8x_unused; |
| 1624 | wire spare3_buf_16x_unused; |
| 1625 | wire spare3_nor2_16x_unused; |
| 1626 | wire spare3_inv_32x_unused; |
| 1627 | wire si_4; |
| 1628 | wire so_4; |
| 1629 | wire spare4_flop_unused; |
| 1630 | wire spare4_buf_32x_unused; |
| 1631 | wire spare4_nand3_8x_unused; |
| 1632 | wire spare4_inv_8x_unused; |
| 1633 | wire spare4_aoi22_4x_unused; |
| 1634 | wire spare4_buf_8x_unused; |
| 1635 | wire spare4_oai22_4x_unused; |
| 1636 | wire spare4_inv_16x_unused; |
| 1637 | wire spare4_nand2_16x_unused; |
| 1638 | wire spare4_nor3_4x_unused; |
| 1639 | wire spare4_nand2_8x_unused; |
| 1640 | wire spare4_buf_16x_unused; |
| 1641 | wire spare4_nor2_16x_unused; |
| 1642 | wire spare4_inv_32x_unused; |
| 1643 | wire si_5; |
| 1644 | wire so_5; |
| 1645 | wire spare5_flop_unused; |
| 1646 | wire spare5_buf_32x_unused; |
| 1647 | wire spare5_nand3_8x_unused; |
| 1648 | wire spare5_inv_8x_unused; |
| 1649 | wire spare5_aoi22_4x_unused; |
| 1650 | wire spare5_buf_8x_unused; |
| 1651 | wire spare5_oai22_4x_unused; |
| 1652 | wire spare5_inv_16x_unused; |
| 1653 | wire spare5_nand2_16x_unused; |
| 1654 | wire spare5_nor3_4x_unused; |
| 1655 | wire spare5_nand2_8x_unused; |
| 1656 | wire spare5_buf_16x_unused; |
| 1657 | wire spare5_nor2_16x_unused; |
| 1658 | wire spare5_inv_32x_unused; |
| 1659 | |
| 1660 | |
| 1661 | input l1clk; |
| 1662 | input scan_in; |
| 1663 | input siclk; |
| 1664 | input soclk; |
| 1665 | output scan_out; |
| 1666 | |
| 1667 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), |
| 1668 | .siclk(siclk), |
| 1669 | .soclk(soclk), |
| 1670 | .si(si_0), |
| 1671 | .so(so_0), |
| 1672 | .d(1'b0), |
| 1673 | .q(spare0_flop_unused)); |
| 1674 | assign si_0 = scan_in; |
| 1675 | |
| 1676 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), |
| 1677 | .out(spare0_buf_32x_unused)); |
| 1678 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), |
| 1679 | .in1(1'b1), |
| 1680 | .in2(1'b1), |
| 1681 | .out(spare0_nand3_8x_unused)); |
| 1682 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), |
| 1683 | .out(spare0_inv_8x_unused)); |
| 1684 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), |
| 1685 | .in01(1'b1), |
| 1686 | .in10(1'b1), |
| 1687 | .in11(1'b1), |
| 1688 | .out(spare0_aoi22_4x_unused)); |
| 1689 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), |
| 1690 | .out(spare0_buf_8x_unused)); |
| 1691 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), |
| 1692 | .in01(1'b1), |
| 1693 | .in10(1'b1), |
| 1694 | .in11(1'b1), |
| 1695 | .out(spare0_oai22_4x_unused)); |
| 1696 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), |
| 1697 | .out(spare0_inv_16x_unused)); |
| 1698 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), |
| 1699 | .in1(1'b1), |
| 1700 | .out(spare0_nand2_16x_unused)); |
| 1701 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), |
| 1702 | .in1(1'b0), |
| 1703 | .in2(1'b0), |
| 1704 | .out(spare0_nor3_4x_unused)); |
| 1705 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), |
| 1706 | .in1(1'b1), |
| 1707 | .out(spare0_nand2_8x_unused)); |
| 1708 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), |
| 1709 | .out(spare0_buf_16x_unused)); |
| 1710 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), |
| 1711 | .in1(1'b0), |
| 1712 | .out(spare0_nor2_16x_unused)); |
| 1713 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), |
| 1714 | .out(spare0_inv_32x_unused)); |
| 1715 | |
| 1716 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), |
| 1717 | .siclk(siclk), |
| 1718 | .soclk(soclk), |
| 1719 | .si(si_1), |
| 1720 | .so(so_1), |
| 1721 | .d(1'b0), |
| 1722 | .q(spare1_flop_unused)); |
| 1723 | assign si_1 = so_0; |
| 1724 | |
| 1725 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), |
| 1726 | .out(spare1_buf_32x_unused)); |
| 1727 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), |
| 1728 | .in1(1'b1), |
| 1729 | .in2(1'b1), |
| 1730 | .out(spare1_nand3_8x_unused)); |
| 1731 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), |
| 1732 | .out(spare1_inv_8x_unused)); |
| 1733 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), |
| 1734 | .in01(1'b1), |
| 1735 | .in10(1'b1), |
| 1736 | .in11(1'b1), |
| 1737 | .out(spare1_aoi22_4x_unused)); |
| 1738 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), |
| 1739 | .out(spare1_buf_8x_unused)); |
| 1740 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), |
| 1741 | .in01(1'b1), |
| 1742 | .in10(1'b1), |
| 1743 | .in11(1'b1), |
| 1744 | .out(spare1_oai22_4x_unused)); |
| 1745 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), |
| 1746 | .out(spare1_inv_16x_unused)); |
| 1747 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), |
| 1748 | .in1(1'b1), |
| 1749 | .out(spare1_nand2_16x_unused)); |
| 1750 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), |
| 1751 | .in1(1'b0), |
| 1752 | .in2(1'b0), |
| 1753 | .out(spare1_nor3_4x_unused)); |
| 1754 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), |
| 1755 | .in1(1'b1), |
| 1756 | .out(spare1_nand2_8x_unused)); |
| 1757 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), |
| 1758 | .out(spare1_buf_16x_unused)); |
| 1759 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), |
| 1760 | .in1(1'b0), |
| 1761 | .out(spare1_nor2_16x_unused)); |
| 1762 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), |
| 1763 | .out(spare1_inv_32x_unused)); |
| 1764 | |
| 1765 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), |
| 1766 | .siclk(siclk), |
| 1767 | .soclk(soclk), |
| 1768 | .si(si_2), |
| 1769 | .so(so_2), |
| 1770 | .d(1'b0), |
| 1771 | .q(spare2_flop_unused)); |
| 1772 | assign si_2 = so_1; |
| 1773 | |
| 1774 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), |
| 1775 | .out(spare2_buf_32x_unused)); |
| 1776 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), |
| 1777 | .in1(1'b1), |
| 1778 | .in2(1'b1), |
| 1779 | .out(spare2_nand3_8x_unused)); |
| 1780 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), |
| 1781 | .out(spare2_inv_8x_unused)); |
| 1782 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), |
| 1783 | .in01(1'b1), |
| 1784 | .in10(1'b1), |
| 1785 | .in11(1'b1), |
| 1786 | .out(spare2_aoi22_4x_unused)); |
| 1787 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), |
| 1788 | .out(spare2_buf_8x_unused)); |
| 1789 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), |
| 1790 | .in01(1'b1), |
| 1791 | .in10(1'b1), |
| 1792 | .in11(1'b1), |
| 1793 | .out(spare2_oai22_4x_unused)); |
| 1794 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), |
| 1795 | .out(spare2_inv_16x_unused)); |
| 1796 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), |
| 1797 | .in1(1'b1), |
| 1798 | .out(spare2_nand2_16x_unused)); |
| 1799 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), |
| 1800 | .in1(1'b0), |
| 1801 | .in2(1'b0), |
| 1802 | .out(spare2_nor3_4x_unused)); |
| 1803 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), |
| 1804 | .in1(1'b1), |
| 1805 | .out(spare2_nand2_8x_unused)); |
| 1806 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), |
| 1807 | .out(spare2_buf_16x_unused)); |
| 1808 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), |
| 1809 | .in1(1'b0), |
| 1810 | .out(spare2_nor2_16x_unused)); |
| 1811 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), |
| 1812 | .out(spare2_inv_32x_unused)); |
| 1813 | |
| 1814 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), |
| 1815 | .siclk(siclk), |
| 1816 | .soclk(soclk), |
| 1817 | .si(si_3), |
| 1818 | .so(so_3), |
| 1819 | .d(1'b0), |
| 1820 | .q(spare3_flop_unused)); |
| 1821 | assign si_3 = so_2; |
| 1822 | |
| 1823 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), |
| 1824 | .out(spare3_buf_32x_unused)); |
| 1825 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), |
| 1826 | .in1(1'b1), |
| 1827 | .in2(1'b1), |
| 1828 | .out(spare3_nand3_8x_unused)); |
| 1829 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), |
| 1830 | .out(spare3_inv_8x_unused)); |
| 1831 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), |
| 1832 | .in01(1'b1), |
| 1833 | .in10(1'b1), |
| 1834 | .in11(1'b1), |
| 1835 | .out(spare3_aoi22_4x_unused)); |
| 1836 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), |
| 1837 | .out(spare3_buf_8x_unused)); |
| 1838 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), |
| 1839 | .in01(1'b1), |
| 1840 | .in10(1'b1), |
| 1841 | .in11(1'b1), |
| 1842 | .out(spare3_oai22_4x_unused)); |
| 1843 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), |
| 1844 | .out(spare3_inv_16x_unused)); |
| 1845 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), |
| 1846 | .in1(1'b1), |
| 1847 | .out(spare3_nand2_16x_unused)); |
| 1848 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), |
| 1849 | .in1(1'b0), |
| 1850 | .in2(1'b0), |
| 1851 | .out(spare3_nor3_4x_unused)); |
| 1852 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), |
| 1853 | .in1(1'b1), |
| 1854 | .out(spare3_nand2_8x_unused)); |
| 1855 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), |
| 1856 | .out(spare3_buf_16x_unused)); |
| 1857 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), |
| 1858 | .in1(1'b0), |
| 1859 | .out(spare3_nor2_16x_unused)); |
| 1860 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), |
| 1861 | .out(spare3_inv_32x_unused)); |
| 1862 | |
| 1863 | cl_sc1_msff_8x spare4_flop (.l1clk(l1clk), |
| 1864 | .siclk(siclk), |
| 1865 | .soclk(soclk), |
| 1866 | .si(si_4), |
| 1867 | .so(so_4), |
| 1868 | .d(1'b0), |
| 1869 | .q(spare4_flop_unused)); |
| 1870 | assign si_4 = so_3; |
| 1871 | |
| 1872 | cl_u1_buf_32x spare4_buf_32x (.in(1'b1), |
| 1873 | .out(spare4_buf_32x_unused)); |
| 1874 | cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1), |
| 1875 | .in1(1'b1), |
| 1876 | .in2(1'b1), |
| 1877 | .out(spare4_nand3_8x_unused)); |
| 1878 | cl_u1_inv_8x spare4_inv_8x (.in(1'b1), |
| 1879 | .out(spare4_inv_8x_unused)); |
| 1880 | cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1), |
| 1881 | .in01(1'b1), |
| 1882 | .in10(1'b1), |
| 1883 | .in11(1'b1), |
| 1884 | .out(spare4_aoi22_4x_unused)); |
| 1885 | cl_u1_buf_8x spare4_buf_8x (.in(1'b1), |
| 1886 | .out(spare4_buf_8x_unused)); |
| 1887 | cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1), |
| 1888 | .in01(1'b1), |
| 1889 | .in10(1'b1), |
| 1890 | .in11(1'b1), |
| 1891 | .out(spare4_oai22_4x_unused)); |
| 1892 | cl_u1_inv_16x spare4_inv_16x (.in(1'b1), |
| 1893 | .out(spare4_inv_16x_unused)); |
| 1894 | cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1), |
| 1895 | .in1(1'b1), |
| 1896 | .out(spare4_nand2_16x_unused)); |
| 1897 | cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0), |
| 1898 | .in1(1'b0), |
| 1899 | .in2(1'b0), |
| 1900 | .out(spare4_nor3_4x_unused)); |
| 1901 | cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1), |
| 1902 | .in1(1'b1), |
| 1903 | .out(spare4_nand2_8x_unused)); |
| 1904 | cl_u1_buf_16x spare4_buf_16x (.in(1'b1), |
| 1905 | .out(spare4_buf_16x_unused)); |
| 1906 | cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0), |
| 1907 | .in1(1'b0), |
| 1908 | .out(spare4_nor2_16x_unused)); |
| 1909 | cl_u1_inv_32x spare4_inv_32x (.in(1'b1), |
| 1910 | .out(spare4_inv_32x_unused)); |
| 1911 | |
| 1912 | cl_sc1_msff_8x spare5_flop (.l1clk(l1clk), |
| 1913 | .siclk(siclk), |
| 1914 | .soclk(soclk), |
| 1915 | .si(si_5), |
| 1916 | .so(so_5), |
| 1917 | .d(1'b0), |
| 1918 | .q(spare5_flop_unused)); |
| 1919 | assign si_5 = so_4; |
| 1920 | |
| 1921 | cl_u1_buf_32x spare5_buf_32x (.in(1'b1), |
| 1922 | .out(spare5_buf_32x_unused)); |
| 1923 | cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1), |
| 1924 | .in1(1'b1), |
| 1925 | .in2(1'b1), |
| 1926 | .out(spare5_nand3_8x_unused)); |
| 1927 | cl_u1_inv_8x spare5_inv_8x (.in(1'b1), |
| 1928 | .out(spare5_inv_8x_unused)); |
| 1929 | cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1), |
| 1930 | .in01(1'b1), |
| 1931 | .in10(1'b1), |
| 1932 | .in11(1'b1), |
| 1933 | .out(spare5_aoi22_4x_unused)); |
| 1934 | cl_u1_buf_8x spare5_buf_8x (.in(1'b1), |
| 1935 | .out(spare5_buf_8x_unused)); |
| 1936 | cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1), |
| 1937 | .in01(1'b1), |
| 1938 | .in10(1'b1), |
| 1939 | .in11(1'b1), |
| 1940 | .out(spare5_oai22_4x_unused)); |
| 1941 | cl_u1_inv_16x spare5_inv_16x (.in(1'b1), |
| 1942 | .out(spare5_inv_16x_unused)); |
| 1943 | cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1), |
| 1944 | .in1(1'b1), |
| 1945 | .out(spare5_nand2_16x_unused)); |
| 1946 | cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0), |
| 1947 | .in1(1'b0), |
| 1948 | .in2(1'b0), |
| 1949 | .out(spare5_nor3_4x_unused)); |
| 1950 | cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1), |
| 1951 | .in1(1'b1), |
| 1952 | .out(spare5_nand2_8x_unused)); |
| 1953 | cl_u1_buf_16x spare5_buf_16x (.in(1'b1), |
| 1954 | .out(spare5_buf_16x_unused)); |
| 1955 | cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0), |
| 1956 | .in1(1'b0), |
| 1957 | .out(spare5_nor2_16x_unused)); |
| 1958 | cl_u1_inv_32x spare5_inv_32x (.in(1'b1), |
| 1959 | .out(spare5_inv_32x_unused)); |
| 1960 | assign scan_out = so_5; |
| 1961 | |
| 1962 | |
| 1963 | |
| 1964 | endmodule |
| 1965 | |
| 1966 | |
| 1967 | |
| 1968 | |
| 1969 | |
| 1970 | |
| 1971 | // any PARAMS parms go into naming of macro |
| 1972 | |
| 1973 | module sii_ilc_ctlmsff_ctl_macro__width_5 ( |
| 1974 | din, |
| 1975 | l1clk, |
| 1976 | scan_in, |
| 1977 | siclk, |
| 1978 | soclk, |
| 1979 | dout, |
| 1980 | scan_out); |
| 1981 | wire [4:0] fdin; |
| 1982 | wire [3:0] so; |
| 1983 | |
| 1984 | input [4:0] din; |
| 1985 | input l1clk; |
| 1986 | input scan_in; |
| 1987 | |
| 1988 | |
| 1989 | input siclk; |
| 1990 | input soclk; |
| 1991 | |
| 1992 | output [4:0] dout; |
| 1993 | output scan_out; |
| 1994 | assign fdin[4:0] = din[4:0]; |
| 1995 | |
| 1996 | |
| 1997 | |
| 1998 | |
| 1999 | |
| 2000 | |
| 2001 | dff #(5) d0_0 ( |
| 2002 | .l1clk(l1clk), |
| 2003 | .siclk(siclk), |
| 2004 | .soclk(soclk), |
| 2005 | .d(fdin[4:0]), |
| 2006 | .si({scan_in,so[3:0]}), |
| 2007 | .so({so[3:0],scan_out}), |
| 2008 | .q(dout[4:0]) |
| 2009 | ); |
| 2010 | |
| 2011 | |
| 2012 | |
| 2013 | |
| 2014 | |
| 2015 | |
| 2016 | |
| 2017 | |
| 2018 | |
| 2019 | |
| 2020 | |
| 2021 | |
| 2022 | endmodule |
| 2023 | |
| 2024 | |
| 2025 | |
| 2026 | |
| 2027 | |
| 2028 | |
| 2029 | |
| 2030 | |
| 2031 | |
| 2032 | |
| 2033 | |
| 2034 | |
| 2035 | |
| 2036 | // any PARAMS parms go into naming of macro |
| 2037 | |
| 2038 | module sii_ilc_ctlmsff_ctl_macro__width_1 ( |
| 2039 | din, |
| 2040 | l1clk, |
| 2041 | scan_in, |
| 2042 | siclk, |
| 2043 | soclk, |
| 2044 | dout, |
| 2045 | scan_out); |
| 2046 | wire [0:0] fdin; |
| 2047 | |
| 2048 | input [0:0] din; |
| 2049 | input l1clk; |
| 2050 | input scan_in; |
| 2051 | |
| 2052 | |
| 2053 | input siclk; |
| 2054 | input soclk; |
| 2055 | |
| 2056 | output [0:0] dout; |
| 2057 | output scan_out; |
| 2058 | assign fdin[0:0] = din[0:0]; |
| 2059 | |
| 2060 | |
| 2061 | |
| 2062 | |
| 2063 | |
| 2064 | |
| 2065 | dff #(1) d0_0 ( |
| 2066 | .l1clk(l1clk), |
| 2067 | .siclk(siclk), |
| 2068 | .soclk(soclk), |
| 2069 | .d(fdin[0:0]), |
| 2070 | .si(scan_in), |
| 2071 | .so(scan_out), |
| 2072 | .q(dout[0:0]) |
| 2073 | ); |
| 2074 | |
| 2075 | |
| 2076 | |
| 2077 | |
| 2078 | |
| 2079 | |
| 2080 | |
| 2081 | |
| 2082 | |
| 2083 | |
| 2084 | |
| 2085 | |
| 2086 | endmodule |
| 2087 | |
| 2088 | |
| 2089 | |
| 2090 | |
| 2091 | |
| 2092 | |
| 2093 | |
| 2094 | |
| 2095 | |
| 2096 | |
| 2097 | |
| 2098 | |
| 2099 | |
| 2100 | // any PARAMS parms go into naming of macro |
| 2101 | |
| 2102 | module sii_ilc_ctlmsff_ctl_macro__width_2 ( |
| 2103 | din, |
| 2104 | l1clk, |
| 2105 | scan_in, |
| 2106 | siclk, |
| 2107 | soclk, |
| 2108 | dout, |
| 2109 | scan_out); |
| 2110 | wire [1:0] fdin; |
| 2111 | wire [0:0] so; |
| 2112 | |
| 2113 | input [1:0] din; |
| 2114 | input l1clk; |
| 2115 | input scan_in; |
| 2116 | |
| 2117 | |
| 2118 | input siclk; |
| 2119 | input soclk; |
| 2120 | |
| 2121 | output [1:0] dout; |
| 2122 | output scan_out; |
| 2123 | assign fdin[1:0] = din[1:0]; |
| 2124 | |
| 2125 | |
| 2126 | |
| 2127 | |
| 2128 | |
| 2129 | |
| 2130 | dff #(2) d0_0 ( |
| 2131 | .l1clk(l1clk), |
| 2132 | .siclk(siclk), |
| 2133 | .soclk(soclk), |
| 2134 | .d(fdin[1:0]), |
| 2135 | .si({scan_in,so[0:0]}), |
| 2136 | .so({so[0:0],scan_out}), |
| 2137 | .q(dout[1:0]) |
| 2138 | ); |
| 2139 | |
| 2140 | |
| 2141 | |
| 2142 | |
| 2143 | |
| 2144 | |
| 2145 | |
| 2146 | |
| 2147 | |
| 2148 | |
| 2149 | |
| 2150 | |
| 2151 | endmodule |
| 2152 | |
| 2153 | |
| 2154 | |
| 2155 | |
| 2156 | |
| 2157 | |
| 2158 | |
| 2159 | |
| 2160 | |
| 2161 | |
| 2162 | |
| 2163 | |
| 2164 | |
| 2165 | // any PARAMS parms go into naming of macro |
| 2166 | |
| 2167 | module sii_ilc_ctlmsff_ctl_macro__width_6 ( |
| 2168 | din, |
| 2169 | l1clk, |
| 2170 | scan_in, |
| 2171 | siclk, |
| 2172 | soclk, |
| 2173 | dout, |
| 2174 | scan_out); |
| 2175 | wire [5:0] fdin; |
| 2176 | wire [4:0] so; |
| 2177 | |
| 2178 | input [5:0] din; |
| 2179 | input l1clk; |
| 2180 | input scan_in; |
| 2181 | |
| 2182 | |
| 2183 | input siclk; |
| 2184 | input soclk; |
| 2185 | |
| 2186 | output [5:0] dout; |
| 2187 | output scan_out; |
| 2188 | assign fdin[5:0] = din[5:0]; |
| 2189 | |
| 2190 | |
| 2191 | |
| 2192 | |
| 2193 | |
| 2194 | |
| 2195 | dff #(6) d0_0 ( |
| 2196 | .l1clk(l1clk), |
| 2197 | .siclk(siclk), |
| 2198 | .soclk(soclk), |
| 2199 | .d(fdin[5:0]), |
| 2200 | .si({scan_in,so[4:0]}), |
| 2201 | .so({so[4:0],scan_out}), |
| 2202 | .q(dout[5:0]) |
| 2203 | ); |
| 2204 | |
| 2205 | |
| 2206 | |
| 2207 | |
| 2208 | |
| 2209 | |
| 2210 | |
| 2211 | |
| 2212 | |
| 2213 | |
| 2214 | |
| 2215 | |
| 2216 | endmodule |
| 2217 | |
| 2218 | |
| 2219 | |
| 2220 | |
| 2221 | |
| 2222 | |
| 2223 | |
| 2224 | |
| 2225 | |
| 2226 | |
| 2227 | |
| 2228 | |
| 2229 | |
| 2230 | // any PARAMS parms go into naming of macro |
| 2231 | |
| 2232 | module sii_ilc_ctlmsff_ctl_macro__width_3 ( |
| 2233 | din, |
| 2234 | l1clk, |
| 2235 | scan_in, |
| 2236 | siclk, |
| 2237 | soclk, |
| 2238 | dout, |
| 2239 | scan_out); |
| 2240 | wire [2:0] fdin; |
| 2241 | wire [1:0] so; |
| 2242 | |
| 2243 | input [2:0] din; |
| 2244 | input l1clk; |
| 2245 | input scan_in; |
| 2246 | |
| 2247 | |
| 2248 | input siclk; |
| 2249 | input soclk; |
| 2250 | |
| 2251 | output [2:0] dout; |
| 2252 | output scan_out; |
| 2253 | assign fdin[2:0] = din[2:0]; |
| 2254 | |
| 2255 | |
| 2256 | |
| 2257 | |
| 2258 | |
| 2259 | |
| 2260 | dff #(3) d0_0 ( |
| 2261 | .l1clk(l1clk), |
| 2262 | .siclk(siclk), |
| 2263 | .soclk(soclk), |
| 2264 | .d(fdin[2:0]), |
| 2265 | .si({scan_in,so[1:0]}), |
| 2266 | .so({so[1:0],scan_out}), |
| 2267 | .q(dout[2:0]) |
| 2268 | ); |
| 2269 | |
| 2270 | |
| 2271 | |
| 2272 | |
| 2273 | |
| 2274 | |
| 2275 | |
| 2276 | |
| 2277 | |
| 2278 | |
| 2279 | |
| 2280 | |
| 2281 | endmodule |
| 2282 | |
| 2283 | |
| 2284 | |
| 2285 | |
| 2286 | |
| 2287 | |
| 2288 | |
| 2289 | |
| 2290 | |
| 2291 | |
| 2292 | |
| 2293 | |
| 2294 | |
| 2295 | // any PARAMS parms go into naming of macro |
| 2296 | |
| 2297 | module sii_ilc_ctlmsff_ctl_macro__width_4 ( |
| 2298 | din, |
| 2299 | l1clk, |
| 2300 | scan_in, |
| 2301 | siclk, |
| 2302 | soclk, |
| 2303 | dout, |
| 2304 | scan_out); |
| 2305 | wire [3:0] fdin; |
| 2306 | wire [2:0] so; |
| 2307 | |
| 2308 | input [3:0] din; |
| 2309 | input l1clk; |
| 2310 | input scan_in; |
| 2311 | |
| 2312 | |
| 2313 | input siclk; |
| 2314 | input soclk; |
| 2315 | |
| 2316 | output [3:0] dout; |
| 2317 | output scan_out; |
| 2318 | assign fdin[3:0] = din[3:0]; |
| 2319 | |
| 2320 | |
| 2321 | |
| 2322 | |
| 2323 | |
| 2324 | |
| 2325 | dff #(4) d0_0 ( |
| 2326 | .l1clk(l1clk), |
| 2327 | .siclk(siclk), |
| 2328 | .soclk(soclk), |
| 2329 | .d(fdin[3:0]), |
| 2330 | .si({scan_in,so[2:0]}), |
| 2331 | .so({so[2:0],scan_out}), |
| 2332 | .q(dout[3:0]) |
| 2333 | ); |
| 2334 | |
| 2335 | |
| 2336 | |
| 2337 | |
| 2338 | |
| 2339 | |
| 2340 | |
| 2341 | |
| 2342 | |
| 2343 | |
| 2344 | |
| 2345 | |
| 2346 | endmodule |
| 2347 | |
| 2348 | |
| 2349 | |
| 2350 | |
| 2351 | |
| 2352 | |
| 2353 | |
| 2354 | |
| 2355 | |
| 2356 | |
| 2357 | |
| 2358 | |
| 2359 | |
| 2360 | // any PARAMS parms go into naming of macro |
| 2361 | |
| 2362 | module sii_ilc_ctlmsff_ctl_macro__en_1__width_8 ( |
| 2363 | din, |
| 2364 | en, |
| 2365 | l1clk, |
| 2366 | scan_in, |
| 2367 | siclk, |
| 2368 | soclk, |
| 2369 | dout, |
| 2370 | scan_out); |
| 2371 | wire [7:0] fdin; |
| 2372 | wire [6:0] so; |
| 2373 | |
| 2374 | input [7:0] din; |
| 2375 | input en; |
| 2376 | input l1clk; |
| 2377 | input scan_in; |
| 2378 | |
| 2379 | |
| 2380 | input siclk; |
| 2381 | input soclk; |
| 2382 | |
| 2383 | output [7:0] dout; |
| 2384 | output scan_out; |
| 2385 | assign fdin[7:0] = (din[7:0] & {8{en}}) | (dout[7:0] & ~{8{en}}); |
| 2386 | |
| 2387 | |
| 2388 | |
| 2389 | |
| 2390 | |
| 2391 | |
| 2392 | dff #(8) d0_0 ( |
| 2393 | .l1clk(l1clk), |
| 2394 | .siclk(siclk), |
| 2395 | .soclk(soclk), |
| 2396 | .d(fdin[7:0]), |
| 2397 | .si({scan_in,so[6:0]}), |
| 2398 | .so({so[6:0],scan_out}), |
| 2399 | .q(dout[7:0]) |
| 2400 | ); |
| 2401 | |
| 2402 | |
| 2403 | |
| 2404 | |
| 2405 | |
| 2406 | |
| 2407 | |
| 2408 | |
| 2409 | |
| 2410 | |
| 2411 | |
| 2412 | |
| 2413 | endmodule |
| 2414 | |
| 2415 | |
| 2416 | |
| 2417 | |
| 2418 | |
| 2419 | |
| 2420 | |
| 2421 | |