| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: sii_mb0_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module sii_mb0_ctl ( |
| 36 | sii_mb0_run, |
| 37 | sii_mb0_addr, |
| 38 | sii_mb0_wdata, |
| 39 | sii_mb0_wr_en, |
| 40 | sii_mb0_rd_en, |
| 41 | sii_mb0_ind_wr_en, |
| 42 | sii_mb0_ind_rd_en, |
| 43 | sii_mb0_done, |
| 44 | sii_mb0_fail, |
| 45 | scan_out, |
| 46 | l2clk, |
| 47 | tcu_scan_en, |
| 48 | scan_in, |
| 49 | tcu_aclk, |
| 50 | tcu_bclk, |
| 51 | tcu_pce_ov, |
| 52 | tcu_clk_stop, |
| 53 | tcu_sii_mb0_start, |
| 54 | sii_mb0_bisi_mode, |
| 55 | sii_mb0_user_mode, |
| 56 | sii_mb0_ild0_fail, |
| 57 | sii_mb0_ild1_fail, |
| 58 | sii_mb0_ild2_fail, |
| 59 | sii_mb0_ild3_fail, |
| 60 | sii_mb0_ild4_fail, |
| 61 | sii_mb0_ild5_fail, |
| 62 | sii_mb0_ild6_fail, |
| 63 | sii_mb0_ild7_fail, |
| 64 | sii_mb0_ind_fail); |
| 65 | wire se; |
| 66 | wire siclk; |
| 67 | wire soclk; |
| 68 | wire pce_ov; |
| 69 | wire stop; |
| 70 | wire l1clk; |
| 71 | wire config_reg_scanin; |
| 72 | wire config_reg_scanout; |
| 73 | wire [7:0] config_in; |
| 74 | wire [7:0] config_out; |
| 75 | wire start_transition; |
| 76 | wire reset_engine; |
| 77 | wire mbist_user_loop_mode; |
| 78 | wire mbist_done; |
| 79 | wire run; |
| 80 | wire bisi; |
| 81 | wire user_mode; |
| 82 | wire user_data_mode; |
| 83 | wire user_addr_mode; |
| 84 | wire user_loop_mode; |
| 85 | wire ten_n_mode; |
| 86 | wire mbist_user_data_mode; |
| 87 | wire mbist_user_addr_mode; |
| 88 | wire mbist_ten_n_mode; |
| 89 | wire user_data_reg_scanin; |
| 90 | wire user_data_reg_scanout; |
| 91 | wire [7:0] user_data_in; |
| 92 | wire [7:0] user_data_out; |
| 93 | wire user_start_addr_reg_scanin; |
| 94 | wire user_start_addr_reg_scanout; |
| 95 | wire [5:0] user_start_addr_in; |
| 96 | wire [5:0] user_start_addr; |
| 97 | wire user_stop_addr_reg_scanin; |
| 98 | wire user_stop_addr_reg_scanout; |
| 99 | wire [5:0] user_stop_addr_in; |
| 100 | wire [5:0] user_stop_addr; |
| 101 | wire user_incr_addr_reg_scanin; |
| 102 | wire user_incr_addr_reg_scanout; |
| 103 | wire [5:0] user_incr_addr_in; |
| 104 | wire [5:0] user_incr_addr; |
| 105 | wire run_reg_scanin; |
| 106 | wire run_reg_scanout; |
| 107 | wire user_bisi_wr_reg_scanin; |
| 108 | wire user_bisi_wr_reg_scanout; |
| 109 | wire user_bisi_wr_mode_in; |
| 110 | wire user_bisi_wr_mode; |
| 111 | wire user_bisi_rd_reg_scanin; |
| 112 | wire user_bisi_rd_reg_scanout; |
| 113 | wire user_bisi_rd_mode_in; |
| 114 | wire user_bisi_rd_mode; |
| 115 | wire mbist_user_bisi_wr_mode; |
| 116 | wire mbist_user_bisi_wr_rd_mode; |
| 117 | wire start_transition_reg_scanin; |
| 118 | wire start_transition_reg_scanout; |
| 119 | wire start_transition_piped; |
| 120 | wire run1_reg_scanin; |
| 121 | wire run1_reg_scanout; |
| 122 | wire run1_in; |
| 123 | wire run1_out; |
| 124 | wire run2_reg_scanin; |
| 125 | wire run2_reg_scanout; |
| 126 | wire run2_in; |
| 127 | wire run2_out; |
| 128 | wire run_piped3; |
| 129 | wire msb; |
| 130 | wire addr_reg_scanin; |
| 131 | wire addr_reg_scanout; |
| 132 | wire [5:0] mbist_address; |
| 133 | wire wdata_reg_scanin; |
| 134 | wire wdata_reg_scanout; |
| 135 | wire [7:0] mbist_wdata; |
| 136 | wire rd_wr_en_reg_scanin; |
| 137 | wire rd_wr_en_reg_scanout; |
| 138 | wire mbist_ind_wr_en; |
| 139 | wire mbist_ind_rd_en; |
| 140 | wire ild_rd_wr_en_reg_scanin; |
| 141 | wire ild_rd_wr_en_reg_scanout; |
| 142 | wire mbist_ild_wr_en; |
| 143 | wire mbist_ild_rd_en; |
| 144 | wire sii_mb0_fail_reg_scanin; |
| 145 | wire sii_mb0_fail_reg_scanout; |
| 146 | wire fail; |
| 147 | wire sii_mb0_done_reg_scanin; |
| 148 | wire sii_mb0_done_reg_scanout; |
| 149 | wire control_reg_scanin; |
| 150 | wire control_reg_scanout; |
| 151 | wire [17:0] control_in; |
| 152 | wire [17:0] control_out; |
| 153 | wire bisi_wr_rd; |
| 154 | wire [1:0] data_control; |
| 155 | wire address_mix; |
| 156 | wire [3:0] march_element; |
| 157 | wire [5:0] array_address; |
| 158 | wire upaddress_march; |
| 159 | wire [2:0] read_write_control; |
| 160 | wire five_cycle_march; |
| 161 | wire one_cycle_march; |
| 162 | wire increment_addr; |
| 163 | wire [5:0] start_addr; |
| 164 | wire [5:0] next_array_address; |
| 165 | wire next_upaddr_march; |
| 166 | wire next_downaddr_march; |
| 167 | wire [5:0] stop_addr; |
| 168 | wire [6:0] overflow_addr; |
| 169 | wire [5:0] incr_addr; |
| 170 | wire overflow; |
| 171 | wire [6:0] compare_addr; |
| 172 | wire [5:0] add; |
| 173 | wire [5:0] adj_address; |
| 174 | wire increment_march_elem; |
| 175 | wire [1:0] next_data_control; |
| 176 | wire next_address_mix; |
| 177 | wire [3:0] next_march_element; |
| 178 | wire array_write; |
| 179 | wire array_read; |
| 180 | wire true_data; |
| 181 | wire [7:0] data_pattern; |
| 182 | wire done_counter_reg_scanin; |
| 183 | wire done_counter_reg_scanout; |
| 184 | wire [2:0] done_counter_in; |
| 185 | wire [2:0] done_counter_out; |
| 186 | wire ind_ren_pipe_reg1_scanin; |
| 187 | wire ind_ren_pipe_reg1_scanout; |
| 188 | wire ind_ren_pipe_reg1_in; |
| 189 | wire ind_ren_pipe_out1; |
| 190 | wire ind_ren_pipe_reg2_scanin; |
| 191 | wire ind_ren_pipe_reg2_scanout; |
| 192 | wire ind_ren_pipe_reg2_in; |
| 193 | wire ind_ren_pipe_out2; |
| 194 | wire ind_ren_pipe_reg3_scanin; |
| 195 | wire ind_ren_pipe_reg3_scanout; |
| 196 | wire ind_ren_pipe_reg3_in; |
| 197 | wire ind_ren_pipe_out3; |
| 198 | wire ind_ren_pipe_reg4_scanin; |
| 199 | wire ind_ren_pipe_reg4_scanout; |
| 200 | wire ind_ren_pipe_reg4_in; |
| 201 | wire ind_ren_pipe_out4; |
| 202 | wire ind_ren_pipe_reg5_scanin; |
| 203 | wire ind_ren_pipe_reg5_scanout; |
| 204 | wire ind_ren_pipe_reg5_in; |
| 205 | wire ind_ren_pipe_out5; |
| 206 | wire sii_piped_ind_ren; |
| 207 | wire ild_ren_pipe_reg1_scanin; |
| 208 | wire ild_ren_pipe_reg1_scanout; |
| 209 | wire ild_ren_pipe_reg1_in; |
| 210 | wire ild_ren_pipe_out1; |
| 211 | wire ild_ren_pipe_reg2_scanin; |
| 212 | wire ild_ren_pipe_reg2_scanout; |
| 213 | wire ild_ren_pipe_reg2_in; |
| 214 | wire ild_ren_pipe_out2; |
| 215 | wire ild_ren_pipe_reg3_scanin; |
| 216 | wire ild_ren_pipe_reg3_scanout; |
| 217 | wire ild_ren_pipe_reg3_in; |
| 218 | wire ild_ren_pipe_out3; |
| 219 | wire ild_ren_pipe_reg4_scanin; |
| 220 | wire ild_ren_pipe_reg4_scanout; |
| 221 | wire ild_ren_pipe_reg4_in; |
| 222 | wire ild_ren_pipe_out4; |
| 223 | wire ild_ren_pipe_reg5_scanin; |
| 224 | wire ild_ren_pipe_reg5_scanout; |
| 225 | wire ild_ren_pipe_reg5_in; |
| 226 | wire ild_ren_pipe_out5; |
| 227 | wire sii_mb0_ild_rd_en; |
| 228 | wire sii_piped_ild_ren; |
| 229 | wire ild0_fail_reg_scanin; |
| 230 | wire ild0_fail_reg_scanout; |
| 231 | wire [1:0] sii_mb0_ild0_fail_piped; |
| 232 | wire ild1_fail_reg_scanin; |
| 233 | wire ild1_fail_reg_scanout; |
| 234 | wire [1:0] sii_mb0_ild1_fail_piped; |
| 235 | wire ild2_fail_reg_scanin; |
| 236 | wire ild2_fail_reg_scanout; |
| 237 | wire [1:0] sii_mb0_ild2_fail_piped; |
| 238 | wire ild3_fail_reg_scanin; |
| 239 | wire ild3_fail_reg_scanout; |
| 240 | wire [1:0] sii_mb0_ild3_fail_piped; |
| 241 | wire ild4_fail_reg_scanin; |
| 242 | wire ild4_fail_reg_scanout; |
| 243 | wire [1:0] sii_mb0_ild4_fail_piped; |
| 244 | wire ild5_fail_reg_scanin; |
| 245 | wire ild5_fail_reg_scanout; |
| 246 | wire [1:0] sii_mb0_ild5_fail_piped; |
| 247 | wire ild6_fail_reg_scanin; |
| 248 | wire ild6_fail_reg_scanout; |
| 249 | wire [1:0] sii_mb0_ild6_fail_piped; |
| 250 | wire ild7_fail_reg_scanin; |
| 251 | wire ild7_fail_reg_scanout; |
| 252 | wire [1:0] sii_mb0_ild7_fail_piped; |
| 253 | wire ind_fail_reg_scanin; |
| 254 | wire ind_fail_reg_scanout; |
| 255 | wire [1:0] sii_mb0_ind_fail_piped; |
| 256 | wire spares_scanin; |
| 257 | wire spares_scanout; |
| 258 | wire fail_reg_scanin; |
| 259 | wire fail_reg_scanout; |
| 260 | wire [17:0] fail_reg_in; |
| 261 | wire [17:0] fail_reg_out; |
| 262 | wire [1:0] qual_sii_ind_fail; |
| 263 | wire [1:0] qual_sii_ild7_fail; |
| 264 | wire [1:0] qual_sii_ild6_fail; |
| 265 | wire [1:0] qual_sii_ild5_fail; |
| 266 | wire [1:0] qual_sii_ild4_fail; |
| 267 | wire [1:0] qual_sii_ild3_fail; |
| 268 | wire [1:0] qual_sii_ild2_fail; |
| 269 | wire [1:0] qual_sii_ild1_fail; |
| 270 | wire [1:0] qual_sii_ild0_fail; |
| 271 | |
| 272 | |
| 273 | |
| 274 | output sii_mb0_run; |
| 275 | |
| 276 | output [5:0] sii_mb0_addr; |
| 277 | output [7:0] sii_mb0_wdata; |
| 278 | |
| 279 | output sii_mb0_wr_en; //ild_wr_en |
| 280 | output sii_mb0_rd_en; //ild_rd_en |
| 281 | |
| 282 | output sii_mb0_ind_wr_en; |
| 283 | output sii_mb0_ind_rd_en; |
| 284 | |
| 285 | |
| 286 | output sii_mb0_done; |
| 287 | output sii_mb0_fail; |
| 288 | output scan_out; |
| 289 | |
| 290 | input l2clk; |
| 291 | input tcu_scan_en; |
| 292 | input scan_in; |
| 293 | input tcu_aclk; |
| 294 | input tcu_bclk; |
| 295 | input tcu_pce_ov; |
| 296 | input tcu_clk_stop; |
| 297 | |
| 298 | input tcu_sii_mb0_start; |
| 299 | input sii_mb0_bisi_mode; |
| 300 | input sii_mb0_user_mode; |
| 301 | |
| 302 | // input [63:0] read_data; |
| 303 | input [1:0] sii_mb0_ild0_fail; |
| 304 | input [1:0] sii_mb0_ild1_fail; |
| 305 | input [1:0] sii_mb0_ild2_fail; |
| 306 | input [1:0] sii_mb0_ild3_fail; |
| 307 | input [1:0] sii_mb0_ild4_fail; |
| 308 | input [1:0] sii_mb0_ild5_fail; |
| 309 | input [1:0] sii_mb0_ild6_fail; |
| 310 | input [1:0] sii_mb0_ild7_fail; |
| 311 | |
| 312 | input [1:0] sii_mb0_ind_fail; |
| 313 | |
| 314 | /////////////////////////////////////// |
| 315 | // Scan chain connections |
| 316 | /////////////////////////////////////// |
| 317 | // scan renames |
| 318 | assign se = tcu_scan_en; |
| 319 | assign siclk = tcu_aclk; |
| 320 | assign soclk = tcu_bclk; |
| 321 | assign pce_ov = tcu_pce_ov; |
| 322 | assign stop = tcu_clk_stop; |
| 323 | // end scan |
| 324 | |
| 325 | sii_mb0_ctll1clkhdr_ctl_macro clkgen ( |
| 326 | .l2clk (l2clk ), |
| 327 | .l1en (1'b1 ), |
| 328 | .l1clk (l1clk), |
| 329 | .pce_ov(pce_ov), |
| 330 | .stop(stop), |
| 331 | .se(se) |
| 332 | ); |
| 333 | |
| 334 | |
| 335 | // ///////////////////////////////////////////////////////////////////////////// |
| 336 | // |
| 337 | // MBIST Config Register |
| 338 | // |
| 339 | // ///////////////////////////////////////////////////////////////////////////// |
| 340 | // |
| 341 | // A low to high transition on mbist_start will reset and start the engine. |
| 342 | // mbist_start must remain active high for the duration of MBIST. |
| 343 | // If mbist_start deasserts the engine will stop but not reset. |
| 344 | // Once MBIST has completed mbist_done will assert and the fail status |
| 345 | // signals will be valid. |
| 346 | // To run MBIST again the mbist_start signal must transition low then high. |
| 347 | // |
| 348 | // Loop on Address will disable the address mix function. |
| 349 | // |
| 350 | // ///////////////////////////////////////////////////////////////////////////// |
| 351 | |
| 352 | sii_mb0_ctlmsff_ctl_macro__width_8 config_reg ( |
| 353 | .scan_in(config_reg_scanin), |
| 354 | .scan_out(config_reg_scanout), |
| 355 | .din ( config_in[7:0] ), |
| 356 | .dout ( config_out[7:0] ), |
| 357 | .l1clk(l1clk), |
| 358 | .siclk(siclk), |
| 359 | .soclk(soclk)); |
| 360 | |
| 361 | |
| 362 | |
| 363 | assign config_in[0] = tcu_sii_mb0_start; |
| 364 | assign config_in[1] = config_out[0]; |
| 365 | assign start_transition = config_out[0] & ~config_out[1]; |
| 366 | assign reset_engine = start_transition | (mbist_user_loop_mode & mbist_done); |
| 367 | // assign run = config_out[1] & (mbist_user_loop_mode | ~mbist_done); |
| 368 | assign run = config_out[0] & config_out[1]; // 9/13/05 run to follow start only! |
| 369 | |
| 370 | assign config_in[2] = start_transition ? sii_mb0_bisi_mode: config_out[2]; |
| 371 | assign bisi = config_out[2]; |
| 372 | |
| 373 | assign config_in[3] = start_transition ? sii_mb0_user_mode: config_out[3]; |
| 374 | assign user_mode = config_out[3]; |
| 375 | |
| 376 | assign config_in[4] = config_out[4]; |
| 377 | assign user_data_mode = config_out[4]; |
| 378 | |
| 379 | assign config_in[5] = config_out[5]; |
| 380 | assign user_addr_mode = config_out[5]; |
| 381 | |
| 382 | assign config_in[6] = config_out[6]; |
| 383 | assign user_loop_mode = config_out[6]; |
| 384 | |
| 385 | assign config_in[7] = config_out[7]; |
| 386 | assign ten_n_mode = config_out[7]; |
| 387 | |
| 388 | |
| 389 | assign mbist_user_data_mode = user_mode & user_data_mode; |
| 390 | assign mbist_user_addr_mode = user_mode & user_addr_mode; |
| 391 | assign mbist_user_loop_mode = user_mode & user_loop_mode; |
| 392 | assign mbist_ten_n_mode = user_mode & ten_n_mode; |
| 393 | |
| 394 | |
| 395 | sii_mb0_ctlmsff_ctl_macro__width_8 user_data_reg ( |
| 396 | .scan_in(user_data_reg_scanin), |
| 397 | .scan_out(user_data_reg_scanout), |
| 398 | .din ( user_data_in[7:0] ), |
| 399 | .dout ( user_data_out[7:0] ), |
| 400 | .l1clk(l1clk), |
| 401 | .siclk(siclk), |
| 402 | .soclk(soclk)); |
| 403 | |
| 404 | |
| 405 | assign user_data_in[7:0] = user_data_out[7:0]; |
| 406 | |
| 407 | // If had array_select, then needed to define a user_array_sel register. |
| 408 | |
| 409 | |
| 410 | // Defining User start, stop, and increment addresses. |
| 411 | |
| 412 | sii_mb0_ctlmsff_ctl_macro__width_6 user_start_addr_reg ( |
| 413 | .scan_in(user_start_addr_reg_scanin), |
| 414 | .scan_out(user_start_addr_reg_scanout), |
| 415 | .din ( user_start_addr_in[5:0] ), |
| 416 | .dout ( user_start_addr[5:0] ), |
| 417 | .l1clk(l1clk), |
| 418 | .siclk(siclk), |
| 419 | .soclk(soclk)); |
| 420 | |
| 421 | assign user_start_addr_in[5:0] = user_start_addr[5:0]; |
| 422 | |
| 423 | sii_mb0_ctlmsff_ctl_macro__width_6 user_stop_addr_reg ( |
| 424 | .scan_in(user_stop_addr_reg_scanin), |
| 425 | .scan_out(user_stop_addr_reg_scanout), |
| 426 | .din ( user_stop_addr_in[5:0] ), |
| 427 | .dout ( user_stop_addr[5:0] ), |
| 428 | .l1clk(l1clk), |
| 429 | .siclk(siclk), |
| 430 | .soclk(soclk)); |
| 431 | |
| 432 | assign user_stop_addr_in[5:0] = user_stop_addr[5:0]; |
| 433 | |
| 434 | |
| 435 | sii_mb0_ctlmsff_ctl_macro__width_6 user_incr_addr_reg ( |
| 436 | .scan_in(user_incr_addr_reg_scanin), |
| 437 | .scan_out(user_incr_addr_reg_scanout), |
| 438 | .din ( user_incr_addr_in[5:0] ), |
| 439 | .dout ( user_incr_addr[5:0] ), |
| 440 | .l1clk(l1clk), |
| 441 | .siclk(siclk), |
| 442 | .soclk(soclk)); |
| 443 | |
| 444 | assign user_incr_addr_in[5:0] = user_incr_addr[5:0]; |
| 445 | |
| 446 | sii_mb0_ctlmsff_ctl_macro__width_1 run_reg ( |
| 447 | .scan_in(run_reg_scanin), |
| 448 | .scan_out(run_reg_scanout), |
| 449 | .din ( run ), |
| 450 | .dout ( sii_mb0_run ), |
| 451 | .l1clk(l1clk), |
| 452 | .siclk(siclk), |
| 453 | .soclk(soclk)); |
| 454 | |
| 455 | // Defining user_bisi write and read registers |
| 456 | |
| 457 | sii_mb0_ctlmsff_ctl_macro__width_1 user_bisi_wr_reg ( |
| 458 | .scan_in(user_bisi_wr_reg_scanin), |
| 459 | .scan_out(user_bisi_wr_reg_scanout), |
| 460 | .din ( user_bisi_wr_mode_in ), |
| 461 | .dout ( user_bisi_wr_mode ), |
| 462 | .l1clk(l1clk), |
| 463 | .siclk(siclk), |
| 464 | .soclk(soclk)); |
| 465 | |
| 466 | assign user_bisi_wr_mode_in = user_bisi_wr_mode; |
| 467 | |
| 468 | sii_mb0_ctlmsff_ctl_macro__width_1 user_bisi_rd_reg ( |
| 469 | .scan_in(user_bisi_rd_reg_scanin), |
| 470 | .scan_out(user_bisi_rd_reg_scanout), |
| 471 | .din ( user_bisi_rd_mode_in ), |
| 472 | .dout ( user_bisi_rd_mode ), |
| 473 | .l1clk(l1clk), |
| 474 | .siclk(siclk), |
| 475 | .soclk(soclk)); |
| 476 | |
| 477 | assign user_bisi_rd_mode_in = user_bisi_rd_mode; |
| 478 | |
| 479 | assign mbist_user_bisi_wr_mode = user_mode & bisi & user_bisi_wr_mode & ~user_bisi_rd_mode; |
| 480 | // assign mbist_user_bisi_rd_mode = user_mode & bisi & user_bisi_rd_mode & ~user_bisi_wr_mode; |
| 481 | |
| 482 | assign mbist_user_bisi_wr_rd_mode = user_mode & bisi & |
| 483 | ((user_bisi_wr_mode & user_bisi_rd_mode) | |
| 484 | (~user_bisi_wr_mode & ~user_bisi_rd_mode)); |
| 485 | |
| 486 | //////////////////////////////////////////////////////////////////////////////// |
| 487 | // Piping start_transition |
| 488 | //////////////////////////////////////////////////////////////////////////////// |
| 489 | |
| 490 | sii_mb0_ctlmsff_ctl_macro__width_1 start_transition_reg ( |
| 491 | .scan_in(start_transition_reg_scanin), |
| 492 | .scan_out(start_transition_reg_scanout), |
| 493 | .din ( start_transition ), |
| 494 | .dout ( start_transition_piped ), |
| 495 | .l1clk(l1clk), |
| 496 | .siclk(siclk), |
| 497 | .soclk(soclk)); |
| 498 | |
| 499 | |
| 500 | // ///////////////////////////////////////////////////////////////////////////// |
| 501 | // Adding 2 extra pipeline stages to run to delay the start of mbist for 3 cycles. |
| 502 | // ///////////////////////////////////////////////////////////////////////////// |
| 503 | |
| 504 | sii_mb0_ctlmsff_ctl_macro__width_1 run1_reg ( |
| 505 | .scan_in(run1_reg_scanin), |
| 506 | .scan_out(run1_reg_scanout), |
| 507 | .din ( run1_in ), |
| 508 | .dout ( run1_out ), |
| 509 | .l1clk(l1clk), |
| 510 | .siclk(siclk), |
| 511 | .soclk(soclk)); |
| 512 | |
| 513 | assign run1_in = reset_engine ? 1'b0: sii_mb0_run; |
| 514 | |
| 515 | sii_mb0_ctlmsff_ctl_macro__width_1 run2_reg ( |
| 516 | .scan_in(run2_reg_scanin), |
| 517 | .scan_out(run2_reg_scanout), |
| 518 | .din ( run2_in ), |
| 519 | .dout ( run2_out ), |
| 520 | .l1clk(l1clk), |
| 521 | .siclk(siclk), |
| 522 | .soclk(soclk)); |
| 523 | |
| 524 | assign run2_in = reset_engine ? 1'b0: run1_out; |
| 525 | // assign run_piped3 = run2_out & run; //As soon as run goes low, mbist operation is done! |
| 526 | assign run_piped3 = config_out[0] & run2_out & ~msb; //As soon as run goes low, mbist operation is done! |
| 527 | |
| 528 | |
| 529 | // ///////////////////////////////////////////////////////////////////////////// |
| 530 | // Pipelining mbist outputs. |
| 531 | // ///////////////////////////////////////////////////////////////////////////// |
| 532 | |
| 533 | sii_mb0_ctlmsff_ctl_macro__width_6 addr_reg ( |
| 534 | .scan_in(addr_reg_scanin), |
| 535 | .scan_out(addr_reg_scanout), |
| 536 | .din ( mbist_address[5:0] ), |
| 537 | .dout ( sii_mb0_addr[5:0] ), |
| 538 | .l1clk(l1clk), |
| 539 | .siclk(siclk), |
| 540 | .soclk(soclk)); |
| 541 | |
| 542 | sii_mb0_ctlmsff_ctl_macro__width_8 wdata_reg ( |
| 543 | .scan_in(wdata_reg_scanin), |
| 544 | .scan_out(wdata_reg_scanout), |
| 545 | .din ( mbist_wdata[7:0] ), |
| 546 | .dout ( sii_mb0_wdata[7:0] ), |
| 547 | .l1clk(l1clk), |
| 548 | .siclk(siclk), |
| 549 | .soclk(soclk)); |
| 550 | |
| 551 | sii_mb0_ctlmsff_ctl_macro__width_2 rd_wr_en_reg ( |
| 552 | .scan_in(rd_wr_en_reg_scanin), |
| 553 | .scan_out(rd_wr_en_reg_scanout), |
| 554 | .din ( {mbist_ind_wr_en, mbist_ind_rd_en} ), |
| 555 | .dout ( {sii_mb0_ind_wr_en, sii_mb0_ind_rd_en} ), |
| 556 | .l1clk(l1clk), |
| 557 | .siclk(siclk), |
| 558 | .soclk(soclk)); |
| 559 | |
| 560 | sii_mb0_ctlmsff_ctl_macro__width_2 ild_rd_wr_en_reg ( |
| 561 | .scan_in(ild_rd_wr_en_reg_scanin), |
| 562 | .scan_out(ild_rd_wr_en_reg_scanout), |
| 563 | .din ( {mbist_ild_wr_en, mbist_ild_rd_en} ), |
| 564 | .dout ( {sii_mb0_wr_en, sii_mb0_rd_en} ), |
| 565 | .l1clk(l1clk), |
| 566 | .siclk(siclk), |
| 567 | .soclk(soclk)); |
| 568 | |
| 569 | // fail and done |
| 570 | sii_mb0_ctlmsff_ctl_macro__width_1 sii_mb0_fail_reg ( |
| 571 | .scan_in(sii_mb0_fail_reg_scanin), |
| 572 | .scan_out(sii_mb0_fail_reg_scanout), |
| 573 | .din ( fail ), |
| 574 | .dout ( sii_mb0_fail ), |
| 575 | .l1clk(l1clk), |
| 576 | .siclk(siclk), |
| 577 | .soclk(soclk)); |
| 578 | |
| 579 | sii_mb0_ctlmsff_ctl_macro__width_1 sii_mb0_done_reg ( |
| 580 | .scan_in(sii_mb0_done_reg_scanin), |
| 581 | .scan_out(sii_mb0_done_reg_scanout), |
| 582 | .din ( mbist_done ), |
| 583 | .dout ( sii_mb0_done ), |
| 584 | .l1clk(l1clk), |
| 585 | .siclk(siclk), |
| 586 | .soclk(soclk)); |
| 587 | |
| 588 | |
| 589 | // ///////////////////////////////////////////////////////////////////////////// |
| 590 | // |
| 591 | // MBIST Control Register |
| 592 | // |
| 593 | // ///////////////////////////////////////////////////////////////////////////// |
| 594 | // Remove Address mix disable before delivery |
| 595 | // ///////////////////////////////////////////////////////////////////////////// |
| 596 | |
| 597 | |
| 598 | sii_mb0_ctlmsff_ctl_macro__width_18 control_reg ( |
| 599 | .scan_in(control_reg_scanin), |
| 600 | .scan_out(control_reg_scanout), |
| 601 | .din ( control_in[17:0] ), |
| 602 | .dout ( control_out[17:0] ), |
| 603 | .l1clk(l1clk), |
| 604 | .siclk(siclk), |
| 605 | .soclk(soclk)); |
| 606 | |
| 607 | assign msb = control_out[17]; |
| 608 | assign bisi_wr_rd = (bisi & ~user_mode) | mbist_user_bisi_wr_rd_mode ? control_out[16] : 1'b1; |
| 609 | assign data_control[1:0] = control_out[15:14]; |
| 610 | assign address_mix = (bisi | mbist_user_addr_mode) ? 1'b0: control_out[13]; |
| 611 | assign march_element[3:0] = control_out[12:9]; |
| 612 | // assign array_address[5:0] = control_out[8:3]; |
| 613 | assign array_address[5:0] = upaddress_march ? control_out[8:3] : ~control_out[8:3]; |
| 614 | |
| 615 | assign read_write_control[2:0] = ~five_cycle_march ? {2'b11, control_out[0]} : |
| 616 | control_out[2:0]; |
| 617 | |
| 618 | assign control_in[2:0] = reset_engine ? 3'b0: |
| 619 | ~run_piped3 ? control_out[2:0]: |
| 620 | (five_cycle_march && (read_write_control[2:0] == 3'b100)) ? 3'b000: |
| 621 | (one_cycle_march && (read_write_control[2:0] == 3'b110)) ? 3'b000: |
| 622 | control_out[2:0] + 3'b001; |
| 623 | |
| 624 | assign increment_addr = (five_cycle_march && (read_write_control[2:0] == 3'b100)) || |
| 625 | (one_cycle_march && (read_write_control[2:0] == 3'b110)) || |
| 626 | (read_write_control[2:0] == 3'b111); |
| 627 | |
| 628 | assign control_in[8:3] = start_transition_piped || reset_engine ? start_addr[5:0]: |
| 629 | ~run_piped3 || ~increment_addr ? control_out[8:3]: |
| 630 | next_array_address[5:0]; |
| 631 | |
| 632 | assign next_array_address[5:0] = next_upaddr_march ? start_addr[5:0]: |
| 633 | next_downaddr_march ? ~stop_addr[5:0]: |
| 634 | (overflow_addr[5:0]); // array_addr + incr_addr |
| 635 | |
| 636 | assign start_addr[5:0] = mbist_user_addr_mode ? user_start_addr[5:0] : 6'b000000; |
| 637 | assign stop_addr[5:0] = mbist_user_addr_mode ? user_stop_addr[5:0] : 6'b111111; |
| 638 | assign incr_addr[5:0] = mbist_user_addr_mode ? user_incr_addr[5:0] : 6'b000001; |
| 639 | |
| 640 | assign overflow_addr[6:0] = {1'b0,control_out[8:3]} + {1'b0,incr_addr[5:0]}; |
| 641 | assign overflow = compare_addr[6:0] < overflow_addr[6:0]; |
| 642 | |
| 643 | assign compare_addr[6:0] = upaddress_march ? {1'b0, stop_addr[5:0]} : |
| 644 | {1'b0, ~start_addr[5:0]}; |
| 645 | |
| 646 | |
| 647 | assign next_upaddr_march = ( (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || |
| 648 | (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h5) || |
| 649 | (march_element[3:0] == 4'h8) ) && overflow; |
| 650 | |
| 651 | |
| 652 | assign next_downaddr_march = ( (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h7) || |
| 653 | (march_element[3:0] == 4'h3) || (march_element[3:0] == 4'h4) ) && |
| 654 | overflow; |
| 655 | |
| 656 | |
| 657 | assign add[5:0] = five_cycle_march && ( (read_write_control[2:0] == 3'h1) || |
| 658 | (read_write_control[2:0] == 3'h3)) ? |
| 659 | adj_address[5:0]: array_address[5:0]; |
| 660 | |
| 661 | assign adj_address[5:0] = { array_address[5:2], ~array_address[1], array_address[0] }; // 16 rows/column |
| 662 | |
| 663 | // Since ildq instances and indq are tested in parallel, add[5] needs to stay as |
| 664 | // MSB as ildq's are 32 words. |
| 665 | assign mbist_address[5:0] = address_mix ? {add[5],add[0],add[4],add[3],add[2],add[1]}: |
| 666 | add[5:0]; |
| 667 | |
| 668 | // Definition of the rest of the control register |
| 669 | assign increment_march_elem = increment_addr && overflow; |
| 670 | |
| 671 | assign control_in[17:9] = reset_engine ? 9'b0: |
| 672 | ~run_piped3 ? control_out[17:9]: |
| 673 | {msb, bisi_wr_rd, next_data_control[1:0], next_address_mix, next_march_element[3:0]} + |
| 674 | {8'b0, increment_march_elem}; |
| 675 | |
| 676 | assign next_data_control[1:0] = (bisi || (mbist_user_data_mode && (data_control[1:0] == 2'b00))) ? 2'b11: |
| 677 | data_control[1:0]; |
| 678 | |
| 679 | assign next_address_mix = bisi | mbist_user_addr_mode ? 1'b1 : address_mix; |
| 680 | |
| 681 | // Incorporated ten_n_mode! |
| 682 | assign next_march_element[3:0] = ( bisi || |
| 683 | (mbist_ten_n_mode && (march_element[3:0] == 4'b0101)) || |
| 684 | ((march_element[3:0] == 4'b1000) && (read_write_control[2:0] == 3'b100)) ) |
| 685 | && overflow ? 4'b1111: march_element[3:0]; |
| 686 | |
| 687 | |
| 688 | assign array_write = ~run_piped3 ? 1'b0: |
| 689 | five_cycle_march ? (read_write_control[2:0] == 3'h0) || |
| 690 | (read_write_control[2:0] == 3'h1) || |
| 691 | (read_write_control[2:0] == 3'h4): |
| 692 | (~five_cycle_march & ~one_cycle_march) ? read_write_control[0]: |
| 693 | ( ((march_element[3:0] == 4'h0) & (~bisi || ~bisi_wr_rd || mbist_user_bisi_wr_mode)) || (march_element[3:0] == 4'h7)); |
| 694 | |
| 695 | assign array_read = ~array_write && run_piped3; // && ~initialize; |
| 696 | // assign mbist_done = msb; |
| 697 | |
| 698 | assign mbist_wdata[7:0] = true_data ? data_pattern[7:0]: ~data_pattern[7:0]; |
| 699 | |
| 700 | |
| 701 | // assign second_time_through = ~loop_on_address && address_mix; |
| 702 | // assign initialize = (march_element[3:0] == 4'b0000) && ~second_time_through; |
| 703 | |
| 704 | |
| 705 | // assign four_cycle_march = (march_element[3:0] == 3'h6) || (march_element[3:0] == 3'h7); |
| 706 | assign five_cycle_march = (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h8); |
| 707 | assign one_cycle_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h5) || |
| 708 | (march_element[3:0] == 4'h7); |
| 709 | |
| 710 | assign upaddress_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || |
| 711 | (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h6) || |
| 712 | (march_element[3:0] == 4'h7); |
| 713 | |
| 714 | // assign true_data = read_write_control[1] ^ ~march_element[0]; |
| 715 | |
| 716 | assign true_data = (five_cycle_march && (march_element[3:0] == 4'h6)) ? |
| 717 | ((read_write_control[2:0] == 3'h0) || (read_write_control[2:0] == 3'h2)): |
| 718 | (five_cycle_march && (march_element[3:0] == 4'h8)) ? |
| 719 | ((read_write_control[2:0] == 3'h1) || |
| 720 | (read_write_control[2:0] == 3'h3) || (read_write_control[2:0] == 3'h4)): |
| 721 | one_cycle_march ? (march_element[3:0] == 4'h7): |
| 722 | ~(read_write_control[0] ^ march_element[0]); |
| 723 | |
| 724 | |
| 725 | |
| 726 | assign data_pattern[7:0] = (bisi & mbist_user_data_mode) ? ~user_data_out[7:0]: |
| 727 | mbist_user_data_mode ? user_data_out[7:0]: |
| 728 | bisi ? 8'hFF: // true_data function will invert to 8'h00 |
| 729 | (data_control[1:0] == 2'h0) ? 8'hAA: |
| 730 | (data_control[1:0] == 2'h1) ? 8'h99: |
| 731 | (data_control[1:0] == 2'h2) ? 8'hCC: |
| 732 | 8'h00; |
| 733 | |
| 734 | // Declaring rd_en and wr_en |
| 735 | assign mbist_ind_rd_en = array_read; |
| 736 | assign mbist_ild_rd_en = array_read & ~array_address[5]; |
| 737 | assign mbist_ind_wr_en = array_write; |
| 738 | assign mbist_ild_wr_en = array_write & ~array_address[5]; |
| 739 | |
| 740 | |
| 741 | ///////////////////////////////////////////////////////////////////////// |
| 742 | // Creating the mbist_done signal |
| 743 | ///////////////////////////////////////////////////////////////////////// |
| 744 | // Delaying mbist_done 8 clock signals after msb going high, to provide |
| 745 | // a generic solution for done going high after the last fail has come back! |
| 746 | |
| 747 | sii_mb0_ctlmsff_ctl_macro__width_3 done_counter_reg ( |
| 748 | .scan_in(done_counter_reg_scanin), |
| 749 | .scan_out(done_counter_reg_scanout), |
| 750 | .din ( done_counter_in[2:0] ), |
| 751 | .dout ( done_counter_out[2:0] ), |
| 752 | .l1clk(l1clk), |
| 753 | .siclk(siclk), |
| 754 | .soclk(soclk)); |
| 755 | |
| 756 | // config_out[1] is AND'ed to force mbist_done low 2 cycles after mbist_start |
| 757 | // goes low. |
| 758 | |
| 759 | assign mbist_done = (&done_counter_out[2:0] == 1'b1) & config_out[1]; |
| 760 | assign done_counter_in[2:0] = reset_engine ? 3'b000: |
| 761 | msb & ~mbist_done & config_out[1] ? done_counter_out[2:0] + 3'b001: |
| 762 | done_counter_out[2:0]; |
| 763 | |
| 764 | // ///////////////////////////////////////////////////////////////////////////// |
| 765 | // Pipeline for wdata, and Read_en |
| 766 | // ///////////////////////////////////////////////////////////////////////////// |
| 767 | |
| 768 | // Since the fail is staged after comparator and at the mbist engine, need to |
| 769 | // stage read_en 4 times. |
| 770 | // 4/27/05: Adding an extra stage to compensate for the inverter and flop stage |
| 771 | // that is added to fail signals coming back to mbist engine to fix the fail logic |
| 772 | // and improve timing. |
| 773 | |
| 774 | sii_mb0_ctlmsff_ctl_macro__width_1 ind_ren_pipe_reg1 ( |
| 775 | .scan_in(ind_ren_pipe_reg1_scanin), |
| 776 | .scan_out(ind_ren_pipe_reg1_scanout), |
| 777 | .din ( ind_ren_pipe_reg1_in ), |
| 778 | .dout ( ind_ren_pipe_out1 ), |
| 779 | .l1clk(l1clk), |
| 780 | .siclk(siclk), |
| 781 | .soclk(soclk)); |
| 782 | |
| 783 | sii_mb0_ctlmsff_ctl_macro__width_1 ind_ren_pipe_reg2 ( |
| 784 | .scan_in(ind_ren_pipe_reg2_scanin), |
| 785 | .scan_out(ind_ren_pipe_reg2_scanout), |
| 786 | .din ( ind_ren_pipe_reg2_in ), |
| 787 | .dout ( ind_ren_pipe_out2 ), |
| 788 | .l1clk(l1clk), |
| 789 | .siclk(siclk), |
| 790 | .soclk(soclk)); |
| 791 | |
| 792 | sii_mb0_ctlmsff_ctl_macro__width_1 ind_ren_pipe_reg3 ( |
| 793 | .scan_in(ind_ren_pipe_reg3_scanin), |
| 794 | .scan_out(ind_ren_pipe_reg3_scanout), |
| 795 | .din ( ind_ren_pipe_reg3_in ), |
| 796 | .dout ( ind_ren_pipe_out3 ), |
| 797 | .l1clk(l1clk), |
| 798 | .siclk(siclk), |
| 799 | .soclk(soclk)); |
| 800 | |
| 801 | sii_mb0_ctlmsff_ctl_macro__width_1 ind_ren_pipe_reg4 ( |
| 802 | .scan_in(ind_ren_pipe_reg4_scanin), |
| 803 | .scan_out(ind_ren_pipe_reg4_scanout), |
| 804 | .din ( ind_ren_pipe_reg4_in ), |
| 805 | .dout ( ind_ren_pipe_out4 ), |
| 806 | .l1clk(l1clk), |
| 807 | .siclk(siclk), |
| 808 | .soclk(soclk)); |
| 809 | |
| 810 | sii_mb0_ctlmsff_ctl_macro__width_1 ind_ren_pipe_reg5 ( |
| 811 | .scan_in(ind_ren_pipe_reg5_scanin), |
| 812 | .scan_out(ind_ren_pipe_reg5_scanout), |
| 813 | .din ( ind_ren_pipe_reg5_in ), |
| 814 | .dout ( ind_ren_pipe_out5 ), |
| 815 | .l1clk(l1clk), |
| 816 | .siclk(siclk), |
| 817 | .soclk(soclk)); |
| 818 | |
| 819 | |
| 820 | assign ind_ren_pipe_reg1_in = reset_engine ? 1'b0: sii_mb0_ind_rd_en; |
| 821 | assign ind_ren_pipe_reg2_in = reset_engine ? 1'b0: ind_ren_pipe_out1; |
| 822 | assign ind_ren_pipe_reg3_in = reset_engine ? 1'b0: ind_ren_pipe_out2; |
| 823 | assign ind_ren_pipe_reg4_in = reset_engine ? 1'b0: ind_ren_pipe_out3; |
| 824 | assign ind_ren_pipe_reg5_in = reset_engine ? 1'b0: ind_ren_pipe_out4; |
| 825 | assign sii_piped_ind_ren = ind_ren_pipe_out5; |
| 826 | |
| 827 | sii_mb0_ctlmsff_ctl_macro__width_1 ild_ren_pipe_reg1 ( |
| 828 | .scan_in(ild_ren_pipe_reg1_scanin), |
| 829 | .scan_out(ild_ren_pipe_reg1_scanout), |
| 830 | .din ( ild_ren_pipe_reg1_in ), |
| 831 | .dout ( ild_ren_pipe_out1 ), |
| 832 | .l1clk(l1clk), |
| 833 | .siclk(siclk), |
| 834 | .soclk(soclk)); |
| 835 | |
| 836 | sii_mb0_ctlmsff_ctl_macro__width_1 ild_ren_pipe_reg2 ( |
| 837 | .scan_in(ild_ren_pipe_reg2_scanin), |
| 838 | .scan_out(ild_ren_pipe_reg2_scanout), |
| 839 | .din ( ild_ren_pipe_reg2_in ), |
| 840 | .dout ( ild_ren_pipe_out2 ), |
| 841 | .l1clk(l1clk), |
| 842 | .siclk(siclk), |
| 843 | .soclk(soclk)); |
| 844 | |
| 845 | sii_mb0_ctlmsff_ctl_macro__width_1 ild_ren_pipe_reg3 ( |
| 846 | .scan_in(ild_ren_pipe_reg3_scanin), |
| 847 | .scan_out(ild_ren_pipe_reg3_scanout), |
| 848 | .din ( ild_ren_pipe_reg3_in ), |
| 849 | .dout ( ild_ren_pipe_out3 ), |
| 850 | .l1clk(l1clk), |
| 851 | .siclk(siclk), |
| 852 | .soclk(soclk)); |
| 853 | |
| 854 | sii_mb0_ctlmsff_ctl_macro__width_1 ild_ren_pipe_reg4 ( |
| 855 | .scan_in(ild_ren_pipe_reg4_scanin), |
| 856 | .scan_out(ild_ren_pipe_reg4_scanout), |
| 857 | .din ( ild_ren_pipe_reg4_in ), |
| 858 | .dout ( ild_ren_pipe_out4 ), |
| 859 | .l1clk(l1clk), |
| 860 | .siclk(siclk), |
| 861 | .soclk(soclk)); |
| 862 | |
| 863 | sii_mb0_ctlmsff_ctl_macro__width_1 ild_ren_pipe_reg5 ( |
| 864 | .scan_in(ild_ren_pipe_reg5_scanin), |
| 865 | .scan_out(ild_ren_pipe_reg5_scanout), |
| 866 | .din ( ild_ren_pipe_reg5_in ), |
| 867 | .dout ( ild_ren_pipe_out5 ), |
| 868 | .l1clk(l1clk), |
| 869 | .siclk(siclk), |
| 870 | .soclk(soclk)); |
| 871 | |
| 872 | |
| 873 | assign sii_mb0_ild_rd_en = sii_mb0_rd_en; |
| 874 | assign ild_ren_pipe_reg1_in = reset_engine ? 1'b0: sii_mb0_ild_rd_en; |
| 875 | assign ild_ren_pipe_reg2_in = reset_engine ? 1'b0: ild_ren_pipe_out1; |
| 876 | assign ild_ren_pipe_reg3_in = reset_engine ? 1'b0: ild_ren_pipe_out2; |
| 877 | assign ild_ren_pipe_reg4_in = reset_engine ? 1'b0: ild_ren_pipe_out3; |
| 878 | assign ild_ren_pipe_reg5_in = reset_engine ? 1'b0: ild_ren_pipe_out4; |
| 879 | assign sii_piped_ild_ren = ild_ren_pipe_out5; |
| 880 | |
| 881 | ///////////////////////////////////////////////////////////////////////// |
| 882 | // Pipelining fail inputs to the memory to guarantee timing. |
| 883 | ///////////////////////////////////////////////////////////////////////// |
| 884 | |
| 885 | sii_mb0_ctlmsff_ctl_macro__width_2 ild0_fail_reg ( |
| 886 | .scan_in(ild0_fail_reg_scanin), |
| 887 | .scan_out(ild0_fail_reg_scanout), |
| 888 | .din ( sii_mb0_ild0_fail[1:0] ), |
| 889 | .dout ( sii_mb0_ild0_fail_piped[1:0] ), |
| 890 | .l1clk(l1clk), |
| 891 | .siclk(siclk), |
| 892 | .soclk(soclk)); |
| 893 | |
| 894 | sii_mb0_ctlmsff_ctl_macro__width_2 ild1_fail_reg ( |
| 895 | .scan_in(ild1_fail_reg_scanin), |
| 896 | .scan_out(ild1_fail_reg_scanout), |
| 897 | .din ( sii_mb0_ild1_fail[1:0] ), |
| 898 | .dout ( sii_mb0_ild1_fail_piped[1:0] ), |
| 899 | .l1clk(l1clk), |
| 900 | .siclk(siclk), |
| 901 | .soclk(soclk)); |
| 902 | |
| 903 | sii_mb0_ctlmsff_ctl_macro__width_2 ild2_fail_reg ( |
| 904 | .scan_in(ild2_fail_reg_scanin), |
| 905 | .scan_out(ild2_fail_reg_scanout), |
| 906 | .din ( sii_mb0_ild2_fail[1:0] ), |
| 907 | .dout ( sii_mb0_ild2_fail_piped[1:0] ), |
| 908 | .l1clk(l1clk), |
| 909 | .siclk(siclk), |
| 910 | .soclk(soclk)); |
| 911 | |
| 912 | sii_mb0_ctlmsff_ctl_macro__width_2 ild3_fail_reg ( |
| 913 | .scan_in(ild3_fail_reg_scanin), |
| 914 | .scan_out(ild3_fail_reg_scanout), |
| 915 | .din ( sii_mb0_ild3_fail[1:0] ), |
| 916 | .dout ( sii_mb0_ild3_fail_piped[1:0] ), |
| 917 | .l1clk(l1clk), |
| 918 | .siclk(siclk), |
| 919 | .soclk(soclk)); |
| 920 | |
| 921 | sii_mb0_ctlmsff_ctl_macro__width_2 ild4_fail_reg ( |
| 922 | .scan_in(ild4_fail_reg_scanin), |
| 923 | .scan_out(ild4_fail_reg_scanout), |
| 924 | .din ( sii_mb0_ild4_fail[1:0] ), |
| 925 | .dout ( sii_mb0_ild4_fail_piped[1:0] ), |
| 926 | .l1clk(l1clk), |
| 927 | .siclk(siclk), |
| 928 | .soclk(soclk)); |
| 929 | |
| 930 | |
| 931 | sii_mb0_ctlmsff_ctl_macro__width_2 ild5_fail_reg ( |
| 932 | .scan_in(ild5_fail_reg_scanin), |
| 933 | .scan_out(ild5_fail_reg_scanout), |
| 934 | .din ( sii_mb0_ild5_fail[1:0] ), |
| 935 | .dout ( sii_mb0_ild5_fail_piped[1:0] ), |
| 936 | .l1clk(l1clk), |
| 937 | .siclk(siclk), |
| 938 | .soclk(soclk)); |
| 939 | |
| 940 | |
| 941 | sii_mb0_ctlmsff_ctl_macro__width_2 ild6_fail_reg ( |
| 942 | .scan_in(ild6_fail_reg_scanin), |
| 943 | .scan_out(ild6_fail_reg_scanout), |
| 944 | .din ( sii_mb0_ild6_fail[1:0] ), |
| 945 | .dout ( sii_mb0_ild6_fail_piped[1:0] ), |
| 946 | .l1clk(l1clk), |
| 947 | .siclk(siclk), |
| 948 | .soclk(soclk)); |
| 949 | |
| 950 | sii_mb0_ctlmsff_ctl_macro__width_2 ild7_fail_reg ( |
| 951 | .scan_in(ild7_fail_reg_scanin), |
| 952 | .scan_out(ild7_fail_reg_scanout), |
| 953 | .din ( sii_mb0_ild7_fail[1:0] ), |
| 954 | .dout ( sii_mb0_ild7_fail_piped[1:0] ), |
| 955 | .l1clk(l1clk), |
| 956 | .siclk(siclk), |
| 957 | .soclk(soclk)); |
| 958 | |
| 959 | sii_mb0_ctlmsff_ctl_macro__width_2 ind_fail_reg ( |
| 960 | .scan_in(ind_fail_reg_scanin), |
| 961 | .scan_out(ind_fail_reg_scanout), |
| 962 | .din ( sii_mb0_ind_fail[1:0] ), |
| 963 | .dout ( sii_mb0_ind_fail_piped[1:0] ), |
| 964 | .l1clk(l1clk), |
| 965 | .siclk(siclk), |
| 966 | .soclk(soclk)); |
| 967 | |
| 968 | |
| 969 | // ///////////////////////////////////////////////////////////////////////////// |
| 970 | // Spare gates |
| 971 | // ///////////////////////////////////////////////////////////////////////////// |
| 972 | |
| 973 | sii_mb0_ctlspare_ctl_macro__num_2 spares ( |
| 974 | .scan_in(spares_scanin), |
| 975 | .scan_out(spares_scanout), |
| 976 | .l1clk (l1clk), |
| 977 | .siclk(siclk), |
| 978 | .soclk(soclk) |
| 979 | ); |
| 980 | |
| 981 | // ///////////////////////////////////////////////////////////////////////////// |
| 982 | // Shared Fail Detection |
| 983 | // ///////////////////////////////////////////////////////////////////////////// |
| 984 | // Updated to meet these new features: |
| 985 | // 1.When mbist_done signal is asserted when it completes all the |
| 986 | // tests, it also need to assert static membist fail signal if |
| 987 | // there were any failures during the tests. |
| 988 | // 2.The mbist_fail signal won't be sticky bit from membist |
| 989 | // engine. The TCU will make it sticky fail bit as needed. |
| 990 | |
| 991 | |
| 992 | sii_mb0_ctlmsff_ctl_macro__width_18 fail_reg ( |
| 993 | .scan_in(fail_reg_scanin), |
| 994 | .scan_out(fail_reg_scanout), |
| 995 | .din ( fail_reg_in[17:0] ), |
| 996 | .dout ( fail_reg_out[17:0] ), |
| 997 | .l1clk(l1clk), |
| 998 | .siclk(siclk), |
| 999 | .soclk(soclk)); |
| 1000 | |
| 1001 | |
| 1002 | assign fail_reg_in[17:0] = reset_engine ? 18'b0: {qual_sii_ind_fail[1:0],qual_sii_ild7_fail[1:0],qual_sii_ild6_fail[1:0],qual_sii_ild5_fail[1:0],qual_sii_ild4_fail[1:0],qual_sii_ild3_fail[1:0],qual_sii_ild2_fail[1:0],qual_sii_ild1_fail[1:0],qual_sii_ild0_fail[1:0]} | fail_reg_out[17:0]; |
| 1003 | |
| 1004 | |
| 1005 | //Assuming Connie has not qualified the fail with read_en staged properly! |
| 1006 | assign qual_sii_ild0_fail[0] = sii_piped_ild_ren && sii_mb0_ild0_fail_piped[0]; |
| 1007 | assign qual_sii_ild0_fail[1] = sii_piped_ild_ren && sii_mb0_ild0_fail_piped[1]; |
| 1008 | assign qual_sii_ild1_fail[0] = sii_piped_ild_ren && sii_mb0_ild1_fail_piped[0]; |
| 1009 | assign qual_sii_ild1_fail[1] = sii_piped_ild_ren && sii_mb0_ild1_fail_piped[1]; |
| 1010 | assign qual_sii_ild2_fail[0] = sii_piped_ild_ren && sii_mb0_ild2_fail_piped[0]; |
| 1011 | assign qual_sii_ild2_fail[1] = sii_piped_ild_ren && sii_mb0_ild2_fail_piped[1]; |
| 1012 | assign qual_sii_ild3_fail[0] = sii_piped_ild_ren && sii_mb0_ild3_fail_piped[0]; |
| 1013 | assign qual_sii_ild3_fail[1] = sii_piped_ild_ren && sii_mb0_ild3_fail_piped[1]; |
| 1014 | assign qual_sii_ild4_fail[0] = sii_piped_ild_ren && sii_mb0_ild4_fail_piped[0]; |
| 1015 | assign qual_sii_ild4_fail[1] = sii_piped_ild_ren && sii_mb0_ild4_fail_piped[1]; |
| 1016 | assign qual_sii_ild5_fail[0] = sii_piped_ild_ren && sii_mb0_ild5_fail_piped[0]; |
| 1017 | assign qual_sii_ild5_fail[1] = sii_piped_ild_ren && sii_mb0_ild5_fail_piped[1]; |
| 1018 | assign qual_sii_ild6_fail[0] = sii_piped_ild_ren && sii_mb0_ild6_fail_piped[0]; |
| 1019 | assign qual_sii_ild6_fail[1] = sii_piped_ild_ren && sii_mb0_ild6_fail_piped[1]; |
| 1020 | assign qual_sii_ild7_fail[0] = sii_piped_ild_ren && sii_mb0_ild7_fail_piped[0]; |
| 1021 | assign qual_sii_ild7_fail[1] = sii_piped_ild_ren && sii_mb0_ild7_fail_piped[1]; |
| 1022 | |
| 1023 | assign qual_sii_ind_fail[0] = sii_piped_ind_ren && sii_mb0_ind_fail_piped[0]; |
| 1024 | assign qual_sii_ind_fail[1] = sii_piped_ind_ren && sii_mb0_ind_fail_piped[1]; |
| 1025 | |
| 1026 | assign fail = mbist_done ? |fail_reg_out[17:0] : |
| 1027 | qual_sii_ild0_fail[0] | qual_sii_ild0_fail[1] | |
| 1028 | qual_sii_ild1_fail[0] | qual_sii_ild1_fail[1] | |
| 1029 | qual_sii_ild2_fail[0] | qual_sii_ild2_fail[1] | |
| 1030 | qual_sii_ild3_fail[0] | qual_sii_ild3_fail[1] | |
| 1031 | qual_sii_ild4_fail[0] | qual_sii_ild4_fail[1] | |
| 1032 | qual_sii_ild5_fail[0] | qual_sii_ild5_fail[1] | |
| 1033 | qual_sii_ild6_fail[0] | qual_sii_ild6_fail[1] | |
| 1034 | qual_sii_ild7_fail[0] | qual_sii_ild7_fail[1] | |
| 1035 | qual_sii_ind_fail[0] | qual_sii_ind_fail[1]; |
| 1036 | |
| 1037 | |
| 1038 | |
| 1039 | // fixscan start: |
| 1040 | assign config_reg_scanin = scan_in ; |
| 1041 | assign user_data_reg_scanin = config_reg_scanout ; |
| 1042 | assign user_start_addr_reg_scanin = user_data_reg_scanout ; |
| 1043 | assign user_stop_addr_reg_scanin = user_start_addr_reg_scanout; |
| 1044 | assign user_incr_addr_reg_scanin = user_stop_addr_reg_scanout; |
| 1045 | assign run_reg_scanin = user_incr_addr_reg_scanout; |
| 1046 | assign user_bisi_wr_reg_scanin = run_reg_scanout ; |
| 1047 | assign user_bisi_rd_reg_scanin = user_bisi_wr_reg_scanout ; |
| 1048 | assign start_transition_reg_scanin = user_bisi_rd_reg_scanout ; |
| 1049 | assign run1_reg_scanin = start_transition_reg_scanout; |
| 1050 | assign run2_reg_scanin = run1_reg_scanout ; |
| 1051 | assign addr_reg_scanin = run2_reg_scanout ; |
| 1052 | assign wdata_reg_scanin = addr_reg_scanout ; |
| 1053 | assign rd_wr_en_reg_scanin = wdata_reg_scanout ; |
| 1054 | assign ild_rd_wr_en_reg_scanin = rd_wr_en_reg_scanout ; |
| 1055 | assign sii_mb0_fail_reg_scanin = ild_rd_wr_en_reg_scanout ; |
| 1056 | assign sii_mb0_done_reg_scanin = sii_mb0_fail_reg_scanout ; |
| 1057 | assign control_reg_scanin = sii_mb0_done_reg_scanout ; |
| 1058 | assign done_counter_reg_scanin = control_reg_scanout ; |
| 1059 | assign ind_ren_pipe_reg1_scanin = done_counter_reg_scanout ; |
| 1060 | assign ind_ren_pipe_reg2_scanin = ind_ren_pipe_reg1_scanout; |
| 1061 | assign ind_ren_pipe_reg3_scanin = ind_ren_pipe_reg2_scanout; |
| 1062 | assign ind_ren_pipe_reg4_scanin = ind_ren_pipe_reg3_scanout; |
| 1063 | assign ind_ren_pipe_reg5_scanin = ind_ren_pipe_reg4_scanout; |
| 1064 | assign ild_ren_pipe_reg1_scanin = ind_ren_pipe_reg5_scanout; |
| 1065 | assign ild_ren_pipe_reg2_scanin = ild_ren_pipe_reg1_scanout; |
| 1066 | assign ild_ren_pipe_reg3_scanin = ild_ren_pipe_reg2_scanout; |
| 1067 | assign ild_ren_pipe_reg4_scanin = ild_ren_pipe_reg3_scanout; |
| 1068 | assign ild_ren_pipe_reg5_scanin = ild_ren_pipe_reg4_scanout; |
| 1069 | assign ild0_fail_reg_scanin = ild_ren_pipe_reg5_scanout; |
| 1070 | assign ild1_fail_reg_scanin = ild0_fail_reg_scanout ; |
| 1071 | assign ild2_fail_reg_scanin = ild1_fail_reg_scanout ; |
| 1072 | assign ild3_fail_reg_scanin = ild2_fail_reg_scanout ; |
| 1073 | assign ild4_fail_reg_scanin = ild3_fail_reg_scanout ; |
| 1074 | assign ild5_fail_reg_scanin = ild4_fail_reg_scanout ; |
| 1075 | assign ild6_fail_reg_scanin = ild5_fail_reg_scanout ; |
| 1076 | assign ild7_fail_reg_scanin = ild6_fail_reg_scanout ; |
| 1077 | assign ind_fail_reg_scanin = ild7_fail_reg_scanout ; |
| 1078 | assign spares_scanin = ind_fail_reg_scanout ; |
| 1079 | assign fail_reg_scanin = spares_scanout ; |
| 1080 | assign scan_out = fail_reg_scanout ; |
| 1081 | // fixscan end: |
| 1082 | endmodule // sii_mb0_ctl |
| 1083 | |
| 1084 | |
| 1085 | |
| 1086 | |
| 1087 | |
| 1088 | |
| 1089 | // any PARAMS parms go into naming of macro |
| 1090 | |
| 1091 | module sii_mb0_ctll1clkhdr_ctl_macro ( |
| 1092 | l2clk, |
| 1093 | l1en, |
| 1094 | pce_ov, |
| 1095 | stop, |
| 1096 | se, |
| 1097 | l1clk); |
| 1098 | |
| 1099 | |
| 1100 | input l2clk; |
| 1101 | input l1en; |
| 1102 | input pce_ov; |
| 1103 | input stop; |
| 1104 | input se; |
| 1105 | output l1clk; |
| 1106 | |
| 1107 | |
| 1108 | |
| 1109 | |
| 1110 | |
| 1111 | cl_sc1_l1hdr_8x c_0 ( |
| 1112 | |
| 1113 | |
| 1114 | .l2clk(l2clk), |
| 1115 | .pce(l1en), |
| 1116 | .l1clk(l1clk), |
| 1117 | .se(se), |
| 1118 | .pce_ov(pce_ov), |
| 1119 | .stop(stop) |
| 1120 | ); |
| 1121 | |
| 1122 | |
| 1123 | |
| 1124 | endmodule |
| 1125 | |
| 1126 | |
| 1127 | |
| 1128 | |
| 1129 | |
| 1130 | |
| 1131 | |
| 1132 | |
| 1133 | |
| 1134 | |
| 1135 | |
| 1136 | |
| 1137 | |
| 1138 | // any PARAMS parms go into naming of macro |
| 1139 | |
| 1140 | module sii_mb0_ctlmsff_ctl_macro__width_8 ( |
| 1141 | din, |
| 1142 | l1clk, |
| 1143 | scan_in, |
| 1144 | siclk, |
| 1145 | soclk, |
| 1146 | dout, |
| 1147 | scan_out); |
| 1148 | wire [7:0] fdin; |
| 1149 | wire [6:0] so; |
| 1150 | |
| 1151 | input [7:0] din; |
| 1152 | input l1clk; |
| 1153 | input scan_in; |
| 1154 | |
| 1155 | |
| 1156 | input siclk; |
| 1157 | input soclk; |
| 1158 | |
| 1159 | output [7:0] dout; |
| 1160 | output scan_out; |
| 1161 | assign fdin[7:0] = din[7:0]; |
| 1162 | |
| 1163 | |
| 1164 | |
| 1165 | |
| 1166 | |
| 1167 | |
| 1168 | dff #(8) d0_0 ( |
| 1169 | .l1clk(l1clk), |
| 1170 | .siclk(siclk), |
| 1171 | .soclk(soclk), |
| 1172 | .d(fdin[7:0]), |
| 1173 | .si({scan_in,so[6:0]}), |
| 1174 | .so({so[6:0],scan_out}), |
| 1175 | .q(dout[7:0]) |
| 1176 | ); |
| 1177 | |
| 1178 | |
| 1179 | |
| 1180 | |
| 1181 | |
| 1182 | |
| 1183 | |
| 1184 | |
| 1185 | |
| 1186 | |
| 1187 | |
| 1188 | |
| 1189 | endmodule |
| 1190 | |
| 1191 | |
| 1192 | |
| 1193 | |
| 1194 | |
| 1195 | |
| 1196 | |
| 1197 | |
| 1198 | |
| 1199 | |
| 1200 | |
| 1201 | |
| 1202 | |
| 1203 | // any PARAMS parms go into naming of macro |
| 1204 | |
| 1205 | module sii_mb0_ctlmsff_ctl_macro__width_6 ( |
| 1206 | din, |
| 1207 | l1clk, |
| 1208 | scan_in, |
| 1209 | siclk, |
| 1210 | soclk, |
| 1211 | dout, |
| 1212 | scan_out); |
| 1213 | wire [5:0] fdin; |
| 1214 | wire [4:0] so; |
| 1215 | |
| 1216 | input [5:0] din; |
| 1217 | input l1clk; |
| 1218 | input scan_in; |
| 1219 | |
| 1220 | |
| 1221 | input siclk; |
| 1222 | input soclk; |
| 1223 | |
| 1224 | output [5:0] dout; |
| 1225 | output scan_out; |
| 1226 | assign fdin[5:0] = din[5:0]; |
| 1227 | |
| 1228 | |
| 1229 | |
| 1230 | |
| 1231 | |
| 1232 | |
| 1233 | dff #(6) d0_0 ( |
| 1234 | .l1clk(l1clk), |
| 1235 | .siclk(siclk), |
| 1236 | .soclk(soclk), |
| 1237 | .d(fdin[5:0]), |
| 1238 | .si({scan_in,so[4:0]}), |
| 1239 | .so({so[4:0],scan_out}), |
| 1240 | .q(dout[5:0]) |
| 1241 | ); |
| 1242 | |
| 1243 | |
| 1244 | |
| 1245 | |
| 1246 | |
| 1247 | |
| 1248 | |
| 1249 | |
| 1250 | |
| 1251 | |
| 1252 | |
| 1253 | |
| 1254 | endmodule |
| 1255 | |
| 1256 | |
| 1257 | |
| 1258 | |
| 1259 | |
| 1260 | |
| 1261 | |
| 1262 | |
| 1263 | |
| 1264 | |
| 1265 | |
| 1266 | |
| 1267 | |
| 1268 | // any PARAMS parms go into naming of macro |
| 1269 | |
| 1270 | module sii_mb0_ctlmsff_ctl_macro__width_1 ( |
| 1271 | din, |
| 1272 | l1clk, |
| 1273 | scan_in, |
| 1274 | siclk, |
| 1275 | soclk, |
| 1276 | dout, |
| 1277 | scan_out); |
| 1278 | wire [0:0] fdin; |
| 1279 | |
| 1280 | input [0:0] din; |
| 1281 | input l1clk; |
| 1282 | input scan_in; |
| 1283 | |
| 1284 | |
| 1285 | input siclk; |
| 1286 | input soclk; |
| 1287 | |
| 1288 | output [0:0] dout; |
| 1289 | output scan_out; |
| 1290 | assign fdin[0:0] = din[0:0]; |
| 1291 | |
| 1292 | |
| 1293 | |
| 1294 | |
| 1295 | |
| 1296 | |
| 1297 | dff #(1) d0_0 ( |
| 1298 | .l1clk(l1clk), |
| 1299 | .siclk(siclk), |
| 1300 | .soclk(soclk), |
| 1301 | .d(fdin[0:0]), |
| 1302 | .si(scan_in), |
| 1303 | .so(scan_out), |
| 1304 | .q(dout[0:0]) |
| 1305 | ); |
| 1306 | |
| 1307 | |
| 1308 | |
| 1309 | |
| 1310 | |
| 1311 | |
| 1312 | |
| 1313 | |
| 1314 | |
| 1315 | |
| 1316 | |
| 1317 | |
| 1318 | endmodule |
| 1319 | |
| 1320 | |
| 1321 | |
| 1322 | |
| 1323 | |
| 1324 | |
| 1325 | |
| 1326 | |
| 1327 | |
| 1328 | |
| 1329 | |
| 1330 | |
| 1331 | |
| 1332 | // any PARAMS parms go into naming of macro |
| 1333 | |
| 1334 | module sii_mb0_ctlmsff_ctl_macro__width_2 ( |
| 1335 | din, |
| 1336 | l1clk, |
| 1337 | scan_in, |
| 1338 | siclk, |
| 1339 | soclk, |
| 1340 | dout, |
| 1341 | scan_out); |
| 1342 | wire [1:0] fdin; |
| 1343 | wire [0:0] so; |
| 1344 | |
| 1345 | input [1:0] din; |
| 1346 | input l1clk; |
| 1347 | input scan_in; |
| 1348 | |
| 1349 | |
| 1350 | input siclk; |
| 1351 | input soclk; |
| 1352 | |
| 1353 | output [1:0] dout; |
| 1354 | output scan_out; |
| 1355 | assign fdin[1:0] = din[1:0]; |
| 1356 | |
| 1357 | |
| 1358 | |
| 1359 | |
| 1360 | |
| 1361 | |
| 1362 | dff #(2) d0_0 ( |
| 1363 | .l1clk(l1clk), |
| 1364 | .siclk(siclk), |
| 1365 | .soclk(soclk), |
| 1366 | .d(fdin[1:0]), |
| 1367 | .si({scan_in,so[0:0]}), |
| 1368 | .so({so[0:0],scan_out}), |
| 1369 | .q(dout[1:0]) |
| 1370 | ); |
| 1371 | |
| 1372 | |
| 1373 | |
| 1374 | |
| 1375 | |
| 1376 | |
| 1377 | |
| 1378 | |
| 1379 | |
| 1380 | |
| 1381 | |
| 1382 | |
| 1383 | endmodule |
| 1384 | |
| 1385 | |
| 1386 | |
| 1387 | |
| 1388 | |
| 1389 | |
| 1390 | |
| 1391 | |
| 1392 | |
| 1393 | |
| 1394 | |
| 1395 | |
| 1396 | |
| 1397 | // any PARAMS parms go into naming of macro |
| 1398 | |
| 1399 | module sii_mb0_ctlmsff_ctl_macro__width_18 ( |
| 1400 | din, |
| 1401 | l1clk, |
| 1402 | scan_in, |
| 1403 | siclk, |
| 1404 | soclk, |
| 1405 | dout, |
| 1406 | scan_out); |
| 1407 | wire [17:0] fdin; |
| 1408 | wire [16:0] so; |
| 1409 | |
| 1410 | input [17:0] din; |
| 1411 | input l1clk; |
| 1412 | input scan_in; |
| 1413 | |
| 1414 | |
| 1415 | input siclk; |
| 1416 | input soclk; |
| 1417 | |
| 1418 | output [17:0] dout; |
| 1419 | output scan_out; |
| 1420 | assign fdin[17:0] = din[17:0]; |
| 1421 | |
| 1422 | |
| 1423 | |
| 1424 | |
| 1425 | |
| 1426 | |
| 1427 | dff #(18) d0_0 ( |
| 1428 | .l1clk(l1clk), |
| 1429 | .siclk(siclk), |
| 1430 | .soclk(soclk), |
| 1431 | .d(fdin[17:0]), |
| 1432 | .si({scan_in,so[16:0]}), |
| 1433 | .so({so[16:0],scan_out}), |
| 1434 | .q(dout[17:0]) |
| 1435 | ); |
| 1436 | |
| 1437 | |
| 1438 | |
| 1439 | |
| 1440 | |
| 1441 | |
| 1442 | |
| 1443 | |
| 1444 | |
| 1445 | |
| 1446 | |
| 1447 | |
| 1448 | endmodule |
| 1449 | |
| 1450 | |
| 1451 | |
| 1452 | |
| 1453 | |
| 1454 | |
| 1455 | |
| 1456 | |
| 1457 | |
| 1458 | |
| 1459 | |
| 1460 | |
| 1461 | |
| 1462 | // any PARAMS parms go into naming of macro |
| 1463 | |
| 1464 | module sii_mb0_ctlmsff_ctl_macro__width_3 ( |
| 1465 | din, |
| 1466 | l1clk, |
| 1467 | scan_in, |
| 1468 | siclk, |
| 1469 | soclk, |
| 1470 | dout, |
| 1471 | scan_out); |
| 1472 | wire [2:0] fdin; |
| 1473 | wire [1:0] so; |
| 1474 | |
| 1475 | input [2:0] din; |
| 1476 | input l1clk; |
| 1477 | input scan_in; |
| 1478 | |
| 1479 | |
| 1480 | input siclk; |
| 1481 | input soclk; |
| 1482 | |
| 1483 | output [2:0] dout; |
| 1484 | output scan_out; |
| 1485 | assign fdin[2:0] = din[2:0]; |
| 1486 | |
| 1487 | |
| 1488 | |
| 1489 | |
| 1490 | |
| 1491 | |
| 1492 | dff #(3) d0_0 ( |
| 1493 | .l1clk(l1clk), |
| 1494 | .siclk(siclk), |
| 1495 | .soclk(soclk), |
| 1496 | .d(fdin[2:0]), |
| 1497 | .si({scan_in,so[1:0]}), |
| 1498 | .so({so[1:0],scan_out}), |
| 1499 | .q(dout[2:0]) |
| 1500 | ); |
| 1501 | |
| 1502 | |
| 1503 | |
| 1504 | |
| 1505 | |
| 1506 | |
| 1507 | |
| 1508 | |
| 1509 | |
| 1510 | |
| 1511 | |
| 1512 | |
| 1513 | endmodule |
| 1514 | |
| 1515 | |
| 1516 | |
| 1517 | |
| 1518 | |
| 1519 | |
| 1520 | |
| 1521 | |
| 1522 | |
| 1523 | // Description: Spare gate macro for control blocks |
| 1524 | // |
| 1525 | // Param num controls the number of times the macro is added |
| 1526 | // flops=0 can be used to use only combination spare logic |
| 1527 | |
| 1528 | |
| 1529 | module sii_mb0_ctlspare_ctl_macro__num_2 ( |
| 1530 | l1clk, |
| 1531 | scan_in, |
| 1532 | siclk, |
| 1533 | soclk, |
| 1534 | scan_out); |
| 1535 | wire si_0; |
| 1536 | wire so_0; |
| 1537 | wire spare0_flop_unused; |
| 1538 | wire spare0_buf_32x_unused; |
| 1539 | wire spare0_nand3_8x_unused; |
| 1540 | wire spare0_inv_8x_unused; |
| 1541 | wire spare0_aoi22_4x_unused; |
| 1542 | wire spare0_buf_8x_unused; |
| 1543 | wire spare0_oai22_4x_unused; |
| 1544 | wire spare0_inv_16x_unused; |
| 1545 | wire spare0_nand2_16x_unused; |
| 1546 | wire spare0_nor3_4x_unused; |
| 1547 | wire spare0_nand2_8x_unused; |
| 1548 | wire spare0_buf_16x_unused; |
| 1549 | wire spare0_nor2_16x_unused; |
| 1550 | wire spare0_inv_32x_unused; |
| 1551 | wire si_1; |
| 1552 | wire so_1; |
| 1553 | wire spare1_flop_unused; |
| 1554 | wire spare1_buf_32x_unused; |
| 1555 | wire spare1_nand3_8x_unused; |
| 1556 | wire spare1_inv_8x_unused; |
| 1557 | wire spare1_aoi22_4x_unused; |
| 1558 | wire spare1_buf_8x_unused; |
| 1559 | wire spare1_oai22_4x_unused; |
| 1560 | wire spare1_inv_16x_unused; |
| 1561 | wire spare1_nand2_16x_unused; |
| 1562 | wire spare1_nor3_4x_unused; |
| 1563 | wire spare1_nand2_8x_unused; |
| 1564 | wire spare1_buf_16x_unused; |
| 1565 | wire spare1_nor2_16x_unused; |
| 1566 | wire spare1_inv_32x_unused; |
| 1567 | |
| 1568 | |
| 1569 | input l1clk; |
| 1570 | input scan_in; |
| 1571 | input siclk; |
| 1572 | input soclk; |
| 1573 | output scan_out; |
| 1574 | |
| 1575 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), |
| 1576 | .siclk(siclk), |
| 1577 | .soclk(soclk), |
| 1578 | .si(si_0), |
| 1579 | .so(so_0), |
| 1580 | .d(1'b0), |
| 1581 | .q(spare0_flop_unused)); |
| 1582 | assign si_0 = scan_in; |
| 1583 | |
| 1584 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), |
| 1585 | .out(spare0_buf_32x_unused)); |
| 1586 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), |
| 1587 | .in1(1'b1), |
| 1588 | .in2(1'b1), |
| 1589 | .out(spare0_nand3_8x_unused)); |
| 1590 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), |
| 1591 | .out(spare0_inv_8x_unused)); |
| 1592 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), |
| 1593 | .in01(1'b1), |
| 1594 | .in10(1'b1), |
| 1595 | .in11(1'b1), |
| 1596 | .out(spare0_aoi22_4x_unused)); |
| 1597 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), |
| 1598 | .out(spare0_buf_8x_unused)); |
| 1599 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), |
| 1600 | .in01(1'b1), |
| 1601 | .in10(1'b1), |
| 1602 | .in11(1'b1), |
| 1603 | .out(spare0_oai22_4x_unused)); |
| 1604 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), |
| 1605 | .out(spare0_inv_16x_unused)); |
| 1606 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), |
| 1607 | .in1(1'b1), |
| 1608 | .out(spare0_nand2_16x_unused)); |
| 1609 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), |
| 1610 | .in1(1'b0), |
| 1611 | .in2(1'b0), |
| 1612 | .out(spare0_nor3_4x_unused)); |
| 1613 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), |
| 1614 | .in1(1'b1), |
| 1615 | .out(spare0_nand2_8x_unused)); |
| 1616 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), |
| 1617 | .out(spare0_buf_16x_unused)); |
| 1618 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), |
| 1619 | .in1(1'b0), |
| 1620 | .out(spare0_nor2_16x_unused)); |
| 1621 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), |
| 1622 | .out(spare0_inv_32x_unused)); |
| 1623 | |
| 1624 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), |
| 1625 | .siclk(siclk), |
| 1626 | .soclk(soclk), |
| 1627 | .si(si_1), |
| 1628 | .so(so_1), |
| 1629 | .d(1'b0), |
| 1630 | .q(spare1_flop_unused)); |
| 1631 | assign si_1 = so_0; |
| 1632 | |
| 1633 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), |
| 1634 | .out(spare1_buf_32x_unused)); |
| 1635 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), |
| 1636 | .in1(1'b1), |
| 1637 | .in2(1'b1), |
| 1638 | .out(spare1_nand3_8x_unused)); |
| 1639 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), |
| 1640 | .out(spare1_inv_8x_unused)); |
| 1641 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), |
| 1642 | .in01(1'b1), |
| 1643 | .in10(1'b1), |
| 1644 | .in11(1'b1), |
| 1645 | .out(spare1_aoi22_4x_unused)); |
| 1646 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), |
| 1647 | .out(spare1_buf_8x_unused)); |
| 1648 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), |
| 1649 | .in01(1'b1), |
| 1650 | .in10(1'b1), |
| 1651 | .in11(1'b1), |
| 1652 | .out(spare1_oai22_4x_unused)); |
| 1653 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), |
| 1654 | .out(spare1_inv_16x_unused)); |
| 1655 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), |
| 1656 | .in1(1'b1), |
| 1657 | .out(spare1_nand2_16x_unused)); |
| 1658 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), |
| 1659 | .in1(1'b0), |
| 1660 | .in2(1'b0), |
| 1661 | .out(spare1_nor3_4x_unused)); |
| 1662 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), |
| 1663 | .in1(1'b1), |
| 1664 | .out(spare1_nand2_8x_unused)); |
| 1665 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), |
| 1666 | .out(spare1_buf_16x_unused)); |
| 1667 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), |
| 1668 | .in1(1'b0), |
| 1669 | .out(spare1_nor2_16x_unused)); |
| 1670 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), |
| 1671 | .out(spare1_inv_32x_unused)); |
| 1672 | assign scan_out = so_1; |
| 1673 | |
| 1674 | |
| 1675 | |
| 1676 | endmodule |
| 1677 | |