| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: sio_mb1_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module sio_mb1_ctl ( |
| 36 | sio_mb1_run, |
| 37 | sio_mb1_addr, |
| 38 | sio_mb1_wdata, |
| 39 | sio_mb1_opddq00_wr_en, |
| 40 | sio_mb1_opddq00_rd_en, |
| 41 | sio_mb1_opddq01_wr_en, |
| 42 | sio_mb1_opddq01_rd_en, |
| 43 | sio_mb1_opddq10_wr_en, |
| 44 | sio_mb1_opddq10_rd_en, |
| 45 | sio_mb1_opddq11_wr_en, |
| 46 | sio_mb1_opddq11_rd_en, |
| 47 | sio_mb1_opdhq0_wr_en, |
| 48 | sio_mb1_opdhq0_rd_en, |
| 49 | sio_mb1_opdhq1_wr_en, |
| 50 | sio_mb1_opdhq1_rd_en, |
| 51 | sio_mb1_opdhq_sel, |
| 52 | sio_mb1_opddq0_sel, |
| 53 | sio_mb1_opddq1_sel, |
| 54 | sio_mb1_done, |
| 55 | sio_mb1_fail, |
| 56 | scan_out, |
| 57 | iol2clk, |
| 58 | tcu_scan_en, |
| 59 | scan_in, |
| 60 | tcu_aclk, |
| 61 | tcu_bclk, |
| 62 | tcu_pce_ov, |
| 63 | tcu_clk_stop, |
| 64 | tcu_sio_mb1_start, |
| 65 | sio_mb1_bisi_mode, |
| 66 | sio_mb1_user_mode, |
| 67 | opd0_read_data, |
| 68 | opd1_read_data); |
| 69 | wire se; |
| 70 | wire siclk; |
| 71 | wire soclk; |
| 72 | wire pce_ov; |
| 73 | wire stop; |
| 74 | wire l1clk; |
| 75 | wire config_reg_scanin; |
| 76 | wire config_reg_scanout; |
| 77 | wire [7:0] config_in; |
| 78 | wire [7:0] config_out; |
| 79 | wire start_transition; |
| 80 | wire reset_engine; |
| 81 | wire mbist_user_loop_mode; |
| 82 | wire mbist_done; |
| 83 | wire run; |
| 84 | wire bisi; |
| 85 | wire user_mode; |
| 86 | wire user_data_mode; |
| 87 | wire user_addr_mode; |
| 88 | wire user_loop_mode; |
| 89 | wire ten_n_mode; |
| 90 | wire mbist_user_data_mode; |
| 91 | wire mbist_user_addr_mode; |
| 92 | wire mbist_ten_n_mode; |
| 93 | wire user_data_reg_scanin; |
| 94 | wire user_data_reg_scanout; |
| 95 | wire [7:0] user_data_in; |
| 96 | wire [7:0] user_data_out; |
| 97 | wire user_start_addr_reg_scanin; |
| 98 | wire user_start_addr_reg_scanout; |
| 99 | wire [5:0] user_start_addr_in; |
| 100 | wire [5:0] user_start_addr; |
| 101 | wire user_stop_addr_reg_scanin; |
| 102 | wire user_stop_addr_reg_scanout; |
| 103 | wire [5:0] user_stop_addr_in; |
| 104 | wire [5:0] user_stop_addr; |
| 105 | wire user_incr_addr_reg_scanin; |
| 106 | wire user_incr_addr_reg_scanout; |
| 107 | wire [5:0] user_incr_addr_in; |
| 108 | wire [5:0] user_incr_addr; |
| 109 | wire user_array_sel_reg_scanin; |
| 110 | wire user_array_sel_reg_scanout; |
| 111 | wire [2:0] user_array_sel_in; |
| 112 | wire [2:0] user_array_sel; |
| 113 | wire user_bisi_wr_reg_scanin; |
| 114 | wire user_bisi_wr_reg_scanout; |
| 115 | wire user_bisi_wr_mode_in; |
| 116 | wire user_bisi_wr_mode; |
| 117 | wire user_bisi_rd_reg_scanin; |
| 118 | wire user_bisi_rd_reg_scanout; |
| 119 | wire user_bisi_rd_mode_in; |
| 120 | wire user_bisi_rd_mode; |
| 121 | wire mbist_user_bisi_wr_mode; |
| 122 | wire mbist_user_bisi_wr_rd_mode; |
| 123 | wire start_transition_reg_scanin; |
| 124 | wire start_transition_reg_scanout; |
| 125 | wire start_transition_piped; |
| 126 | wire run_reg_scanin; |
| 127 | wire run_reg_scanout; |
| 128 | wire counter_reg_scanin; |
| 129 | wire counter_reg_scanout; |
| 130 | wire [3:0] counter_in; |
| 131 | wire [3:0] counter_out; |
| 132 | wire cycle16; |
| 133 | wire run_piped16; |
| 134 | wire msb; |
| 135 | wire addr_reg_scanin; |
| 136 | wire addr_reg_scanout; |
| 137 | wire [5:0] mbist_address; |
| 138 | wire wdata_reg_scanin; |
| 139 | wire wdata_reg_scanout; |
| 140 | wire [7:0] mbist_wdata; |
| 141 | wire wr_rd_en_reg0_scanin; |
| 142 | wire wr_rd_en_reg0_scanout; |
| 143 | wire mbist_opddq00_wr_en; |
| 144 | wire mbist_opddq00_rd_en; |
| 145 | wire wr_rd_en_reg1_scanin; |
| 146 | wire wr_rd_en_reg1_scanout; |
| 147 | wire mbist_opddq01_wr_en; |
| 148 | wire mbist_opddq01_rd_en; |
| 149 | wire wr_rd_en_reg2_scanin; |
| 150 | wire wr_rd_en_reg2_scanout; |
| 151 | wire mbist_opddq10_wr_en; |
| 152 | wire mbist_opddq10_rd_en; |
| 153 | wire wr_rd_en_reg3_scanin; |
| 154 | wire wr_rd_en_reg3_scanout; |
| 155 | wire mbist_opddq11_wr_en; |
| 156 | wire mbist_opddq11_rd_en; |
| 157 | wire wr_rd_en_reg4_scanin; |
| 158 | wire wr_rd_en_reg4_scanout; |
| 159 | wire mbist_opdhq0_wr_en; |
| 160 | wire mbist_opdhq0_rd_en; |
| 161 | wire wr_rd_en_reg5_scanin; |
| 162 | wire wr_rd_en_reg5_scanout; |
| 163 | wire mbist_opdhq1_wr_en; |
| 164 | wire mbist_opdhq1_rd_en; |
| 165 | wire sel_reg_scanin; |
| 166 | wire sel_reg_scanout; |
| 167 | wire mbist_opdhq_sel; |
| 168 | wire mbist_opddq0_sel; |
| 169 | wire mbist_opddq1_sel; |
| 170 | wire done_reg_scanin; |
| 171 | wire done_reg_scanout; |
| 172 | wire new_fail_reg_scanin; |
| 173 | wire new_fail_reg_scanout; |
| 174 | wire fail; |
| 175 | wire control_reg_scanin; |
| 176 | wire control_reg_scanout; |
| 177 | wire [20:0] control_in; |
| 178 | wire [20:0] control_out; |
| 179 | wire bisi_wr_rd; |
| 180 | wire [2:0] array_sel; |
| 181 | wire [1:0] data_control; |
| 182 | wire address_mix; |
| 183 | wire [3:0] march_element; |
| 184 | wire [5:0] array_address; |
| 185 | wire upaddress_march; |
| 186 | wire [2:0] read_write_control; |
| 187 | wire five_cycle_march; |
| 188 | wire one_cycle_march; |
| 189 | wire increment_addr; |
| 190 | wire [5:0] start_addr; |
| 191 | wire [5:0] next_array_address; |
| 192 | wire next_upaddr_march; |
| 193 | wire next_downaddr_march; |
| 194 | wire [5:0] stop_addr; |
| 195 | wire [6:0] overflow_addr; |
| 196 | wire opdhq_sel; |
| 197 | wire [5:0] incr_addr; |
| 198 | wire overflow; |
| 199 | wire [6:0] compare_addr; |
| 200 | wire [5:0] add; |
| 201 | wire [5:0] adj_address; |
| 202 | wire increment_march_elem; |
| 203 | wire [2:0] next_array_sel; |
| 204 | wire [1:0] next_data_control; |
| 205 | wire next_address_mix; |
| 206 | wire [3:0] next_march_element; |
| 207 | wire array_write; |
| 208 | wire array_read; |
| 209 | wire true_data; |
| 210 | wire [7:0] data_pattern; |
| 211 | wire done_counter_reg_scanin; |
| 212 | wire done_counter_reg_scanout; |
| 213 | wire [2:0] done_counter_in; |
| 214 | wire [2:0] done_counter_out; |
| 215 | wire opddq00_sel; |
| 216 | wire opddq10_sel; |
| 217 | wire opddq01_sel; |
| 218 | wire opddq11_sel; |
| 219 | wire opdhq0_sel; |
| 220 | wire opdhq1_sel; |
| 221 | wire opd1_or_opd0_sel; |
| 222 | wire opddq0_sel; |
| 223 | wire opddq1_sel; |
| 224 | wire data_pipe_reg1_scanin; |
| 225 | wire data_pipe_reg1_scanout; |
| 226 | wire [7:0] data_pipe_reg1_in; |
| 227 | wire [7:0] data_pipe_out1; |
| 228 | wire data_pipe_reg2_scanin; |
| 229 | wire data_pipe_reg2_scanout; |
| 230 | wire [7:0] data_pipe_reg2_in; |
| 231 | wire [7:0] data_pipe_out2; |
| 232 | wire data_pipe_reg3_scanin; |
| 233 | wire data_pipe_reg3_scanout; |
| 234 | wire [7:0] data_pipe_reg3_in; |
| 235 | wire [7:0] data_pipe_out3; |
| 236 | wire [7:0] sio_opd_piped_wdata; |
| 237 | wire ren_pipe_reg1_scanin; |
| 238 | wire ren_pipe_reg1_scanout; |
| 239 | wire ren_pipe_reg1_in; |
| 240 | wire ren_pipe_out1; |
| 241 | wire ren_pipe_reg2_scanin; |
| 242 | wire ren_pipe_reg2_scanout; |
| 243 | wire ren_pipe_reg2_in; |
| 244 | wire ren_pipe_out2; |
| 245 | wire ren_pipe_reg3_scanin; |
| 246 | wire ren_pipe_reg3_scanout; |
| 247 | wire ren_pipe_reg3_in; |
| 248 | wire ren_pipe_out3; |
| 249 | wire ren_pipe_reg4_scanin; |
| 250 | wire ren_pipe_reg4_scanout; |
| 251 | wire ren_pipe_reg4_in; |
| 252 | wire ren_pipe_out4; |
| 253 | wire sio_opd_piped_ren; |
| 254 | wire opd_sel_reg1_scanin; |
| 255 | wire opd_sel_reg1_scanout; |
| 256 | wire opdhq_sel_reg1_in; |
| 257 | wire opddq0_sel_reg1_in; |
| 258 | wire opddq1_sel_reg1_in; |
| 259 | wire opdhq_sel_reg1_out; |
| 260 | wire opddq0_sel_reg1_out; |
| 261 | wire opddq1_sel_reg1_out; |
| 262 | wire opd_sel_reg2_scanin; |
| 263 | wire opd_sel_reg2_scanout; |
| 264 | wire opdhq_sel_reg2_in; |
| 265 | wire opddq0_sel_reg2_in; |
| 266 | wire opddq1_sel_reg2_in; |
| 267 | wire opdhq_sel_reg2_out; |
| 268 | wire opddq0_sel_reg2_out; |
| 269 | wire opddq1_sel_reg2_out; |
| 270 | wire opd_sel_reg4_scanin; |
| 271 | wire opd_sel_reg4_scanout; |
| 272 | wire opdhq_sel_reg4_in; |
| 273 | wire opddq0_sel_reg4_in; |
| 274 | wire opddq1_sel_reg4_in; |
| 275 | wire opdhq_sel_reg4_out; |
| 276 | wire opddq0_sel_reg4_out; |
| 277 | wire opddq1_sel_reg4_out; |
| 278 | wire sio_mb1_opdhq_sel_piped; |
| 279 | wire sio_mb1_opddq0_sel_piped; |
| 280 | wire sio_mb1_opddq1_sel_piped; |
| 281 | wire opd1or0_sel_reg1_scanin; |
| 282 | wire opd1or0_sel_reg1_scanout; |
| 283 | wire opd1or0_sel_reg1_in; |
| 284 | wire opd1or0_sel_out1; |
| 285 | wire opd1or0_sel_reg2_scanin; |
| 286 | wire opd1or0_sel_reg2_scanout; |
| 287 | wire opd1or0_sel_reg2_in; |
| 288 | wire opd1or0_sel_out2; |
| 289 | wire opd1or0_sel_reg3_scanin; |
| 290 | wire opd1or0_sel_reg3_scanout; |
| 291 | wire opd1or0_sel_reg3_in; |
| 292 | wire opd1or0_sel_out3; |
| 293 | wire opd1or0_sel_reg4_scanin; |
| 294 | wire opd1or0_sel_reg4_scanout; |
| 295 | wire opd1or0_sel_reg4_in; |
| 296 | wire opd1or0_sel_out4; |
| 297 | wire sio_mb1_opd1_or_opd0_sel; |
| 298 | wire sio_mb1_opd1_or_opd0_sel_piped; |
| 299 | wire opddq00_sel_piped; |
| 300 | wire opddq01_sel_piped; |
| 301 | wire opddq10_sel_piped; |
| 302 | wire opddq11_sel_piped; |
| 303 | wire opdhq0_sel_piped; |
| 304 | wire opdhq1_sel_piped; |
| 305 | wire spares_scanin; |
| 306 | wire spares_scanout; |
| 307 | wire read_data_pipe_reg_scanin; |
| 308 | wire read_data_pipe_reg_scanout; |
| 309 | wire [71:0] opd1_or_opd0_read_data; |
| 310 | wire [71:0] read_data_pipe; |
| 311 | wire fail_reg_scanin; |
| 312 | wire fail_reg_scanout; |
| 313 | wire [5:0] fail_reg_in; |
| 314 | wire [5:0] fail_reg_out; |
| 315 | wire qual_sio_opdhq1_fail; |
| 316 | wire qual_sio_opddq11_fail; |
| 317 | wire qual_sio_opddq10_fail; |
| 318 | wire qual_sio_opdhq0_fail; |
| 319 | wire qual_sio_opddq01_fail; |
| 320 | wire qual_sio_opddq00_fail; |
| 321 | wire fail_detect; |
| 322 | |
| 323 | |
| 324 | |
| 325 | output sio_mb1_run; |
| 326 | |
| 327 | output [5:0] sio_mb1_addr; |
| 328 | output [7:0] sio_mb1_wdata; |
| 329 | |
| 330 | output sio_mb1_opddq00_wr_en; |
| 331 | output sio_mb1_opddq00_rd_en; |
| 332 | |
| 333 | output sio_mb1_opddq01_wr_en; |
| 334 | output sio_mb1_opddq01_rd_en; |
| 335 | |
| 336 | output sio_mb1_opddq10_wr_en; |
| 337 | output sio_mb1_opddq10_rd_en; |
| 338 | |
| 339 | output sio_mb1_opddq11_wr_en; |
| 340 | output sio_mb1_opddq11_rd_en; |
| 341 | |
| 342 | output sio_mb1_opdhq0_wr_en; |
| 343 | output sio_mb1_opdhq0_rd_en; |
| 344 | |
| 345 | output sio_mb1_opdhq1_wr_en; |
| 346 | output sio_mb1_opdhq1_rd_en; |
| 347 | |
| 348 | output sio_mb1_opdhq_sel; |
| 349 | output sio_mb1_opddq0_sel; |
| 350 | output sio_mb1_opddq1_sel; |
| 351 | |
| 352 | output sio_mb1_done; |
| 353 | output sio_mb1_fail; |
| 354 | output scan_out; |
| 355 | |
| 356 | input iol2clk; |
| 357 | input tcu_scan_en; |
| 358 | input scan_in; |
| 359 | input tcu_aclk; |
| 360 | input tcu_bclk; |
| 361 | input tcu_pce_ov; |
| 362 | input tcu_clk_stop; |
| 363 | |
| 364 | input tcu_sio_mb1_start; |
| 365 | input sio_mb1_bisi_mode; |
| 366 | input sio_mb1_user_mode; |
| 367 | |
| 368 | |
| 369 | input [71:0] opd0_read_data; |
| 370 | input [71:0] opd1_read_data; |
| 371 | |
| 372 | |
| 373 | |
| 374 | /////////////////////////////////////// |
| 375 | // Scan chain connections |
| 376 | /////////////////////////////////////// |
| 377 | // scan renames |
| 378 | assign se = tcu_scan_en; |
| 379 | assign siclk = tcu_aclk; |
| 380 | assign soclk = tcu_bclk; |
| 381 | assign pce_ov = tcu_pce_ov; |
| 382 | assign stop = tcu_clk_stop; |
| 383 | // end scan |
| 384 | |
| 385 | sio_mb1_ctl_l1clkhdr_ctl_macro clkgen ( |
| 386 | .l2clk (iol2clk ), |
| 387 | .l1en (1'b1 ), |
| 388 | .l1clk (l1clk), |
| 389 | .pce_ov(pce_ov), |
| 390 | .stop(stop), |
| 391 | .se(se) |
| 392 | ); |
| 393 | |
| 394 | |
| 395 | |
| 396 | // ///////////////////////////////////////////////////////////////////////////// |
| 397 | // |
| 398 | // MBIST Config Register |
| 399 | // |
| 400 | // ///////////////////////////////////////////////////////////////////////////// |
| 401 | // |
| 402 | // A low to high transition on mbist_start will reset and start the engine. |
| 403 | // mbist_start must remain active high for the duration of MBIST. |
| 404 | // If mbist_start deasserts the engine will stop but not reset. |
| 405 | // Once MBIST has completed mbist_done will assert and the fail status |
| 406 | // signals will be valid. |
| 407 | // To run MBIST again the mbist_start signal must transition low then high. |
| 408 | // |
| 409 | // Loop on Address will disable the address mix function. |
| 410 | // |
| 411 | // ///////////////////////////////////////////////////////////////////////////// |
| 412 | |
| 413 | |
| 414 | sio_mb1_ctl_msff_ctl_macro__width_8 config_reg ( |
| 415 | .scan_in(config_reg_scanin), |
| 416 | .scan_out(config_reg_scanout), |
| 417 | .din ( config_in[7:0] ), |
| 418 | .dout ( config_out[7:0] ), |
| 419 | .l1clk(l1clk), |
| 420 | .siclk(siclk), |
| 421 | .soclk(soclk)); |
| 422 | |
| 423 | |
| 424 | assign config_in[0] = tcu_sio_mb1_start; |
| 425 | assign config_in[1] = config_out[0]; |
| 426 | assign start_transition = config_out[0] & ~config_out[1]; |
| 427 | assign reset_engine = start_transition | (mbist_user_loop_mode & mbist_done); |
| 428 | // assign run = config_out[1] & (mbist_user_loop_mode | ~mbist_done); |
| 429 | assign run = config_out[0] & config_out[1]; // 9/19/05 run to follow start only! |
| 430 | |
| 431 | assign config_in[2] = start_transition ? sio_mb1_bisi_mode: config_out[2]; |
| 432 | assign bisi = config_out[2]; |
| 433 | |
| 434 | assign config_in[3] = start_transition ? sio_mb1_user_mode: config_out[3]; |
| 435 | assign user_mode = config_out[3]; |
| 436 | |
| 437 | assign config_in[4] = config_out[4]; |
| 438 | assign user_data_mode = config_out[4]; |
| 439 | |
| 440 | assign config_in[5] = config_out[5]; |
| 441 | assign user_addr_mode = config_out[5]; |
| 442 | |
| 443 | assign config_in[6] = config_out[6]; |
| 444 | assign user_loop_mode = config_out[6]; |
| 445 | |
| 446 | assign config_in[7] = config_out[7]; |
| 447 | assign ten_n_mode = config_out[7]; |
| 448 | |
| 449 | |
| 450 | assign mbist_user_data_mode = user_mode & user_data_mode; |
| 451 | assign mbist_user_addr_mode = user_mode & user_addr_mode; |
| 452 | assign mbist_user_loop_mode = user_mode & user_loop_mode; |
| 453 | assign mbist_ten_n_mode = user_mode & ten_n_mode; |
| 454 | |
| 455 | |
| 456 | sio_mb1_ctl_msff_ctl_macro__width_8 user_data_reg ( |
| 457 | .scan_in(user_data_reg_scanin), |
| 458 | .scan_out(user_data_reg_scanout), |
| 459 | .din ( user_data_in[7:0] ), |
| 460 | .dout ( user_data_out[7:0] ), |
| 461 | .l1clk(l1clk), |
| 462 | .siclk(siclk), |
| 463 | .soclk(soclk)); |
| 464 | |
| 465 | |
| 466 | assign user_data_in[7:0] = user_data_out[7:0]; |
| 467 | |
| 468 | |
| 469 | // Defining User start, stop, and increment addresses. |
| 470 | |
| 471 | sio_mb1_ctl_msff_ctl_macro__width_6 user_start_addr_reg ( |
| 472 | .scan_in(user_start_addr_reg_scanin), |
| 473 | .scan_out(user_start_addr_reg_scanout), |
| 474 | .din ( user_start_addr_in[5:0] ), |
| 475 | .dout ( user_start_addr[5:0] ), |
| 476 | .l1clk(l1clk), |
| 477 | .siclk(siclk), |
| 478 | .soclk(soclk)); |
| 479 | |
| 480 | assign user_start_addr_in[5:0] = user_start_addr[5:0]; |
| 481 | |
| 482 | sio_mb1_ctl_msff_ctl_macro__width_6 user_stop_addr_reg ( |
| 483 | .scan_in(user_stop_addr_reg_scanin), |
| 484 | .scan_out(user_stop_addr_reg_scanout), |
| 485 | .din ( user_stop_addr_in[5:0] ), |
| 486 | .dout ( user_stop_addr[5:0] ), |
| 487 | .l1clk(l1clk), |
| 488 | .siclk(siclk), |
| 489 | .soclk(soclk)); |
| 490 | |
| 491 | assign user_stop_addr_in[5:0] = user_stop_addr[5:0]; |
| 492 | |
| 493 | |
| 494 | sio_mb1_ctl_msff_ctl_macro__width_6 user_incr_addr_reg ( |
| 495 | .scan_in(user_incr_addr_reg_scanin), |
| 496 | .scan_out(user_incr_addr_reg_scanout), |
| 497 | .din ( user_incr_addr_in[5:0] ), |
| 498 | .dout ( user_incr_addr[5:0] ), |
| 499 | .l1clk(l1clk), |
| 500 | .siclk(siclk), |
| 501 | .soclk(soclk)); |
| 502 | |
| 503 | assign user_incr_addr_in[5:0] = user_incr_addr[5:0]; |
| 504 | |
| 505 | // Defining User array_sel. |
| 506 | |
| 507 | sio_mb1_ctl_msff_ctl_macro__width_3 user_array_sel_reg ( |
| 508 | .scan_in(user_array_sel_reg_scanin), |
| 509 | .scan_out(user_array_sel_reg_scanout), |
| 510 | .din ( user_array_sel_in[2:0] ), |
| 511 | .dout ( user_array_sel[2:0] ), |
| 512 | .l1clk(l1clk), |
| 513 | .siclk(siclk), |
| 514 | .soclk(soclk)); |
| 515 | |
| 516 | assign user_array_sel_in[2:0] = user_array_sel[2:0]; |
| 517 | |
| 518 | // Defining user_bisi write and read registers |
| 519 | |
| 520 | sio_mb1_ctl_msff_ctl_macro__width_1 user_bisi_wr_reg ( |
| 521 | .scan_in(user_bisi_wr_reg_scanin), |
| 522 | .scan_out(user_bisi_wr_reg_scanout), |
| 523 | .din ( user_bisi_wr_mode_in ), |
| 524 | .dout ( user_bisi_wr_mode ), |
| 525 | .l1clk(l1clk), |
| 526 | .siclk(siclk), |
| 527 | .soclk(soclk)); |
| 528 | |
| 529 | assign user_bisi_wr_mode_in = user_bisi_wr_mode; |
| 530 | |
| 531 | sio_mb1_ctl_msff_ctl_macro__width_1 user_bisi_rd_reg ( |
| 532 | .scan_in(user_bisi_rd_reg_scanin), |
| 533 | .scan_out(user_bisi_rd_reg_scanout), |
| 534 | .din ( user_bisi_rd_mode_in ), |
| 535 | .dout ( user_bisi_rd_mode ), |
| 536 | .l1clk(l1clk), |
| 537 | .siclk(siclk), |
| 538 | .soclk(soclk)); |
| 539 | |
| 540 | assign user_bisi_rd_mode_in = user_bisi_rd_mode; |
| 541 | |
| 542 | assign mbist_user_bisi_wr_mode = user_mode & bisi & user_bisi_wr_mode & ~user_bisi_rd_mode; |
| 543 | // assign mbist_user_bisi_rd_mode = user_mode & bisi & user_bisi_rd_mode & ~user_bisi_wr_mode; |
| 544 | |
| 545 | assign mbist_user_bisi_wr_rd_mode = user_mode & bisi & |
| 546 | ((user_bisi_wr_mode & user_bisi_rd_mode) | |
| 547 | (~user_bisi_wr_mode & ~user_bisi_rd_mode)); |
| 548 | |
| 549 | //////////////////////////////////////////////////////////////////////////////// |
| 550 | // Piping start_transition |
| 551 | //////////////////////////////////////////////////////////////////////////////// |
| 552 | |
| 553 | sio_mb1_ctl_msff_ctl_macro__width_1 start_transition_reg ( |
| 554 | .scan_in(start_transition_reg_scanin), |
| 555 | .scan_out(start_transition_reg_scanout), |
| 556 | .din ( start_transition ), |
| 557 | .dout ( start_transition_piped ), |
| 558 | .l1clk(l1clk), |
| 559 | .siclk(siclk), |
| 560 | .soclk(soclk)); |
| 561 | |
| 562 | |
| 563 | //////////////////////////////////////////////////////////////////////////////// |
| 564 | // Staging run for 16 cycles for mbist engines supporting async FIFO's |
| 565 | //////////////////////////////////////////////////////////////////////////////// |
| 566 | |
| 567 | sio_mb1_ctl_msff_ctl_macro__width_1 run_reg ( |
| 568 | .scan_in(run_reg_scanin), |
| 569 | .scan_out(run_reg_scanout), |
| 570 | .din ( run ), |
| 571 | .dout ( sio_mb1_run ), |
| 572 | .l1clk(l1clk), |
| 573 | .siclk(siclk), |
| 574 | .soclk(soclk)); |
| 575 | |
| 576 | sio_mb1_ctl_msff_ctl_macro__width_4 counter_reg ( |
| 577 | .scan_in(counter_reg_scanin), |
| 578 | .scan_out(counter_reg_scanout), |
| 579 | .din ( counter_in[3:0] ), |
| 580 | .dout ( counter_out[3:0] ), |
| 581 | .l1clk(l1clk), |
| 582 | .siclk(siclk), |
| 583 | .soclk(soclk)); |
| 584 | |
| 585 | assign cycle16 = (&counter_out[3:0] == 1'b1); |
| 586 | assign counter_in[3:0] = reset_engine ? 4'b0: |
| 587 | run & ~cycle16 ? counter_out[3:0] + 4'b0001: |
| 588 | counter_out[3:0]; |
| 589 | |
| 590 | // assign run_piped16 = cycle16 & run; // As soon as run goes low, mbist operation is done! |
| 591 | assign run_piped16 = config_out[0] & cycle16 & ~msb; // As soon as run goes low, mbist operation is done! |
| 592 | |
| 593 | //////////////////////////////////////////////////////////////////////////////// |
| 594 | // Creating flop boundaries for the outputs of the mbist |
| 595 | //////////////////////////////////////////////////////////////////////////////// |
| 596 | |
| 597 | sio_mb1_ctl_msff_ctl_macro__width_6 addr_reg ( |
| 598 | .scan_in(addr_reg_scanin), |
| 599 | .scan_out(addr_reg_scanout), |
| 600 | .din ( mbist_address[5:0] ), |
| 601 | .dout ( sio_mb1_addr[5:0] ), |
| 602 | .l1clk(l1clk), |
| 603 | .siclk(siclk), |
| 604 | .soclk(soclk)); |
| 605 | |
| 606 | sio_mb1_ctl_msff_ctl_macro__width_8 wdata_reg ( |
| 607 | .scan_in(wdata_reg_scanin), |
| 608 | .scan_out(wdata_reg_scanout), |
| 609 | .din ( mbist_wdata[7:0] ), |
| 610 | .dout ( sio_mb1_wdata[7:0] ), |
| 611 | .l1clk(l1clk), |
| 612 | .siclk(siclk), |
| 613 | .soclk(soclk)); |
| 614 | |
| 615 | sio_mb1_ctl_msff_ctl_macro__width_2 wr_rd_en_reg0 ( |
| 616 | .scan_in(wr_rd_en_reg0_scanin), |
| 617 | .scan_out(wr_rd_en_reg0_scanout), |
| 618 | .din ( {mbist_opddq00_wr_en, mbist_opddq00_rd_en } ), |
| 619 | .dout ( {sio_mb1_opddq00_wr_en, sio_mb1_opddq00_rd_en } ), |
| 620 | .l1clk(l1clk), |
| 621 | .siclk(siclk), |
| 622 | .soclk(soclk)); |
| 623 | |
| 624 | sio_mb1_ctl_msff_ctl_macro__width_2 wr_rd_en_reg1 ( |
| 625 | .scan_in(wr_rd_en_reg1_scanin), |
| 626 | .scan_out(wr_rd_en_reg1_scanout), |
| 627 | .din ( {mbist_opddq01_wr_en, mbist_opddq01_rd_en } ), |
| 628 | .dout ( {sio_mb1_opddq01_wr_en, sio_mb1_opddq01_rd_en } ), |
| 629 | .l1clk(l1clk), |
| 630 | .siclk(siclk), |
| 631 | .soclk(soclk)); |
| 632 | |
| 633 | sio_mb1_ctl_msff_ctl_macro__width_2 wr_rd_en_reg2 ( |
| 634 | .scan_in(wr_rd_en_reg2_scanin), |
| 635 | .scan_out(wr_rd_en_reg2_scanout), |
| 636 | .din ( {mbist_opddq10_wr_en, mbist_opddq10_rd_en } ), |
| 637 | .dout ( { sio_mb1_opddq10_wr_en, sio_mb1_opddq10_rd_en } ), |
| 638 | .l1clk(l1clk), |
| 639 | .siclk(siclk), |
| 640 | .soclk(soclk)); |
| 641 | |
| 642 | sio_mb1_ctl_msff_ctl_macro__width_2 wr_rd_en_reg3 ( |
| 643 | .scan_in(wr_rd_en_reg3_scanin), |
| 644 | .scan_out(wr_rd_en_reg3_scanout), |
| 645 | .din ( {mbist_opddq11_wr_en, mbist_opddq11_rd_en } ), |
| 646 | .dout ( { sio_mb1_opddq11_wr_en, sio_mb1_opddq11_rd_en } ), |
| 647 | .l1clk(l1clk), |
| 648 | .siclk(siclk), |
| 649 | .soclk(soclk)); |
| 650 | |
| 651 | sio_mb1_ctl_msff_ctl_macro__width_2 wr_rd_en_reg4 ( |
| 652 | .scan_in(wr_rd_en_reg4_scanin), |
| 653 | .scan_out(wr_rd_en_reg4_scanout), |
| 654 | .din ( {mbist_opdhq0_wr_en, mbist_opdhq0_rd_en} ), |
| 655 | .dout ( {sio_mb1_opdhq0_wr_en, sio_mb1_opdhq0_rd_en} ), |
| 656 | .l1clk(l1clk), |
| 657 | .siclk(siclk), |
| 658 | .soclk(soclk)); |
| 659 | |
| 660 | sio_mb1_ctl_msff_ctl_macro__width_2 wr_rd_en_reg5 ( |
| 661 | .scan_in(wr_rd_en_reg5_scanin), |
| 662 | .scan_out(wr_rd_en_reg5_scanout), |
| 663 | .din ( {mbist_opdhq1_wr_en, mbist_opdhq1_rd_en } ), |
| 664 | .dout ( {sio_mb1_opdhq1_wr_en, sio_mb1_opdhq1_rd_en } ), |
| 665 | .l1clk(l1clk), |
| 666 | .siclk(siclk), |
| 667 | .soclk(soclk)); |
| 668 | |
| 669 | |
| 670 | sio_mb1_ctl_msff_ctl_macro__width_3 sel_reg ( |
| 671 | .scan_in(sel_reg_scanin), |
| 672 | .scan_out(sel_reg_scanout), |
| 673 | .din ( { mbist_opdhq_sel, mbist_opddq0_sel, mbist_opddq1_sel } ), |
| 674 | .dout ( { sio_mb1_opdhq_sel, sio_mb1_opddq0_sel, sio_mb1_opddq1_sel } ), |
| 675 | .l1clk(l1clk), |
| 676 | .siclk(siclk), |
| 677 | .soclk(soclk)); |
| 678 | |
| 679 | sio_mb1_ctl_msff_ctl_macro__width_1 done_reg ( |
| 680 | .scan_in(done_reg_scanin), |
| 681 | .scan_out(done_reg_scanout), |
| 682 | .din ( mbist_done ), |
| 683 | .dout ( sio_mb1_done ), |
| 684 | .l1clk(l1clk), |
| 685 | .siclk(siclk), |
| 686 | .soclk(soclk)); |
| 687 | |
| 688 | sio_mb1_ctl_msff_ctl_macro__width_1 new_fail_reg ( |
| 689 | .scan_in(new_fail_reg_scanin), |
| 690 | .scan_out(new_fail_reg_scanout), |
| 691 | .din ( fail ), |
| 692 | .dout ( sio_mb1_fail ), |
| 693 | .l1clk(l1clk), |
| 694 | .siclk(siclk), |
| 695 | .soclk(soclk)); |
| 696 | |
| 697 | |
| 698 | |
| 699 | // ///////////////////////////////////////////////////////////////////////////// |
| 700 | // |
| 701 | // MBIST Control Register |
| 702 | // |
| 703 | // ///////////////////////////////////////////////////////////////////////////// |
| 704 | // Remove Address mix disable before delivery |
| 705 | // ///////////////////////////////////////////////////////////////////////////// |
| 706 | |
| 707 | sio_mb1_ctl_msff_ctl_macro__width_21 control_reg ( |
| 708 | .scan_in(control_reg_scanin), |
| 709 | .scan_out(control_reg_scanout), |
| 710 | .din ( control_in[20:0] ), |
| 711 | .dout ( control_out[20:0] ), |
| 712 | .l1clk(l1clk), |
| 713 | .siclk(siclk), |
| 714 | .soclk(soclk)); |
| 715 | |
| 716 | assign msb = control_out[20]; |
| 717 | assign bisi_wr_rd = (bisi & ~user_mode) | mbist_user_bisi_wr_rd_mode ? control_out[19] : 1'b1; |
| 718 | assign array_sel[2:0] = user_mode ? user_array_sel[2:0] : control_out[18:16]; |
| 719 | assign data_control[1:0] = control_out[15:14]; |
| 720 | assign address_mix = (bisi | mbist_user_addr_mode) ? 1'b0: control_out[13]; |
| 721 | assign march_element[3:0] = control_out[12:9]; |
| 722 | // assign array_address[5:0] = opdhq_sel ? {2'b11, control_out[6:3]} : control_out[8:3]; |
| 723 | assign array_address[5:0] = upaddress_march ? control_out[8:3] : ~control_out[8:3]; |
| 724 | |
| 725 | assign read_write_control[2:0] = ~five_cycle_march ? {2'b11, control_out[0]} : |
| 726 | control_out[2:0]; |
| 727 | |
| 728 | |
| 729 | assign control_in[2:0] = reset_engine ? 3'b0: |
| 730 | ~run_piped16 ? control_out[2:0]: |
| 731 | (five_cycle_march && (read_write_control[2:0] == 3'b100)) ? 3'b000: |
| 732 | (one_cycle_march && (read_write_control[2:0] == 3'b110)) ? 3'b000: |
| 733 | control_out[2:0] + 3'b001; |
| 734 | |
| 735 | assign increment_addr = (five_cycle_march && (read_write_control[2:0] == 3'b100)) || |
| 736 | (one_cycle_march && (read_write_control[2:0] == 3'b110)) || |
| 737 | (read_write_control[2:0] == 3'b111); |
| 738 | |
| 739 | // start_transition_piped was added to have the correct start_addr at the start |
| 740 | // of mbist during user_addr_mode |
| 741 | assign control_in[8:3] = start_transition_piped || reset_engine ? start_addr[5:0]: |
| 742 | ~run_piped16 || ~increment_addr ? control_out[8:3]: |
| 743 | next_array_address[5:0]; |
| 744 | |
| 745 | assign next_array_address[5:0] = next_upaddr_march ? start_addr[5:0]: |
| 746 | next_downaddr_march ? ~stop_addr[5:0]: |
| 747 | (overflow_addr[5:0]); // array_addr + incr_addr |
| 748 | |
| 749 | assign start_addr[5:0] = mbist_user_addr_mode ? user_start_addr[5:0]: 6'b000000; |
| 750 | assign stop_addr[5:0] = mbist_user_addr_mode ? user_stop_addr[5:0] : |
| 751 | opdhq_sel ? 6'b001111 : 6'b111111; |
| 752 | assign incr_addr[5:0] = mbist_user_addr_mode ? user_incr_addr[5:0] : 6'b000001; |
| 753 | |
| 754 | assign overflow_addr[6:0] = {1'b0,control_out[8:3]} + {1'b0,incr_addr[5:0]}; |
| 755 | assign overflow = compare_addr[6:0] < overflow_addr[6:0]; |
| 756 | |
| 757 | assign compare_addr[6:0] = upaddress_march ? {1'b0, stop_addr[5:0]} : |
| 758 | {1'b0, ~start_addr[5:0]}; |
| 759 | |
| 760 | |
| 761 | assign next_upaddr_march = ( (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || |
| 762 | (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h5) || |
| 763 | (march_element[3:0] == 4'h8) ) && overflow; |
| 764 | |
| 765 | assign next_downaddr_march = ( (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h7) || |
| 766 | (march_element[3:0] == 4'h3) || (march_element[3:0] == 4'h4) ) && |
| 767 | overflow; |
| 768 | |
| 769 | |
| 770 | |
| 771 | |
| 772 | assign add[5:0] = five_cycle_march && ( (read_write_control[2:0] == 3'h1) || |
| 773 | (read_write_control[2:0] == 3'h3)) ? |
| 774 | adj_address[5:0]: array_address[5:0]; |
| 775 | |
| 776 | assign adj_address[5:0] = { array_address[5:2], ~array_address[1], array_address[0] }; |
| 777 | |
| 778 | // opd_data is 2 blks of 32 row each and opd_hdr is a blk of 16 rows. |
| 779 | assign mbist_address[5:0] = address_mix & opdhq_sel ? {add[5],add[4],add[0],add[3],add[2],add[1]}: |
| 780 | address_mix ? {add[0],add[5],add[4],add[3],add[2],add[1]}: |
| 781 | add[5:0]; |
| 782 | |
| 783 | // Definition of the rest of the control register |
| 784 | |
| 785 | assign increment_march_elem = increment_addr && overflow; |
| 786 | |
| 787 | assign control_in[20:9] = reset_engine ? 12'b0: |
| 788 | ~run_piped16 ? control_out[20:9]: |
| 789 | {msb, bisi_wr_rd, next_array_sel[2:0], next_data_control[1:0], next_address_mix, next_march_element[3:0]} + |
| 790 | {11'b0, increment_march_elem}; |
| 791 | |
| 792 | |
| 793 | assign next_array_sel[2:0] = user_mode ? 3'b111: |
| 794 | bisi & |
| 795 | (array_sel[2:0] == 3'b101) & (array_address == stop_addr) ? 3'b111: |
| 796 | (array_sel[2:0] == 3'b101) & (data_control[1:0] == 2'b11) & |
| 797 | (next_address_mix == 1'b1) & (march_element[3:0] == 4'b1000) & |
| 798 | (array_address == 6'b0) & (read_write_control[2:0] == 3'h4) ? 3'b111: control_out[18:16]; |
| 799 | |
| 800 | assign next_data_control[1:0] = (bisi || (mbist_user_data_mode && (data_control[1:0] == 2'b00))) ? 2'b11: |
| 801 | data_control[1:0]; |
| 802 | |
| 803 | assign next_address_mix = bisi | mbist_user_addr_mode ? 1'b1 : address_mix; |
| 804 | |
| 805 | // Incorporated ten_n_mode! |
| 806 | assign next_march_element[3:0] = ( bisi || |
| 807 | (mbist_ten_n_mode && (march_element[3:0] == 4'b0101)) || |
| 808 | ((march_element[3:0] == 4'b1000) && (read_write_control[2:0] == 3'b100)) ) |
| 809 | && overflow ? 4'b1111: march_element[3:0]; |
| 810 | |
| 811 | |
| 812 | assign array_write = ~run_piped16 ? 1'b0: |
| 813 | five_cycle_march ? (read_write_control[2:0] == 3'h0) || |
| 814 | (read_write_control[2:0] == 3'h1) || |
| 815 | (read_write_control[2:0] == 3'h4): |
| 816 | (~five_cycle_march & ~one_cycle_march) ? read_write_control[0]: |
| 817 | ( ((march_element[3:0] == 4'h0) & (~bisi || ~bisi_wr_rd || mbist_user_bisi_wr_mode)) || (march_element[3:0] == 4'h7)); |
| 818 | |
| 819 | assign array_read = ~array_write && run_piped16; // && ~initialize; |
| 820 | // assign mbist_done = msb; |
| 821 | |
| 822 | assign mbist_wdata[7:0] = true_data ? data_pattern[7:0]: ~data_pattern[7:0]; |
| 823 | |
| 824 | |
| 825 | assign five_cycle_march = (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h8); |
| 826 | assign one_cycle_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h5) || |
| 827 | (march_element[3:0] == 4'h7); |
| 828 | |
| 829 | assign upaddress_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || |
| 830 | (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h6) || |
| 831 | (march_element[3:0] == 4'h7); |
| 832 | |
| 833 | // assign true_data = read_write_control[1] ^ ~march_element[0]; |
| 834 | |
| 835 | assign true_data = (five_cycle_march && (march_element[3:0] == 4'h6)) ? |
| 836 | ((read_write_control[2:0] == 3'h0) || (read_write_control[2:0] == 3'h2)): |
| 837 | (five_cycle_march && (march_element[3:0] == 4'h8)) ? |
| 838 | ((read_write_control[2:0] == 3'h1) || |
| 839 | (read_write_control[2:0] == 3'h3) || (read_write_control[2:0] == 3'h4)): |
| 840 | one_cycle_march ? (march_element[3:0] == 4'h7): |
| 841 | ~(read_write_control[0] ^ march_element[0]); |
| 842 | |
| 843 | |
| 844 | assign data_pattern[7:0] = (bisi & mbist_user_data_mode) ? ~user_data_out[7:0]: |
| 845 | mbist_user_data_mode ? user_data_out[7:0]: |
| 846 | bisi ? 8'hFF: // true_data function will invert to 8'h00 |
| 847 | (data_control[1:0] == 2'h0) ? 8'hAA: |
| 848 | (data_control[1:0] == 2'h1) ? 8'h99: |
| 849 | (data_control[1:0] == 2'h2) ? 8'hCC: |
| 850 | 8'h00; |
| 851 | |
| 852 | |
| 853 | ///////////////////////////////////////////////////////////////////////// |
| 854 | // Creating the mbist_done signal |
| 855 | ///////////////////////////////////////////////////////////////////////// |
| 856 | // Delaying mbist_done 8 clock signals after msb going high, to provide |
| 857 | // a generic solution for done going high after the last fail has come back! |
| 858 | |
| 859 | sio_mb1_ctl_msff_ctl_macro__width_3 done_counter_reg ( |
| 860 | .scan_in(done_counter_reg_scanin), |
| 861 | .scan_out(done_counter_reg_scanout), |
| 862 | .din ( done_counter_in[2:0] ), |
| 863 | .dout ( done_counter_out[2:0] ), |
| 864 | .l1clk(l1clk), |
| 865 | .siclk(siclk), |
| 866 | .soclk(soclk)); |
| 867 | |
| 868 | // config_out[1] is AND'ed to force mbist_done low 2 cycles after mbist_start |
| 869 | // goes low. |
| 870 | |
| 871 | assign mbist_done = (&done_counter_out[2:0] == 1'b1) & config_out[1]; |
| 872 | assign done_counter_in[2:0] = reset_engine ? 3'b000: |
| 873 | msb & ~mbist_done & config_out[1] ? done_counter_out[2:0] + 3'b001: |
| 874 | done_counter_out[2:0]; |
| 875 | |
| 876 | |
| 877 | ///////////////////////////////////////////////////////////////////////// |
| 878 | // Creating the select lines. |
| 879 | ///////////////////////////////////////////////////////////////////////// |
| 880 | // array_sel[0] is to select between opd0 or opd1 (0: opd0; 1:opd1) |
| 881 | |
| 882 | assign opddq00_sel = ~array_sel[2] & ~array_sel[1] & ~array_sel[0]; |
| 883 | assign opddq10_sel = ~array_sel[2] & ~array_sel[1] & array_sel[0]; |
| 884 | |
| 885 | assign opddq01_sel = ~array_sel[2] & array_sel[1] & ~array_sel[0]; |
| 886 | assign opddq11_sel = ~array_sel[2] & array_sel[1] & array_sel[0]; |
| 887 | |
| 888 | assign opdhq0_sel = array_sel[2] & ~array_sel[1] & ~array_sel[0]; |
| 889 | assign opdhq1_sel = array_sel[2] & ~array_sel[1] & array_sel[0]; |
| 890 | |
| 891 | assign opd1_or_opd0_sel = array_sel[0]; // 0: opd0; 1:opd1 |
| 892 | |
| 893 | assign opdhq_sel = array_sel[2] & ~array_sel[1]; |
| 894 | assign opddq0_sel = ~array_sel[2] & ~array_sel[1]; |
| 895 | assign opddq1_sel = ~array_sel[2] & array_sel[1]; |
| 896 | |
| 897 | // rd_en and wr_en |
| 898 | |
| 899 | assign mbist_opddq00_rd_en = opddq00_sel && array_read; |
| 900 | assign mbist_opddq00_wr_en = opddq00_sel && array_write; |
| 901 | |
| 902 | assign mbist_opddq01_rd_en = opddq01_sel && array_read; |
| 903 | assign mbist_opddq01_wr_en = opddq01_sel && array_write; |
| 904 | |
| 905 | assign mbist_opddq10_rd_en = opddq10_sel && array_read; |
| 906 | assign mbist_opddq10_wr_en = opddq10_sel && array_write; |
| 907 | |
| 908 | assign mbist_opddq11_rd_en = opddq11_sel && array_read; |
| 909 | assign mbist_opddq11_wr_en = opddq11_sel && array_write; |
| 910 | |
| 911 | assign mbist_opdhq0_rd_en = opdhq0_sel && array_read; |
| 912 | assign mbist_opdhq0_wr_en = opdhq0_sel && array_write; |
| 913 | |
| 914 | assign mbist_opdhq1_rd_en = opdhq1_sel && array_read; |
| 915 | assign mbist_opdhq1_wr_en = opdhq1_sel && array_write; |
| 916 | |
| 917 | |
| 918 | // ///////////////////////////////////////////////////////////////////////////// |
| 919 | // Pipeline for Address, wdata, and Read_en |
| 920 | // ///////////////////////////////////////////////////////////////////////////// |
| 921 | |
| 922 | // Adding proper pipe stages for wdata |
| 923 | sio_mb1_ctl_msff_ctl_macro__width_8 data_pipe_reg1 ( |
| 924 | .scan_in(data_pipe_reg1_scanin), |
| 925 | .scan_out(data_pipe_reg1_scanout), |
| 926 | .din ( data_pipe_reg1_in[7:0] ), |
| 927 | .dout ( data_pipe_out1[7:0] ), |
| 928 | .l1clk(l1clk), |
| 929 | .siclk(siclk), |
| 930 | .soclk(soclk)); |
| 931 | |
| 932 | sio_mb1_ctl_msff_ctl_macro__width_8 data_pipe_reg2 ( |
| 933 | .scan_in(data_pipe_reg2_scanin), |
| 934 | .scan_out(data_pipe_reg2_scanout), |
| 935 | .din ( data_pipe_reg2_in[7:0] ), |
| 936 | .dout ( data_pipe_out2[7:0] ), |
| 937 | .l1clk(l1clk), |
| 938 | .siclk(siclk), |
| 939 | .soclk(soclk)); |
| 940 | |
| 941 | sio_mb1_ctl_msff_ctl_macro__width_8 data_pipe_reg3 ( |
| 942 | .scan_in(data_pipe_reg3_scanin), |
| 943 | .scan_out(data_pipe_reg3_scanout), |
| 944 | .din ( data_pipe_reg3_in[7:0] ), |
| 945 | .dout ( data_pipe_out3[7:0] ), |
| 946 | .l1clk(l1clk), |
| 947 | .siclk(siclk), |
| 948 | .soclk(soclk)); |
| 949 | |
| 950 | assign data_pipe_reg1_in[7:0] = reset_engine ? 8'h00: sio_mb1_wdata[7:0]; |
| 951 | assign data_pipe_reg2_in[7:0] = reset_engine ? 8'h00: data_pipe_out1[7:0]; |
| 952 | assign data_pipe_reg3_in[7:0] = reset_engine ? 8'h00: data_pipe_out2[7:0]; |
| 953 | |
| 954 | assign sio_opd_piped_wdata[7:0] = data_pipe_out3[7:0]; |
| 955 | |
| 956 | // Adding proper pipe stages for read_en |
| 957 | sio_mb1_ctl_msff_ctl_macro__width_1 ren_pipe_reg1 ( |
| 958 | .scan_in(ren_pipe_reg1_scanin), |
| 959 | .scan_out(ren_pipe_reg1_scanout), |
| 960 | .din ( ren_pipe_reg1_in ), |
| 961 | .dout ( ren_pipe_out1 ), |
| 962 | .l1clk(l1clk), |
| 963 | .siclk(siclk), |
| 964 | .soclk(soclk)); |
| 965 | |
| 966 | sio_mb1_ctl_msff_ctl_macro__width_1 ren_pipe_reg2 ( |
| 967 | .scan_in(ren_pipe_reg2_scanin), |
| 968 | .scan_out(ren_pipe_reg2_scanout), |
| 969 | .din ( ren_pipe_reg2_in ), |
| 970 | .dout ( ren_pipe_out2 ), |
| 971 | .l1clk(l1clk), |
| 972 | .siclk(siclk), |
| 973 | .soclk(soclk)); |
| 974 | |
| 975 | sio_mb1_ctl_msff_ctl_macro__width_1 ren_pipe_reg3 ( |
| 976 | .scan_in(ren_pipe_reg3_scanin), |
| 977 | .scan_out(ren_pipe_reg3_scanout), |
| 978 | .din ( ren_pipe_reg3_in ), |
| 979 | .dout ( ren_pipe_out3 ), |
| 980 | .l1clk(l1clk), |
| 981 | .siclk(siclk), |
| 982 | .soclk(soclk)); |
| 983 | |
| 984 | sio_mb1_ctl_msff_ctl_macro__width_1 ren_pipe_reg4 ( |
| 985 | .scan_in(ren_pipe_reg4_scanin), |
| 986 | .scan_out(ren_pipe_reg4_scanout), |
| 987 | .din ( ren_pipe_reg4_in ), |
| 988 | .dout ( ren_pipe_out4 ), |
| 989 | .l1clk(l1clk), |
| 990 | .siclk(siclk), |
| 991 | .soclk(soclk)); |
| 992 | |
| 993 | assign ren_pipe_reg1_in = reset_engine ? 1'b0: array_read; |
| 994 | assign ren_pipe_reg2_in = reset_engine ? 1'b0: ren_pipe_out1; |
| 995 | assign ren_pipe_reg3_in = reset_engine ? 1'b0: ren_pipe_out2; |
| 996 | assign ren_pipe_reg4_in = reset_engine ? 1'b0: ren_pipe_out3; |
| 997 | assign sio_opd_piped_ren = ren_pipe_out4; |
| 998 | |
| 999 | |
| 1000 | //Defining array_sel |
| 1001 | |
| 1002 | sio_mb1_ctl_msff_ctl_macro__width_3 opd_sel_reg1 ( |
| 1003 | .scan_in(opd_sel_reg1_scanin), |
| 1004 | .scan_out(opd_sel_reg1_scanout), |
| 1005 | .din ( { opdhq_sel_reg1_in, opddq0_sel_reg1_in, opddq1_sel_reg1_in } ), |
| 1006 | .dout ( { opdhq_sel_reg1_out, opddq0_sel_reg1_out, opddq1_sel_reg1_out } ), |
| 1007 | .l1clk(l1clk), |
| 1008 | .siclk(siclk), |
| 1009 | .soclk(soclk)); |
| 1010 | |
| 1011 | sio_mb1_ctl_msff_ctl_macro__width_3 opd_sel_reg2 ( |
| 1012 | .scan_in(opd_sel_reg2_scanin), |
| 1013 | .scan_out(opd_sel_reg2_scanout), |
| 1014 | .din ( { opdhq_sel_reg2_in, opddq0_sel_reg2_in, opddq1_sel_reg2_in } ), |
| 1015 | .dout ( { opdhq_sel_reg2_out, opddq0_sel_reg2_out, opddq1_sel_reg2_out } ), |
| 1016 | .l1clk(l1clk), |
| 1017 | .siclk(siclk), |
| 1018 | .soclk(soclk)); |
| 1019 | |
| 1020 | assign opdhq_sel_reg1_in = reset_engine ? 1'b0: opdhq_sel; |
| 1021 | assign opdhq_sel_reg2_in = reset_engine ? 1'b0: opdhq_sel_reg1_out; |
| 1022 | assign mbist_opdhq_sel = opdhq_sel_reg2_out; |
| 1023 | |
| 1024 | assign opddq0_sel_reg1_in = reset_engine ? 1'b0: opddq0_sel; |
| 1025 | assign opddq0_sel_reg2_in = reset_engine ? 1'b0: opddq0_sel_reg1_out; |
| 1026 | assign mbist_opddq0_sel = opddq0_sel_reg2_out; |
| 1027 | |
| 1028 | assign opddq1_sel_reg1_in = reset_engine ? 1'b0: opddq1_sel; |
| 1029 | assign opddq1_sel_reg2_in = reset_engine ? 1'b0: opddq1_sel_reg1_out; |
| 1030 | assign mbist_opddq1_sel = opddq1_sel_reg2_out; |
| 1031 | |
| 1032 | sio_mb1_ctl_msff_ctl_macro__width_3 opd_sel_reg4 ( |
| 1033 | .scan_in(opd_sel_reg4_scanin), |
| 1034 | .scan_out(opd_sel_reg4_scanout), |
| 1035 | .din ( { opdhq_sel_reg4_in, opddq0_sel_reg4_in, opddq1_sel_reg4_in } ), |
| 1036 | .dout ( { opdhq_sel_reg4_out, opddq0_sel_reg4_out, opddq1_sel_reg4_out } ), |
| 1037 | .l1clk(l1clk), |
| 1038 | .siclk(siclk), |
| 1039 | .soclk(soclk)); |
| 1040 | |
| 1041 | assign opdhq_sel_reg4_in = reset_engine ? 1'b0: sio_mb1_opdhq_sel; |
| 1042 | assign opddq0_sel_reg4_in = reset_engine ? 1'b0: sio_mb1_opddq0_sel; |
| 1043 | assign opddq1_sel_reg4_in = reset_engine ? 1'b0: sio_mb1_opddq1_sel; |
| 1044 | |
| 1045 | assign sio_mb1_opdhq_sel_piped = opdhq_sel_reg4_out; |
| 1046 | assign sio_mb1_opddq0_sel_piped = opddq0_sel_reg4_out; |
| 1047 | assign sio_mb1_opddq1_sel_piped = opddq1_sel_reg4_out; |
| 1048 | |
| 1049 | //opd1_or_opd0_sel |
| 1050 | sio_mb1_ctl_msff_ctl_macro__width_1 opd1or0_sel_reg1 ( |
| 1051 | .scan_in(opd1or0_sel_reg1_scanin), |
| 1052 | .scan_out(opd1or0_sel_reg1_scanout), |
| 1053 | .din ( opd1or0_sel_reg1_in ), |
| 1054 | .dout ( opd1or0_sel_out1 ), |
| 1055 | .l1clk(l1clk), |
| 1056 | .siclk(siclk), |
| 1057 | .soclk(soclk)); |
| 1058 | |
| 1059 | sio_mb1_ctl_msff_ctl_macro__width_1 opd1or0_sel_reg2 ( |
| 1060 | .scan_in(opd1or0_sel_reg2_scanin), |
| 1061 | .scan_out(opd1or0_sel_reg2_scanout), |
| 1062 | .din ( opd1or0_sel_reg2_in ), |
| 1063 | .dout ( opd1or0_sel_out2 ), |
| 1064 | .l1clk(l1clk), |
| 1065 | .siclk(siclk), |
| 1066 | .soclk(soclk)); |
| 1067 | |
| 1068 | sio_mb1_ctl_msff_ctl_macro__width_1 opd1or0_sel_reg3 ( |
| 1069 | .scan_in(opd1or0_sel_reg3_scanin), |
| 1070 | .scan_out(opd1or0_sel_reg3_scanout), |
| 1071 | .din ( opd1or0_sel_reg3_in ), |
| 1072 | .dout ( opd1or0_sel_out3 ), |
| 1073 | .l1clk(l1clk), |
| 1074 | .siclk(siclk), |
| 1075 | .soclk(soclk)); |
| 1076 | |
| 1077 | sio_mb1_ctl_msff_ctl_macro__width_1 opd1or0_sel_reg4 ( |
| 1078 | .scan_in(opd1or0_sel_reg4_scanin), |
| 1079 | .scan_out(opd1or0_sel_reg4_scanout), |
| 1080 | .din ( opd1or0_sel_reg4_in ), |
| 1081 | .dout ( opd1or0_sel_out4 ), |
| 1082 | .l1clk(l1clk), |
| 1083 | .siclk(siclk), |
| 1084 | .soclk(soclk)); |
| 1085 | |
| 1086 | assign opd1or0_sel_reg1_in = reset_engine ? 1'b0: opd1_or_opd0_sel; |
| 1087 | assign opd1or0_sel_reg2_in = reset_engine ? 1'b0: opd1or0_sel_out1; |
| 1088 | assign opd1or0_sel_reg3_in = reset_engine ? 1'b0: opd1or0_sel_out2; |
| 1089 | assign opd1or0_sel_reg4_in = reset_engine ? 1'b0: opd1or0_sel_out3; |
| 1090 | |
| 1091 | assign sio_mb1_opd1_or_opd0_sel = opd1or0_sel_out3; |
| 1092 | assign sio_mb1_opd1_or_opd0_sel_piped = opd1or0_sel_out4; |
| 1093 | |
| 1094 | |
| 1095 | assign opddq00_sel_piped = ~sio_mb1_opd1_or_opd0_sel_piped & sio_mb1_opddq0_sel_piped; |
| 1096 | assign opddq01_sel_piped = ~sio_mb1_opd1_or_opd0_sel_piped & sio_mb1_opddq1_sel_piped; |
| 1097 | |
| 1098 | assign opddq10_sel_piped = sio_mb1_opd1_or_opd0_sel_piped & sio_mb1_opddq0_sel_piped; |
| 1099 | assign opddq11_sel_piped = sio_mb1_opd1_or_opd0_sel_piped & sio_mb1_opddq1_sel_piped; |
| 1100 | |
| 1101 | assign opdhq0_sel_piped = ~sio_mb1_opd1_or_opd0_sel_piped & sio_mb1_opdhq_sel_piped; |
| 1102 | assign opdhq1_sel_piped = sio_mb1_opd1_or_opd0_sel_piped & sio_mb1_opdhq_sel_piped; |
| 1103 | |
| 1104 | |
| 1105 | // ///////////////////////////////////////////////////////////////////////////// |
| 1106 | // Spare gates |
| 1107 | // ///////////////////////////////////////////////////////////////////////////// |
| 1108 | |
| 1109 | sio_mb1_ctl_spare_ctl_macro__num_3 spares ( |
| 1110 | .scan_in(spares_scanin), |
| 1111 | .scan_out(spares_scanout), |
| 1112 | .l1clk (l1clk), |
| 1113 | .siclk(siclk), |
| 1114 | .soclk(soclk) |
| 1115 | ); |
| 1116 | |
| 1117 | // ///////////////////////////////////////////////////////////////////////////// |
| 1118 | // Shared Fail Detection |
| 1119 | // ///////////////////////////////////////////////////////////////////////////// |
| 1120 | // Updated to meet these new features: |
| 1121 | // 1.When mbist_done signal is asserted when it completes all the |
| 1122 | // tests, it also need to assert static membist fail signal if |
| 1123 | // there were any failures during the tests. |
| 1124 | // 2.The mbist_fail signal won't be sticky bit from membist |
| 1125 | // engine. The TCU will make it sticky fail bit as needed. |
| 1126 | |
| 1127 | |
| 1128 | // Pipelining the read_data to meet the sio timing requirement |
| 1129 | |
| 1130 | sio_mb1_ctl_msff_ctl_macro__width_72 read_data_pipe_reg ( |
| 1131 | .scan_in(read_data_pipe_reg_scanin), |
| 1132 | .scan_out(read_data_pipe_reg_scanout), |
| 1133 | .din ( opd1_or_opd0_read_data[71:0] ), |
| 1134 | .dout ( read_data_pipe[71:0] ), |
| 1135 | .l1clk(l1clk), |
| 1136 | .siclk(siclk), |
| 1137 | .soclk(soclk)); |
| 1138 | |
| 1139 | assign opd1_or_opd0_read_data[71:0] = sio_mb1_opd1_or_opd0_sel ? opd1_read_data[71:0]: |
| 1140 | opd0_read_data[71:0]; |
| 1141 | |
| 1142 | sio_mb1_ctl_msff_ctl_macro__width_6 fail_reg ( |
| 1143 | .scan_in(fail_reg_scanin), |
| 1144 | .scan_out(fail_reg_scanout), |
| 1145 | .din ( fail_reg_in[5:0] ), |
| 1146 | .dout ( fail_reg_out[5:0] ), |
| 1147 | .l1clk(l1clk), |
| 1148 | .siclk(siclk), |
| 1149 | .soclk(soclk)); |
| 1150 | |
| 1151 | |
| 1152 | assign fail_reg_in[5:0] = reset_engine ? 6'b0: {qual_sio_opdhq1_fail, qual_sio_opddq11_fail, qual_sio_opddq10_fail,qual_sio_opdhq0_fail, qual_sio_opddq01_fail, qual_sio_opddq00_fail} | fail_reg_out[5:0]; |
| 1153 | |
| 1154 | |
| 1155 | assign qual_sio_opddq00_fail = fail_detect && opddq00_sel_piped; |
| 1156 | assign qual_sio_opddq01_fail = fail_detect && opddq01_sel_piped; |
| 1157 | assign qual_sio_opdhq0_fail = fail_detect && opdhq0_sel_piped; |
| 1158 | assign qual_sio_opddq10_fail = fail_detect && opddq10_sel_piped; |
| 1159 | assign qual_sio_opddq11_fail = fail_detect && opddq11_sel_piped; |
| 1160 | assign qual_sio_opdhq1_fail = fail_detect && opdhq1_sel_piped; |
| 1161 | |
| 1162 | assign fail = mbist_done ? |fail_reg_out[5:0] : |
| 1163 | qual_sio_opddq00_fail | qual_sio_opddq01_fail | |
| 1164 | qual_sio_opdhq0_fail | qual_sio_opdhq1_fail | |
| 1165 | qual_sio_opddq10_fail | qual_sio_opddq11_fail; |
| 1166 | |
| 1167 | |
| 1168 | assign fail_detect = (opdhq0_sel_piped || opdhq1_sel_piped) ? |
| 1169 | (({ 40'b0, {4{sio_opd_piped_wdata[7:0]}} } != read_data_pipe[71:0]) && sio_opd_piped_ren): |
| 1170 | (({9{sio_opd_piped_wdata[7:0]}} != read_data_pipe[71:0]) && sio_opd_piped_ren); |
| 1171 | |
| 1172 | |
| 1173 | // fixscan start: |
| 1174 | assign config_reg_scanin = scan_in ; |
| 1175 | assign user_data_reg_scanin = config_reg_scanout ; |
| 1176 | assign user_start_addr_reg_scanin = user_data_reg_scanout ; |
| 1177 | assign user_stop_addr_reg_scanin = user_start_addr_reg_scanout; |
| 1178 | assign user_incr_addr_reg_scanin = user_stop_addr_reg_scanout; |
| 1179 | assign user_array_sel_reg_scanin = user_incr_addr_reg_scanout; |
| 1180 | assign user_bisi_wr_reg_scanin = user_array_sel_reg_scanout; |
| 1181 | assign user_bisi_rd_reg_scanin = user_bisi_wr_reg_scanout ; |
| 1182 | assign start_transition_reg_scanin = user_bisi_rd_reg_scanout ; |
| 1183 | assign run_reg_scanin = start_transition_reg_scanout; |
| 1184 | assign counter_reg_scanin = run_reg_scanout ; |
| 1185 | assign addr_reg_scanin = counter_reg_scanout ; |
| 1186 | assign wdata_reg_scanin = addr_reg_scanout ; |
| 1187 | assign wr_rd_en_reg0_scanin = wdata_reg_scanout ; |
| 1188 | assign wr_rd_en_reg1_scanin = wr_rd_en_reg0_scanout ; |
| 1189 | assign wr_rd_en_reg2_scanin = wr_rd_en_reg1_scanout ; |
| 1190 | assign wr_rd_en_reg3_scanin = wr_rd_en_reg2_scanout ; |
| 1191 | assign wr_rd_en_reg4_scanin = wr_rd_en_reg3_scanout ; |
| 1192 | assign wr_rd_en_reg5_scanin = wr_rd_en_reg4_scanout ; |
| 1193 | assign sel_reg_scanin = wr_rd_en_reg5_scanout ; |
| 1194 | assign done_reg_scanin = sel_reg_scanout ; |
| 1195 | assign new_fail_reg_scanin = done_reg_scanout ; |
| 1196 | assign control_reg_scanin = new_fail_reg_scanout ; |
| 1197 | assign done_counter_reg_scanin = control_reg_scanout ; |
| 1198 | assign data_pipe_reg1_scanin = done_counter_reg_scanout ; |
| 1199 | assign data_pipe_reg2_scanin = data_pipe_reg1_scanout ; |
| 1200 | assign data_pipe_reg3_scanin = data_pipe_reg2_scanout ; |
| 1201 | assign ren_pipe_reg1_scanin = data_pipe_reg3_scanout ; |
| 1202 | assign ren_pipe_reg2_scanin = ren_pipe_reg1_scanout ; |
| 1203 | assign ren_pipe_reg3_scanin = ren_pipe_reg2_scanout ; |
| 1204 | assign ren_pipe_reg4_scanin = ren_pipe_reg3_scanout ; |
| 1205 | assign opd_sel_reg1_scanin = ren_pipe_reg4_scanout ; |
| 1206 | assign opd_sel_reg2_scanin = opd_sel_reg1_scanout ; |
| 1207 | assign opd_sel_reg4_scanin = opd_sel_reg2_scanout ; |
| 1208 | assign opd1or0_sel_reg1_scanin = opd_sel_reg4_scanout ; |
| 1209 | assign opd1or0_sel_reg2_scanin = opd1or0_sel_reg1_scanout ; |
| 1210 | assign opd1or0_sel_reg3_scanin = opd1or0_sel_reg2_scanout ; |
| 1211 | assign opd1or0_sel_reg4_scanin = opd1or0_sel_reg3_scanout ; |
| 1212 | assign spares_scanin = opd1or0_sel_reg4_scanout ; |
| 1213 | assign read_data_pipe_reg_scanin = spares_scanout ; |
| 1214 | assign fail_reg_scanin = read_data_pipe_reg_scanout; |
| 1215 | assign scan_out = fail_reg_scanout ; |
| 1216 | // fixscan end: |
| 1217 | endmodule // sio_mbist_ctl |
| 1218 | |
| 1219 | |
| 1220 | |
| 1221 | |
| 1222 | |
| 1223 | |
| 1224 | // any PARAMS parms go into naming of macro |
| 1225 | |
| 1226 | module sio_mb1_ctl_l1clkhdr_ctl_macro ( |
| 1227 | l2clk, |
| 1228 | l1en, |
| 1229 | pce_ov, |
| 1230 | stop, |
| 1231 | se, |
| 1232 | l1clk); |
| 1233 | |
| 1234 | |
| 1235 | input l2clk; |
| 1236 | input l1en; |
| 1237 | input pce_ov; |
| 1238 | input stop; |
| 1239 | input se; |
| 1240 | output l1clk; |
| 1241 | |
| 1242 | |
| 1243 | |
| 1244 | |
| 1245 | |
| 1246 | cl_sc1_l1hdr_8x c_0 ( |
| 1247 | |
| 1248 | |
| 1249 | .l2clk(l2clk), |
| 1250 | .pce(l1en), |
| 1251 | .l1clk(l1clk), |
| 1252 | .se(se), |
| 1253 | .pce_ov(pce_ov), |
| 1254 | .stop(stop) |
| 1255 | ); |
| 1256 | |
| 1257 | |
| 1258 | |
| 1259 | endmodule |
| 1260 | |
| 1261 | |
| 1262 | |
| 1263 | |
| 1264 | |
| 1265 | |
| 1266 | |
| 1267 | |
| 1268 | |
| 1269 | |
| 1270 | |
| 1271 | |
| 1272 | |
| 1273 | // any PARAMS parms go into naming of macro |
| 1274 | |
| 1275 | module sio_mb1_ctl_msff_ctl_macro__width_8 ( |
| 1276 | din, |
| 1277 | l1clk, |
| 1278 | scan_in, |
| 1279 | siclk, |
| 1280 | soclk, |
| 1281 | dout, |
| 1282 | scan_out); |
| 1283 | wire [7:0] fdin; |
| 1284 | wire [6:0] so; |
| 1285 | |
| 1286 | input [7:0] din; |
| 1287 | input l1clk; |
| 1288 | input scan_in; |
| 1289 | |
| 1290 | |
| 1291 | input siclk; |
| 1292 | input soclk; |
| 1293 | |
| 1294 | output [7:0] dout; |
| 1295 | output scan_out; |
| 1296 | assign fdin[7:0] = din[7:0]; |
| 1297 | |
| 1298 | |
| 1299 | |
| 1300 | |
| 1301 | |
| 1302 | |
| 1303 | dff #(8) d0_0 ( |
| 1304 | .l1clk(l1clk), |
| 1305 | .siclk(siclk), |
| 1306 | .soclk(soclk), |
| 1307 | .d(fdin[7:0]), |
| 1308 | .si({scan_in,so[6:0]}), |
| 1309 | .so({so[6:0],scan_out}), |
| 1310 | .q(dout[7:0]) |
| 1311 | ); |
| 1312 | |
| 1313 | |
| 1314 | |
| 1315 | |
| 1316 | |
| 1317 | |
| 1318 | |
| 1319 | |
| 1320 | |
| 1321 | |
| 1322 | |
| 1323 | |
| 1324 | endmodule |
| 1325 | |
| 1326 | |
| 1327 | |
| 1328 | |
| 1329 | |
| 1330 | |
| 1331 | |
| 1332 | |
| 1333 | |
| 1334 | |
| 1335 | |
| 1336 | |
| 1337 | |
| 1338 | // any PARAMS parms go into naming of macro |
| 1339 | |
| 1340 | module sio_mb1_ctl_msff_ctl_macro__width_6 ( |
| 1341 | din, |
| 1342 | l1clk, |
| 1343 | scan_in, |
| 1344 | siclk, |
| 1345 | soclk, |
| 1346 | dout, |
| 1347 | scan_out); |
| 1348 | wire [5:0] fdin; |
| 1349 | wire [4:0] so; |
| 1350 | |
| 1351 | input [5:0] din; |
| 1352 | input l1clk; |
| 1353 | input scan_in; |
| 1354 | |
| 1355 | |
| 1356 | input siclk; |
| 1357 | input soclk; |
| 1358 | |
| 1359 | output [5:0] dout; |
| 1360 | output scan_out; |
| 1361 | assign fdin[5:0] = din[5:0]; |
| 1362 | |
| 1363 | |
| 1364 | |
| 1365 | |
| 1366 | |
| 1367 | |
| 1368 | dff #(6) d0_0 ( |
| 1369 | .l1clk(l1clk), |
| 1370 | .siclk(siclk), |
| 1371 | .soclk(soclk), |
| 1372 | .d(fdin[5:0]), |
| 1373 | .si({scan_in,so[4:0]}), |
| 1374 | .so({so[4:0],scan_out}), |
| 1375 | .q(dout[5:0]) |
| 1376 | ); |
| 1377 | |
| 1378 | |
| 1379 | |
| 1380 | |
| 1381 | |
| 1382 | |
| 1383 | |
| 1384 | |
| 1385 | |
| 1386 | |
| 1387 | |
| 1388 | |
| 1389 | endmodule |
| 1390 | |
| 1391 | |
| 1392 | |
| 1393 | |
| 1394 | |
| 1395 | |
| 1396 | |
| 1397 | |
| 1398 | |
| 1399 | |
| 1400 | |
| 1401 | |
| 1402 | |
| 1403 | // any PARAMS parms go into naming of macro |
| 1404 | |
| 1405 | module sio_mb1_ctl_msff_ctl_macro__width_3 ( |
| 1406 | din, |
| 1407 | l1clk, |
| 1408 | scan_in, |
| 1409 | siclk, |
| 1410 | soclk, |
| 1411 | dout, |
| 1412 | scan_out); |
| 1413 | wire [2:0] fdin; |
| 1414 | wire [1:0] so; |
| 1415 | |
| 1416 | input [2:0] din; |
| 1417 | input l1clk; |
| 1418 | input scan_in; |
| 1419 | |
| 1420 | |
| 1421 | input siclk; |
| 1422 | input soclk; |
| 1423 | |
| 1424 | output [2:0] dout; |
| 1425 | output scan_out; |
| 1426 | assign fdin[2:0] = din[2:0]; |
| 1427 | |
| 1428 | |
| 1429 | |
| 1430 | |
| 1431 | |
| 1432 | |
| 1433 | dff #(3) d0_0 ( |
| 1434 | .l1clk(l1clk), |
| 1435 | .siclk(siclk), |
| 1436 | .soclk(soclk), |
| 1437 | .d(fdin[2:0]), |
| 1438 | .si({scan_in,so[1:0]}), |
| 1439 | .so({so[1:0],scan_out}), |
| 1440 | .q(dout[2:0]) |
| 1441 | ); |
| 1442 | |
| 1443 | |
| 1444 | |
| 1445 | |
| 1446 | |
| 1447 | |
| 1448 | |
| 1449 | |
| 1450 | |
| 1451 | |
| 1452 | |
| 1453 | |
| 1454 | endmodule |
| 1455 | |
| 1456 | |
| 1457 | |
| 1458 | |
| 1459 | |
| 1460 | |
| 1461 | |
| 1462 | |
| 1463 | |
| 1464 | |
| 1465 | |
| 1466 | |
| 1467 | |
| 1468 | // any PARAMS parms go into naming of macro |
| 1469 | |
| 1470 | module sio_mb1_ctl_msff_ctl_macro__width_1 ( |
| 1471 | din, |
| 1472 | l1clk, |
| 1473 | scan_in, |
| 1474 | siclk, |
| 1475 | soclk, |
| 1476 | dout, |
| 1477 | scan_out); |
| 1478 | wire [0:0] fdin; |
| 1479 | |
| 1480 | input [0:0] din; |
| 1481 | input l1clk; |
| 1482 | input scan_in; |
| 1483 | |
| 1484 | |
| 1485 | input siclk; |
| 1486 | input soclk; |
| 1487 | |
| 1488 | output [0:0] dout; |
| 1489 | output scan_out; |
| 1490 | assign fdin[0:0] = din[0:0]; |
| 1491 | |
| 1492 | |
| 1493 | |
| 1494 | |
| 1495 | |
| 1496 | |
| 1497 | dff #(1) d0_0 ( |
| 1498 | .l1clk(l1clk), |
| 1499 | .siclk(siclk), |
| 1500 | .soclk(soclk), |
| 1501 | .d(fdin[0:0]), |
| 1502 | .si(scan_in), |
| 1503 | .so(scan_out), |
| 1504 | .q(dout[0:0]) |
| 1505 | ); |
| 1506 | |
| 1507 | |
| 1508 | |
| 1509 | |
| 1510 | |
| 1511 | |
| 1512 | |
| 1513 | |
| 1514 | |
| 1515 | |
| 1516 | |
| 1517 | |
| 1518 | endmodule |
| 1519 | |
| 1520 | |
| 1521 | |
| 1522 | |
| 1523 | |
| 1524 | |
| 1525 | |
| 1526 | |
| 1527 | |
| 1528 | |
| 1529 | |
| 1530 | |
| 1531 | |
| 1532 | // any PARAMS parms go into naming of macro |
| 1533 | |
| 1534 | module sio_mb1_ctl_msff_ctl_macro__width_4 ( |
| 1535 | din, |
| 1536 | l1clk, |
| 1537 | scan_in, |
| 1538 | siclk, |
| 1539 | soclk, |
| 1540 | dout, |
| 1541 | scan_out); |
| 1542 | wire [3:0] fdin; |
| 1543 | wire [2:0] so; |
| 1544 | |
| 1545 | input [3:0] din; |
| 1546 | input l1clk; |
| 1547 | input scan_in; |
| 1548 | |
| 1549 | |
| 1550 | input siclk; |
| 1551 | input soclk; |
| 1552 | |
| 1553 | output [3:0] dout; |
| 1554 | output scan_out; |
| 1555 | assign fdin[3:0] = din[3:0]; |
| 1556 | |
| 1557 | |
| 1558 | |
| 1559 | |
| 1560 | |
| 1561 | |
| 1562 | dff #(4) d0_0 ( |
| 1563 | .l1clk(l1clk), |
| 1564 | .siclk(siclk), |
| 1565 | .soclk(soclk), |
| 1566 | .d(fdin[3:0]), |
| 1567 | .si({scan_in,so[2:0]}), |
| 1568 | .so({so[2:0],scan_out}), |
| 1569 | .q(dout[3:0]) |
| 1570 | ); |
| 1571 | |
| 1572 | |
| 1573 | |
| 1574 | |
| 1575 | |
| 1576 | |
| 1577 | |
| 1578 | |
| 1579 | |
| 1580 | |
| 1581 | |
| 1582 | |
| 1583 | endmodule |
| 1584 | |
| 1585 | |
| 1586 | |
| 1587 | |
| 1588 | |
| 1589 | |
| 1590 | |
| 1591 | |
| 1592 | |
| 1593 | |
| 1594 | |
| 1595 | |
| 1596 | |
| 1597 | // any PARAMS parms go into naming of macro |
| 1598 | |
| 1599 | module sio_mb1_ctl_msff_ctl_macro__width_2 ( |
| 1600 | din, |
| 1601 | l1clk, |
| 1602 | scan_in, |
| 1603 | siclk, |
| 1604 | soclk, |
| 1605 | dout, |
| 1606 | scan_out); |
| 1607 | wire [1:0] fdin; |
| 1608 | wire [0:0] so; |
| 1609 | |
| 1610 | input [1:0] din; |
| 1611 | input l1clk; |
| 1612 | input scan_in; |
| 1613 | |
| 1614 | |
| 1615 | input siclk; |
| 1616 | input soclk; |
| 1617 | |
| 1618 | output [1:0] dout; |
| 1619 | output scan_out; |
| 1620 | assign fdin[1:0] = din[1:0]; |
| 1621 | |
| 1622 | |
| 1623 | |
| 1624 | |
| 1625 | |
| 1626 | |
| 1627 | dff #(2) d0_0 ( |
| 1628 | .l1clk(l1clk), |
| 1629 | .siclk(siclk), |
| 1630 | .soclk(soclk), |
| 1631 | .d(fdin[1:0]), |
| 1632 | .si({scan_in,so[0:0]}), |
| 1633 | .so({so[0:0],scan_out}), |
| 1634 | .q(dout[1:0]) |
| 1635 | ); |
| 1636 | |
| 1637 | |
| 1638 | |
| 1639 | |
| 1640 | |
| 1641 | |
| 1642 | |
| 1643 | |
| 1644 | |
| 1645 | |
| 1646 | |
| 1647 | |
| 1648 | endmodule |
| 1649 | |
| 1650 | |
| 1651 | |
| 1652 | |
| 1653 | |
| 1654 | |
| 1655 | |
| 1656 | |
| 1657 | |
| 1658 | |
| 1659 | |
| 1660 | |
| 1661 | |
| 1662 | // any PARAMS parms go into naming of macro |
| 1663 | |
| 1664 | module sio_mb1_ctl_msff_ctl_macro__width_21 ( |
| 1665 | din, |
| 1666 | l1clk, |
| 1667 | scan_in, |
| 1668 | siclk, |
| 1669 | soclk, |
| 1670 | dout, |
| 1671 | scan_out); |
| 1672 | wire [20:0] fdin; |
| 1673 | wire [19:0] so; |
| 1674 | |
| 1675 | input [20:0] din; |
| 1676 | input l1clk; |
| 1677 | input scan_in; |
| 1678 | |
| 1679 | |
| 1680 | input siclk; |
| 1681 | input soclk; |
| 1682 | |
| 1683 | output [20:0] dout; |
| 1684 | output scan_out; |
| 1685 | assign fdin[20:0] = din[20:0]; |
| 1686 | |
| 1687 | |
| 1688 | |
| 1689 | |
| 1690 | |
| 1691 | |
| 1692 | dff #(21) d0_0 ( |
| 1693 | .l1clk(l1clk), |
| 1694 | .siclk(siclk), |
| 1695 | .soclk(soclk), |
| 1696 | .d(fdin[20:0]), |
| 1697 | .si({scan_in,so[19:0]}), |
| 1698 | .so({so[19:0],scan_out}), |
| 1699 | .q(dout[20:0]) |
| 1700 | ); |
| 1701 | |
| 1702 | |
| 1703 | |
| 1704 | |
| 1705 | |
| 1706 | |
| 1707 | |
| 1708 | |
| 1709 | |
| 1710 | |
| 1711 | |
| 1712 | |
| 1713 | endmodule |
| 1714 | |
| 1715 | |
| 1716 | |
| 1717 | |
| 1718 | |
| 1719 | |
| 1720 | |
| 1721 | |
| 1722 | |
| 1723 | // Description: Spare gate macro for control blocks |
| 1724 | // |
| 1725 | // Param num controls the number of times the macro is added |
| 1726 | // flops=0 can be used to use only combination spare logic |
| 1727 | |
| 1728 | |
| 1729 | module sio_mb1_ctl_spare_ctl_macro__num_3 ( |
| 1730 | l1clk, |
| 1731 | scan_in, |
| 1732 | siclk, |
| 1733 | soclk, |
| 1734 | scan_out); |
| 1735 | wire si_0; |
| 1736 | wire so_0; |
| 1737 | wire spare0_flop_unused; |
| 1738 | wire spare0_buf_32x_unused; |
| 1739 | wire spare0_nand3_8x_unused; |
| 1740 | wire spare0_inv_8x_unused; |
| 1741 | wire spare0_aoi22_4x_unused; |
| 1742 | wire spare0_buf_8x_unused; |
| 1743 | wire spare0_oai22_4x_unused; |
| 1744 | wire spare0_inv_16x_unused; |
| 1745 | wire spare0_nand2_16x_unused; |
| 1746 | wire spare0_nor3_4x_unused; |
| 1747 | wire spare0_nand2_8x_unused; |
| 1748 | wire spare0_buf_16x_unused; |
| 1749 | wire spare0_nor2_16x_unused; |
| 1750 | wire spare0_inv_32x_unused; |
| 1751 | wire si_1; |
| 1752 | wire so_1; |
| 1753 | wire spare1_flop_unused; |
| 1754 | wire spare1_buf_32x_unused; |
| 1755 | wire spare1_nand3_8x_unused; |
| 1756 | wire spare1_inv_8x_unused; |
| 1757 | wire spare1_aoi22_4x_unused; |
| 1758 | wire spare1_buf_8x_unused; |
| 1759 | wire spare1_oai22_4x_unused; |
| 1760 | wire spare1_inv_16x_unused; |
| 1761 | wire spare1_nand2_16x_unused; |
| 1762 | wire spare1_nor3_4x_unused; |
| 1763 | wire spare1_nand2_8x_unused; |
| 1764 | wire spare1_buf_16x_unused; |
| 1765 | wire spare1_nor2_16x_unused; |
| 1766 | wire spare1_inv_32x_unused; |
| 1767 | wire si_2; |
| 1768 | wire so_2; |
| 1769 | wire spare2_flop_unused; |
| 1770 | wire spare2_buf_32x_unused; |
| 1771 | wire spare2_nand3_8x_unused; |
| 1772 | wire spare2_inv_8x_unused; |
| 1773 | wire spare2_aoi22_4x_unused; |
| 1774 | wire spare2_buf_8x_unused; |
| 1775 | wire spare2_oai22_4x_unused; |
| 1776 | wire spare2_inv_16x_unused; |
| 1777 | wire spare2_nand2_16x_unused; |
| 1778 | wire spare2_nor3_4x_unused; |
| 1779 | wire spare2_nand2_8x_unused; |
| 1780 | wire spare2_buf_16x_unused; |
| 1781 | wire spare2_nor2_16x_unused; |
| 1782 | wire spare2_inv_32x_unused; |
| 1783 | |
| 1784 | |
| 1785 | input l1clk; |
| 1786 | input scan_in; |
| 1787 | input siclk; |
| 1788 | input soclk; |
| 1789 | output scan_out; |
| 1790 | |
| 1791 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), |
| 1792 | .siclk(siclk), |
| 1793 | .soclk(soclk), |
| 1794 | .si(si_0), |
| 1795 | .so(so_0), |
| 1796 | .d(1'b0), |
| 1797 | .q(spare0_flop_unused)); |
| 1798 | assign si_0 = scan_in; |
| 1799 | |
| 1800 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), |
| 1801 | .out(spare0_buf_32x_unused)); |
| 1802 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), |
| 1803 | .in1(1'b1), |
| 1804 | .in2(1'b1), |
| 1805 | .out(spare0_nand3_8x_unused)); |
| 1806 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), |
| 1807 | .out(spare0_inv_8x_unused)); |
| 1808 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), |
| 1809 | .in01(1'b1), |
| 1810 | .in10(1'b1), |
| 1811 | .in11(1'b1), |
| 1812 | .out(spare0_aoi22_4x_unused)); |
| 1813 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), |
| 1814 | .out(spare0_buf_8x_unused)); |
| 1815 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), |
| 1816 | .in01(1'b1), |
| 1817 | .in10(1'b1), |
| 1818 | .in11(1'b1), |
| 1819 | .out(spare0_oai22_4x_unused)); |
| 1820 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), |
| 1821 | .out(spare0_inv_16x_unused)); |
| 1822 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), |
| 1823 | .in1(1'b1), |
| 1824 | .out(spare0_nand2_16x_unused)); |
| 1825 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), |
| 1826 | .in1(1'b0), |
| 1827 | .in2(1'b0), |
| 1828 | .out(spare0_nor3_4x_unused)); |
| 1829 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), |
| 1830 | .in1(1'b1), |
| 1831 | .out(spare0_nand2_8x_unused)); |
| 1832 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), |
| 1833 | .out(spare0_buf_16x_unused)); |
| 1834 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), |
| 1835 | .in1(1'b0), |
| 1836 | .out(spare0_nor2_16x_unused)); |
| 1837 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), |
| 1838 | .out(spare0_inv_32x_unused)); |
| 1839 | |
| 1840 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), |
| 1841 | .siclk(siclk), |
| 1842 | .soclk(soclk), |
| 1843 | .si(si_1), |
| 1844 | .so(so_1), |
| 1845 | .d(1'b0), |
| 1846 | .q(spare1_flop_unused)); |
| 1847 | assign si_1 = so_0; |
| 1848 | |
| 1849 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), |
| 1850 | .out(spare1_buf_32x_unused)); |
| 1851 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), |
| 1852 | .in1(1'b1), |
| 1853 | .in2(1'b1), |
| 1854 | .out(spare1_nand3_8x_unused)); |
| 1855 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), |
| 1856 | .out(spare1_inv_8x_unused)); |
| 1857 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), |
| 1858 | .in01(1'b1), |
| 1859 | .in10(1'b1), |
| 1860 | .in11(1'b1), |
| 1861 | .out(spare1_aoi22_4x_unused)); |
| 1862 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), |
| 1863 | .out(spare1_buf_8x_unused)); |
| 1864 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), |
| 1865 | .in01(1'b1), |
| 1866 | .in10(1'b1), |
| 1867 | .in11(1'b1), |
| 1868 | .out(spare1_oai22_4x_unused)); |
| 1869 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), |
| 1870 | .out(spare1_inv_16x_unused)); |
| 1871 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), |
| 1872 | .in1(1'b1), |
| 1873 | .out(spare1_nand2_16x_unused)); |
| 1874 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), |
| 1875 | .in1(1'b0), |
| 1876 | .in2(1'b0), |
| 1877 | .out(spare1_nor3_4x_unused)); |
| 1878 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), |
| 1879 | .in1(1'b1), |
| 1880 | .out(spare1_nand2_8x_unused)); |
| 1881 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), |
| 1882 | .out(spare1_buf_16x_unused)); |
| 1883 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), |
| 1884 | .in1(1'b0), |
| 1885 | .out(spare1_nor2_16x_unused)); |
| 1886 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), |
| 1887 | .out(spare1_inv_32x_unused)); |
| 1888 | |
| 1889 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), |
| 1890 | .siclk(siclk), |
| 1891 | .soclk(soclk), |
| 1892 | .si(si_2), |
| 1893 | .so(so_2), |
| 1894 | .d(1'b0), |
| 1895 | .q(spare2_flop_unused)); |
| 1896 | assign si_2 = so_1; |
| 1897 | |
| 1898 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), |
| 1899 | .out(spare2_buf_32x_unused)); |
| 1900 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), |
| 1901 | .in1(1'b1), |
| 1902 | .in2(1'b1), |
| 1903 | .out(spare2_nand3_8x_unused)); |
| 1904 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), |
| 1905 | .out(spare2_inv_8x_unused)); |
| 1906 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), |
| 1907 | .in01(1'b1), |
| 1908 | .in10(1'b1), |
| 1909 | .in11(1'b1), |
| 1910 | .out(spare2_aoi22_4x_unused)); |
| 1911 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), |
| 1912 | .out(spare2_buf_8x_unused)); |
| 1913 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), |
| 1914 | .in01(1'b1), |
| 1915 | .in10(1'b1), |
| 1916 | .in11(1'b1), |
| 1917 | .out(spare2_oai22_4x_unused)); |
| 1918 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), |
| 1919 | .out(spare2_inv_16x_unused)); |
| 1920 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), |
| 1921 | .in1(1'b1), |
| 1922 | .out(spare2_nand2_16x_unused)); |
| 1923 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), |
| 1924 | .in1(1'b0), |
| 1925 | .in2(1'b0), |
| 1926 | .out(spare2_nor3_4x_unused)); |
| 1927 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), |
| 1928 | .in1(1'b1), |
| 1929 | .out(spare2_nand2_8x_unused)); |
| 1930 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), |
| 1931 | .out(spare2_buf_16x_unused)); |
| 1932 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), |
| 1933 | .in1(1'b0), |
| 1934 | .out(spare2_nor2_16x_unused)); |
| 1935 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), |
| 1936 | .out(spare2_inv_32x_unused)); |
| 1937 | assign scan_out = so_2; |
| 1938 | |
| 1939 | |
| 1940 | |
| 1941 | endmodule |
| 1942 | |
| 1943 | |
| 1944 | |
| 1945 | |
| 1946 | |
| 1947 | |
| 1948 | // any PARAMS parms go into naming of macro |
| 1949 | |
| 1950 | module sio_mb1_ctl_msff_ctl_macro__width_72 ( |
| 1951 | din, |
| 1952 | l1clk, |
| 1953 | scan_in, |
| 1954 | siclk, |
| 1955 | soclk, |
| 1956 | dout, |
| 1957 | scan_out); |
| 1958 | wire [71:0] fdin; |
| 1959 | wire [70:0] so; |
| 1960 | |
| 1961 | input [71:0] din; |
| 1962 | input l1clk; |
| 1963 | input scan_in; |
| 1964 | |
| 1965 | |
| 1966 | input siclk; |
| 1967 | input soclk; |
| 1968 | |
| 1969 | output [71:0] dout; |
| 1970 | output scan_out; |
| 1971 | assign fdin[71:0] = din[71:0]; |
| 1972 | |
| 1973 | |
| 1974 | |
| 1975 | |
| 1976 | |
| 1977 | |
| 1978 | dff #(72) d0_0 ( |
| 1979 | .l1clk(l1clk), |
| 1980 | .siclk(siclk), |
| 1981 | .soclk(soclk), |
| 1982 | .d(fdin[71:0]), |
| 1983 | .si({scan_in,so[70:0]}), |
| 1984 | .so({so[70:0],scan_out}), |
| 1985 | .q(dout[71:0]) |
| 1986 | ); |
| 1987 | |
| 1988 | |
| 1989 | |
| 1990 | |
| 1991 | |
| 1992 | |
| 1993 | |
| 1994 | |
| 1995 | |
| 1996 | |
| 1997 | |
| 1998 | |
| 1999 | endmodule |
| 2000 | |
| 2001 | |
| 2002 | |
| 2003 | |
| 2004 | |
| 2005 | |
| 2006 | |
| 2007 | |