| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dec.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dec ( |
| 36 | l2clk, |
| 37 | scan_in, |
| 38 | tcu_pce_ov, |
| 39 | spc_aclk, |
| 40 | spc_bclk, |
| 41 | tcu_scan_en, |
| 42 | power_throttle, |
| 43 | lb_lbist_running, |
| 44 | lsu_dec_pmen, |
| 45 | lsu_exu_pmen, |
| 46 | spc_core_running_status, |
| 47 | exu_test_tid0, |
| 48 | exu_test_addr0, |
| 49 | exu_test_valid0, |
| 50 | exu_test_tid1, |
| 51 | exu_test_addr1, |
| 52 | exu_test_valid1, |
| 53 | tlu_cerer_icdp, |
| 54 | tlu_dec_pstate_pef, |
| 55 | fgu_fprs_fef, |
| 56 | tlu_dec_hpstate_hpriv, |
| 57 | tlu_dec_pstate_priv, |
| 58 | tlu_pstate_am, |
| 59 | tlu_window_block, |
| 60 | exu0_window_block, |
| 61 | exu1_window_block, |
| 62 | lsu_cpq_stall, |
| 63 | ifu_buf0_inst0, |
| 64 | ifu_buf0_inst1, |
| 65 | ifu_buf0_inst2, |
| 66 | ifu_buf0_inst3, |
| 67 | ifu_buf0_inst4, |
| 68 | ifu_buf0_inst5, |
| 69 | ifu_buf0_inst6, |
| 70 | ifu_buf0_inst7, |
| 71 | ifu_buf0_excp0, |
| 72 | ifu_buf0_excp1, |
| 73 | ifu_buf0_excp2, |
| 74 | ifu_buf0_excp3, |
| 75 | ifu_buf0_excp4, |
| 76 | ifu_buf0_excp5, |
| 77 | ifu_buf0_excp6, |
| 78 | ifu_buf0_excp7, |
| 79 | tlu_flush_ifu, |
| 80 | pku_load_flush_w, |
| 81 | pku_inst_cnt_brtaken00, |
| 82 | pku_inst_cnt_brtaken01, |
| 83 | pku_inst_cnt_brtaken02, |
| 84 | pku_inst_cnt_brtaken03, |
| 85 | pku_inst_cnt_brtaken04, |
| 86 | pku_inst_cnt_brtaken05, |
| 87 | pku_inst_cnt_brtaken06, |
| 88 | pku_inst_cnt_brtaken07, |
| 89 | pku_inst_cnt_brtaken10, |
| 90 | pku_inst_cnt_brtaken11, |
| 91 | pku_inst_cnt_brtaken12, |
| 92 | pku_inst_cnt_brtaken13, |
| 93 | pku_inst_cnt_brtaken14, |
| 94 | pku_inst_cnt_brtaken15, |
| 95 | pku_inst_cnt_brtaken16, |
| 96 | pku_inst_cnt_brtaken17, |
| 97 | pku_base_pick_p, |
| 98 | pku_raw_pick0_p, |
| 99 | pku_raw_pick1_p, |
| 100 | pku_annul_ds_dcti_brtaken0_e, |
| 101 | pku_annul_ds_dcti_brtaken1_e, |
| 102 | pku_valid_e, |
| 103 | pku_ds_e, |
| 104 | pku_lsu_p, |
| 105 | pku_fgu_p, |
| 106 | pku_pdist_p, |
| 107 | pku_twocycle_p, |
| 108 | pku_idest_p, |
| 109 | pku_fdest_p, |
| 110 | pku_fsrc_rd_p, |
| 111 | pku_isrc_rs1_p, |
| 112 | pku_isrc_rs2_p, |
| 113 | pku_isrc_rd_p, |
| 114 | pku_flush_f1, |
| 115 | pku_flush_f2, |
| 116 | pku_flush_lm, |
| 117 | pku_flush_lb, |
| 118 | pku_flush_m, |
| 119 | pku_flush_b, |
| 120 | spu_mult_request, |
| 121 | lsu_block_store_stall, |
| 122 | lsu_block_store_rd, |
| 123 | lsu_block_store_tid, |
| 124 | tlu_dtlb_reload_stall, |
| 125 | fgu_ecc_asi_stall, |
| 126 | exu0_oddwin_b, |
| 127 | exu1_oddwin_b, |
| 128 | fgu_idiv_stall, |
| 129 | fgu_fdiv_stall, |
| 130 | dec_br_taken_e1, |
| 131 | del_pick_d, |
| 132 | dec_inst0_rd_d, |
| 133 | dec_inst1_rd_d, |
| 134 | dec_rs1_addr0_e, |
| 135 | dec_rs1_addr1_e, |
| 136 | dec_inst0_d, |
| 137 | dec_inst1_d, |
| 138 | dec_decode0_d, |
| 139 | dec_decode1_d, |
| 140 | dec_valid0_d, |
| 141 | dec_valid1_d, |
| 142 | dec_true_valid_e, |
| 143 | dec_tid0_d, |
| 144 | dec_tid1_d, |
| 145 | dec_tid0_p, |
| 146 | dec_tid1_p, |
| 147 | dec_raw_pick_p, |
| 148 | dec_inst0_rs1_p, |
| 149 | dec_inst0_rs2_p, |
| 150 | dec_inst0_rs3_p, |
| 151 | dec_inst0_rs1_vld_p, |
| 152 | dec_inst0_rs2_vld_p, |
| 153 | dec_inst0_rs3_vld_p, |
| 154 | dec_inst1_rs1_p, |
| 155 | dec_inst1_rs2_p, |
| 156 | dec_inst1_rs3_p, |
| 157 | dec_inst1_rs1_vld_p, |
| 158 | dec_inst1_rs2_vld_p, |
| 159 | dec_inst1_rs3_vld_p, |
| 160 | dec_frf_r1_addr_d, |
| 161 | dec_frf_r2_addr_d, |
| 162 | dec_frf_r1_vld_d, |
| 163 | dec_frf_r2_vld_d, |
| 164 | dec_frf_r1_32b_d, |
| 165 | dec_frf_r2_32b_d, |
| 166 | dec_frf_r1_odd32b_d, |
| 167 | dec_frf_r2_odd32b_d, |
| 168 | dec_frf_w_addr_d, |
| 169 | dec_frf_w_vld_d, |
| 170 | dec_frf_w_32b_d, |
| 171 | dec_frf_w_odd32b_d, |
| 172 | dec_exu_src_vld_d, |
| 173 | dec_irf_w_addr_d, |
| 174 | dec_frf_store_d, |
| 175 | dec_fsr_store_d, |
| 176 | dec_fgu_op3_d, |
| 177 | dec_fgu_opf_d, |
| 178 | dec_fgu_decode_d, |
| 179 | dec_fgu_tid_d, |
| 180 | dec_flush_f1, |
| 181 | dec_flush_f2, |
| 182 | dec_flush_lm, |
| 183 | dec_flush_lb, |
| 184 | dec_flush_m, |
| 185 | dec_flush_b, |
| 186 | dec_spu_grant_d, |
| 187 | dec_spu_grant_fgu_d, |
| 188 | dec_block_store_b, |
| 189 | dec_load_flush_w, |
| 190 | dec_exc0_m, |
| 191 | dec_exc1_m, |
| 192 | dec_inst0_cnt, |
| 193 | dec_inst1_cnt, |
| 194 | dec_tid0_m, |
| 195 | dec_tid1_m, |
| 196 | dec_inst_valid_m, |
| 197 | dec_lsu_inst_m, |
| 198 | dec_fgu_inst_m, |
| 199 | dec_cti_inst_m, |
| 200 | dec_illegal_inst_m, |
| 201 | dec_icache_perr_m, |
| 202 | dec_priv_exc_m, |
| 203 | dec_hpriv_exc_m, |
| 204 | dec_fpdisable_exc_m, |
| 205 | dec_br_taken_m, |
| 206 | dec_done_inst_m, |
| 207 | dec_retry_inst_m, |
| 208 | dec_sir_inst_m, |
| 209 | dec_annul_ds_m, |
| 210 | dec_ds_m, |
| 211 | dec_fgu_sel_e, |
| 212 | dec_fgu_sel_m, |
| 213 | dec_lsu_sel0_e, |
| 214 | dec_lsu_sel1_e, |
| 215 | dec_lsu_sel0_lower_e, |
| 216 | dec_lsu_sel1_lower_e, |
| 217 | dec_lsu_sel0_upper_e, |
| 218 | dec_lsu_sel1_upper_e, |
| 219 | dec_rs1_addr0_upper_e, |
| 220 | dec_rs1_addr1_upper_e, |
| 221 | dec_ld_inst_e, |
| 222 | dec_st_inst_e, |
| 223 | dec_fsr_ldst_e, |
| 224 | dec_fpldst_inst_e, |
| 225 | dec_ldst_dbl_e, |
| 226 | dec_pref_inst_e, |
| 227 | dec_flush_inst_e, |
| 228 | dec_memstbar_inst_e, |
| 229 | dec_ldst_sz_e, |
| 230 | dec_frf_r2_addr_e, |
| 231 | dec_sr_inst_e, |
| 232 | dec_pr_inst_e, |
| 233 | dec_hpr_inst_e, |
| 234 | dec_casa_inst_e, |
| 235 | dec_ldstub_inst_e, |
| 236 | dec_swap_inst_e, |
| 237 | dec_altspace_d, |
| 238 | dec_sign_ext_e, |
| 239 | dec_sraddr_e, |
| 240 | dec_imm_asi_vld_d, |
| 241 | dec_imm_asi_d, |
| 242 | dec_lsu_tid0_d, |
| 243 | dec_lsu_tid1_d, |
| 244 | dec_lsu_tg_d, |
| 245 | dec_lsu_rd_e, |
| 246 | dec_ld_inst_d, |
| 247 | dec_instr0_type_d, |
| 248 | dec_instr1_type_d, |
| 249 | dec_valid_e, |
| 250 | dec_pmu_valid_e, |
| 251 | dec_fgu_valid_e, |
| 252 | dec_exu_clken, |
| 253 | dec_lsu_sel0_d, |
| 254 | dec_ierr_d, |
| 255 | dec_block_store_stall, |
| 256 | scan_out); |
| 257 | wire del_scanin; |
| 258 | wire del_scanout; |
| 259 | wire ded0_scanin; |
| 260 | wire ded0_scanout; |
| 261 | wire [1:0] del_tg_clken; |
| 262 | wire del_test0_sel_p; |
| 263 | wire del_twocycle0_std_p; |
| 264 | wire del_twocycle0_rs2_p; |
| 265 | wire del_default0_sel_p; |
| 266 | wire [4:0] del_test_addr0_p; |
| 267 | wire del_noshift0_d; |
| 268 | wire [1:0] ded_ferr_p; |
| 269 | wire [1:0] ded_perr_p; |
| 270 | wire [1:0] ded_ferr_d; |
| 271 | wire [1:0] ded_perr_d; |
| 272 | wire [1:0] ded_legal_p; |
| 273 | wire ded_oddwin0_d; |
| 274 | wire [4:0] ded_exc0_d; |
| 275 | wire ded1_scanin; |
| 276 | wire ded1_scanout; |
| 277 | wire del_test1_sel_p; |
| 278 | wire del_twocycle1_std_p; |
| 279 | wire del_twocycle1_rs2_p; |
| 280 | wire del_default1_sel_p; |
| 281 | wire [4:0] del_test_addr1_p; |
| 282 | wire del_noshift1_d; |
| 283 | wire ded_oddwin1_d; |
| 284 | wire [4:0] ded_exc1_d; |
| 285 | wire [1:0] dcd_sir_d; |
| 286 | wire [1:0] dcd_stdfa_d; |
| 287 | wire [1:0] dcd_save_restore_d; |
| 288 | wire [1:0] dcd_exu_src_d; |
| 289 | wire [1:0] dcd_killfgu_d; |
| 290 | wire [1:0] dcd_lsize0_d; |
| 291 | wire [1:0] dcd_lsu_sign_ext_d; |
| 292 | wire [1:0] dcd_load_d; |
| 293 | wire [1:0] dcd_store_d; |
| 294 | wire [1:0] dcd_lsdouble_d; |
| 295 | wire [1:0] dcd_prefetch_d; |
| 296 | wire [1:0] dcd_flush_d; |
| 297 | wire [1:0] dcd_memstbar_d; |
| 298 | wire [1:0] dcd_hpr_d; |
| 299 | wire [1:0] dcd_pr_d; |
| 300 | wire [1:0] dcd_priv_d; |
| 301 | wire [1:0] dcd_sr_d; |
| 302 | wire [1:0] dcd_casa_d; |
| 303 | wire [1:0] dcd_ldstub_d; |
| 304 | wire [1:0] dcd_alt_d; |
| 305 | wire [1:0] dcd_alti_d; |
| 306 | wire [1:0] dcd_swap_d; |
| 307 | wire [1:0] dcd_done_d; |
| 308 | wire [1:0] dcd_retry_d; |
| 309 | wire [1:0] dcd_fsrc_rs1_d; |
| 310 | wire [1:0] dcd_fsrc_rs2_d; |
| 311 | wire [1:0] dcd_fpdest_single_d; |
| 312 | wire [1:0] dcd_fp_rs1_single_d; |
| 313 | wire [1:0] dcd_fp_rs2_single_d; |
| 314 | wire [1:0] dcd_fsrsync_d; |
| 315 | wire [1:0] dcd_callclass_d; |
| 316 | wire [1:0] dcd_specbr_d; |
| 317 | wire [1:0] dcd_specfp_d; |
| 318 | wire [1:0] dcd_tcc_d; |
| 319 | wire [1:0] dcd_sethi_d; |
| 320 | wire [1:0] dcd_fpdisable_d; |
| 321 | wire [1:0] dcd_wrtick_d; |
| 322 | wire [1:0] dcd_lsize1_d; |
| 323 | |
| 324 | input l2clk; |
| 325 | input scan_in; |
| 326 | input tcu_pce_ov; // scan signals |
| 327 | input spc_aclk; |
| 328 | input spc_bclk; |
| 329 | input tcu_scan_en; |
| 330 | |
| 331 | input [2:0] power_throttle; // power throttle, [2:0] is encoded number of stalls in 8 cycle window |
| 332 | // 000 - no stalls, 001 - 1 stall, ... 111 - 7 stalls |
| 333 | |
| 334 | input lb_lbist_running; |
| 335 | |
| 336 | input lsu_dec_pmen; // power management enable for dec |
| 337 | input lsu_exu_pmen; // power management enable for exu |
| 338 | |
| 339 | input [7:0] spc_core_running_status; // active bits for each of the threads |
| 340 | |
| 341 | input [1:0] exu_test_tid0; // exu test interface to the irf (bist or ecc errors) |
| 342 | input [4:0] exu_test_addr0; |
| 343 | input exu_test_valid0; |
| 344 | |
| 345 | input [1:0] exu_test_tid1; // exu test interface to the irf (bist or ecc errors) |
| 346 | input [4:0] exu_test_addr1; |
| 347 | input exu_test_valid1; |
| 348 | |
| 349 | input tlu_cerer_icdp; // enable for icdp perr |
| 350 | |
| 351 | input [7:0] tlu_dec_pstate_pef; // pstate enable fp bit |
| 352 | input [7:0] fgu_fprs_fef; // fprs enable fp bit |
| 353 | input [7:0] tlu_dec_hpstate_hpriv; // hpriv bits |
| 354 | input [7:0] tlu_dec_pstate_priv; // priv bits |
| 355 | |
| 356 | input [7:0] tlu_pstate_am; // address mask bit from the pstate register |
| 357 | |
| 358 | input [1:0] tlu_window_block; // tlu is doing a window operation and needs a hole created |
| 359 | |
| 360 | input exu0_window_block; // exu0 is doing a window operation and needs a hole created |
| 361 | input exu1_window_block; // exu1 is doing a window operation and needs a hole created |
| 362 | |
| 363 | input lsu_cpq_stall; // lsu stalls all other lsu ops at decode |
| 364 | |
| 365 | input [32:0] ifu_buf0_inst0; // instructions for each of the threads |
| 366 | input [32:0] ifu_buf0_inst1; |
| 367 | input [32:0] ifu_buf0_inst2; |
| 368 | input [32:0] ifu_buf0_inst3; |
| 369 | input [32:0] ifu_buf0_inst4; |
| 370 | input [32:0] ifu_buf0_inst5; |
| 371 | input [32:0] ifu_buf0_inst6; |
| 372 | input [32:0] ifu_buf0_inst7; |
| 373 | |
| 374 | input [4:0] ifu_buf0_excp0; // encoding of the various fetch exceptions that can occur |
| 375 | input [4:0] ifu_buf0_excp1; |
| 376 | input [4:0] ifu_buf0_excp2; |
| 377 | input [4:0] ifu_buf0_excp3; |
| 378 | input [4:0] ifu_buf0_excp4; |
| 379 | input [4:0] ifu_buf0_excp5; |
| 380 | input [4:0] ifu_buf0_excp6; |
| 381 | input [4:0] ifu_buf0_excp7; |
| 382 | |
| 383 | input [7:0] tlu_flush_ifu; |
| 384 | |
| 385 | input [7:0] pku_load_flush_w; |
| 386 | |
| 387 | input [1:0] pku_inst_cnt_brtaken00; // count of instructions at e,m,b stages needed to compute the PC at decode (to tlu) |
| 388 | input [1:0] pku_inst_cnt_brtaken01; |
| 389 | input [1:0] pku_inst_cnt_brtaken02; |
| 390 | input [1:0] pku_inst_cnt_brtaken03; |
| 391 | input [1:0] pku_inst_cnt_brtaken04; |
| 392 | input [1:0] pku_inst_cnt_brtaken05; |
| 393 | input [1:0] pku_inst_cnt_brtaken06; |
| 394 | input [1:0] pku_inst_cnt_brtaken07; |
| 395 | |
| 396 | input [1:0] pku_inst_cnt_brtaken10; // count of instructions at e,m,b stages needed to compute the PC at decode (to tlu) |
| 397 | input [1:0] pku_inst_cnt_brtaken11; |
| 398 | input [1:0] pku_inst_cnt_brtaken12; |
| 399 | input [1:0] pku_inst_cnt_brtaken13; |
| 400 | input [1:0] pku_inst_cnt_brtaken14; |
| 401 | input [1:0] pku_inst_cnt_brtaken15; |
| 402 | input [1:0] pku_inst_cnt_brtaken16; |
| 403 | input [1:0] pku_inst_cnt_brtaken17; |
| 404 | |
| 405 | input [7:0] pku_base_pick_p; // base pick signals with swl_cancel_pick but not decode cancel |
| 406 | |
| 407 | input [3:0] pku_raw_pick0_p; // raw pick signals to ifu to mux pc addresses (no swl_cancel_pick or decode cancel) |
| 408 | input [7:4] pku_raw_pick1_p; |
| 409 | |
| 410 | input [7:0] pku_annul_ds_dcti_brtaken0_e; // the DS of the dcti at the e stage is annulled this cycle |
| 411 | input [7:0] pku_annul_ds_dcti_brtaken1_e; // the DS of the dcti at the e stage is annulled this cycle |
| 412 | |
| 413 | input [7:0] pku_valid_e; // inst at e stage is valid (takes annul into account) |
| 414 | |
| 415 | input [7:0] pku_ds_e; // inst at e stage is a DS (tlu) |
| 416 | |
| 417 | input [7:0] pku_lsu_p; // lsu op at pick |
| 418 | input [7:0] pku_fgu_p; // fgu op at pick |
| 419 | input [7:0] pku_pdist_p; // pdist op at pick |
| 420 | input [7:0] pku_twocycle_p; // twocycle op at pick (std or casa) |
| 421 | input [7:0] pku_idest_p; // inst at p has int dest |
| 422 | input [7:0] pku_fdest_p; // inst at p has fp dest |
| 423 | |
| 424 | input [7:0] pku_fsrc_rd_p; // inst at p has fp rd src |
| 425 | input [7:0] pku_isrc_rs1_p; // inst at p has rs1 src |
| 426 | input [7:0] pku_isrc_rs2_p; // inst at p has rs2 src |
| 427 | input [7:0] pku_isrc_rd_p; // inst at p has rd src |
| 428 | |
| 429 | input [7:0] pku_flush_f1; // flush inst at f1 in the fgu pipe |
| 430 | input [7:0] pku_flush_f2; // flush inst at f2 in the fgu pipe |
| 431 | input [7:0] pku_flush_lm; // flush inst at m in the lsu pipe |
| 432 | input [7:0] pku_flush_lb; // flush inst at b in the lsu pipe |
| 433 | input [7:0] pku_flush_m; // flush inst at m in the integer pipe |
| 434 | input [7:0] pku_flush_b; // flush inst at b in the integer pipe |
| 435 | |
| 436 | input spu_mult_request; // spu is requesting a hole be created for running a crypto multiply through the fgu pipe |
| 437 | |
| 438 | input lsu_block_store_stall; // stall decode to read the sources of the store |
| 439 | input [4:3] lsu_block_store_rd; // rd of the block store |
| 440 | input [2:0] lsu_block_store_tid; // tid of the block store |
| 441 | |
| 442 | input tlu_dtlb_reload_stall; // stall decode of lsu ops due to dtlb fill operation |
| 443 | |
| 444 | input fgu_ecc_asi_stall; // fgu ecc stall |
| 445 | |
| 446 | input [3:0] exu0_oddwin_b; // is the current window odd or not for TG0 |
| 447 | input [3:0] exu1_oddwin_b; // is the current window odd or not for TG1 |
| 448 | |
| 449 | input [1:0] fgu_idiv_stall; // integer divide stall; no int ops to FGU |
| 450 | input fgu_fdiv_stall; // float divide stall; no float loads to the LSU |
| 451 | |
| 452 | input [1:0] dec_br_taken_e1; |
| 453 | |
| 454 | // exu interface |
| 455 | output [7:0] del_pick_d; |
| 456 | |
| 457 | output [4:0] dec_inst0_rd_d; // rd for TG0 at decode |
| 458 | output [4:0] dec_inst1_rd_d; // rd for TG1 at decode |
| 459 | |
| 460 | output dec_rs1_addr0_e; // tell exu to put rs1 onto the lsu address bus for casa |
| 461 | output dec_rs1_addr1_e; |
| 462 | |
| 463 | output [32:0] dec_inst0_d; // inst for TG0 at decode |
| 464 | output [32:0] dec_inst1_d; // inst for TG1 at decode |
| 465 | |
| 466 | output dec_decode0_d; // inst at d stage for TG0 is decoded this cycle |
| 467 | output dec_decode1_d; // inst at d stage for TG1 is decoded this cycle |
| 468 | output dec_valid0_d; // inst at d stage for TG0 is valid this cycle |
| 469 | output dec_valid1_d; // inst at d stage for TG1 is valid this cycle |
| 470 | |
| 471 | output [1:0] dec_true_valid_e; // inst at E are valid taking exceptions into account |
| 472 | |
| 473 | output [1:0] dec_tid0_d; // TID for exu0 |
| 474 | output [1:0] dec_tid1_d; // TID for exu1 |
| 475 | output [1:0] dec_tid0_p; // TID for IRF |
| 476 | output [1:0] dec_tid1_p; |
| 477 | |
| 478 | output [7:0] dec_raw_pick_p; // fast signals for tlu address calculations |
| 479 | |
| 480 | output [4:0] dec_inst0_rs1_p; // TG0 rs1 |
| 481 | output [4:0] dec_inst0_rs2_p; // TG0 rs2 |
| 482 | output [4:0] dec_inst0_rs3_p; // TG0 rs3 |
| 483 | output dec_inst0_rs1_vld_p; // TG0 rs1 valid |
| 484 | output dec_inst0_rs2_vld_p; // TG0 rs2 valid |
| 485 | output dec_inst0_rs3_vld_p; // TG0 rs3 valid |
| 486 | |
| 487 | output [4:0] dec_inst1_rs1_p; // TG1 rs1 |
| 488 | output [4:0] dec_inst1_rs2_p; // TG1 rs2 |
| 489 | output [4:0] dec_inst1_rs3_p; // TG1 rs3 |
| 490 | output dec_inst1_rs1_vld_p; // TG1 rs1 valid |
| 491 | output dec_inst1_rs2_vld_p; // TG1 rs2 valid |
| 492 | output dec_inst1_rs3_vld_p; // TG1 rs3 valid |
| 493 | |
| 494 | // fgu interface |
| 495 | output [4:0] dec_frf_r1_addr_d; // FRF r1 read addr |
| 496 | output [4:0] dec_frf_r2_addr_d; // FRF r2 read addr (including store-floats) |
| 497 | output dec_frf_r1_vld_d; // FRF r1 read valid |
| 498 | output dec_frf_r2_vld_d; // FRF r2 read valid |
| 499 | output dec_frf_r1_32b_d; // FRF rs1 source is single-precision |
| 500 | output dec_frf_r2_32b_d; // FRF rs2 source is single-precision |
| 501 | output dec_frf_r1_odd32b_d; // FRF rs1 source is single-precision and odd |
| 502 | output dec_frf_r2_odd32b_d; // FRF rs2 source is single-precision and odd |
| 503 | output [4:0] dec_frf_w_addr_d; // FRF write addr |
| 504 | output dec_frf_w_vld_d; // FRF write addr is valid |
| 505 | output dec_frf_w_32b_d; // FRF write is single precision |
| 506 | output dec_frf_w_odd32b_d; // FRF write is single precision; rd is odd |
| 507 | output dec_exu_src_vld_d; // FGU op has any valid exu src |
| 508 | output [4:0] dec_irf_w_addr_d; // RD for an integer op executed by the FGU |
| 509 | output dec_frf_store_d; // store-float of FRF data |
| 510 | output dec_fsr_store_d; // store-float of FSR data |
| 511 | output [5:0] dec_fgu_op3_d; // op3 field |
| 512 | output [7:0] dec_fgu_opf_d; // opf field |
| 513 | output dec_fgu_decode_d; // FGU op decoded this cycle |
| 514 | output [2:0] dec_fgu_tid_d; // TID for FGU op |
| 515 | output dec_flush_f1; // Flush f1 stage of the FGU |
| 516 | output dec_flush_f2; // Flush f2 stage of the FGU |
| 517 | output dec_flush_lm; // Flush the m stage of a load |
| 518 | output dec_flush_lb; // Flush the bypass stage of a load |
| 519 | output [1:0] dec_flush_m; // Flush the m stage of the exu's |
| 520 | output [1:0] dec_flush_b; // Flush the b stage of the exu's |
| 521 | output dec_spu_grant_d; // SPU grant for a crypto multiply |
| 522 | output dec_spu_grant_fgu_d; // SPU grant for a crypto multiply |
| 523 | output [7:0] dec_block_store_b; // to the TLU |
| 524 | output [1:0] dec_load_flush_w; // to IFU |
| 525 | |
| 526 | |
| 527 | // tlu interface |
| 528 | output [4:0] dec_exc0_m; // encoded exception status to tlu |
| 529 | output [4:0] dec_exc1_m; |
| 530 | |
| 531 | output [1:0] dec_inst0_cnt; // count of instructions at e,m,b stages for inst at decode (TG0) |
| 532 | output [1:0] dec_inst1_cnt; // count of instructions at e,m,b stages for inst at decode (TG1) |
| 533 | |
| 534 | output [1:0] dec_tid0_m; // TID for inst TG0 |
| 535 | output [1:0] dec_tid1_m; // TID for inst TG1 |
| 536 | output [1:0] dec_inst_valid_m; // valid inst |
| 537 | output [1:0] dec_lsu_inst_m; // lsu inst |
| 538 | output [1:0] dec_fgu_inst_m; // fgu inst |
| 539 | output [1:0] dec_cti_inst_m; // cti inst |
| 540 | |
| 541 | output [1:0] dec_illegal_inst_m; // illegal inst |
| 542 | output [1:0] dec_icache_perr_m; // icache parity error at m stage |
| 543 | output [1:0] dec_priv_exc_m; // priv exception |
| 544 | output [1:0] dec_hpriv_exc_m; // hpriv exception |
| 545 | output [1:0] dec_fpdisable_exc_m; // fp disable exception |
| 546 | output [1:0] dec_br_taken_m; // br is taken at m stage |
| 547 | output [1:0] dec_done_inst_m; // DONE |
| 548 | output [1:0] dec_retry_inst_m; // RETRY |
| 549 | output [1:0] dec_sir_inst_m; // SIR |
| 550 | |
| 551 | output [1:0] dec_annul_ds_m; // DS of branch is annuled |
| 552 | output [1:0] dec_ds_m; // this inst is DS |
| 553 | |
| 554 | output [1:0] dec_fgu_sel_e; // mux select between TG's for fgu ops |
| 555 | output [1:0] dec_fgu_sel_m; // mux select between TG's for fgu ops |
| 556 | |
| 557 | output dec_lsu_sel0_e; // mux select between TG's for lsu ops |
| 558 | output dec_lsu_sel1_e; |
| 559 | |
| 560 | output dec_lsu_sel0_lower_e; // mux selects taking pstate AM into account (exu) |
| 561 | output dec_lsu_sel1_lower_e; |
| 562 | |
| 563 | output dec_lsu_sel0_upper_e; // mux selects taking pstate AM into account (exu) |
| 564 | output dec_lsu_sel1_upper_e; |
| 565 | |
| 566 | output dec_rs1_addr0_upper_e; |
| 567 | output dec_rs1_addr1_upper_e; |
| 568 | |
| 569 | // lsu interface |
| 570 | output dec_ld_inst_e; // operation is a load or load-like |
| 571 | output dec_st_inst_e; // operation is a store or store-like |
| 572 | output dec_fsr_ldst_e; // ldfsr, stfsr inst |
| 573 | output dec_fpldst_inst_e; // FP load or store |
| 574 | output dec_ldst_dbl_e; // ldd inst |
| 575 | output dec_pref_inst_e; // prefetch inst |
| 576 | output dec_flush_inst_e; // flush inst |
| 577 | output dec_memstbar_inst_e; // membar, stbar inst |
| 578 | output [1:0] dec_ldst_sz_e; // size of the memory reference |
| 579 | output [4:3] dec_frf_r2_addr_e; // FRF r2 read addr |
| 580 | output dec_sr_inst_e; // state register instruction |
| 581 | output dec_pr_inst_e; // privileged instruction |
| 582 | output dec_hpr_inst_e; // hypervisor instruction |
| 583 | output dec_casa_inst_e; // casa inst |
| 584 | output dec_ldstub_inst_e; // ldstub inst |
| 585 | output dec_swap_inst_e; // swap inst |
| 586 | output dec_altspace_d; // is an alternate inst |
| 587 | output dec_sign_ext_e; // is a signed load |
| 588 | output [4:0] dec_sraddr_e; // register number for rdasr inst |
| 589 | output dec_imm_asi_vld_d; // immediate form of ASI's |
| 590 | output [7:0] dec_imm_asi_d; // value of ASI access |
| 591 | output [1:0] dec_lsu_tid0_d; // lsu tid at d; real lsu |
| 592 | output [1:0] dec_lsu_tid1_d; // lsu tid at d; real lsu |
| 593 | output dec_lsu_tg_d; // lsu thread group at d |
| 594 | output [4:0] dec_lsu_rd_e; // lsu rd at e |
| 595 | output dec_ld_inst_d; // load inst decoded |
| 596 | |
| 597 | // pmu interface |
| 598 | output [9:0] dec_instr0_type_d; // pmu stuff thread group 0 |
| 599 | output [9:0] dec_instr1_type_d; // pmu stuff thread group 1 |
| 600 | |
| 601 | output [1:0] dec_valid_e; // valid for inst at e stage (takes annul into account) |
| 602 | output [1:0] dec_pmu_valid_e; // valid for inst at e stage (takes annul into account); dont include ifetch_err |
| 603 | output dec_fgu_valid_e; // fgu is valid at e stage (takes annul into account) |
| 604 | |
| 605 | |
| 606 | output [1:0] dec_exu_clken; // clk enable signals to the exu |
| 607 | output dec_lsu_sel0_d; // to the pmu to decide which tid to use for lsu at d stage |
| 608 | |
| 609 | output [1:0] dec_ierr_d; // tell pku that an inst error has occurred: illegal, parity error or ifetch error |
| 610 | |
| 611 | output [7:0] dec_block_store_stall; // prevent window ops from coming too early after a block store |
| 612 | |
| 613 | output scan_out; |
| 614 | |
| 615 | dec_del_ctl del ( |
| 616 | .scan_in(del_scanin), |
| 617 | .scan_out(del_scanout), |
| 618 | .l2clk(l2clk), |
| 619 | .dec_inst0_rs1_d(dec_inst0_d[18:14]), |
| 620 | .dec_inst0_rs2_d(dec_inst0_d[4:0]), |
| 621 | .dec_inst0_b31(dec_inst0_d[31]), |
| 622 | .dec_inst0_raw_rd_d(dec_inst0_d[29:25]), |
| 623 | .dec_inst0_op3_d(dec_inst0_d[24:19]), |
| 624 | .dec_inst0_opf_d(dec_inst0_d[12:5]), |
| 625 | .dec_inst1_rs1_d(dec_inst1_d[18:14]), |
| 626 | .dec_inst1_rs2_d(dec_inst1_d[4:0]), |
| 627 | .dec_inst1_b31(dec_inst1_d[31]), |
| 628 | .dec_inst1_raw_rd_d(dec_inst1_d[29:25]), |
| 629 | .dec_inst1_op3_d(dec_inst1_d[24:19]), |
| 630 | .dec_inst1_opf_d(dec_inst1_d[12:5]), |
| 631 | .tcu_pce_ov(tcu_pce_ov), |
| 632 | .spc_aclk(spc_aclk), |
| 633 | .spc_bclk(spc_bclk), |
| 634 | .tcu_scan_en(tcu_scan_en), |
| 635 | .lsu_dec_pmen(lsu_dec_pmen), |
| 636 | .lsu_exu_pmen(lsu_exu_pmen), |
| 637 | .spc_core_running_status(spc_core_running_status[7:0]), |
| 638 | .power_throttle(power_throttle[2:0]), |
| 639 | .lb_lbist_running(lb_lbist_running), |
| 640 | .pku_idest_p(pku_idest_p[7:0]), |
| 641 | .pku_fdest_p(pku_fdest_p[7:0]), |
| 642 | .pku_fsrc_rd_p(pku_fsrc_rd_p[7:0]), |
| 643 | .pku_lsu_p(pku_lsu_p[7:0]), |
| 644 | .pku_fgu_p(pku_fgu_p[7:0]), |
| 645 | .pku_pdist_p(pku_pdist_p[7:0]), |
| 646 | .pku_twocycle_p(pku_twocycle_p[7:0]), |
| 647 | .pku_inst_cnt_brtaken00(pku_inst_cnt_brtaken00[1:0]), |
| 648 | .pku_inst_cnt_brtaken01(pku_inst_cnt_brtaken01[1:0]), |
| 649 | .pku_inst_cnt_brtaken02(pku_inst_cnt_brtaken02[1:0]), |
| 650 | .pku_inst_cnt_brtaken03(pku_inst_cnt_brtaken03[1:0]), |
| 651 | .pku_inst_cnt_brtaken04(pku_inst_cnt_brtaken04[1:0]), |
| 652 | .pku_inst_cnt_brtaken05(pku_inst_cnt_brtaken05[1:0]), |
| 653 | .pku_inst_cnt_brtaken06(pku_inst_cnt_brtaken06[1:0]), |
| 654 | .pku_inst_cnt_brtaken07(pku_inst_cnt_brtaken07[1:0]), |
| 655 | .pku_inst_cnt_brtaken10(pku_inst_cnt_brtaken10[1:0]), |
| 656 | .pku_inst_cnt_brtaken11(pku_inst_cnt_brtaken11[1:0]), |
| 657 | .pku_inst_cnt_brtaken12(pku_inst_cnt_brtaken12[1:0]), |
| 658 | .pku_inst_cnt_brtaken13(pku_inst_cnt_brtaken13[1:0]), |
| 659 | .pku_inst_cnt_brtaken14(pku_inst_cnt_brtaken14[1:0]), |
| 660 | .pku_inst_cnt_brtaken15(pku_inst_cnt_brtaken15[1:0]), |
| 661 | .pku_inst_cnt_brtaken16(pku_inst_cnt_brtaken16[1:0]), |
| 662 | .pku_inst_cnt_brtaken17(pku_inst_cnt_brtaken17[1:0]), |
| 663 | .exu_test_tid0(exu_test_tid0[1:0]), |
| 664 | .exu_test_addr0(exu_test_addr0[4:0]), |
| 665 | .exu_test_valid0(exu_test_valid0), |
| 666 | .exu_test_tid1(exu_test_tid1[1:0]), |
| 667 | .exu_test_addr1(exu_test_addr1[4:0]), |
| 668 | .exu_test_valid1(exu_test_valid1), |
| 669 | .ded_exc0_d(ded_exc0_d[4:0]), |
| 670 | .ded_exc1_d(ded_exc1_d[4:0]), |
| 671 | .tlu_dec_pstate_pef(tlu_dec_pstate_pef[7:0]), |
| 672 | .fgu_fprs_fef(fgu_fprs_fef[7:0]), |
| 673 | .tlu_dec_hpstate_hpriv(tlu_dec_hpstate_hpriv[7:0]), |
| 674 | .tlu_dec_pstate_priv(tlu_dec_pstate_priv[7:0]), |
| 675 | .dcd_wrtick_d(dcd_wrtick_d[1:0]), |
| 676 | .lsu_cpq_stall(lsu_cpq_stall), |
| 677 | .dcd_callclass_d(dcd_callclass_d[1:0]), |
| 678 | .dcd_tcc_d(dcd_tcc_d[1:0]), |
| 679 | .dcd_specbr_d(dcd_specbr_d[1:0]), |
| 680 | .dcd_specfp_d(dcd_specfp_d[1:0]), |
| 681 | .dcd_exu_src_d(dcd_exu_src_d[1:0]), |
| 682 | .dcd_killfgu_d(dcd_killfgu_d[1:0]), |
| 683 | .dcd_sir_d(dcd_sir_d[1:0]), |
| 684 | .dcd_stdfa_d(dcd_stdfa_d[1:0]), |
| 685 | .pku_valid_e(pku_valid_e[7:0]), |
| 686 | .pku_annul_ds_dcti_brtaken0_e(pku_annul_ds_dcti_brtaken0_e[7:0]), |
| 687 | .pku_annul_ds_dcti_brtaken1_e(pku_annul_ds_dcti_brtaken1_e[7:0]), |
| 688 | .exu0_window_block(exu0_window_block), |
| 689 | .exu1_window_block(exu1_window_block), |
| 690 | .tlu_window_block(tlu_window_block[1:0]), |
| 691 | .fgu_idiv_stall(fgu_idiv_stall[1:0]), |
| 692 | .fgu_fdiv_stall(fgu_fdiv_stall), |
| 693 | .fgu_ecc_asi_stall(fgu_ecc_asi_stall), |
| 694 | .dcd_fpdisable_d(dcd_fpdisable_d[1:0]), |
| 695 | .dcd_lsize0_d(dcd_lsize0_d[1:0]), |
| 696 | .dcd_lsize1_d(dcd_lsize1_d[1:0]), |
| 697 | .dcd_lsu_sign_ext_d(dcd_lsu_sign_ext_d[1:0]), |
| 698 | .dcd_load_d(dcd_load_d[1:0]), |
| 699 | .dcd_store_d(dcd_store_d[1:0]), |
| 700 | .dcd_sethi_d(dcd_sethi_d[1:0]), |
| 701 | .dcd_lsdouble_d(dcd_lsdouble_d[1:0]), |
| 702 | .dcd_prefetch_d(dcd_prefetch_d[1:0]), |
| 703 | .dcd_flush_d(dcd_flush_d[1:0]), |
| 704 | .dcd_memstbar_d(dcd_memstbar_d[1:0]), |
| 705 | .dcd_pr_d(dcd_pr_d[1:0]), |
| 706 | .dcd_priv_d(dcd_priv_d[1:0]), |
| 707 | .dcd_hpr_d(dcd_hpr_d[1:0]), |
| 708 | .dcd_sr_d(dcd_sr_d[1:0]), |
| 709 | .dcd_casa_d(dcd_casa_d[1:0]), |
| 710 | .dcd_ldstub_d(dcd_ldstub_d[1:0]), |
| 711 | .dcd_alt_d(dcd_alt_d[1:0]), |
| 712 | .dcd_alti_d(dcd_alti_d[1:0]), |
| 713 | .dcd_swap_d(dcd_swap_d[1:0]), |
| 714 | .dcd_fsrc_rs1_d(dcd_fsrc_rs1_d[1:0]), |
| 715 | .dcd_fsrc_rs2_d(dcd_fsrc_rs2_d[1:0]), |
| 716 | .dcd_fpdest_single_d(dcd_fpdest_single_d[1:0]), |
| 717 | .dcd_fp_rs1_single_d(dcd_fp_rs1_single_d[1:0]), |
| 718 | .dcd_fp_rs2_single_d(dcd_fp_rs2_single_d[1:0]), |
| 719 | .dcd_fsrsync_d(dcd_fsrsync_d[1:0]), |
| 720 | .dcd_done_d(dcd_done_d[1:0]), |
| 721 | .dcd_retry_d(dcd_retry_d[1:0]), |
| 722 | .dcd_save_restore_d(dcd_save_restore_d[1:0]), |
| 723 | .ded_oddwin0_d(ded_oddwin0_d), |
| 724 | .ded_oddwin1_d(ded_oddwin1_d), |
| 725 | .ded_perr_p(ded_perr_p[1:0]), |
| 726 | .ded_ferr_p(ded_ferr_p[1:0]), |
| 727 | .ded_legal_p(ded_legal_p[1:0]), |
| 728 | .pku_base_pick_p(pku_base_pick_p[7:0]), |
| 729 | .pku_raw_pick0_p(pku_raw_pick0_p[3:0]), |
| 730 | .pku_raw_pick1_p(pku_raw_pick1_p[7:4]), |
| 731 | .pku_ds_e(pku_ds_e[7:0]), |
| 732 | .pku_load_flush_w(pku_load_flush_w[7:0]), |
| 733 | .tlu_flush_ifu(tlu_flush_ifu[7:0]), |
| 734 | .pku_flush_f1(pku_flush_f1[7:0]), |
| 735 | .pku_flush_f2(pku_flush_f2[7:0]), |
| 736 | .pku_flush_lm(pku_flush_lm[7:0]), |
| 737 | .pku_flush_lb(pku_flush_lb[7:0]), |
| 738 | .pku_flush_m(pku_flush_m[7:0]), |
| 739 | .pku_flush_b(pku_flush_b[7:0]), |
| 740 | .dec_br_taken_e1(dec_br_taken_e1[1:0]), |
| 741 | .spu_mult_request(spu_mult_request), |
| 742 | .lsu_block_store_stall(lsu_block_store_stall), |
| 743 | .lsu_block_store_rd(lsu_block_store_rd[4:3]), |
| 744 | .lsu_block_store_tid(lsu_block_store_tid[2:0]), |
| 745 | .tlu_dtlb_reload_stall(tlu_dtlb_reload_stall), |
| 746 | .tlu_pstate_am(tlu_pstate_am[7:0]), |
| 747 | .dec_valid0_d(dec_valid0_d), |
| 748 | .dec_valid1_d(dec_valid1_d), |
| 749 | .dec_decode0_d(dec_decode0_d), |
| 750 | .dec_decode1_d(dec_decode1_d), |
| 751 | .del_noshift0_d(del_noshift0_d), |
| 752 | .del_noshift1_d(del_noshift1_d), |
| 753 | .dec_inst0_rd_d(dec_inst0_rd_d[4:0]), |
| 754 | .dec_inst1_rd_d(dec_inst1_rd_d[4:0]), |
| 755 | .dec_tid0_d(dec_tid0_d[1:0]), |
| 756 | .dec_tid1_d(dec_tid1_d[1:0]), |
| 757 | .dec_tid0_p(dec_tid0_p[1:0]), |
| 758 | .dec_tid1_p(dec_tid1_p[1:0]), |
| 759 | .dec_valid_e(dec_valid_e[1:0]), |
| 760 | .dec_pmu_valid_e(dec_pmu_valid_e[1:0]), |
| 761 | .dec_fgu_valid_e(dec_fgu_valid_e), |
| 762 | .dec_frf_r1_addr_d(dec_frf_r1_addr_d[4:0]), |
| 763 | .dec_frf_r2_addr_d(dec_frf_r2_addr_d[4:0]), |
| 764 | .dec_frf_r2_addr_e(dec_frf_r2_addr_e[4:3]), |
| 765 | .dec_frf_r1_vld_d(dec_frf_r1_vld_d), |
| 766 | .dec_frf_r2_vld_d(dec_frf_r2_vld_d), |
| 767 | .dec_frf_r1_32b_d(dec_frf_r1_32b_d), |
| 768 | .dec_frf_r2_32b_d(dec_frf_r2_32b_d), |
| 769 | .dec_frf_r1_odd32b_d(dec_frf_r1_odd32b_d), |
| 770 | .dec_frf_r2_odd32b_d(dec_frf_r2_odd32b_d), |
| 771 | .dec_frf_w_addr_d(dec_frf_w_addr_d[4:0]), |
| 772 | .dec_frf_w_vld_d(dec_frf_w_vld_d), |
| 773 | .dec_frf_w_32b_d(dec_frf_w_32b_d), |
| 774 | .dec_frf_w_odd32b_d(dec_frf_w_odd32b_d), |
| 775 | .dec_spu_grant_d(dec_spu_grant_d), |
| 776 | .dec_spu_grant_fgu_d(dec_spu_grant_fgu_d), |
| 777 | .dec_exu_src_vld_d(dec_exu_src_vld_d), |
| 778 | .dec_irf_w_addr_d(dec_irf_w_addr_d[4:0]), |
| 779 | .dec_frf_store_d(dec_frf_store_d), |
| 780 | .dec_fsr_store_d(dec_fsr_store_d), |
| 781 | .dec_fgu_op3_d(dec_fgu_op3_d[5:0]), |
| 782 | .dec_fgu_opf_d(dec_fgu_opf_d[7:0]), |
| 783 | .dec_fgu_decode_d(dec_fgu_decode_d), |
| 784 | .dec_fgu_tid_d(dec_fgu_tid_d[2:0]), |
| 785 | .dec_flush_f1(dec_flush_f1), |
| 786 | .dec_flush_f2(dec_flush_f2), |
| 787 | .dec_flush_lm(dec_flush_lm), |
| 788 | .dec_flush_lb(dec_flush_lb), |
| 789 | .dec_flush_m(dec_flush_m[1:0]), |
| 790 | .dec_flush_b(dec_flush_b[1:0]), |
| 791 | .dec_block_store_b(dec_block_store_b[7:0]), |
| 792 | .dec_exc0_m(dec_exc0_m[4:0]), |
| 793 | .dec_exc1_m(dec_exc1_m[4:0]), |
| 794 | .dec_inst0_cnt(dec_inst0_cnt[1:0]), |
| 795 | .dec_inst1_cnt(dec_inst1_cnt[1:0]), |
| 796 | .dec_tid0_m(dec_tid0_m[1:0]), |
| 797 | .dec_tid1_m(dec_tid1_m[1:0]), |
| 798 | .dec_inst_valid_m(dec_inst_valid_m[1:0]), |
| 799 | .dec_lsu_inst_m(dec_lsu_inst_m[1:0]), |
| 800 | .dec_fgu_inst_m(dec_fgu_inst_m[1:0]), |
| 801 | .dec_cti_inst_m(dec_cti_inst_m[1:0]), |
| 802 | .dec_illegal_inst_m(dec_illegal_inst_m[1:0]), |
| 803 | .dec_icache_perr_m(dec_icache_perr_m[1:0]), |
| 804 | .dec_priv_exc_m(dec_priv_exc_m[1:0]), |
| 805 | .dec_hpriv_exc_m(dec_hpriv_exc_m[1:0]), |
| 806 | .dec_fpdisable_exc_m(dec_fpdisable_exc_m[1:0]), |
| 807 | .dec_br_taken_m(dec_br_taken_m[1:0]), |
| 808 | .dec_done_inst_m(dec_done_inst_m[1:0]), |
| 809 | .dec_retry_inst_m(dec_retry_inst_m[1:0]), |
| 810 | .dec_sir_inst_m(dec_sir_inst_m[1:0]), |
| 811 | .dec_ds_m(dec_ds_m[1:0]), |
| 812 | .dec_annul_ds_m(dec_annul_ds_m[1:0]), |
| 813 | .dec_fgu_sel_e(dec_fgu_sel_e[1:0]), |
| 814 | .dec_fgu_sel_m(dec_fgu_sel_m[1:0]), |
| 815 | .dec_lsu_sel0_e(dec_lsu_sel0_e), |
| 816 | .dec_lsu_sel1_e(dec_lsu_sel1_e), |
| 817 | .dec_rs1_addr0_e(dec_rs1_addr0_e), |
| 818 | .dec_rs1_addr1_e(dec_rs1_addr1_e), |
| 819 | .dec_lsu_sel0_upper_e(dec_lsu_sel0_upper_e), |
| 820 | .dec_lsu_sel1_upper_e(dec_lsu_sel1_upper_e), |
| 821 | .dec_lsu_sel0_lower_e(dec_lsu_sel0_lower_e), |
| 822 | .dec_lsu_sel1_lower_e(dec_lsu_sel1_lower_e), |
| 823 | .dec_rs1_addr0_upper_e(dec_rs1_addr0_upper_e), |
| 824 | .dec_rs1_addr1_upper_e(dec_rs1_addr1_upper_e), |
| 825 | .del_pick_d(del_pick_d[7:0]), |
| 826 | .dec_ld_inst_e(dec_ld_inst_e), |
| 827 | .dec_st_inst_e(dec_st_inst_e), |
| 828 | .dec_fsr_ldst_e(dec_fsr_ldst_e), |
| 829 | .dec_fpldst_inst_e(dec_fpldst_inst_e), |
| 830 | .dec_ldst_dbl_e(dec_ldst_dbl_e), |
| 831 | .dec_pref_inst_e(dec_pref_inst_e), |
| 832 | .dec_flush_inst_e(dec_flush_inst_e), |
| 833 | .dec_memstbar_inst_e(dec_memstbar_inst_e), |
| 834 | .dec_sr_inst_e(dec_sr_inst_e), |
| 835 | .dec_pr_inst_e(dec_pr_inst_e), |
| 836 | .dec_hpr_inst_e(dec_hpr_inst_e), |
| 837 | .dec_casa_inst_e(dec_casa_inst_e), |
| 838 | .dec_ldstub_inst_e(dec_ldstub_inst_e), |
| 839 | .dec_swap_inst_e(dec_swap_inst_e), |
| 840 | .dec_altspace_d(dec_altspace_d), |
| 841 | .dec_sign_ext_e(dec_sign_ext_e), |
| 842 | .dec_sraddr_e(dec_sraddr_e[4:0]), |
| 843 | .dec_imm_asi_vld_d(dec_imm_asi_vld_d), |
| 844 | .dec_imm_asi_d(dec_imm_asi_d[7:0]), |
| 845 | .dec_ldst_sz_e(dec_ldst_sz_e[1:0]), |
| 846 | .dec_ld_inst_d(dec_ld_inst_d), |
| 847 | .dec_lsu_tid0_d(dec_lsu_tid0_d[1:0]), |
| 848 | .dec_lsu_tid1_d(dec_lsu_tid1_d[1:0]), |
| 849 | .dec_lsu_tg_d(dec_lsu_tg_d), |
| 850 | .dec_lsu_rd_e(dec_lsu_rd_e[4:0]), |
| 851 | .del_test0_sel_p(del_test0_sel_p), |
| 852 | .del_twocycle0_std_p(del_twocycle0_std_p), |
| 853 | .del_twocycle0_rs2_p(del_twocycle0_rs2_p), |
| 854 | .del_default0_sel_p(del_default0_sel_p), |
| 855 | .del_test1_sel_p(del_test1_sel_p), |
| 856 | .del_twocycle1_std_p(del_twocycle1_std_p), |
| 857 | .del_twocycle1_rs2_p(del_twocycle1_rs2_p), |
| 858 | .del_default1_sel_p(del_default1_sel_p), |
| 859 | .del_test_addr0_p(del_test_addr0_p[4:0]), |
| 860 | .del_test_addr1_p(del_test_addr1_p[4:0]), |
| 861 | .dec_instr0_type_d(dec_instr0_type_d[9:0]), |
| 862 | .dec_instr1_type_d(dec_instr1_type_d[9:0]), |
| 863 | .dec_exu_clken(dec_exu_clken[1:0]), |
| 864 | .del_tg_clken(del_tg_clken[1:0]), |
| 865 | .dec_true_valid_e(dec_true_valid_e[1:0]), |
| 866 | .dec_load_flush_w(dec_load_flush_w[1:0]), |
| 867 | .dec_lsu_sel0_d(dec_lsu_sel0_d), |
| 868 | .dec_raw_pick_p(dec_raw_pick_p[7:0]), |
| 869 | .dec_ierr_d(dec_ierr_d[1:0]), |
| 870 | .dec_block_store_stall(dec_block_store_stall[7:0]) |
| 871 | ); |
| 872 | |
| 873 | |
| 874 | dec_ded_ctl ded0 ( |
| 875 | .scan_in(ded0_scanin), |
| 876 | .scan_out(ded0_scanout), |
| 877 | .l2clk(l2clk), |
| 878 | .clken(del_tg_clken[0]), |
| 879 | .del_test_sel_p(del_test0_sel_p), |
| 880 | .del_twocycle_std_p(del_twocycle0_std_p), |
| 881 | .del_twocycle_rs2_p(del_twocycle0_rs2_p), |
| 882 | .del_default_sel_p(del_default0_sel_p), |
| 883 | .del_test_addr_p(del_test_addr0_p), |
| 884 | .ifu_buf0_inst0(ifu_buf0_inst0[32:0]), |
| 885 | .ifu_buf0_inst1(ifu_buf0_inst1[32:0]), |
| 886 | .ifu_buf0_inst2(ifu_buf0_inst2[32:0]), |
| 887 | .ifu_buf0_inst3(ifu_buf0_inst3[32:0]), |
| 888 | .ifu_buf0_excp0(ifu_buf0_excp0[4:0]), |
| 889 | .ifu_buf0_excp1(ifu_buf0_excp1[4:0]), |
| 890 | .ifu_buf0_excp2(ifu_buf0_excp2[4:0]), |
| 891 | .ifu_buf0_excp3(ifu_buf0_excp3[4:0]), |
| 892 | .del_noshift_d(del_noshift0_d), |
| 893 | .pku_raw_pick_p(pku_raw_pick0_p[3:0]), |
| 894 | .pku_isrc_rs1_p(pku_isrc_rs1_p[3:0]), |
| 895 | .pku_isrc_rs2_p(pku_isrc_rs2_p[3:0]), |
| 896 | .pku_isrc_rd_p(pku_isrc_rd_p[3:0]), |
| 897 | .exu_oddwin_b(exu0_oddwin_b[3:0]), |
| 898 | .ded_ferr_p(ded_ferr_p[0]), |
| 899 | .ded_perr_p(ded_perr_p[0]), |
| 900 | .ded_ferr_d(ded_ferr_d[0]), |
| 901 | .ded_perr_d(ded_perr_d[0]), |
| 902 | .ded_legal_p(ded_legal_p[0]), |
| 903 | .ded_oddwin_d(ded_oddwin0_d), |
| 904 | .dec_inst_d(dec_inst0_d[32:0]), |
| 905 | .dec_inst_rs1_p(dec_inst0_rs1_p[4:0]), |
| 906 | .dec_inst_rs2_p(dec_inst0_rs2_p[4:0]), |
| 907 | .dec_inst_rs3_p(dec_inst0_rs3_p[4:0]), |
| 908 | .dec_inst_rs1_vld_p(dec_inst0_rs1_vld_p), |
| 909 | .dec_inst_rs2_vld_p(dec_inst0_rs2_vld_p), |
| 910 | .dec_inst_rs3_vld_p(dec_inst0_rs3_vld_p), |
| 911 | .ded_exc_d(ded_exc0_d[4:0]), |
| 912 | .tcu_pce_ov(tcu_pce_ov), |
| 913 | .spc_aclk(spc_aclk), |
| 914 | .spc_bclk(spc_bclk), |
| 915 | .tcu_scan_en(tcu_scan_en), |
| 916 | .tlu_cerer_icdp(tlu_cerer_icdp) |
| 917 | ); |
| 918 | |
| 919 | dec_ded_ctl ded1 ( |
| 920 | .scan_in(ded1_scanin), |
| 921 | .scan_out(ded1_scanout), |
| 922 | .l2clk(l2clk), |
| 923 | .clken(del_tg_clken[1]), |
| 924 | .del_test_sel_p(del_test1_sel_p), |
| 925 | .del_twocycle_std_p(del_twocycle1_std_p), |
| 926 | .del_twocycle_rs2_p(del_twocycle1_rs2_p), |
| 927 | .del_default_sel_p(del_default1_sel_p), |
| 928 | .del_test_addr_p(del_test_addr1_p), |
| 929 | .ifu_buf0_inst0(ifu_buf0_inst4[32:0]), |
| 930 | .ifu_buf0_inst1(ifu_buf0_inst5[32:0]), |
| 931 | .ifu_buf0_inst2(ifu_buf0_inst6[32:0]), |
| 932 | .ifu_buf0_inst3(ifu_buf0_inst7[32:0]), |
| 933 | .ifu_buf0_excp0(ifu_buf0_excp4[4:0]), |
| 934 | .ifu_buf0_excp1(ifu_buf0_excp5[4:0]), |
| 935 | .ifu_buf0_excp2(ifu_buf0_excp6[4:0]), |
| 936 | .ifu_buf0_excp3(ifu_buf0_excp7[4:0]), |
| 937 | .del_noshift_d(del_noshift1_d), |
| 938 | .pku_raw_pick_p(pku_raw_pick1_p[7:4]), |
| 939 | .pku_isrc_rs1_p(pku_isrc_rs1_p[7:4]), |
| 940 | .pku_isrc_rs2_p(pku_isrc_rs2_p[7:4]), |
| 941 | .pku_isrc_rd_p(pku_isrc_rd_p[7:4]), |
| 942 | .exu_oddwin_b(exu1_oddwin_b[3:0]), |
| 943 | .ded_ferr_p(ded_ferr_p[1]), |
| 944 | .ded_perr_p(ded_perr_p[1]), |
| 945 | .ded_ferr_d(ded_ferr_d[1]), |
| 946 | .ded_perr_d(ded_perr_d[1]), |
| 947 | .ded_legal_p(ded_legal_p[1]), |
| 948 | .ded_oddwin_d(ded_oddwin1_d), |
| 949 | .dec_inst_d(dec_inst1_d[32:0]), |
| 950 | .dec_inst_rs1_p(dec_inst1_rs1_p[4:0]), |
| 951 | .dec_inst_rs2_p(dec_inst1_rs2_p[4:0]), |
| 952 | .dec_inst_rs3_p(dec_inst1_rs3_p[4:0]), |
| 953 | .dec_inst_rs1_vld_p(dec_inst1_rs1_vld_p), |
| 954 | .dec_inst_rs2_vld_p(dec_inst1_rs2_vld_p), |
| 955 | .dec_inst_rs3_vld_p(dec_inst1_rs3_vld_p), |
| 956 | .ded_exc_d(ded_exc1_d[4:0]), |
| 957 | .tcu_pce_ov(tcu_pce_ov), |
| 958 | .spc_aclk(spc_aclk), |
| 959 | .spc_bclk(spc_bclk), |
| 960 | .tcu_scan_en(tcu_scan_en), |
| 961 | .tlu_cerer_icdp(tlu_cerer_icdp) |
| 962 | ); |
| 963 | |
| 964 | |
| 965 | |
| 966 | dec_dcd_ctl dcd0 ( |
| 967 | .ded_ferr_d(ded_ferr_d[0]), |
| 968 | .ded_perr_d(ded_perr_d[0]), |
| 969 | .dec_inst_d(dec_inst0_d[31:0]), |
| 970 | .dcd_sir_d(dcd_sir_d[0]), |
| 971 | .dcd_stdfa_d(dcd_stdfa_d[0]), |
| 972 | .dcd_save_restore_d(dcd_save_restore_d[0]), |
| 973 | .dcd_exu_src_d(dcd_exu_src_d[0]), |
| 974 | .dcd_killfgu_d(dcd_killfgu_d[0]), |
| 975 | .dcd_lsize_d(dcd_lsize0_d[1:0]), |
| 976 | .dcd_lsu_sign_ext_d(dcd_lsu_sign_ext_d[0]), |
| 977 | .dcd_load_d(dcd_load_d[0]), |
| 978 | .dcd_store_d(dcd_store_d[0]), |
| 979 | .dcd_lsdouble_d(dcd_lsdouble_d[0]), |
| 980 | .dcd_prefetch_d(dcd_prefetch_d[0]), |
| 981 | .dcd_flush_d(dcd_flush_d[0]), |
| 982 | .dcd_memstbar_d(dcd_memstbar_d[0]), |
| 983 | .dcd_hpr_d(dcd_hpr_d[0]), |
| 984 | .dcd_pr_d(dcd_pr_d[0]), |
| 985 | .dcd_priv_d(dcd_priv_d[0]), |
| 986 | .dcd_sr_d(dcd_sr_d[0]), |
| 987 | .dcd_casa_d(dcd_casa_d[0]), |
| 988 | .dcd_ldstub_d(dcd_ldstub_d[0]), |
| 989 | .dcd_alt_d(dcd_alt_d[0]), |
| 990 | .dcd_alti_d(dcd_alti_d[0]), |
| 991 | .dcd_swap_d(dcd_swap_d[0]), |
| 992 | .dcd_done_d(dcd_done_d[0]), |
| 993 | .dcd_retry_d(dcd_retry_d[0]), |
| 994 | .dcd_fsrc_rs1_d(dcd_fsrc_rs1_d[0]), |
| 995 | .dcd_fsrc_rs2_d(dcd_fsrc_rs2_d[0]), |
| 996 | .dcd_fpdest_single_d(dcd_fpdest_single_d[0]), |
| 997 | .dcd_fp_rs1_single_d(dcd_fp_rs1_single_d[0]), |
| 998 | .dcd_fp_rs2_single_d(dcd_fp_rs2_single_d[0]), |
| 999 | .dcd_fsrsync_d(dcd_fsrsync_d[0]), |
| 1000 | .dcd_callclass_d(dcd_callclass_d[0]), |
| 1001 | .dcd_specbr_d(dcd_specbr_d[0]), |
| 1002 | .dcd_specfp_d(dcd_specfp_d[0]), |
| 1003 | .dcd_tcc_d(dcd_tcc_d[0]), |
| 1004 | .dcd_sethi_d(dcd_sethi_d[0]), |
| 1005 | .dcd_fpdisable_d(dcd_fpdisable_d[0]), |
| 1006 | .dcd_wrtick_d(dcd_wrtick_d[0]) |
| 1007 | ); |
| 1008 | |
| 1009 | dec_dcd_ctl dcd1 ( |
| 1010 | .ded_ferr_d(ded_ferr_d[1]), |
| 1011 | .ded_perr_d(ded_perr_d[1]), |
| 1012 | .dec_inst_d(dec_inst1_d[31:0]), |
| 1013 | .dcd_sir_d(dcd_sir_d[1]), |
| 1014 | .dcd_stdfa_d(dcd_stdfa_d[1]), |
| 1015 | .dcd_save_restore_d(dcd_save_restore_d[1]), |
| 1016 | .dcd_exu_src_d(dcd_exu_src_d[1]), |
| 1017 | .dcd_killfgu_d(dcd_killfgu_d[1]), |
| 1018 | .dcd_lsize_d(dcd_lsize1_d[1:0]), |
| 1019 | .dcd_lsu_sign_ext_d(dcd_lsu_sign_ext_d[1]), |
| 1020 | .dcd_load_d(dcd_load_d[1]), |
| 1021 | .dcd_store_d(dcd_store_d[1]), |
| 1022 | .dcd_lsdouble_d(dcd_lsdouble_d[1]), |
| 1023 | .dcd_prefetch_d(dcd_prefetch_d[1]), |
| 1024 | .dcd_flush_d(dcd_flush_d[1]), |
| 1025 | .dcd_memstbar_d(dcd_memstbar_d[1]), |
| 1026 | .dcd_hpr_d(dcd_hpr_d[1]), |
| 1027 | .dcd_pr_d(dcd_pr_d[1]), |
| 1028 | .dcd_priv_d(dcd_priv_d[1]), |
| 1029 | .dcd_sr_d(dcd_sr_d[1]), |
| 1030 | .dcd_casa_d(dcd_casa_d[1]), |
| 1031 | .dcd_ldstub_d(dcd_ldstub_d[1]), |
| 1032 | .dcd_alt_d(dcd_alt_d[1]), |
| 1033 | .dcd_alti_d(dcd_alti_d[1]), |
| 1034 | .dcd_swap_d(dcd_swap_d[1]), |
| 1035 | .dcd_done_d(dcd_done_d[1]), |
| 1036 | .dcd_retry_d(dcd_retry_d[1]), |
| 1037 | .dcd_fsrc_rs1_d(dcd_fsrc_rs1_d[1]), |
| 1038 | .dcd_fsrc_rs2_d(dcd_fsrc_rs2_d[1]), |
| 1039 | .dcd_fpdest_single_d(dcd_fpdest_single_d[1]), |
| 1040 | .dcd_fp_rs1_single_d(dcd_fp_rs1_single_d[1]), |
| 1041 | .dcd_fp_rs2_single_d(dcd_fp_rs2_single_d[1]), |
| 1042 | .dcd_fsrsync_d(dcd_fsrsync_d[1]), |
| 1043 | .dcd_callclass_d(dcd_callclass_d[1]), |
| 1044 | .dcd_specbr_d(dcd_specbr_d[1]), |
| 1045 | .dcd_specfp_d(dcd_specfp_d[1]), |
| 1046 | .dcd_tcc_d(dcd_tcc_d[1]), |
| 1047 | .dcd_sethi_d(dcd_sethi_d[1]), |
| 1048 | .dcd_fpdisable_d(dcd_fpdisable_d[1]), |
| 1049 | .dcd_wrtick_d(dcd_wrtick_d[1]) |
| 1050 | ); |
| 1051 | |
| 1052 | // fixscan start: |
| 1053 | assign del_scanin = scan_in ; |
| 1054 | assign ded0_scanin = del_scanout ; |
| 1055 | assign ded1_scanin = ded0_scanout ; |
| 1056 | assign scan_out = ded1_scanout ; |
| 1057 | // fixscan end: |
| 1058 | endmodule |
| 1059 | |