| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dec_ded_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dec_ded_ctl ( |
| 36 | l2clk, |
| 37 | scan_in, |
| 38 | tcu_pce_ov, |
| 39 | spc_aclk, |
| 40 | spc_bclk, |
| 41 | tcu_scan_en, |
| 42 | clken, |
| 43 | tlu_cerer_icdp, |
| 44 | del_test_sel_p, |
| 45 | del_twocycle_std_p, |
| 46 | del_twocycle_rs2_p, |
| 47 | del_default_sel_p, |
| 48 | del_test_addr_p, |
| 49 | ifu_buf0_inst0, |
| 50 | ifu_buf0_inst1, |
| 51 | ifu_buf0_inst2, |
| 52 | ifu_buf0_inst3, |
| 53 | ifu_buf0_excp0, |
| 54 | ifu_buf0_excp1, |
| 55 | ifu_buf0_excp2, |
| 56 | ifu_buf0_excp3, |
| 57 | del_noshift_d, |
| 58 | pku_raw_pick_p, |
| 59 | pku_isrc_rs1_p, |
| 60 | pku_isrc_rs2_p, |
| 61 | pku_isrc_rd_p, |
| 62 | exu_oddwin_b, |
| 63 | ded_oddwin_d, |
| 64 | dec_inst_d, |
| 65 | dec_inst_rs1_p, |
| 66 | dec_inst_rs2_p, |
| 67 | dec_inst_rs3_p, |
| 68 | dec_inst_rs1_vld_p, |
| 69 | dec_inst_rs2_vld_p, |
| 70 | dec_inst_rs3_vld_p, |
| 71 | ded_exc_d, |
| 72 | ded_perr_p, |
| 73 | ded_ferr_p, |
| 74 | ded_perr_d, |
| 75 | ded_ferr_d, |
| 76 | ded_legal_p, |
| 77 | scan_out); |
| 78 | wire l1clk; |
| 79 | wire spares_scanin; |
| 80 | wire spares_scanout; |
| 81 | wire icdf_perr_f_scanin; |
| 82 | wire icdf_perr_f_scanout; |
| 83 | wire icdp_perr_en; |
| 84 | wire pce_ov; |
| 85 | wire stop; |
| 86 | wire siclk; |
| 87 | wire soclk; |
| 88 | wire se; |
| 89 | wire oddwinf_scanin; |
| 90 | wire oddwinf_scanout; |
| 91 | wire [3:0] oddwin; |
| 92 | wire [2:0] xor0; |
| 93 | wire [2:0] xor1; |
| 94 | wire [2:0] xor2; |
| 95 | wire [2:0] xor3; |
| 96 | wire [3:0] window_in; |
| 97 | wire [2:0] xor_d; |
| 98 | wire windowf_scanin; |
| 99 | wire windowf_scanout; |
| 100 | wire twocyclef_scanin; |
| 101 | wire twocyclef_scanout; |
| 102 | wire [4:0] inst_rs2_d; |
| 103 | wire [4:1] inst_rs3_d; |
| 104 | wire [2:0] isrc_in; |
| 105 | wire [32:0] decode_mux; |
| 106 | wire [2:0] isrc0_in; |
| 107 | wire [2:0] isrc1_in; |
| 108 | wire [2:0] isrc2_in; |
| 109 | wire [2:0] isrc3_in; |
| 110 | wire [2:0] isrc_d; |
| 111 | wire isrcf_scanin; |
| 112 | wire isrcf_scanout; |
| 113 | wire [4:0] exc_in; |
| 114 | wire excf_scanin; |
| 115 | wire excf_scanout; |
| 116 | wire decodef_scanin; |
| 117 | wire decodef_scanout; |
| 118 | wire parityerrf_scanin; |
| 119 | wire parityerrf_scanout; |
| 120 | wire [3:0] ifetch_err_p; |
| 121 | wire ifetcherrf_scanin; |
| 122 | wire ifetcherrf_scanout; |
| 123 | wire illegal0_p; |
| 124 | wire illegal1_p; |
| 125 | wire illegal2_p; |
| 126 | wire illegal3_p; |
| 127 | wire legal_d; |
| 128 | wire legalf_scanin; |
| 129 | wire legalf_scanout; |
| 130 | |
| 131 | |
| 132 | |
| 133 | input l2clk; |
| 134 | input scan_in; |
| 135 | input tcu_pce_ov; // scan signals |
| 136 | input spc_aclk; |
| 137 | input spc_bclk; |
| 138 | input tcu_scan_en; |
| 139 | |
| 140 | input clken; |
| 141 | |
| 142 | input tlu_cerer_icdp; // enable for icdp perr (0 then mask it) |
| 143 | |
| 144 | input del_test_sel_p; // mux selects for IRF read port rs3 |
| 145 | input del_twocycle_std_p; |
| 146 | input del_twocycle_rs2_p; |
| 147 | input del_default_sel_p; |
| 148 | |
| 149 | |
| 150 | input [4:0] del_test_addr_p; // address to read for exu test access |
| 151 | |
| 152 | input [32:0] ifu_buf0_inst0; // instructions for each of the threads at p stage |
| 153 | input [32:0] ifu_buf0_inst1; |
| 154 | input [32:0] ifu_buf0_inst2; |
| 155 | input [32:0] ifu_buf0_inst3; |
| 156 | |
| 157 | input [4:0] ifu_buf0_excp0; // exception info for each of the threads at p stage |
| 158 | input [4:0] ifu_buf0_excp1; |
| 159 | input [4:0] ifu_buf0_excp2; |
| 160 | input [4:0] ifu_buf0_excp3; |
| 161 | |
| 162 | input del_noshift_d; // dont shift anything into decode0 stage |
| 163 | input [3:0] pku_raw_pick_p; // raw pick signals to ifu to mux pc addresses |
| 164 | |
| 165 | |
| 166 | input [3:0] pku_isrc_rs1_p; // has rs1 source |
| 167 | input [3:0] pku_isrc_rs2_p; // has rs2 source |
| 168 | input [3:0] pku_isrc_rd_p; // has rd source |
| 169 | |
| 170 | input [3:0] exu_oddwin_b; // whether window for current thread is odd or not |
| 171 | |
| 172 | output ded_oddwin_d; // window is odd for decode0 |
| 173 | |
| 174 | output [32:0] dec_inst_d; |
| 175 | |
| 176 | output [4:0] dec_inst_rs1_p; |
| 177 | output [4:0] dec_inst_rs2_p; |
| 178 | output [4:0] dec_inst_rs3_p; |
| 179 | output dec_inst_rs1_vld_p; |
| 180 | output dec_inst_rs2_vld_p; |
| 181 | output dec_inst_rs3_vld_p; |
| 182 | |
| 183 | |
| 184 | output [4:0] ded_exc_d; |
| 185 | |
| 186 | output ded_perr_p; // inst parity error at p stage; to del to squash predecodes |
| 187 | output ded_ferr_p; // inst ifetch error at p stage; to del to squash predecodes |
| 188 | |
| 189 | output ded_perr_d; // inst parity error at d stage; to dcd to squash main decode |
| 190 | output ded_ferr_d; // inst ifetch error at d stage; to dcd to squash main decode |
| 191 | |
| 192 | output ded_legal_p; // illegal instruction at p stage |
| 193 | |
| 194 | output scan_out; |
| 195 | |
| 196 | |
| 197 | dec_ded_ctl_l1clkhdr_ctl_macro clkgen ( |
| 198 | .l2clk(l2clk), |
| 199 | .l1en (clken), |
| 200 | .l1clk(l1clk), |
| 201 | .pce_ov(pce_ov), |
| 202 | .stop(stop), |
| 203 | .se(se)); |
| 204 | |
| 205 | dec_ded_ctl_spare_ctl_macro__num_2 spares ( |
| 206 | .scan_in(spares_scanin), |
| 207 | .scan_out(spares_scanout), |
| 208 | .l1clk (l1clk), |
| 209 | .siclk(siclk), |
| 210 | .soclk(soclk) |
| 211 | ); |
| 212 | |
| 213 | dec_ded_ctl_msff_ctl_macro__width_1 icdf_perr_f ( |
| 214 | .scan_in(icdf_perr_f_scanin), |
| 215 | .scan_out(icdf_perr_f_scanout), |
| 216 | .l1clk(l1clk), |
| 217 | .din (tlu_cerer_icdp), |
| 218 | .dout (icdp_perr_en), |
| 219 | .siclk(siclk), |
| 220 | .soclk(soclk) |
| 221 | ); |
| 222 | |
| 223 | |
| 224 | // scan renames |
| 225 | assign pce_ov = tcu_pce_ov; |
| 226 | assign stop = 1'b0; |
| 227 | assign siclk = spc_aclk; |
| 228 | assign soclk = spc_bclk; |
| 229 | assign se = tcu_scan_en; |
| 230 | // end scan |
| 231 | |
| 232 | // 0in value -var pku_raw_pick_p[3:0] -val 0 1 2 4 8 |
| 233 | |
| 234 | |
| 235 | dec_ded_ctl_msff_ctl_macro__width_4 oddwinf ( |
| 236 | .scan_in(oddwinf_scanin), |
| 237 | .scan_out(oddwinf_scanout), |
| 238 | .din(exu_oddwin_b[3:0]), |
| 239 | .dout(oddwin[3:0]), |
| 240 | .l1clk(l1clk), |
| 241 | .siclk(siclk), |
| 242 | .soclk(soclk) |
| 243 | ); |
| 244 | |
| 245 | |
| 246 | // generate correct pointers for rd, rs1 and rs2 for each thread |
| 247 | |
| 248 | assign xor0[2:0] = {ifu_buf0_inst0[29],ifu_buf0_inst0[18],ifu_buf0_inst0[4]} ^ ({3{oddwin[0]}} & {ifu_buf0_inst0[28],ifu_buf0_inst0[17],ifu_buf0_inst0[3]}); |
| 249 | |
| 250 | assign xor1[2:0] = {ifu_buf0_inst1[29],ifu_buf0_inst1[18],ifu_buf0_inst1[4]} ^ ({3{oddwin[1]}} & {ifu_buf0_inst1[28],ifu_buf0_inst1[17],ifu_buf0_inst1[3]}); |
| 251 | |
| 252 | assign xor2[2:0] = {ifu_buf0_inst2[29],ifu_buf0_inst2[18],ifu_buf0_inst2[4]} ^ ({3{oddwin[2]}} & {ifu_buf0_inst2[28],ifu_buf0_inst2[17],ifu_buf0_inst2[3]}); |
| 253 | |
| 254 | assign xor3[2:0] = {ifu_buf0_inst3[29],ifu_buf0_inst3[18],ifu_buf0_inst3[4]} ^ ({3{oddwin[3]}} & {ifu_buf0_inst3[28],ifu_buf0_inst3[17],ifu_buf0_inst3[3]}); |
| 255 | |
| 256 | |
| 257 | |
| 258 | assign window_in[3:0] = ({4{del_noshift_d}} & {ded_oddwin_d,xor_d[2:0]}) | |
| 259 | ({4{~del_noshift_d & pku_raw_pick_p[0]}} & {oddwin[0],xor0[2:0]}) | |
| 260 | ({4{~del_noshift_d & pku_raw_pick_p[1]}} & {oddwin[1],xor1[2:0]}) | |
| 261 | ({4{~del_noshift_d & pku_raw_pick_p[2]}} & {oddwin[2],xor2[2:0]}) | |
| 262 | ({4{~del_noshift_d & pku_raw_pick_p[3]}} & {oddwin[3],xor3[2:0]}); |
| 263 | |
| 264 | |
| 265 | dec_ded_ctl_msff_ctl_macro__width_4 windowf ( |
| 266 | .scan_in(windowf_scanin), |
| 267 | .scan_out(windowf_scanout), |
| 268 | .din(window_in[3:0]), |
| 269 | .dout({ded_oddwin_d,xor_d[2:0]}), |
| 270 | .l1clk(l1clk), |
| 271 | .siclk(siclk), |
| 272 | .soclk(soclk) |
| 273 | ); |
| 274 | |
| 275 | |
| 276 | // twocycle operations use the rs3 port to the irf for the second read operation |
| 277 | |
| 278 | dec_ded_ctl_msff_ctl_macro__width_9 twocyclef ( |
| 279 | .scan_in(twocyclef_scanin), |
| 280 | .scan_out(twocyclef_scanout), |
| 281 | .din({dec_inst_rs2_p[4:0],dec_inst_rs3_p[4:1]}), |
| 282 | .dout({inst_rs2_d[4:0],inst_rs3_d[4:1]}), |
| 283 | .l1clk(l1clk), |
| 284 | .siclk(siclk), |
| 285 | .soclk(soclk) |
| 286 | ); |
| 287 | |
| 288 | |
| 289 | |
| 290 | assign {dec_inst_rs3_vld_p,dec_inst_rs3_p[4:0]} = ({6{del_test_sel_p}} & {1'b1,del_test_addr_p[4:0]}) | |
| 291 | ({6{del_twocycle_std_p}} & {1'b1,inst_rs3_d[4:1],1'b1}) | |
| 292 | ({6{del_twocycle_rs2_p}} & {1'b1,inst_rs2_d[4:0]}) | |
| 293 | ({6{del_default_sel_p}} & {isrc_in[2],window_in[2],decode_mux[28:25]}); |
| 294 | |
| 295 | |
| 296 | assign dec_inst_rs1_vld_p = isrc_in[1]; |
| 297 | assign dec_inst_rs2_vld_p = isrc_in[0]; |
| 298 | |
| 299 | assign dec_inst_rs1_p[4:0] = {window_in[1],decode_mux[17:14]}; |
| 300 | assign dec_inst_rs2_p[4:0] = {window_in[0],decode_mux[3:0]}; |
| 301 | |
| 302 | |
| 303 | assign isrc0_in[2:0] = { pku_isrc_rd_p[0],pku_isrc_rs1_p[0],pku_isrc_rs2_p[0] }; |
| 304 | |
| 305 | assign isrc1_in[2:0] = { pku_isrc_rd_p[1],pku_isrc_rs1_p[1],pku_isrc_rs2_p[1] }; |
| 306 | |
| 307 | assign isrc2_in[2:0] = { pku_isrc_rd_p[2],pku_isrc_rs1_p[2],pku_isrc_rs2_p[2] }; |
| 308 | |
| 309 | assign isrc3_in[2:0] = { pku_isrc_rd_p[3],pku_isrc_rs1_p[3],pku_isrc_rs2_p[3] }; |
| 310 | |
| 311 | |
| 312 | assign isrc_in[2:0] = ({3{del_noshift_d}} & isrc_d[2:0]) | |
| 313 | ({3{~del_noshift_d & pku_raw_pick_p[0]}} & isrc0_in[2:0]) | |
| 314 | ({3{~del_noshift_d & pku_raw_pick_p[1]}} & isrc1_in[2:0]) | |
| 315 | ({3{~del_noshift_d & pku_raw_pick_p[2]}} & isrc2_in[2:0]) | |
| 316 | ({3{~del_noshift_d & pku_raw_pick_p[3]}} & isrc3_in[2:0]); |
| 317 | |
| 318 | |
| 319 | dec_ded_ctl_msff_ctl_macro__width_3 isrcf ( |
| 320 | .scan_in(isrcf_scanin), |
| 321 | .scan_out(isrcf_scanout), |
| 322 | .din(isrc_in[2:0]), |
| 323 | .dout(isrc_d[2:0]), |
| 324 | .l1clk(l1clk), |
| 325 | .siclk(siclk), |
| 326 | .soclk(soclk) |
| 327 | ); |
| 328 | |
| 329 | |
| 330 | |
| 331 | |
| 332 | |
| 333 | assign exc_in[4:0] = ({5{del_noshift_d}} & ded_exc_d[4:0]) | |
| 334 | ({5{~del_noshift_d & pku_raw_pick_p[0]}} & ifu_buf0_excp0[4:0]) | |
| 335 | ({5{~del_noshift_d & pku_raw_pick_p[1]}} & ifu_buf0_excp1[4:0]) | |
| 336 | ({5{~del_noshift_d & pku_raw_pick_p[2]}} & ifu_buf0_excp2[4:0]) | |
| 337 | ({5{~del_noshift_d & pku_raw_pick_p[3]}} & ifu_buf0_excp3[4:0]); |
| 338 | |
| 339 | dec_ded_ctl_msff_ctl_macro__width_5 excf ( |
| 340 | .scan_in(excf_scanin), |
| 341 | .scan_out(excf_scanout), |
| 342 | .din(exc_in[4:0]), |
| 343 | .dout(ded_exc_d[4:0]), |
| 344 | .l1clk(l1clk), |
| 345 | .siclk(siclk), |
| 346 | .soclk(soclk) |
| 347 | ); |
| 348 | |
| 349 | |
| 350 | assign decode_mux[32:0] = ({33{del_noshift_d}} & dec_inst_d[32:0]) | |
| 351 | ({33{~del_noshift_d & pku_raw_pick_p[0]}} & ifu_buf0_inst0[32:0]) | |
| 352 | ({33{~del_noshift_d & pku_raw_pick_p[1]}} & ifu_buf0_inst1[32:0]) | |
| 353 | ({33{~del_noshift_d & pku_raw_pick_p[2]}} & ifu_buf0_inst2[32:0]) | |
| 354 | ({33{~del_noshift_d & pku_raw_pick_p[3]}} & ifu_buf0_inst3[32:0]); |
| 355 | |
| 356 | dec_ded_ctl_msff_ctl_macro__width_33 decodef ( |
| 357 | .scan_in(decodef_scanin), |
| 358 | .scan_out(decodef_scanout), |
| 359 | .din(decode_mux[32:0]), |
| 360 | .dout(dec_inst_d[32:0]), |
| 361 | .l1clk(l1clk), |
| 362 | .siclk(siclk), |
| 363 | .soclk(soclk) |
| 364 | ); |
| 365 | |
| 366 | |
| 367 | // its only a parity error if its enabled |
| 368 | assign ded_perr_p = ( del_noshift_d & ded_perr_d) | |
| 369 | (~del_noshift_d & pku_raw_pick_p[0] & icdp_perr_en & (ifu_buf0_inst0[32] ^ (^ifu_buf0_inst0[31:0]))) | |
| 370 | (~del_noshift_d & pku_raw_pick_p[1] & icdp_perr_en & (ifu_buf0_inst1[32] ^ (^ifu_buf0_inst1[31:0]))) | |
| 371 | (~del_noshift_d & pku_raw_pick_p[2] & icdp_perr_en & (ifu_buf0_inst2[32] ^ (^ifu_buf0_inst2[31:0]))) | |
| 372 | (~del_noshift_d & pku_raw_pick_p[3] & icdp_perr_en & (ifu_buf0_inst3[32] ^ (^ifu_buf0_inst3[31:0]))); |
| 373 | |
| 374 | dec_ded_ctl_msff_ctl_macro__width_1 parityerrf ( |
| 375 | .scan_in(parityerrf_scanin), |
| 376 | .scan_out(parityerrf_scanout), |
| 377 | .din(ded_perr_p), |
| 378 | .dout(ded_perr_d), |
| 379 | .l1clk(l1clk), |
| 380 | .siclk(siclk), |
| 381 | .soclk(soclk) |
| 382 | ); |
| 383 | |
| 384 | assign ifetch_err_p[0] = (ifu_buf0_excp0[4:0] == 5'b00001) | |
| 385 | (ifu_buf0_excp0[4:0] == 5'b00010) | |
| 386 | (ifu_buf0_excp0[4:0] == 5'b00011) | |
| 387 | (ifu_buf0_excp0[4:0] == 5'b00100) | |
| 388 | (ifu_buf0_excp0[4:0] == 5'b00111) | |
| 389 | (ifu_buf0_excp0[4:0] == 5'b11111) | |
| 390 | (ifu_buf0_excp0[4:0] == 5'b01001) | |
| 391 | (ifu_buf0_excp0[4:0] == 5'b01010) | |
| 392 | (ifu_buf0_excp0[4:0] == 5'b01011) | |
| 393 | (ifu_buf0_excp0[4:0] == 5'b01100) | |
| 394 | (ifu_buf0_excp0[4:0] == 5'b01101) | |
| 395 | (ifu_buf0_excp0[4:0] == 5'b01111) | |
| 396 | (ifu_buf0_excp0[4:0] == 5'b10000) | |
| 397 | (ifu_buf0_excp0[4:0] == 5'b10001) | |
| 398 | (ifu_buf0_excp0[4:0] == 5'b10011) | |
| 399 | (ifu_buf0_excp0[4:0] == 5'b10111) | |
| 400 | (ifu_buf0_excp0[4:0] == 5'b11000); |
| 401 | |
| 402 | assign ifetch_err_p[1] = (ifu_buf0_excp1[4:0] == 5'b00001) | |
| 403 | (ifu_buf0_excp1[4:0] == 5'b00010) | |
| 404 | (ifu_buf0_excp1[4:0] == 5'b00011) | |
| 405 | (ifu_buf0_excp1[4:0] == 5'b00100) | |
| 406 | (ifu_buf0_excp1[4:0] == 5'b00111) | |
| 407 | (ifu_buf0_excp1[4:0] == 5'b11111) | |
| 408 | (ifu_buf0_excp1[4:0] == 5'b01001) | |
| 409 | (ifu_buf0_excp1[4:0] == 5'b01010) | |
| 410 | (ifu_buf0_excp1[4:0] == 5'b01011) | |
| 411 | (ifu_buf0_excp1[4:0] == 5'b01100) | |
| 412 | (ifu_buf0_excp1[4:0] == 5'b01101) | |
| 413 | (ifu_buf0_excp1[4:0] == 5'b01111) | |
| 414 | (ifu_buf0_excp1[4:0] == 5'b10000) | |
| 415 | (ifu_buf0_excp1[4:0] == 5'b10001) | |
| 416 | (ifu_buf0_excp1[4:0] == 5'b10011) | |
| 417 | (ifu_buf0_excp1[4:0] == 5'b10111) | |
| 418 | (ifu_buf0_excp1[4:0] == 5'b11000); |
| 419 | |
| 420 | assign ifetch_err_p[2] = (ifu_buf0_excp2[4:0] == 5'b00001) | |
| 421 | (ifu_buf0_excp2[4:0] == 5'b00010) | |
| 422 | (ifu_buf0_excp2[4:0] == 5'b00011) | |
| 423 | (ifu_buf0_excp2[4:0] == 5'b00100) | |
| 424 | (ifu_buf0_excp2[4:0] == 5'b00111) | |
| 425 | (ifu_buf0_excp2[4:0] == 5'b11111) | |
| 426 | (ifu_buf0_excp2[4:0] == 5'b01001) | |
| 427 | (ifu_buf0_excp2[4:0] == 5'b01010) | |
| 428 | (ifu_buf0_excp2[4:0] == 5'b01011) | |
| 429 | (ifu_buf0_excp2[4:0] == 5'b01100) | |
| 430 | (ifu_buf0_excp2[4:0] == 5'b01101) | |
| 431 | (ifu_buf0_excp2[4:0] == 5'b01111) | |
| 432 | (ifu_buf0_excp2[4:0] == 5'b10000) | |
| 433 | (ifu_buf0_excp2[4:0] == 5'b10001) | |
| 434 | (ifu_buf0_excp2[4:0] == 5'b10011) | |
| 435 | (ifu_buf0_excp2[4:0] == 5'b10111) | |
| 436 | (ifu_buf0_excp2[4:0] == 5'b11000); |
| 437 | |
| 438 | assign ifetch_err_p[3] = (ifu_buf0_excp3[4:0] == 5'b00001) | |
| 439 | (ifu_buf0_excp3[4:0] == 5'b00010) | |
| 440 | (ifu_buf0_excp3[4:0] == 5'b00011) | |
| 441 | (ifu_buf0_excp3[4:0] == 5'b00100) | |
| 442 | (ifu_buf0_excp3[4:0] == 5'b00111) | |
| 443 | (ifu_buf0_excp3[4:0] == 5'b11111) | |
| 444 | (ifu_buf0_excp3[4:0] == 5'b01001) | |
| 445 | (ifu_buf0_excp3[4:0] == 5'b01010) | |
| 446 | (ifu_buf0_excp3[4:0] == 5'b01011) | |
| 447 | (ifu_buf0_excp3[4:0] == 5'b01100) | |
| 448 | (ifu_buf0_excp3[4:0] == 5'b01101) | |
| 449 | (ifu_buf0_excp3[4:0] == 5'b01111) | |
| 450 | (ifu_buf0_excp3[4:0] == 5'b10000) | |
| 451 | (ifu_buf0_excp3[4:0] == 5'b10001) | |
| 452 | (ifu_buf0_excp3[4:0] == 5'b10011) | |
| 453 | (ifu_buf0_excp3[4:0] == 5'b10111) | |
| 454 | (ifu_buf0_excp3[4:0] == 5'b11000); |
| 455 | |
| 456 | assign ded_ferr_p = ( del_noshift_d & ded_ferr_d) | |
| 457 | (~del_noshift_d & pku_raw_pick_p[0] & ifetch_err_p[0]) | |
| 458 | (~del_noshift_d & pku_raw_pick_p[1] & ifetch_err_p[1] ) | |
| 459 | (~del_noshift_d & pku_raw_pick_p[2] & ifetch_err_p[2] ) | |
| 460 | (~del_noshift_d & pku_raw_pick_p[3] & ifetch_err_p[3] ); |
| 461 | |
| 462 | dec_ded_ctl_msff_ctl_macro__width_1 ifetcherrf ( |
| 463 | .scan_in(ifetcherrf_scanin), |
| 464 | .scan_out(ifetcherrf_scanout), |
| 465 | .din(ded_ferr_p), |
| 466 | .dout(ded_ferr_d), |
| 467 | .l1clk(l1clk), |
| 468 | .siclk(siclk), |
| 469 | .soclk(soclk) |
| 470 | ); |
| 471 | |
| 472 | assign illegal0_p = ~ifu_buf0_inst0[31] & ~ifu_buf0_inst0[30] & ~ifu_buf0_inst0[24] & ~ifu_buf0_inst0[23] & ~ifu_buf0_inst0[22]; |
| 473 | assign illegal1_p = ~ifu_buf0_inst1[31] & ~ifu_buf0_inst1[30] & ~ifu_buf0_inst1[24] & ~ifu_buf0_inst1[23] & ~ifu_buf0_inst1[22]; |
| 474 | assign illegal2_p = ~ifu_buf0_inst2[31] & ~ifu_buf0_inst2[30] & ~ifu_buf0_inst2[24] & ~ifu_buf0_inst2[23] & ~ifu_buf0_inst2[22]; |
| 475 | assign illegal3_p = ~ifu_buf0_inst3[31] & ~ifu_buf0_inst3[30] & ~ifu_buf0_inst3[24] & ~ifu_buf0_inst3[23] & ~ifu_buf0_inst3[22]; |
| 476 | |
| 477 | |
| 478 | assign ded_legal_p = ( del_noshift_d & legal_d) | |
| 479 | (~del_noshift_d & pku_raw_pick_p[0] & ~illegal0_p) | |
| 480 | (~del_noshift_d & pku_raw_pick_p[1] & ~illegal1_p) | |
| 481 | (~del_noshift_d & pku_raw_pick_p[2] & ~illegal2_p) | |
| 482 | (~del_noshift_d & pku_raw_pick_p[3] & ~illegal3_p); |
| 483 | |
| 484 | dec_ded_ctl_msff_ctl_macro__width_1 legalf ( |
| 485 | .scan_in(legalf_scanin), |
| 486 | .scan_out(legalf_scanout), |
| 487 | .din(ded_legal_p), |
| 488 | .dout(legal_d), |
| 489 | .l1clk(l1clk), |
| 490 | .siclk(siclk), |
| 491 | .soclk(soclk) |
| 492 | ); |
| 493 | |
| 494 | |
| 495 | // fixscan start: |
| 496 | assign spares_scanin = scan_in ; |
| 497 | assign icdf_perr_f_scanin = spares_scanout ; |
| 498 | assign oddwinf_scanin = icdf_perr_f_scanout ; |
| 499 | assign windowf_scanin = oddwinf_scanout ; |
| 500 | assign twocyclef_scanin = windowf_scanout ; |
| 501 | assign isrcf_scanin = twocyclef_scanout ; |
| 502 | assign excf_scanin = isrcf_scanout ; |
| 503 | assign decodef_scanin = excf_scanout ; |
| 504 | assign parityerrf_scanin = decodef_scanout ; |
| 505 | assign ifetcherrf_scanin = parityerrf_scanout ; |
| 506 | assign legalf_scanin = ifetcherrf_scanout ; |
| 507 | assign scan_out = legalf_scanout ; |
| 508 | // fixscan end: |
| 509 | endmodule |
| 510 | |
| 511 | |
| 512 | |
| 513 | |
| 514 | |
| 515 | |
| 516 | // any PARAMS parms go into naming of macro |
| 517 | |
| 518 | module dec_ded_ctl_l1clkhdr_ctl_macro ( |
| 519 | l2clk, |
| 520 | l1en, |
| 521 | pce_ov, |
| 522 | stop, |
| 523 | se, |
| 524 | l1clk); |
| 525 | |
| 526 | |
| 527 | input l2clk; |
| 528 | input l1en; |
| 529 | input pce_ov; |
| 530 | input stop; |
| 531 | input se; |
| 532 | output l1clk; |
| 533 | |
| 534 | |
| 535 | |
| 536 | |
| 537 | |
| 538 | cl_sc1_l1hdr_8x c_0 ( |
| 539 | |
| 540 | |
| 541 | .l2clk(l2clk), |
| 542 | .pce(l1en), |
| 543 | .l1clk(l1clk), |
| 544 | .se(se), |
| 545 | .pce_ov(pce_ov), |
| 546 | .stop(stop) |
| 547 | ); |
| 548 | |
| 549 | |
| 550 | |
| 551 | endmodule |
| 552 | |
| 553 | |
| 554 | |
| 555 | |
| 556 | |
| 557 | |
| 558 | |
| 559 | |
| 560 | |
| 561 | // Description: Spare gate macro for control blocks |
| 562 | // |
| 563 | // Param num controls the number of times the macro is added |
| 564 | // flops=0 can be used to use only combination spare logic |
| 565 | |
| 566 | |
| 567 | module dec_ded_ctl_spare_ctl_macro__num_2 ( |
| 568 | l1clk, |
| 569 | scan_in, |
| 570 | siclk, |
| 571 | soclk, |
| 572 | scan_out); |
| 573 | wire si_0; |
| 574 | wire so_0; |
| 575 | wire spare0_flop_unused; |
| 576 | wire spare0_buf_32x_unused; |
| 577 | wire spare0_nand3_8x_unused; |
| 578 | wire spare0_inv_8x_unused; |
| 579 | wire spare0_aoi22_4x_unused; |
| 580 | wire spare0_buf_8x_unused; |
| 581 | wire spare0_oai22_4x_unused; |
| 582 | wire spare0_inv_16x_unused; |
| 583 | wire spare0_nand2_16x_unused; |
| 584 | wire spare0_nor3_4x_unused; |
| 585 | wire spare0_nand2_8x_unused; |
| 586 | wire spare0_buf_16x_unused; |
| 587 | wire spare0_nor2_16x_unused; |
| 588 | wire spare0_inv_32x_unused; |
| 589 | wire si_1; |
| 590 | wire so_1; |
| 591 | wire spare1_flop_unused; |
| 592 | wire spare1_buf_32x_unused; |
| 593 | wire spare1_nand3_8x_unused; |
| 594 | wire spare1_inv_8x_unused; |
| 595 | wire spare1_aoi22_4x_unused; |
| 596 | wire spare1_buf_8x_unused; |
| 597 | wire spare1_oai22_4x_unused; |
| 598 | wire spare1_inv_16x_unused; |
| 599 | wire spare1_nand2_16x_unused; |
| 600 | wire spare1_nor3_4x_unused; |
| 601 | wire spare1_nand2_8x_unused; |
| 602 | wire spare1_buf_16x_unused; |
| 603 | wire spare1_nor2_16x_unused; |
| 604 | wire spare1_inv_32x_unused; |
| 605 | |
| 606 | |
| 607 | input l1clk; |
| 608 | input scan_in; |
| 609 | input siclk; |
| 610 | input soclk; |
| 611 | output scan_out; |
| 612 | |
| 613 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), |
| 614 | .siclk(siclk), |
| 615 | .soclk(soclk), |
| 616 | .si(si_0), |
| 617 | .so(so_0), |
| 618 | .d(1'b0), |
| 619 | .q(spare0_flop_unused)); |
| 620 | assign si_0 = scan_in; |
| 621 | |
| 622 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), |
| 623 | .out(spare0_buf_32x_unused)); |
| 624 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), |
| 625 | .in1(1'b1), |
| 626 | .in2(1'b1), |
| 627 | .out(spare0_nand3_8x_unused)); |
| 628 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), |
| 629 | .out(spare0_inv_8x_unused)); |
| 630 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), |
| 631 | .in01(1'b1), |
| 632 | .in10(1'b1), |
| 633 | .in11(1'b1), |
| 634 | .out(spare0_aoi22_4x_unused)); |
| 635 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), |
| 636 | .out(spare0_buf_8x_unused)); |
| 637 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), |
| 638 | .in01(1'b1), |
| 639 | .in10(1'b1), |
| 640 | .in11(1'b1), |
| 641 | .out(spare0_oai22_4x_unused)); |
| 642 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), |
| 643 | .out(spare0_inv_16x_unused)); |
| 644 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), |
| 645 | .in1(1'b1), |
| 646 | .out(spare0_nand2_16x_unused)); |
| 647 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), |
| 648 | .in1(1'b0), |
| 649 | .in2(1'b0), |
| 650 | .out(spare0_nor3_4x_unused)); |
| 651 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), |
| 652 | .in1(1'b1), |
| 653 | .out(spare0_nand2_8x_unused)); |
| 654 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), |
| 655 | .out(spare0_buf_16x_unused)); |
| 656 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), |
| 657 | .in1(1'b0), |
| 658 | .out(spare0_nor2_16x_unused)); |
| 659 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), |
| 660 | .out(spare0_inv_32x_unused)); |
| 661 | |
| 662 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), |
| 663 | .siclk(siclk), |
| 664 | .soclk(soclk), |
| 665 | .si(si_1), |
| 666 | .so(so_1), |
| 667 | .d(1'b0), |
| 668 | .q(spare1_flop_unused)); |
| 669 | assign si_1 = so_0; |
| 670 | |
| 671 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), |
| 672 | .out(spare1_buf_32x_unused)); |
| 673 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), |
| 674 | .in1(1'b1), |
| 675 | .in2(1'b1), |
| 676 | .out(spare1_nand3_8x_unused)); |
| 677 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), |
| 678 | .out(spare1_inv_8x_unused)); |
| 679 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), |
| 680 | .in01(1'b1), |
| 681 | .in10(1'b1), |
| 682 | .in11(1'b1), |
| 683 | .out(spare1_aoi22_4x_unused)); |
| 684 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), |
| 685 | .out(spare1_buf_8x_unused)); |
| 686 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), |
| 687 | .in01(1'b1), |
| 688 | .in10(1'b1), |
| 689 | .in11(1'b1), |
| 690 | .out(spare1_oai22_4x_unused)); |
| 691 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), |
| 692 | .out(spare1_inv_16x_unused)); |
| 693 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), |
| 694 | .in1(1'b1), |
| 695 | .out(spare1_nand2_16x_unused)); |
| 696 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), |
| 697 | .in1(1'b0), |
| 698 | .in2(1'b0), |
| 699 | .out(spare1_nor3_4x_unused)); |
| 700 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), |
| 701 | .in1(1'b1), |
| 702 | .out(spare1_nand2_8x_unused)); |
| 703 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), |
| 704 | .out(spare1_buf_16x_unused)); |
| 705 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), |
| 706 | .in1(1'b0), |
| 707 | .out(spare1_nor2_16x_unused)); |
| 708 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), |
| 709 | .out(spare1_inv_32x_unused)); |
| 710 | assign scan_out = so_1; |
| 711 | |
| 712 | |
| 713 | |
| 714 | endmodule |
| 715 | |
| 716 | |
| 717 | |
| 718 | |
| 719 | |
| 720 | |
| 721 | // any PARAMS parms go into naming of macro |
| 722 | |
| 723 | module dec_ded_ctl_msff_ctl_macro__width_1 ( |
| 724 | din, |
| 725 | l1clk, |
| 726 | scan_in, |
| 727 | siclk, |
| 728 | soclk, |
| 729 | dout, |
| 730 | scan_out); |
| 731 | wire [0:0] fdin; |
| 732 | |
| 733 | input [0:0] din; |
| 734 | input l1clk; |
| 735 | input scan_in; |
| 736 | |
| 737 | |
| 738 | input siclk; |
| 739 | input soclk; |
| 740 | |
| 741 | output [0:0] dout; |
| 742 | output scan_out; |
| 743 | assign fdin[0:0] = din[0:0]; |
| 744 | |
| 745 | |
| 746 | |
| 747 | |
| 748 | |
| 749 | |
| 750 | dff #(1) d0_0 ( |
| 751 | .l1clk(l1clk), |
| 752 | .siclk(siclk), |
| 753 | .soclk(soclk), |
| 754 | .d(fdin[0:0]), |
| 755 | .si(scan_in), |
| 756 | .so(scan_out), |
| 757 | .q(dout[0:0]) |
| 758 | ); |
| 759 | |
| 760 | |
| 761 | |
| 762 | |
| 763 | |
| 764 | |
| 765 | |
| 766 | |
| 767 | |
| 768 | |
| 769 | |
| 770 | |
| 771 | endmodule |
| 772 | |
| 773 | |
| 774 | |
| 775 | |
| 776 | |
| 777 | |
| 778 | |
| 779 | |
| 780 | |
| 781 | |
| 782 | |
| 783 | |
| 784 | |
| 785 | // any PARAMS parms go into naming of macro |
| 786 | |
| 787 | module dec_ded_ctl_msff_ctl_macro__width_4 ( |
| 788 | din, |
| 789 | l1clk, |
| 790 | scan_in, |
| 791 | siclk, |
| 792 | soclk, |
| 793 | dout, |
| 794 | scan_out); |
| 795 | wire [3:0] fdin; |
| 796 | wire [2:0] so; |
| 797 | |
| 798 | input [3:0] din; |
| 799 | input l1clk; |
| 800 | input scan_in; |
| 801 | |
| 802 | |
| 803 | input siclk; |
| 804 | input soclk; |
| 805 | |
| 806 | output [3:0] dout; |
| 807 | output scan_out; |
| 808 | assign fdin[3:0] = din[3:0]; |
| 809 | |
| 810 | |
| 811 | |
| 812 | |
| 813 | |
| 814 | |
| 815 | dff #(4) d0_0 ( |
| 816 | .l1clk(l1clk), |
| 817 | .siclk(siclk), |
| 818 | .soclk(soclk), |
| 819 | .d(fdin[3:0]), |
| 820 | .si({scan_in,so[2:0]}), |
| 821 | .so({so[2:0],scan_out}), |
| 822 | .q(dout[3:0]) |
| 823 | ); |
| 824 | |
| 825 | |
| 826 | |
| 827 | |
| 828 | |
| 829 | |
| 830 | |
| 831 | |
| 832 | |
| 833 | |
| 834 | |
| 835 | |
| 836 | endmodule |
| 837 | |
| 838 | |
| 839 | |
| 840 | |
| 841 | |
| 842 | |
| 843 | |
| 844 | |
| 845 | |
| 846 | |
| 847 | |
| 848 | |
| 849 | |
| 850 | // any PARAMS parms go into naming of macro |
| 851 | |
| 852 | module dec_ded_ctl_msff_ctl_macro__width_9 ( |
| 853 | din, |
| 854 | l1clk, |
| 855 | scan_in, |
| 856 | siclk, |
| 857 | soclk, |
| 858 | dout, |
| 859 | scan_out); |
| 860 | wire [8:0] fdin; |
| 861 | wire [7:0] so; |
| 862 | |
| 863 | input [8:0] din; |
| 864 | input l1clk; |
| 865 | input scan_in; |
| 866 | |
| 867 | |
| 868 | input siclk; |
| 869 | input soclk; |
| 870 | |
| 871 | output [8:0] dout; |
| 872 | output scan_out; |
| 873 | assign fdin[8:0] = din[8:0]; |
| 874 | |
| 875 | |
| 876 | |
| 877 | |
| 878 | |
| 879 | |
| 880 | dff #(9) d0_0 ( |
| 881 | .l1clk(l1clk), |
| 882 | .siclk(siclk), |
| 883 | .soclk(soclk), |
| 884 | .d(fdin[8:0]), |
| 885 | .si({scan_in,so[7:0]}), |
| 886 | .so({so[7:0],scan_out}), |
| 887 | .q(dout[8:0]) |
| 888 | ); |
| 889 | |
| 890 | |
| 891 | |
| 892 | |
| 893 | |
| 894 | |
| 895 | |
| 896 | |
| 897 | |
| 898 | |
| 899 | |
| 900 | |
| 901 | endmodule |
| 902 | |
| 903 | |
| 904 | |
| 905 | |
| 906 | |
| 907 | |
| 908 | |
| 909 | |
| 910 | |
| 911 | |
| 912 | |
| 913 | |
| 914 | |
| 915 | // any PARAMS parms go into naming of macro |
| 916 | |
| 917 | module dec_ded_ctl_msff_ctl_macro__width_3 ( |
| 918 | din, |
| 919 | l1clk, |
| 920 | scan_in, |
| 921 | siclk, |
| 922 | soclk, |
| 923 | dout, |
| 924 | scan_out); |
| 925 | wire [2:0] fdin; |
| 926 | wire [1:0] so; |
| 927 | |
| 928 | input [2:0] din; |
| 929 | input l1clk; |
| 930 | input scan_in; |
| 931 | |
| 932 | |
| 933 | input siclk; |
| 934 | input soclk; |
| 935 | |
| 936 | output [2:0] dout; |
| 937 | output scan_out; |
| 938 | assign fdin[2:0] = din[2:0]; |
| 939 | |
| 940 | |
| 941 | |
| 942 | |
| 943 | |
| 944 | |
| 945 | dff #(3) d0_0 ( |
| 946 | .l1clk(l1clk), |
| 947 | .siclk(siclk), |
| 948 | .soclk(soclk), |
| 949 | .d(fdin[2:0]), |
| 950 | .si({scan_in,so[1:0]}), |
| 951 | .so({so[1:0],scan_out}), |
| 952 | .q(dout[2:0]) |
| 953 | ); |
| 954 | |
| 955 | |
| 956 | |
| 957 | |
| 958 | |
| 959 | |
| 960 | |
| 961 | |
| 962 | |
| 963 | |
| 964 | |
| 965 | |
| 966 | endmodule |
| 967 | |
| 968 | |
| 969 | |
| 970 | |
| 971 | |
| 972 | |
| 973 | |
| 974 | |
| 975 | |
| 976 | |
| 977 | |
| 978 | |
| 979 | |
| 980 | // any PARAMS parms go into naming of macro |
| 981 | |
| 982 | module dec_ded_ctl_msff_ctl_macro__width_5 ( |
| 983 | din, |
| 984 | l1clk, |
| 985 | scan_in, |
| 986 | siclk, |
| 987 | soclk, |
| 988 | dout, |
| 989 | scan_out); |
| 990 | wire [4:0] fdin; |
| 991 | wire [3:0] so; |
| 992 | |
| 993 | input [4:0] din; |
| 994 | input l1clk; |
| 995 | input scan_in; |
| 996 | |
| 997 | |
| 998 | input siclk; |
| 999 | input soclk; |
| 1000 | |
| 1001 | output [4:0] dout; |
| 1002 | output scan_out; |
| 1003 | assign fdin[4:0] = din[4:0]; |
| 1004 | |
| 1005 | |
| 1006 | |
| 1007 | |
| 1008 | |
| 1009 | |
| 1010 | dff #(5) d0_0 ( |
| 1011 | .l1clk(l1clk), |
| 1012 | .siclk(siclk), |
| 1013 | .soclk(soclk), |
| 1014 | .d(fdin[4:0]), |
| 1015 | .si({scan_in,so[3:0]}), |
| 1016 | .so({so[3:0],scan_out}), |
| 1017 | .q(dout[4:0]) |
| 1018 | ); |
| 1019 | |
| 1020 | |
| 1021 | |
| 1022 | |
| 1023 | |
| 1024 | |
| 1025 | |
| 1026 | |
| 1027 | |
| 1028 | |
| 1029 | |
| 1030 | |
| 1031 | endmodule |
| 1032 | |
| 1033 | |
| 1034 | |
| 1035 | |
| 1036 | |
| 1037 | |
| 1038 | |
| 1039 | |
| 1040 | |
| 1041 | |
| 1042 | |
| 1043 | |
| 1044 | |
| 1045 | // any PARAMS parms go into naming of macro |
| 1046 | |
| 1047 | module dec_ded_ctl_msff_ctl_macro__width_33 ( |
| 1048 | din, |
| 1049 | l1clk, |
| 1050 | scan_in, |
| 1051 | siclk, |
| 1052 | soclk, |
| 1053 | dout, |
| 1054 | scan_out); |
| 1055 | wire [32:0] fdin; |
| 1056 | wire [31:0] so; |
| 1057 | |
| 1058 | input [32:0] din; |
| 1059 | input l1clk; |
| 1060 | input scan_in; |
| 1061 | |
| 1062 | |
| 1063 | input siclk; |
| 1064 | input soclk; |
| 1065 | |
| 1066 | output [32:0] dout; |
| 1067 | output scan_out; |
| 1068 | assign fdin[32:0] = din[32:0]; |
| 1069 | |
| 1070 | |
| 1071 | |
| 1072 | |
| 1073 | |
| 1074 | |
| 1075 | dff #(33) d0_0 ( |
| 1076 | .l1clk(l1clk), |
| 1077 | .siclk(siclk), |
| 1078 | .soclk(soclk), |
| 1079 | .d(fdin[32:0]), |
| 1080 | .si({scan_in,so[31:0]}), |
| 1081 | .so({so[31:0],scan_out}), |
| 1082 | .q(dout[32:0]) |
| 1083 | ); |
| 1084 | |
| 1085 | |
| 1086 | |
| 1087 | |
| 1088 | |
| 1089 | |
| 1090 | |
| 1091 | |
| 1092 | |
| 1093 | |
| 1094 | |
| 1095 | |
| 1096 | endmodule |
| 1097 | |
| 1098 | |
| 1099 | |
| 1100 | |
| 1101 | |
| 1102 | |
| 1103 | |
| 1104 | |