| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: exu.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module exu ( |
| 36 | l2clk, |
| 37 | scan_in, |
| 38 | wmr_scan_in, |
| 39 | tcu_pce_ov, |
| 40 | spc_aclk, |
| 41 | spc_bclk, |
| 42 | spc_aclk_wmr, |
| 43 | tcu_scan_en, |
| 44 | tcu_array_wr_inhibit, |
| 45 | tcu_se_scancollar_in, |
| 46 | tcu_dectest, |
| 47 | tcu_muxtest, |
| 48 | in_rngl_cdbus, |
| 49 | dec_tid_p, |
| 50 | dec_inst_rs1_vld_p, |
| 51 | dec_inst_rs2_vld_p, |
| 52 | dec_inst_rs3_vld_p, |
| 53 | dec_inst_rs1_p, |
| 54 | dec_inst_rs2_p, |
| 55 | dec_inst_rs3_p, |
| 56 | dec_exu_clken, |
| 57 | dec_inst_rd_d, |
| 58 | dec_inst_d, |
| 59 | dec_decode_d, |
| 60 | dec_thread_group, |
| 61 | tlu_pc_d, |
| 62 | dec_valid_e, |
| 63 | tlu_itlb_bypass_e, |
| 64 | dec_flush_m, |
| 65 | dec_flush_b, |
| 66 | fgu_exu_icc_fx5, |
| 67 | fgu_exu_xcc_fx5, |
| 68 | fgu_exu_cc_vld_fx5, |
| 69 | fgu_exu_result_fx5, |
| 70 | fgu_result_tid_fx5, |
| 71 | fgu_irf_w_addr_fx5, |
| 72 | fgu_exu_w_vld_fx5, |
| 73 | lsu_exu_ld_data_b, |
| 74 | lsu_exu_ld_b, |
| 75 | lsu_exu_rd_m, |
| 76 | lsu_exu_tid_m, |
| 77 | lsu_exu_ld_vld_w, |
| 78 | tlu_flush_exu_b, |
| 79 | tlu_ccr, |
| 80 | tlu_cwp, |
| 81 | tlu_ccr_cwp_valid, |
| 82 | tlu_ccr_cwp_tid, |
| 83 | tlu_pstate_am, |
| 84 | tlu_gl_thr0, |
| 85 | tlu_gl_thr1, |
| 86 | tlu_gl_thr2, |
| 87 | tlu_gl_thr3, |
| 88 | tlu_cerer_irf, |
| 89 | tlu_ceter_pscce, |
| 90 | lsu_asi_error_inject_b31, |
| 91 | lsu_asi_error_inject_b25, |
| 92 | lsu_asi_error_inject, |
| 93 | lsu_exu_pmen, |
| 94 | lsu_asi_clken, |
| 95 | spc_core_running_status, |
| 96 | mbi_run, |
| 97 | mbi_addr, |
| 98 | mbi_write_data_p1, |
| 99 | mbi_irf_read_en, |
| 100 | mbi_irf_write_en, |
| 101 | mbi_irf_save_en, |
| 102 | mbi_irf_restore_en, |
| 103 | fgu_fld_fcc_fx3, |
| 104 | lsu_fgu_fld_tid_b, |
| 105 | fgu_fld_fcc_vld_fx3, |
| 106 | lsu_fgu_fld_vld_w, |
| 107 | fgu_cmp_fcc_fx3, |
| 108 | fgu_cmp_fcc_tid_fx2, |
| 109 | fgu_cmp_fcc_vld_fx3, |
| 110 | dec_pick_d, |
| 111 | exu_rngl_cdbus, |
| 112 | exu_oddwin_b, |
| 113 | exu_address_e, |
| 114 | exu_mdp_mux_sel_e, |
| 115 | exu_ms_icc_e, |
| 116 | exu_rs1_data_e, |
| 117 | exu_rs2_data_e, |
| 118 | exu_store_data_e, |
| 119 | exu_y_data_e, |
| 120 | exu_ecc_m, |
| 121 | exu_ecc_winop_flush_m, |
| 122 | exu_gsr_data_m, |
| 123 | exu_gsr_vld_m, |
| 124 | exu_lsu_va_error_m, |
| 125 | exu_ibp_m, |
| 126 | exu_ecc_addr_m, |
| 127 | exu_ecc_check_m, |
| 128 | exu_cecc_m, |
| 129 | exu_uecc_m, |
| 130 | exu_misalign_m, |
| 131 | exu_oor_va_m, |
| 132 | exu_tcc_m, |
| 133 | exu_tof_m, |
| 134 | exu_trap_number_b, |
| 135 | exu_spill_b, |
| 136 | exu_fill_m, |
| 137 | exu_normal_b, |
| 138 | exu_cleanwin_b, |
| 139 | exu_wstate_b, |
| 140 | exu_ccr0, |
| 141 | exu_ccr1, |
| 142 | exu_ccr2, |
| 143 | exu_ccr3, |
| 144 | exu_cwp_thr0, |
| 145 | exu_cwp_thr1, |
| 146 | exu_cwp_thr2, |
| 147 | exu_cwp_thr3, |
| 148 | exu_window_block_m, |
| 149 | exu_tlu_window_block, |
| 150 | exu_test_valid, |
| 151 | exu_test_tid, |
| 152 | exu_test_addr, |
| 153 | exu_mbi_irf_fail_, |
| 154 | exu_br_taken_e, |
| 155 | exu_br_taken_e1, |
| 156 | exu_cmov_true_m, |
| 157 | scan_out, |
| 158 | wmr_scan_out); |
| 159 | wire edp_scanin; |
| 160 | wire edp_scanout; |
| 161 | wire ect_wmr_scanin; |
| 162 | wire ect_wmr_scanout; |
| 163 | wire ect_scanin; |
| 164 | wire ect_scanout; |
| 165 | wire [64:0] edp_rng_in_ff; |
| 166 | wire ecc_scanin; |
| 167 | wire ecc_scanout; |
| 168 | wire rml_wmr_scanin; |
| 169 | wire rml_wmr_scanout; |
| 170 | wire rml_scanin; |
| 171 | wire rml_scanout; |
| 172 | wire irf_scanin; |
| 173 | wire irf_scanout; |
| 174 | wire ect_tg_clken; |
| 175 | wire ect_valid_lth_w; |
| 176 | wire [1:0] ect_tid_lth_w; |
| 177 | wire [4:0] ect_rd_lth_w; |
| 178 | wire [7:0] ecc_w_synd_w; |
| 179 | wire [63:0] edp_rd_ff_w; |
| 180 | wire ect_valid_in_w2; |
| 181 | wire [1:0] ect_tid_lth_w2; |
| 182 | wire [4:0] ect_rd_lth_w2; |
| 183 | wire [7:0] ecc_w2_synd_w2; |
| 184 | wire [63:0] edp_rd_ff_w2; |
| 185 | wire [1:0] rml_irf_cwpswap_tid_m; |
| 186 | wire [2:0] rml_irf_old_lo_cwp_m; |
| 187 | wire [2:1] rml_irf_old_e_cwp_m; |
| 188 | wire rml_irf_save_even_m; |
| 189 | wire rml_irf_save_odd_m; |
| 190 | wire rml_irf_save_local_m; |
| 191 | wire [1:0] rml_irf_cwpswap_tid_b; |
| 192 | wire [2:0] rml_irf_new_lo_cwp_b; |
| 193 | wire [2:1] rml_irf_new_e_cwp_b; |
| 194 | wire rml_irf_restore_even_b; |
| 195 | wire rml_irf_restore_odd_b; |
| 196 | wire rml_irf_restore_local_b; |
| 197 | wire rml_irf_save_global; |
| 198 | wire [1:0] rml_irf_global_tid; |
| 199 | wire [1:0] rml_irf_old_agp; |
| 200 | wire rml_irf_restore_global; |
| 201 | wire [1:0] rml_irf_global_tid_ff; |
| 202 | wire [1:0] rml_irf_new_agp_ff; |
| 203 | wire [71:0] irf_rs1_data_d; |
| 204 | wire [71:0] irf_rs2_data_d; |
| 205 | wire [71:0] irf_rs3_data_d; |
| 206 | wire [5:0] rml_rng_data_out; |
| 207 | wire [4:0] rml_rng_rd_ctl; |
| 208 | wire [1:0] rml_rng_ack_ctl; |
| 209 | wire [1:0] rml_rng_ack_cwp_tid; |
| 210 | wire [1:0] rml_rng_ack_ecc_tid; |
| 211 | wire rml_rng_ack_det_vld; |
| 212 | wire rml_rng_wt_imask_ctl; |
| 213 | wire [7:0] rml_irf_ecc_data; |
| 214 | wire rml_rng_ack_sel_ctl; |
| 215 | wire [31:0] rml_rng_y_data; |
| 216 | wire [7:0] ect_rng_ccr_data; |
| 217 | wire ect_mbist_sel; |
| 218 | wire [7:0] ecc_mbist_write_data_p4; |
| 219 | wire [4:0] ect_rs1_early_sel_d; |
| 220 | wire [4:0] ect_rs2_early_sel_d; |
| 221 | wire [4:0] ect_rs3_early_sel_d; |
| 222 | wire [7:0] ect_rs2_imm_sel_d; |
| 223 | wire [3:0] ect_rs1_late_sel_d; |
| 224 | wire [3:0] ect_rs2_late_sel_d; |
| 225 | wire [3:0] ect_rs3_late_sel_d; |
| 226 | wire [3:0] ect_logic_sel_d; |
| 227 | wire [6:0] ect_shift_sel_d; |
| 228 | wire ect_br_taken_z0_e; |
| 229 | wire ect_br_taken_z1_e; |
| 230 | wire ect_alignaddress_little_e; |
| 231 | wire ect_as_clip_e_; |
| 232 | wire ect_as_cin_e; |
| 233 | wire [1:0] ect_array_sel_e; |
| 234 | wire [7:0] ect_edge_lmask_e; |
| 235 | wire [7:0] ect_edge_lrmask_e; |
| 236 | wire ect_pstate_am_e; |
| 237 | wire [5:0] ect_rm_early_sel_e; |
| 238 | wire [2:0] ect_rm_late_sel_e; |
| 239 | wire ect_store_mux_sel_e; |
| 240 | wire ect_ex_emb_clken; |
| 241 | wire [1:0] edp_br_flag_e; |
| 242 | wire [63:0] edp_rcc_data_e; |
| 243 | wire [63:0] edp_rs3_data_e; |
| 244 | wire [7:0] edp_rcc_ecc_e; |
| 245 | wire [7:0] edp_rs2_ecc_e; |
| 246 | wire [7:0] edp_rs3_ecc_e; |
| 247 | wire edp_add_cout64_e; |
| 248 | wire edp_add_data_e_b63; |
| 249 | wire [1:0] edp_add_zdetect_e_; |
| 250 | wire edp_sub_cout64_e; |
| 251 | wire edp_sub_data_e_b63; |
| 252 | wire edp_sub_data_e_b31; |
| 253 | wire [1:0] edp_sub_zdetect_e_; |
| 254 | wire edp_logical_data_e_b63; |
| 255 | wire edp_logical_data_e_b31; |
| 256 | wire [1:0] edp_lg_zdetect_e; |
| 257 | wire [63:47] edp_address_m; |
| 258 | wire [63:47] edp_rd_ff_m; |
| 259 | wire rml_rng_wt_ccr_ctl; |
| 260 | wire rml_test_valid_d; |
| 261 | wire [1:0] ect_tid_lth_e; |
| 262 | wire [4:0] ect_rs1_addr_e; |
| 263 | wire [4:0] ect_rs2_addr_e; |
| 264 | wire [4:0] ect_rs3_addr_e; |
| 265 | wire ect_rs1_valid_e; |
| 266 | wire ect_rs2_valid_e; |
| 267 | wire ect_rs3_valid_e; |
| 268 | wire ect_two_cycle_m; |
| 269 | wire ect_yreg_wr_w; |
| 270 | wire ect_misaligned_error_m; |
| 271 | |
| 272 | |
| 273 | input l2clk; |
| 274 | input scan_in; |
| 275 | input wmr_scan_in; |
| 276 | input tcu_pce_ov; // scan signals |
| 277 | input spc_aclk; |
| 278 | input spc_bclk; |
| 279 | input spc_aclk_wmr; |
| 280 | input tcu_scan_en; |
| 281 | input tcu_array_wr_inhibit; |
| 282 | input tcu_se_scancollar_in; |
| 283 | input tcu_dectest; // Passgate mux test control |
| 284 | input tcu_muxtest; // Passgate mux test control |
| 285 | |
| 286 | input [64:0] in_rngl_cdbus; // ASI Ring |
| 287 | |
| 288 | input [1:0] dec_tid_p; |
| 289 | input dec_inst_rs1_vld_p; |
| 290 | input dec_inst_rs2_vld_p; |
| 291 | input dec_inst_rs3_vld_p; |
| 292 | input [4:0] dec_inst_rs1_p; |
| 293 | input [4:0] dec_inst_rs2_p; |
| 294 | input [4:0] dec_inst_rs3_p; |
| 295 | |
| 296 | input dec_exu_clken; // Powerdown for D->E Flops |
| 297 | input [4:0] dec_inst_rd_d; |
| 298 | input [31:0] dec_inst_d; |
| 299 | input dec_decode_d; // Instruction and TID are valid |
| 300 | input dec_thread_group; // Static Signal : Tie UP or DOWN where cloning occurs |
| 301 | input [47:2] tlu_pc_d; |
| 302 | |
| 303 | input dec_valid_e; // Late "E" Stage Valid |
| 304 | input tlu_itlb_bypass_e; // Ignore Address Out-Of-Range |
| 305 | |
| 306 | input dec_flush_m; |
| 307 | input dec_flush_b; |
| 308 | |
| 309 | input [3:0] fgu_exu_icc_fx5; // FGU int icc cond code {N,Z,V,C} |
| 310 | input [1:0] fgu_exu_xcc_fx5; // FGU int xcc cond code {N,Z} |
| 311 | input fgu_exu_cc_vld_fx5; // FGU int icc/xcc cond code valid |
| 312 | input [63:0] fgu_exu_result_fx5; // FGU Integer results |
| 313 | input [1:0] fgu_result_tid_fx5; |
| 314 | input [4:0] fgu_irf_w_addr_fx5; |
| 315 | input fgu_exu_w_vld_fx5; |
| 316 | |
| 317 | input [63:0] lsu_exu_ld_data_b; |
| 318 | input lsu_exu_ld_b; |
| 319 | input [4:0] lsu_exu_rd_m; |
| 320 | input [2:0] lsu_exu_tid_m; |
| 321 | input lsu_exu_ld_vld_w; |
| 322 | |
| 323 | input tlu_flush_exu_b; // EXU to flush instr in B stage |
| 324 | input [7:0] tlu_ccr; |
| 325 | input [2:0] tlu_cwp; |
| 326 | input tlu_ccr_cwp_valid; |
| 327 | input [1:0] tlu_ccr_cwp_tid; |
| 328 | input [3:0] tlu_pstate_am; // 32-bit addressing mode if = 1 |
| 329 | |
| 330 | input [1:0] tlu_gl_thr0; // From TLU : current GL value to update |
| 331 | input [1:0] tlu_gl_thr1; // From TLU : current GL value to update |
| 332 | input [1:0] tlu_gl_thr2; // From TLU : current GL value to update |
| 333 | input [1:0] tlu_gl_thr3; // From TLU : current GL value to update |
| 334 | |
| 335 | input tlu_cerer_irf; // IRF ecc error trap enable |
| 336 | input [3:0] tlu_ceter_pscce; // core error trap enable reg precise enable |
| 337 | |
| 338 | |
| 339 | input lsu_asi_error_inject_b31; // [31]=global inject en |
| 340 | input lsu_asi_error_inject_b25; // [25]=IRF inject en |
| 341 | input [7:0] lsu_asi_error_inject; // [7:0]=mask |
| 342 | input lsu_exu_pmen; // Power Management : Master Enable |
| 343 | input lsu_asi_clken; // Power Management : ASI ring |
| 344 | input [3:0] spc_core_running_status; // Power Management : Thread active |
| 345 | |
| 346 | input mbi_run; // MBIST |
| 347 | input [9:0] mbi_addr; // MBIST |
| 348 | input [7:0] mbi_write_data_p1; // MBIST |
| 349 | input mbi_irf_read_en; // MBIST |
| 350 | input mbi_irf_write_en; // MBIST |
| 351 | input mbi_irf_save_en; // MBIST |
| 352 | input mbi_irf_restore_en; // MBIST |
| 353 | |
| 354 | // *** DEC_CCR Inputs *** |
| 355 | |
| 356 | input [7:0] fgu_fld_fcc_fx3; // fcc's from the fgu |
| 357 | input [2:0] lsu_fgu_fld_tid_b; |
| 358 | input [1:0] fgu_fld_fcc_vld_fx3; |
| 359 | input lsu_fgu_fld_vld_w; // Float load valid |
| 360 | |
| 361 | input [1:0] fgu_cmp_fcc_fx3; // fcc's from the fgu |
| 362 | input [2:0] fgu_cmp_fcc_tid_fx2; |
| 363 | input [3:0] fgu_cmp_fcc_vld_fx3; |
| 364 | |
| 365 | input [3:0] dec_pick_d; // which stand is valid at d |
| 366 | |
| 367 | |
| 368 | output [64:0] exu_rngl_cdbus; // ASI Ring |
| 369 | |
| 370 | output [3:0] exu_oddwin_b; // To Decode |
| 371 | output [47:0] exu_address_e; // To IFU and LSU |
| 372 | output [5:0] exu_mdp_mux_sel_e; // To MDP |
| 373 | output exu_ms_icc_e; |
| 374 | output [63:0] exu_rs1_data_e; // To MDP |
| 375 | output [63:0] exu_rs2_data_e; // To MDP |
| 376 | output [63:0] exu_store_data_e; // To LSU |
| 377 | output [31:0] exu_y_data_e; // To MDP |
| 378 | |
| 379 | output exu_ecc_m; // To FGU |
| 380 | output exu_ecc_winop_flush_m; // To FGU : signal "1" when ECC or WINOP exception |
| 381 | // to flush FGU |
| 382 | output [31:0] exu_gsr_data_m; // To FGU |
| 383 | output [1:0] exu_gsr_vld_m; // To FGU |
| 384 | output exu_lsu_va_error_m; // To LSU : Address Out of Range |
| 385 | |
| 386 | output exu_ibp_m; // To TLU : Raw Intruction Breakpoint |
| 387 | output [4:0] exu_ecc_addr_m; // To TLU : |
| 388 | output [7:0] exu_ecc_check_m; // To TLU : |
| 389 | output exu_cecc_m; // To TLU : Correctable ECC Error |
| 390 | output exu_uecc_m; // To TLU : Uncorrectable ECC Error |
| 391 | |
| 392 | output exu_misalign_m; // To TLU : Misaligned address for Jump,Return |
| 393 | output exu_oor_va_m; // To TLU : Address Out of Range |
| 394 | output exu_tcc_m; // To TLU : Trap taken |
| 395 | output exu_tof_m; // To TLU : Tagged Add TV with overflow |
| 396 | output [7:0] exu_trap_number_b; // To TLU |
| 397 | |
| 398 | output exu_spill_b; // To TLU : report window spill exception |
| 399 | output exu_fill_m; // To TLU : report window fill exception |
| 400 | output exu_normal_b; // To TLU : report window spill/fill exception type |
| 401 | output exu_cleanwin_b; // To TLU : report clean window exception |
| 402 | output [2:0] exu_wstate_b; // To TLU : report fill/spill vector |
| 403 | |
| 404 | output [7:0] exu_ccr0; // To TLU : Architected CCR |
| 405 | output [7:0] exu_ccr1; // To TLU : Architected CCR |
| 406 | output [7:0] exu_ccr2; // To TLU : Architected CCR |
| 407 | output [7:0] exu_ccr3; // To TLU : Architected CCR |
| 408 | |
| 409 | output [2:0] exu_cwp_thr0; // To TLU : Current Window Pointer - thr0 |
| 410 | output [2:0] exu_cwp_thr1; // To TLU : Current Window Pointer - thr1 |
| 411 | output [2:0] exu_cwp_thr2; // To TLU : Current Window Pointer - thr2 |
| 412 | output [2:0] exu_cwp_thr3; // To TLU : Current Window Pointer - thr3 |
| 413 | |
| 414 | output exu_window_block_m; // create bubble for SWAP signal for IRF |
| 415 | output exu_tlu_window_block; // create bubble for SWAP signal for IRF |
| 416 | |
| 417 | output exu_test_valid; // To PKU : read IRF data |
| 418 | output [1:0] exu_test_tid; |
| 419 | output [4:0] exu_test_addr; |
| 420 | |
| 421 | output [1:0] exu_mbi_irf_fail_; // MBIST [0] == [63:0]; [1] == [71:64] |
| 422 | |
| 423 | |
| 424 | // *** DEC_CCR Outputs *** |
| 425 | |
| 426 | output exu_br_taken_e; // To IFU : branch is taken |
| 427 | output exu_br_taken_e1; // To DEC_DEL and PKU : branch is taken |
| 428 | output exu_cmov_true_m; |
| 429 | |
| 430 | output scan_out; |
| 431 | output wmr_scan_out; |
| 432 | |
| 433 | |
| 434 | |
| 435 | exu_edp_dp edp ( |
| 436 | .scan_in(edp_scanin), |
| 437 | .scan_out(edp_scanout), |
| 438 | .l2clk(l2clk), |
| 439 | .tcu_pce_ov(tcu_pce_ov), |
| 440 | .spc_aclk(spc_aclk), |
| 441 | .spc_bclk(spc_bclk), |
| 442 | .tcu_scan_en(tcu_scan_en), |
| 443 | .tcu_dectest(tcu_dectest), |
| 444 | .tcu_muxtest(tcu_muxtest), |
| 445 | .in_rngl_cdbus(in_rngl_cdbus[64:0]), |
| 446 | .tlu_pc_d(tlu_pc_d[47:2]), |
| 447 | .dec_inst_d(dec_inst_d[31:0]), |
| 448 | .dec_thread_group(dec_thread_group), |
| 449 | .dec_exu_clken(dec_exu_clken), |
| 450 | .fgu_exu_w_vld_fx5(fgu_exu_w_vld_fx5), |
| 451 | .fgu_exu_result_fx5(fgu_exu_result_fx5[63:0]), |
| 452 | .irf_rs1_data_d(irf_rs1_data_d[71:0]), |
| 453 | .irf_rs2_data_d(irf_rs2_data_d[71:0]), |
| 454 | .irf_rs3_data_d(irf_rs3_data_d[71:0]), |
| 455 | .lsu_asi_clken(lsu_asi_clken), |
| 456 | .lsu_exu_ld_data_b(lsu_exu_ld_data_b[63:0]), |
| 457 | .mbi_write_data_p1(mbi_write_data_p1[7:0]), |
| 458 | .exu_y_data_e(exu_y_data_e[31:0]), |
| 459 | .rml_rng_data_out(rml_rng_data_out[5:0]), |
| 460 | .rml_rng_rd_ctl(rml_rng_rd_ctl[4:0]), |
| 461 | .rml_rng_ack_ctl(rml_rng_ack_ctl[1:0]), |
| 462 | .rml_rng_ack_cwp_tid(rml_rng_ack_cwp_tid[1:0]), |
| 463 | .rml_rng_ack_ecc_tid(rml_rng_ack_ecc_tid[1:0]), |
| 464 | .rml_rng_ack_det_vld(rml_rng_ack_det_vld), |
| 465 | .rml_rng_wt_imask_ctl(rml_rng_wt_imask_ctl), |
| 466 | .rml_irf_ecc_data(rml_irf_ecc_data[7:0]), |
| 467 | .rml_rng_ack_sel_ctl(rml_rng_ack_sel_ctl), |
| 468 | .rml_rng_y_data(rml_rng_y_data[31:0]), |
| 469 | .ect_rng_ccr_data(ect_rng_ccr_data[7:0]), |
| 470 | .ect_mbist_sel(ect_mbist_sel), |
| 471 | .ecc_mbist_write_data_p4(ecc_mbist_write_data_p4[7:0]), |
| 472 | .ect_rs1_early_sel_d(ect_rs1_early_sel_d[4:0]), |
| 473 | .ect_rs2_early_sel_d(ect_rs2_early_sel_d[4:0]), |
| 474 | .ect_rs3_early_sel_d(ect_rs3_early_sel_d[4:0]), |
| 475 | .ect_rs2_imm_sel_d(ect_rs2_imm_sel_d[7:0]), |
| 476 | .ect_rs1_late_sel_d(ect_rs1_late_sel_d[3:0]), |
| 477 | .ect_rs2_late_sel_d(ect_rs2_late_sel_d[3:0]), |
| 478 | .ect_rs3_late_sel_d(ect_rs3_late_sel_d[3:0]), |
| 479 | .ect_logic_sel_d(ect_logic_sel_d[3:0]), |
| 480 | .ect_shift_sel_d(ect_shift_sel_d[6:0]), |
| 481 | .ect_br_taken_z0_e(ect_br_taken_z0_e), |
| 482 | .ect_br_taken_z1_e(ect_br_taken_z1_e), |
| 483 | .ect_alignaddress_little_e(ect_alignaddress_little_e), |
| 484 | .ect_as_clip_e_(ect_as_clip_e_), |
| 485 | .ect_as_cin_e(ect_as_cin_e), |
| 486 | .ect_array_sel_e(ect_array_sel_e[1:0]), |
| 487 | .ect_edge_lmask_e(ect_edge_lmask_e[7:0]), |
| 488 | .ect_edge_lrmask_e(ect_edge_lrmask_e[7:0]), |
| 489 | .ect_pstate_am_e(ect_pstate_am_e), |
| 490 | .ect_rm_early_sel_e(ect_rm_early_sel_e[5:0]), |
| 491 | .ect_rm_late_sel_e(ect_rm_late_sel_e[2:0]), |
| 492 | .ect_store_mux_sel_e(ect_store_mux_sel_e), |
| 493 | .ect_ex_emb_clken(ect_ex_emb_clken), |
| 494 | .ect_tg_clken(ect_tg_clken), |
| 495 | .exu_rngl_cdbus(exu_rngl_cdbus[64:0]), |
| 496 | .exu_br_taken_e(exu_br_taken_e), |
| 497 | .exu_br_taken_e1(exu_br_taken_e1), |
| 498 | .exu_address_e(exu_address_e[47:0]), |
| 499 | .exu_gsr_data_m(exu_gsr_data_m[31:0]), |
| 500 | .exu_store_data_e(exu_store_data_e[63:0]), |
| 501 | .exu_ibp_m(exu_ibp_m), |
| 502 | .exu_trap_number_b(exu_trap_number_b[7:0]), |
| 503 | .exu_mbi_irf_fail_(exu_mbi_irf_fail_[1:0]), |
| 504 | .edp_rng_in_ff(edp_rng_in_ff[64:0]), |
| 505 | .edp_br_flag_e(edp_br_flag_e[1:0]), |
| 506 | .exu_rs1_data_e(exu_rs1_data_e[63:0]), |
| 507 | .edp_rcc_data_e(edp_rcc_data_e[63:0]), |
| 508 | .exu_rs2_data_e(exu_rs2_data_e[63:0]), |
| 509 | .edp_rs3_data_e(edp_rs3_data_e[63:0]), |
| 510 | .edp_rcc_ecc_e(edp_rcc_ecc_e[7:0]), |
| 511 | .edp_rs2_ecc_e(edp_rs2_ecc_e[7:0]), |
| 512 | .edp_rs3_ecc_e(edp_rs3_ecc_e[7:0]), |
| 513 | .edp_add_cout64_e(edp_add_cout64_e), |
| 514 | .edp_add_data_e_b63(edp_add_data_e_b63), |
| 515 | .edp_add_zdetect_e_(edp_add_zdetect_e_[1:0]), |
| 516 | .edp_sub_cout64_e(edp_sub_cout64_e), |
| 517 | .edp_sub_data_e_b63(edp_sub_data_e_b63), |
| 518 | .edp_sub_data_e_b31(edp_sub_data_e_b31), |
| 519 | .edp_sub_zdetect_e_(edp_sub_zdetect_e_[1:0]), |
| 520 | .edp_logical_data_e_b63(edp_logical_data_e_b63), |
| 521 | .edp_logical_data_e_b31(edp_logical_data_e_b31), |
| 522 | .edp_lg_zdetect_e(edp_lg_zdetect_e[1:0]), |
| 523 | .edp_address_m(edp_address_m[63:47]), |
| 524 | .edp_rd_ff_m(edp_rd_ff_m[63:47]), |
| 525 | .edp_rd_ff_w(edp_rd_ff_w[63:0]), |
| 526 | .edp_rd_ff_w2(edp_rd_ff_w2[63:0]) |
| 527 | ); |
| 528 | |
| 529 | exu_ect_ctl ect ( // FS:wmr_protect |
| 530 | .wmr_scan_in(ect_wmr_scanin), |
| 531 | .wmr_scan_out(ect_wmr_scanout), |
| 532 | .scan_in(ect_scanin), |
| 533 | .scan_out(ect_scanout), |
| 534 | .l2clk(l2clk), |
| 535 | .edp_add_data_e_b0 ( exu_address_e[0] ), |
| 536 | .edp_add_data_e_b1 ( exu_address_e[1] ), |
| 537 | .edp_add_data_e_b31( exu_address_e[31] ), |
| 538 | .edp_rng_in_ff_b57 ( edp_rng_in_ff[57] ), |
| 539 | .edp_rng_in_ff_b56 ( edp_rng_in_ff[56] ), |
| 540 | .tcu_pce_ov(tcu_pce_ov), |
| 541 | .spc_aclk(spc_aclk), |
| 542 | .spc_bclk(spc_bclk), |
| 543 | .spc_aclk_wmr(spc_aclk_wmr), |
| 544 | .tcu_scan_en(tcu_scan_en), |
| 545 | .dec_tid_p(dec_tid_p[1:0]), |
| 546 | .dec_inst_rs1_vld_p(dec_inst_rs1_vld_p), |
| 547 | .dec_inst_rs2_vld_p(dec_inst_rs2_vld_p), |
| 548 | .dec_inst_rs3_vld_p(dec_inst_rs3_vld_p), |
| 549 | .dec_inst_rs1_p(dec_inst_rs1_p[4:0]), |
| 550 | .dec_inst_rs2_p(dec_inst_rs2_p[4:0]), |
| 551 | .dec_inst_rs3_p(dec_inst_rs3_p[4:0]), |
| 552 | .dec_inst_rd_d(dec_inst_rd_d[4:0]), |
| 553 | .dec_inst_d(dec_inst_d[31:5]), |
| 554 | .dec_decode_d(dec_decode_d), |
| 555 | .dec_thread_group(dec_thread_group), |
| 556 | .dec_valid_e(dec_valid_e), |
| 557 | .tlu_itlb_bypass_e(tlu_itlb_bypass_e), |
| 558 | .dec_flush_m(dec_flush_m), |
| 559 | .dec_flush_b(dec_flush_b), |
| 560 | .fgu_exu_icc_fx5(fgu_exu_icc_fx5[3:0]), |
| 561 | .fgu_exu_xcc_fx5(fgu_exu_xcc_fx5[1:0]), |
| 562 | .fgu_exu_cc_vld_fx5(fgu_exu_cc_vld_fx5), |
| 563 | .fgu_result_tid_fx5(fgu_result_tid_fx5[1:0]), |
| 564 | .fgu_irf_w_addr_fx5(fgu_irf_w_addr_fx5[4:0]), |
| 565 | .fgu_exu_w_vld_fx5(fgu_exu_w_vld_fx5), |
| 566 | .lsu_exu_ld_b(lsu_exu_ld_b), |
| 567 | .lsu_exu_rd_m(lsu_exu_rd_m[4:0]), |
| 568 | .lsu_exu_tid_m(lsu_exu_tid_m[2:0]), |
| 569 | .lsu_exu_ld_vld_w(lsu_exu_ld_vld_w), |
| 570 | .tlu_flush_exu_b(tlu_flush_exu_b), |
| 571 | .tlu_ccr(tlu_ccr[7:0]), |
| 572 | .tlu_ccr_cwp_valid(tlu_ccr_cwp_valid), |
| 573 | .tlu_ccr_cwp_tid(tlu_ccr_cwp_tid[1:0]), |
| 574 | .tlu_pstate_am(tlu_pstate_am[3:0]), |
| 575 | .lsu_exu_pmen(lsu_exu_pmen), |
| 576 | .spc_core_running_status(spc_core_running_status[3:0]), |
| 577 | .mbi_run(mbi_run), |
| 578 | .mbi_addr(mbi_addr[6:0]), |
| 579 | .mbi_irf_write_en(mbi_irf_write_en), |
| 580 | .edp_rng_in_ff(edp_rng_in_ff[7:0]), |
| 581 | .rml_rng_wt_ccr_ctl(rml_rng_wt_ccr_ctl), |
| 582 | .edp_br_flag_e(edp_br_flag_e[1:0]), |
| 583 | .exu_rs1_data_e(exu_rs1_data_e[63:0]), |
| 584 | .exu_rs2_data_e(exu_rs2_data_e[63:0]), |
| 585 | .edp_add_cout64_e(edp_add_cout64_e), |
| 586 | .edp_add_data_e_b63(edp_add_data_e_b63), |
| 587 | .edp_add_zdetect_e_(edp_add_zdetect_e_[1:0]), |
| 588 | .edp_sub_cout64_e(edp_sub_cout64_e), |
| 589 | .edp_sub_data_e_b63(edp_sub_data_e_b63), |
| 590 | .edp_sub_data_e_b31(edp_sub_data_e_b31), |
| 591 | .edp_sub_zdetect_e_(edp_sub_zdetect_e_[1:0]), |
| 592 | .edp_logical_data_e_b63(edp_logical_data_e_b63), |
| 593 | .edp_logical_data_e_b31(edp_logical_data_e_b31), |
| 594 | .edp_lg_zdetect_e(edp_lg_zdetect_e[1:0]), |
| 595 | .edp_address_m(edp_address_m[63:47]), |
| 596 | .edp_rd_ff_m(edp_rd_ff_m[63:47]), |
| 597 | .exu_ecc_m(exu_ecc_m), |
| 598 | .rml_test_valid_d(rml_test_valid_d), |
| 599 | .fgu_fld_fcc_fx3(fgu_fld_fcc_fx3[7:0]), |
| 600 | .lsu_fgu_fld_tid_b(lsu_fgu_fld_tid_b[2:0]), |
| 601 | .fgu_fld_fcc_vld_fx3(fgu_fld_fcc_vld_fx3[1:0]), |
| 602 | .lsu_fgu_fld_vld_w(lsu_fgu_fld_vld_w), |
| 603 | .fgu_cmp_fcc_fx3(fgu_cmp_fcc_fx3[1:0]), |
| 604 | .fgu_cmp_fcc_tid_fx2(fgu_cmp_fcc_tid_fx2[2:0]), |
| 605 | .fgu_cmp_fcc_vld_fx3(fgu_cmp_fcc_vld_fx3[3:0]), |
| 606 | .dec_pick_d(dec_pick_d[3:0]), |
| 607 | .exu_mdp_mux_sel_e(exu_mdp_mux_sel_e[5:0]), |
| 608 | .exu_ms_icc_e(exu_ms_icc_e), |
| 609 | .exu_gsr_vld_m(exu_gsr_vld_m[1:0]), |
| 610 | .exu_cmov_true_m(exu_cmov_true_m), |
| 611 | .exu_lsu_va_error_m(exu_lsu_va_error_m), |
| 612 | .exu_misalign_m(exu_misalign_m), |
| 613 | .exu_oor_va_m(exu_oor_va_m), |
| 614 | .exu_tcc_m(exu_tcc_m), |
| 615 | .exu_tof_m(exu_tof_m), |
| 616 | .exu_ccr0(exu_ccr0[7:0]), |
| 617 | .exu_ccr1(exu_ccr1[7:0]), |
| 618 | .exu_ccr2(exu_ccr2[7:0]), |
| 619 | .exu_ccr3(exu_ccr3[7:0]), |
| 620 | .ect_mbist_sel(ect_mbist_sel), |
| 621 | .ect_rs1_early_sel_d(ect_rs1_early_sel_d[4:0]), |
| 622 | .ect_rs2_early_sel_d(ect_rs2_early_sel_d[4:0]), |
| 623 | .ect_rs3_early_sel_d(ect_rs3_early_sel_d[4:0]), |
| 624 | .ect_rs2_imm_sel_d(ect_rs2_imm_sel_d[7:0]), |
| 625 | .ect_rs1_late_sel_d(ect_rs1_late_sel_d[3:0]), |
| 626 | .ect_rs2_late_sel_d(ect_rs2_late_sel_d[3:0]), |
| 627 | .ect_rs3_late_sel_d(ect_rs3_late_sel_d[3:0]), |
| 628 | .ect_logic_sel_d(ect_logic_sel_d[3:0]), |
| 629 | .ect_shift_sel_d(ect_shift_sel_d[6:0]), |
| 630 | .ect_br_taken_z0_e(ect_br_taken_z0_e), |
| 631 | .ect_br_taken_z1_e(ect_br_taken_z1_e), |
| 632 | .ect_alignaddress_little_e(ect_alignaddress_little_e), |
| 633 | .ect_as_clip_e_(ect_as_clip_e_), |
| 634 | .ect_as_cin_e(ect_as_cin_e), |
| 635 | .ect_array_sel_e(ect_array_sel_e[1:0]), |
| 636 | .ect_edge_lmask_e(ect_edge_lmask_e[7:0]), |
| 637 | .ect_edge_lrmask_e(ect_edge_lrmask_e[7:0]), |
| 638 | .ect_pstate_am_e(ect_pstate_am_e), |
| 639 | .ect_rm_early_sel_e(ect_rm_early_sel_e[5:0]), |
| 640 | .ect_rm_late_sel_e(ect_rm_late_sel_e[2:0]), |
| 641 | .ect_store_mux_sel_e(ect_store_mux_sel_e), |
| 642 | .ect_tid_lth_e(ect_tid_lth_e[1:0]), |
| 643 | .ect_rs1_addr_e(ect_rs1_addr_e[4:0]), |
| 644 | .ect_rs2_addr_e(ect_rs2_addr_e[4:0]), |
| 645 | .ect_rs3_addr_e(ect_rs3_addr_e[4:0]), |
| 646 | .ect_rs1_valid_e(ect_rs1_valid_e), |
| 647 | .ect_rs2_valid_e(ect_rs2_valid_e), |
| 648 | .ect_rs3_valid_e(ect_rs3_valid_e), |
| 649 | .ect_two_cycle_m(ect_two_cycle_m), |
| 650 | .ect_rd_lth_w(ect_rd_lth_w[4:0]), |
| 651 | .ect_rd_lth_w2(ect_rd_lth_w2[4:0]), |
| 652 | .ect_tid_lth_w(ect_tid_lth_w[1:0]), |
| 653 | .ect_tid_lth_w2(ect_tid_lth_w2[1:0]), |
| 654 | .ect_valid_lth_w(ect_valid_lth_w), |
| 655 | .ect_valid_in_w2(ect_valid_in_w2), |
| 656 | .ect_yreg_wr_w(ect_yreg_wr_w), |
| 657 | .ect_rng_ccr_data(ect_rng_ccr_data[7:0]), |
| 658 | .ect_misaligned_error_m(ect_misaligned_error_m), |
| 659 | .ect_ex_emb_clken(ect_ex_emb_clken), |
| 660 | .ect_tg_clken(ect_tg_clken) |
| 661 | ); |
| 662 | |
| 663 | exu_ecc_ctl ecc ( |
| 664 | .scan_in(ecc_scanin), |
| 665 | .scan_out(ecc_scanout), |
| 666 | .l2clk(l2clk), |
| 667 | .tcu_pce_ov(tcu_pce_ov), |
| 668 | .spc_aclk(spc_aclk), |
| 669 | .spc_bclk(spc_bclk), |
| 670 | .tcu_scan_en(tcu_scan_en), |
| 671 | .ect_mbist_sel(ect_mbist_sel), |
| 672 | .mbi_write_data_p1(mbi_write_data_p1[7:0]), |
| 673 | .edp_rd_ff_w(edp_rd_ff_w[63:0]), |
| 674 | .edp_rd_ff_w2(edp_rd_ff_w2[63:0]), |
| 675 | .tlu_cerer_irf(tlu_cerer_irf), |
| 676 | .tlu_ceter_pscce(tlu_ceter_pscce[3:0]), |
| 677 | .lsu_asi_error_inject_b31(lsu_asi_error_inject_b31), |
| 678 | .lsu_asi_error_inject_b25(lsu_asi_error_inject_b25), |
| 679 | .lsu_asi_error_inject(lsu_asi_error_inject[7:0]), |
| 680 | .ecc_w_synd_w(ecc_w_synd_w[7:0]), |
| 681 | .ecc_w2_synd_w2(ecc_w2_synd_w2[7:0]), |
| 682 | .ecc_mbist_write_data_p4(ecc_mbist_write_data_p4[7:0]), |
| 683 | .ect_ex_emb_clken(ect_ex_emb_clken), |
| 684 | .ect_tg_clken(ect_tg_clken), |
| 685 | .ect_tid_lth_e(ect_tid_lth_e[1:0]), |
| 686 | .ect_rs1_valid_e(ect_rs1_valid_e), |
| 687 | .ect_rs2_valid_e(ect_rs2_valid_e), |
| 688 | .ect_rs3_valid_e(ect_rs3_valid_e), |
| 689 | .ect_two_cycle_m(ect_two_cycle_m), |
| 690 | .ect_rs1_addr_e(ect_rs1_addr_e[4:0]), |
| 691 | .ect_rs2_addr_e(ect_rs2_addr_e[4:0]), |
| 692 | .ect_rs3_addr_e(ect_rs3_addr_e[4:0]), |
| 693 | .edp_rcc_data_e(edp_rcc_data_e[63:0]), |
| 694 | .exu_rs2_data_e(exu_rs2_data_e[63:0]), |
| 695 | .edp_rs3_data_e(edp_rs3_data_e[63:0]), |
| 696 | .edp_rcc_ecc_e(edp_rcc_ecc_e[7:0]), |
| 697 | .edp_rs2_ecc_e(edp_rs2_ecc_e[7:0]), |
| 698 | .edp_rs3_ecc_e(edp_rs3_ecc_e[7:0]), |
| 699 | .dec_valid_e(dec_valid_e), |
| 700 | .dec_flush_m(dec_flush_m), |
| 701 | .exu_ecc_check_m(exu_ecc_check_m[7:0]), |
| 702 | .exu_ecc_addr_m(exu_ecc_addr_m[4:0]), |
| 703 | .exu_ecc_m(exu_ecc_m), |
| 704 | .exu_cecc_m(exu_cecc_m), |
| 705 | .exu_uecc_m(exu_uecc_m) |
| 706 | ); |
| 707 | |
| 708 | exu_rml_ctl rml ( // FS:wmr_protect |
| 709 | .wmr_scan_in(rml_wmr_scanin), |
| 710 | .wmr_scan_out(rml_wmr_scanout), |
| 711 | .scan_in(rml_scanin), |
| 712 | .scan_out(rml_scanout), |
| 713 | .l2clk(l2clk), |
| 714 | .tcu_pce_ov(tcu_pce_ov), |
| 715 | .spc_aclk(spc_aclk), |
| 716 | .spc_bclk(spc_bclk), |
| 717 | .spc_aclk_wmr(spc_aclk_wmr), |
| 718 | .tcu_scan_en(tcu_scan_en), |
| 719 | .dec_tid_p(dec_tid_p[1:0]), |
| 720 | .dec_inst_d(dec_inst_d[31:13]), |
| 721 | .dec_valid_e(dec_valid_e), |
| 722 | .dec_thread_group(dec_thread_group), |
| 723 | .tlu_flush_exu_b(tlu_flush_exu_b), |
| 724 | .dec_flush_m(dec_flush_m), |
| 725 | .dec_flush_b(dec_flush_b), |
| 726 | .tlu_gl_thr0(tlu_gl_thr0[1:0]), |
| 727 | .tlu_gl_thr1(tlu_gl_thr1[1:0]), |
| 728 | .tlu_gl_thr2(tlu_gl_thr2[1:0]), |
| 729 | .tlu_gl_thr3(tlu_gl_thr3[1:0]), |
| 730 | .tlu_ccr_cwp_valid(tlu_ccr_cwp_valid), |
| 731 | .tlu_ccr_cwp_tid(tlu_ccr_cwp_tid[1:0]), |
| 732 | .tlu_cwp(tlu_cwp[2:0]), |
| 733 | .mbi_run(mbi_run), |
| 734 | .mbi_addr(mbi_addr[9:0]), |
| 735 | .mbi_irf_read_en(mbi_irf_read_en), |
| 736 | .mbi_irf_save_en(mbi_irf_save_en), |
| 737 | .mbi_irf_restore_en(mbi_irf_restore_en), |
| 738 | .edp_rng_in_ff(edp_rng_in_ff[64:0]), |
| 739 | .edp_rd_ff_w(edp_rd_ff_w[63:32]), |
| 740 | .ect_misaligned_error_m(ect_misaligned_error_m), |
| 741 | .ect_yreg_wr_w(ect_yreg_wr_w), |
| 742 | .ect_tid_lth_w(ect_tid_lth_w[1:0]), |
| 743 | .exu_lsu_va_error_m(exu_lsu_va_error_m), |
| 744 | .exu_ecc_m(exu_ecc_m), |
| 745 | .edp_rs3_ecc_e(edp_rs3_ecc_e[7:0]), |
| 746 | .ect_tg_clken(ect_tg_clken), |
| 747 | .exu_y_data_e(exu_y_data_e[31:0]), |
| 748 | .exu_fill_m(exu_fill_m), |
| 749 | .exu_spill_b(exu_spill_b), |
| 750 | .exu_normal_b(exu_normal_b), |
| 751 | .exu_cleanwin_b(exu_cleanwin_b), |
| 752 | .exu_wstate_b(exu_wstate_b[2:0]), |
| 753 | .exu_cwp_thr0(exu_cwp_thr0[2:0]), |
| 754 | .exu_cwp_thr1(exu_cwp_thr1[2:0]), |
| 755 | .exu_cwp_thr2(exu_cwp_thr2[2:0]), |
| 756 | .exu_cwp_thr3(exu_cwp_thr3[2:0]), |
| 757 | .exu_oddwin_b(exu_oddwin_b[3:0]), |
| 758 | .exu_window_block_m(exu_window_block_m), |
| 759 | .exu_tlu_window_block(exu_tlu_window_block), |
| 760 | .exu_ecc_winop_flush_m(exu_ecc_winop_flush_m), |
| 761 | .exu_test_valid(exu_test_valid), |
| 762 | .exu_test_tid(exu_test_tid[1:0]), |
| 763 | .exu_test_addr(exu_test_addr[4:0]), |
| 764 | .rml_test_valid_d(rml_test_valid_d), |
| 765 | .rml_rng_data_out(rml_rng_data_out[5:0]), |
| 766 | .rml_rng_rd_ctl(rml_rng_rd_ctl[4:0]), |
| 767 | .rml_rng_ack_ctl(rml_rng_ack_ctl[1:0]), |
| 768 | .rml_rng_ack_cwp_tid(rml_rng_ack_cwp_tid[1:0]), |
| 769 | .rml_rng_ack_ecc_tid(rml_rng_ack_ecc_tid[1:0]), |
| 770 | .rml_rng_ack_det_vld(rml_rng_ack_det_vld), |
| 771 | .rml_rng_wt_imask_ctl(rml_rng_wt_imask_ctl), |
| 772 | .rml_rng_wt_ccr_ctl(rml_rng_wt_ccr_ctl), |
| 773 | .rml_irf_ecc_data(rml_irf_ecc_data[7:0]), |
| 774 | .rml_rng_ack_sel_ctl(rml_rng_ack_sel_ctl), |
| 775 | .rml_rng_y_data(rml_rng_y_data[31:0]), |
| 776 | .rml_irf_cwpswap_tid_m(rml_irf_cwpswap_tid_m[1:0]), |
| 777 | .rml_irf_old_lo_cwp_m(rml_irf_old_lo_cwp_m[2:0]), |
| 778 | .rml_irf_old_e_cwp_m(rml_irf_old_e_cwp_m[2:1]), |
| 779 | .rml_irf_cwpswap_tid_b(rml_irf_cwpswap_tid_b[1:0]), |
| 780 | .rml_irf_new_lo_cwp_b(rml_irf_new_lo_cwp_b[2:0]), |
| 781 | .rml_irf_new_e_cwp_b(rml_irf_new_e_cwp_b[2:1]), |
| 782 | .rml_irf_save_even_m(rml_irf_save_even_m), |
| 783 | .rml_irf_save_odd_m(rml_irf_save_odd_m), |
| 784 | .rml_irf_save_local_m(rml_irf_save_local_m), |
| 785 | .rml_irf_restore_even_b(rml_irf_restore_even_b), |
| 786 | .rml_irf_restore_odd_b(rml_irf_restore_odd_b), |
| 787 | .rml_irf_restore_local_b(rml_irf_restore_local_b), |
| 788 | .rml_irf_global_tid(rml_irf_global_tid[1:0]), |
| 789 | .rml_irf_global_tid_ff(rml_irf_global_tid_ff[1:0]), |
| 790 | .rml_irf_old_agp(rml_irf_old_agp[1:0]), |
| 791 | .rml_irf_new_agp_ff(rml_irf_new_agp_ff[1:0]), |
| 792 | .rml_irf_save_global(rml_irf_save_global), |
| 793 | .rml_irf_restore_global(rml_irf_restore_global) |
| 794 | ); |
| 795 | |
| 796 | |
| 797 | |
| 798 | |
| 799 | |
| 800 | // Note : All IRF READ/WRITE/SAVE/RESTORE pins are flopped inside the IRF. |
| 801 | // Note : The save and restore have one full cycle to decode. The actual save or restore will occur in the 1st phase of the cycle after decode. |
| 802 | // Note : The READ and WRITE decode in the 1st phase and the actual read/write occurs in the 2nd phase. |
| 803 | |
| 804 | // Note : To delay a signal in a 0in assertion : use "$0in_delay(signal_name,# of cycles)" example $0in_delay(a_wr_en_p0,1) |
| 805 | |
| 806 | |
| 807 | // 0. N2 : Read and Write without bypassing |
| 808 | // 1. N1 : WRITE p0 and WRITE p1 to the same TID in the same cycle |
| 809 | // 2. N2 : Any WRITE port followed by a SAVE in the 1st phase of next cycle (coded as the SAVE pins the same cycle as the WRITE pins) |
| 810 | // 3. N1 : Any WRITE port followed by a RESTORE in the 1st phase of next cycle (coded as the RESTORE pins the same cycle as the WRITE pins) |
| 811 | // 4. N1 : Any READ port followed by a SAVE in the 1st phase of next cycle (coded as the SAVE pins the same cycle as the READ pins) |
| 812 | // 5. N1 : Any READ port followed by a RESTORE in the 1st phase of next cycle (coded as the RESTORE pins the same cycle as the READ pins) |
| 813 | // 6. N2 : Any SAVE port followed by a READ in the same cycle (coded as the SAVE pins one cycle ahead of the READ pins) |
| 814 | // 7. N2 : Any RESTORE port followed by a READ in the same cycle (coded as the RESTORE pins one cycle ahead of the READ pins) |
| 815 | // 8. N2 : Any SAVE port followed by a WRITE in the same cycle (coded as the SAVE pins one cycle ahead as the WRITE pins) |
| 816 | // 9. N2 : Any RESTORE port followed by a WRITE in the same cycle (coded as the RESTORE pins one cycle ahead as the WRITE pins) |
| 817 | |
| 818 | |
| 819 | // #0 |
| 820 | // 0in custom -fire ( $0in_delay((dec_inst_rs1_vld_p & ect_valid_lth_w & (dec_tid_p[1:0] == ect_tid_lth_w[1:0]) & (dec_inst_rs1_p[4:0] == ect_rd_lth_w[4:0] )),1) & (ect_rs1_late_sel_d[3:1] == 3'b000 )) -message "IRF p0 write & p0 read without bypass" -group core_array |
| 821 | // 0in custom -fire ( $0in_delay((dec_inst_rs2_vld_p & ect_valid_lth_w & (dec_tid_p[1:0] == ect_tid_lth_w[1:0]) & (dec_inst_rs2_p[4:0] == ect_rd_lth_w[4:0] )),1) & (ect_rs2_late_sel_d[3:0] == 4'b0000)) -message "IRF p0 write & p1 read without bypass" -group core_array |
| 822 | // 0in custom -fire ( $0in_delay((dec_inst_rs3_vld_p & ect_valid_lth_w & (dec_tid_p[1:0] == ect_tid_lth_w[1:0]) & (dec_inst_rs3_p[4:0] == ect_rd_lth_w[4:0] )),1) & (ect_rs3_late_sel_d[3:0] == 4'b0000)) -message "IRF p0 write & p2 read without bypass" -group core_array |
| 823 | // 0in custom -fire ( $0in_delay((dec_inst_rs1_vld_p & ect_valid_in_w2 & (dec_tid_p[1:0] == ect_tid_lth_w2[1:0]) & (dec_inst_rs1_p[4:0] == ect_rd_lth_w2[4:0])),1) & (ect_rs1_late_sel_d[3:1] == 3'b000 )) -message "IRF p1 write & p0 read without bypass" -group core_array |
| 824 | // 0in custom -fire ( $0in_delay((dec_inst_rs2_vld_p & ect_valid_in_w2 & (dec_tid_p[1:0] == ect_tid_lth_w2[1:0]) & (dec_inst_rs2_p[4:0] == ect_rd_lth_w2[4:0])),1) & (ect_rs2_late_sel_d[3:0] == 4'b0000)) -message "IRF p1 write & p1 read without bypass" -group core_array |
| 825 | // 0in custom -fire ( $0in_delay((dec_inst_rs3_vld_p & ect_valid_in_w2 & (dec_tid_p[1:0] == ect_tid_lth_w2[1:0]) & (dec_inst_rs3_p[4:0] == ect_rd_lth_w2[4:0])),1) & (ect_rs3_late_sel_d[3:0] == 4'b0000)) -message "IRF p1 write & p2 read without bypass" -group core_array |
| 826 | |
| 827 | // #1 |
| 828 | // 0in custom -fire (ect_valid_lth_w & ect_valid_in_w2 & (ect_tid_lth_w[1:0] == ect_tid_lth_w2[1:0]) ) -message "IRF p0 & p1 ports wrote to same TID" -group core_array |
| 829 | |
| 830 | // #2 |
| 831 | // 0in custom -fire (ect_valid_lth_w & (rml_irf_save_odd_m | rml_irf_save_local_m | rml_irf_save_even_m ) & (ect_tid_lth_w[1:0] == rml_irf_cwpswap_tid_m[1:0])) -message "IRF p0 write & save to same TID" -group core_array |
| 832 | // 0in custom -fire (ect_valid_in_w2 & (rml_irf_save_odd_m | rml_irf_save_local_m | rml_irf_save_even_m ) & (ect_tid_lth_w2[1:0] == rml_irf_cwpswap_tid_m[1:0])) -message "IRF p1 write & save to same TID" -group core_array |
| 833 | // 0in custom -fire (ect_valid_lth_w & rml_irf_save_global & (ect_tid_lth_w[1:0] == rml_irf_global_tid[1:0]) ) -message "IRF p0 write & save global to same TID" -group core_array |
| 834 | // 0in custom -fire (ect_valid_in_w2 & rml_irf_save_global & (ect_tid_lth_w2[1:0] == rml_irf_global_tid[1:0]) ) -message "IRF p1 write & save global to same TID" -group core_array |
| 835 | |
| 836 | // #3 |
| 837 | // 0in custom -fire (ect_valid_lth_w & (rml_irf_restore_odd_b | rml_irf_restore_local_b | rml_irf_restore_even_b) & (ect_tid_lth_w[1:0] == rml_irf_cwpswap_tid_b[1:0])) -message "IRF p0 write & restore to same TID" -group core_array |
| 838 | // 0in custom -fire (ect_valid_in_w2 & (rml_irf_restore_odd_b | rml_irf_restore_local_b | rml_irf_restore_even_b) & (ect_tid_lth_w2[1:0] == rml_irf_cwpswap_tid_b[1:0])) -message "IRF p1 write & restore to same TID" -group core_array |
| 839 | // 0in custom -fire (ect_valid_lth_w & rml_irf_restore_global & (ect_tid_lth_w[1:0] == rml_irf_global_tid_ff[1:0])) -message "IRF p0 write & restore global to same TID" -group core_array |
| 840 | // 0in custom -fire (ect_valid_in_w2 & rml_irf_restore_global & (ect_tid_lth_w2[1:0] == rml_irf_global_tid_ff[1:0])) -message "IRF p1 write & restore global to same TID" -group core_array |
| 841 | |
| 842 | // #4 |
| 843 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs1_vld_p & (rml_irf_save_odd_m | rml_irf_save_local_m | rml_irf_save_even_m ) & (dec_tid_p[1:0] == rml_irf_cwpswap_tid_m[1:0])),2))) -message "IRF p0 read & save to same TID" -group core_array |
| 844 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs1_vld_p & rml_irf_save_global & (dec_tid_p[1:0] == rml_irf_global_tid[1:0] )),2))) -message "IRF p0 read & save global to same TID" -group core_array |
| 845 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs2_vld_p & (rml_irf_save_odd_m | rml_irf_save_local_m | rml_irf_save_even_m ) & (dec_tid_p[1:0] == rml_irf_cwpswap_tid_m[1:0])),2))) -message "IRF p1 read & save to same TID" -group core_array |
| 846 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs2_vld_p & rml_irf_save_global & (dec_tid_p[1:0] == rml_irf_global_tid[1:0] )),2))) -message "IRF p1 read & save global to same TID" -group core_array |
| 847 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs3_vld_p & (rml_irf_save_odd_m | rml_irf_save_local_m | rml_irf_save_even_m ) & (dec_tid_p[1:0] == rml_irf_cwpswap_tid_m[1:0])),2))) -message "IRF p2 read & save to same TID" -group core_array |
| 848 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs3_vld_p & rml_irf_save_global & (dec_tid_p[1:0] == rml_irf_global_tid[1:0] )),2))) -message "IRF p2 read & save global to same TID" -group core_array |
| 849 | |
| 850 | |
| 851 | // #5 |
| 852 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs1_vld_p & (rml_irf_restore_odd_b | rml_irf_restore_local_b | rml_irf_restore_even_b) & (dec_tid_p[1:0] == rml_irf_cwpswap_tid_b[1:0])),2))) -message "IRF p0 read & restore to same TID" -group core_array |
| 853 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs1_vld_p & rml_irf_restore_global & (dec_tid_p[1:0] == rml_irf_global_tid_ff[1:0])),2))) -message "IRF p0 read & restore global to same TID" -group core_array |
| 854 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs2_vld_p & (rml_irf_restore_odd_b | rml_irf_restore_local_b | rml_irf_restore_even_b) & (dec_tid_p[1:0] == rml_irf_cwpswap_tid_b[1:0])),2))) -message "IRF p1 read & restore to same TID" -group core_array |
| 855 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs2_vld_p & rml_irf_restore_global & (dec_tid_p[1:0] == rml_irf_global_tid_ff[1:0])),2))) -message "IRF p1 read & restore global to same TID" -group core_array |
| 856 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs3_vld_p & (rml_irf_restore_odd_b | rml_irf_restore_local_b | rml_irf_restore_even_b) & (dec_tid_p[1:0] == rml_irf_cwpswap_tid_b[1:0])),2))) -message "IRF p2 read & restore to same TID" -group core_array |
| 857 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs3_vld_p & rml_irf_restore_global & (dec_tid_p[1:0] == rml_irf_global_tid_ff[1:0])),2))) -message "IRF p2 read & restore global to same TID" -group core_array |
| 858 | |
| 859 | |
| 860 | // #6 |
| 861 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs1_vld_p & $0in_delay((rml_irf_save_odd_m | rml_irf_save_local_m | rml_irf_save_even_m ),1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_cwpswap_tid_m[1:0],1))),2))) -message "IRF p0 read & save to same TID in same cycle" -group core_array |
| 862 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs1_vld_p & $0in_delay( rml_irf_save_global ,1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_global_tid[1:0] ,1))),2))) -message "IRF p0 read & save global to same TID in same cycle" -group core_array |
| 863 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs2_vld_p & $0in_delay((rml_irf_save_odd_m | rml_irf_save_local_m | rml_irf_save_even_m ),1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_cwpswap_tid_m[1:0],1))),2))) -message "IRF p1 read & save to same TID in same cycle" -group core_array |
| 864 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs2_vld_p & $0in_delay( rml_irf_save_global ,1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_global_tid[1:0] ,1))),2))) -message "IRF p1 read & save global to same TID in same cycle" -group core_array |
| 865 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs3_vld_p & $0in_delay((rml_irf_save_odd_m | rml_irf_save_local_m | rml_irf_save_even_m ),1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_cwpswap_tid_m[1:0],1))),2))) -message "IRF p2 read & save to same TID in same cycle" -group core_array |
| 866 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs3_vld_p & $0in_delay( rml_irf_save_global ,1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_global_tid[1:0] ,1))),2))) -message "IRF p2 read & save global to same TID in same cycle" -group core_array |
| 867 | |
| 868 | |
| 869 | // #7 fails isa3_scratchpad_f2.s single thread at 130000 |
| 870 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs1_vld_p & $0in_delay((rml_irf_restore_odd_b | rml_irf_restore_local_b | rml_irf_restore_even_b),1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_cwpswap_tid_b[1:0],1))),2))) -message "IRF p0 read & restore to same TID in same cycle" -name "EXU_7a" -group core_array |
| 871 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs1_vld_p & $0in_delay( rml_irf_restore_global ,1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_global_tid_ff[1:0],1))),2))) -message "IRF p0 read & restore global to same TID in same cycle" -name "EXU_7b" -group core_array |
| 872 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs2_vld_p & $0in_delay((rml_irf_restore_odd_b | rml_irf_restore_local_b | rml_irf_restore_even_b),1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_cwpswap_tid_b[1:0],1))),2))) -message "IRF p1 read & restore to same TID in same cycle" -name "EXU_7c" -group core_array |
| 873 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs2_vld_p & $0in_delay( rml_irf_restore_global ,1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_global_tid_ff[1:0],1))),2))) -message "IRF p1 read & restore global to same TID in same cycle" -name "EXU_7d" -group core_array |
| 874 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs3_vld_p & $0in_delay((rml_irf_restore_odd_b | rml_irf_restore_local_b | rml_irf_restore_even_b),1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_cwpswap_tid_b[1:0],1))),2))) -message "IRF p2 read & restore to same TID in same cycle" -name "EXU_7e" -group core_array |
| 875 | // 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs3_vld_p & $0in_delay( rml_irf_restore_global ,1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_global_tid_ff[1:0],1))),2))) -message "IRF p2 read & restore global to same TID in same cycle" -name "EXU_7f" -group core_array |
| 876 | |
| 877 | |
| 878 | // #8 |
| 879 | // 0in custom -fire (ect_valid_lth_w & $0in_delay((rml_irf_save_odd_m | rml_irf_save_local_m | rml_irf_save_even_m ),1) & (ect_tid_lth_w[1:0] == $0in_delay(rml_irf_cwpswap_tid_m[1:0],1))) -message "IRF p0 write & save to same TID in same cycle" -group core_array |
| 880 | // 0in custom -fire (ect_valid_in_w2 & $0in_delay((rml_irf_save_odd_m | rml_irf_save_local_m | rml_irf_save_even_m ),1) & (ect_tid_lth_w2[1:0] == $0in_delay(rml_irf_cwpswap_tid_m[1:0],1))) -message "IRF p1 write & save to same TID in same cycle" -group core_array |
| 881 | // 0in custom -fire (ect_valid_lth_w & $0in_delay( rml_irf_save_global ,1) & (ect_tid_lth_w[1:0] == $0in_delay(rml_irf_global_tid[1:0] ,1))) -message "IRF p0 write & save global to same TID in same cycle" -group core_array |
| 882 | // 0in custom -fire (ect_valid_in_w2 & $0in_delay( rml_irf_save_global ,1) & (ect_tid_lth_w2[1:0] == $0in_delay(rml_irf_global_tid[1:0] ,1))) -message "IRF p1 write & save global to same TID in same cycle" -group core_array |
| 883 | |
| 884 | // #9 |
| 885 | // 0in custom -fire (ect_valid_lth_w & $0in_delay((rml_irf_restore_odd_b | rml_irf_restore_local_b | rml_irf_restore_even_b),1) & (ect_tid_lth_w[1:0] == $0in_delay(rml_irf_cwpswap_tid_b[1:0],1))) -message "IRF p0 write & restore to same TID in same cycle" -group core_array |
| 886 | // 0in custom -fire (ect_valid_in_w2 & $0in_delay((rml_irf_restore_odd_b | rml_irf_restore_local_b | rml_irf_restore_even_b),1) & (ect_tid_lth_w2[1:0] == $0in_delay(rml_irf_cwpswap_tid_b[1:0],1))) -message "IRF p1 write & restore to same TID in same cycle" -group core_array |
| 887 | // 0in custom -fire (ect_valid_lth_w & $0in_delay( rml_irf_restore_global ,1) & (ect_tid_lth_w[1:0] == $0in_delay(rml_irf_global_tid_ff[1:0],1))) -message "IRF p0 write & restore global to same TID in same cycle" -group core_array |
| 888 | // 0in custom -fire (ect_valid_in_w2 & $0in_delay( rml_irf_restore_global ,1) & (ect_tid_lth_w2[1:0] == $0in_delay(rml_irf_global_tid_ff[1:0],1))) -message "IRF p1 write & restore global to same TID in same cycle" -group core_array |
| 889 | |
| 890 | |
| 891 | n2_irf_mp_128x72_cust irf ( |
| 892 | |
| 893 | .scan_in(irf_scanin), |
| 894 | .scan_out(irf_scanout), |
| 895 | .l2clk ( l2clk ), |
| 896 | .tcu_pce_ov ( tcu_pce_ov ), |
| 897 | .tcu_aclk ( spc_aclk ), |
| 898 | .tcu_bclk ( spc_bclk ), |
| 899 | .clken ( ect_tg_clken ), |
| 900 | |
| 901 | .rd_tid ( dec_tid_p[1:0] ), |
| 902 | .rd_addr_p0 ( dec_inst_rs1_p[4:0] ), |
| 903 | .rd_addr_p1 ( dec_inst_rs2_p[4:0] ), |
| 904 | .rd_addr_p2 ( dec_inst_rs3_p[4:0] ), |
| 905 | .rd_en_p0 ( dec_inst_rs1_vld_p ), |
| 906 | .rd_en_p1 ( dec_inst_rs2_vld_p ), |
| 907 | .rd_en_p2 ( dec_inst_rs3_vld_p ), |
| 908 | |
| 909 | .wr_en_p0 ( ect_valid_lth_w ), |
| 910 | .wr_tid_p0 ( ect_tid_lth_w[1:0] ), |
| 911 | .wr_addr_p0 ( ect_rd_lth_w[4:0] ), |
| 912 | .wr_data_p0 ({ecc_w_synd_w[7:0] , edp_rd_ff_w[63:0]} ), |
| 913 | .wr_en_p1 ( ect_valid_in_w2 ), |
| 914 | .wr_tid_p1 ( ect_tid_lth_w2[1:0] ), |
| 915 | .wr_addr_p1 ( ect_rd_lth_w2[4:0] ), |
| 916 | .wr_data_p1 ({ecc_w2_synd_w2[7:0] , edp_rd_ff_w2[63:0]} ), |
| 917 | |
| 918 | .save_tid ( rml_irf_cwpswap_tid_m[1:0] ), |
| 919 | .save_local_addr ( rml_irf_old_lo_cwp_m[2:0] ), |
| 920 | .save_even_addr ( rml_irf_old_e_cwp_m[2:1] ), |
| 921 | .save_odd_addr ( rml_irf_old_lo_cwp_m[2:1] ), |
| 922 | .save_even_en ( rml_irf_save_even_m ), |
| 923 | .save_odd_en ( rml_irf_save_odd_m ), |
| 924 | .save_local_en ( rml_irf_save_local_m ), |
| 925 | |
| 926 | .restore_tid ( rml_irf_cwpswap_tid_b[1:0] ), |
| 927 | .restore_local_addr ( rml_irf_new_lo_cwp_b[2:0] ), |
| 928 | .restore_even_addr ( rml_irf_new_e_cwp_b[2:1] ), |
| 929 | .restore_odd_addr ( rml_irf_new_lo_cwp_b[2:1] ), |
| 930 | .restore_even_en ( rml_irf_restore_even_b ), |
| 931 | .restore_odd_en ( rml_irf_restore_odd_b ), |
| 932 | .restore_local_en ( rml_irf_restore_local_b ), |
| 933 | |
| 934 | .save_global_en ( rml_irf_save_global ), |
| 935 | .save_global_tid ( rml_irf_global_tid[1:0] ), |
| 936 | .save_global_addr ( rml_irf_old_agp[1:0] ), |
| 937 | |
| 938 | .restore_global_en ( rml_irf_restore_global ), |
| 939 | .restore_global_tid ( rml_irf_global_tid_ff[1:0] ), |
| 940 | .restore_global_addr ( rml_irf_new_agp_ff[1:0] ), |
| 941 | |
| 942 | |
| 943 | .dout_p0 ( irf_rs1_data_d[71:0] ), |
| 944 | .dout_p1 ( irf_rs2_data_d[71:0] ), |
| 945 | .dout_p2 ( irf_rs3_data_d[71:0] ), |
| 946 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), |
| 947 | .tcu_scan_en(tcu_scan_en), |
| 948 | .tcu_se_scancollar_in(tcu_se_scancollar_in)); |
| 949 | |
| 950 | |
| 951 | //******************************************************************************** |
| 952 | // |
| 953 | // Instruction Notes |
| 954 | // |
| 955 | // |
| 956 | // Opcode Page FUNCTION Comments Implementation |
| 957 | // ------ ---- ------------------------ ----------------------- -------------- |
| 958 | // |
| 959 | // Add/Sub |
| 960 | // |
| 961 | // ADD 135 rs1 + rs2 |
| 962 | // ADDcc 135 rs1 + rs2 CCR.icc,xcc |
| 963 | // ADDC 135 rs1 + rs2 + icc.c |
| 964 | // ADDCcc 135 rs1 + rs2 + icc.c CCR.icc,xcc |
| 965 | // ADDi 135 rs1 + sext(imm) imm=[12:0] |
| 966 | // ADDcci 135 rs1 + sext(imm) imm=[12:0] CCR.icc,xcc |
| 967 | // ADDCi 135 rs1 + sext(imm) + icc.c imm=[12:0] |
| 968 | // ADDCcci 135 rs1 + sext(imm) + icc.c imm=[12:0] CCR.icc,xcc |
| 969 | // |
| 970 | // SUB 230 rs1 - rs2 |
| 971 | // SUBcc 230 rs1 - rs2 CCR.icc,xcc |
| 972 | // SUBC 230 rs1 - rs2 + icc.c |
| 973 | // SUBCcc 230 rs1 - rs2 + icc.c CCR.icc,xcc |
| 974 | // SUBi 230 rs1 - sext(imm) imm=[12:0] |
| 975 | // SUBcci 230 rs1 - sext(imm) imm=[12:0] CCR.icc,xcc |
| 976 | // SUBCi 230 rs1 - sext(imm) + icc.c imm=[12:0] |
| 977 | // SUBCcci 230 rs1 - sext(imm) + icc.c imm=[12:0] CCR.icc,xcc |
| 978 | // |
| 979 | // |
| 980 | // Logical |
| 981 | // |
| 982 | // AND 181 rs1 & rs2 lg_sel=1000 |
| 983 | // ANDcc 181 rs1 & rs2 CCR.icc,xcc lg_sel=1000 |
| 984 | // ANDN 181 rs1 & ~rs2 lg_sel=0100 |
| 985 | // ANDNcc 181 rs1 & ~rs2 CCR.icc,xcc lg_sel=0100 |
| 986 | // OR 181 rs1 | rs2 lg_sel=1110 |
| 987 | // ORcc 181 rs1 | rs2 CCR.icc,xcc lg_sel=1110 |
| 988 | // ORN 181 rs1 | ~rs2 lg_sel=1101 |
| 989 | // ORNcc 181 rs1 | ~rs2 CCR.icc,xcc lg_sel=1101 |
| 990 | // XOR 181 rs1 ^ rs2 lg_sel=0110 |
| 991 | // XORcc 181 rs1 ^ rs2 CCR.icc,xcc lg_sel=0110 |
| 992 | // XORN 181 rs1 ^ ~rs2 lg_sel=1001 |
| 993 | // XORNcc 181 rs1 ^ ~rs2 CCR.icc,xcc lg_sel=1001 |
| 994 | // ANDi 181 rs1 & sext(imm) imm=[12:0] lg_sel=1000 |
| 995 | // ANDcci 181 rs1 & sext(imm) imm=[12:0] CCR.icc,xcc lg_sel=1000 |
| 996 | // ANDNi 181 rs1 & ~sext(imm) imm=[12:0] lg_sel=0100 |
| 997 | // ANDNcci 181 rs1 & ~sext(imm) imm=[12:0] CCR.icc,xcc lg_sel=0100 |
| 998 | // ORi 181 rs1 | sext(imm) imm=[12:0] lg_sel=1110 |
| 999 | // ORcci 181 rs1 | sext(imm) imm=[12:0] CCR.icc,xcc lg_sel=1110 |
| 1000 | // ORNi 181 rs1 | ~sext(imm) imm=[12:0] lg_sel=1101 |
| 1001 | // ORNcci 181 rs1 | ~sext(imm) imm=[12:0] CCR.icc,xcc lg_sel=1101 |
| 1002 | // XORi 181 rs1 ^ sext(imm) imm=[12:0] lg_sel=0110 |
| 1003 | // XORcci 181 rs1 ^ sext(imm) imm=[12:0] CCR.icc,xcc lg_sel=0110 |
| 1004 | // XORNi 181 rs1 ^ ~sext(imm) imm=[12:0] lg_sel=1001 |
| 1005 | // XORNcci 181 rs1 ^ ~sext(imm) imm=[12:0] CCR.icc,xcc lg_sel=1001 |
| 1006 | // |
| 1007 | // SETHI 217 {32'b0,imm[21:0],10'b0} NOP if rd=0 & imm=0 |
| 1008 | // |
| 1009 | // |
| 1010 | // Shift |
| 1011 | // |
| 1012 | // SLL 218 shift_left(rs1) fill w/ 0 sa=rs2[4:0] sh_sel=0100001 |
| 1013 | // SRL 218 shift_right(rs1) fill w/ 0 sa=rs2[4:0] rd[63:32]=32'b0 sh_sel=1000001 |
| 1014 | // SRA 218 shift_right(rs1) w/ sext sa=rs2[4:0] rd[63:32]=rs1[31] sh_sel=1001001 |
| 1015 | // SLLX 218 shift_left(rs1) fill w/ 0 sa=rs2[5:0] sh_sel=0100010 |
| 1016 | // SRLX 218 shift_right(rs1) fill w/ 0 sa=rs2[5:0] sh_sel=1000100 |
| 1017 | // SRAX 218 shift_right(rs1) w/ sext sa=rs2[5:0] sh_sel=1010100 |
| 1018 | // |
| 1019 | // SLLi 218 shift_left(rs1) fill w/ 0 sa=rs2[4:0] sh_sel=0100001 |
| 1020 | // SRLi 218 shift_right(rs1) fill w/ 0 sa=rs2[4:0] rd[63:32]=32'b0 sh_sel=1000001 |
| 1021 | // SRAi 218 shift_right(rs1) w/ sext sa=rs2[4:0] rd[63:32]=rs1[31] sh_sel=1001001 |
| 1022 | // SLLXi 218 shift_left(rs1) fill w/ 0 sa=rs2[5:0] sh_sel=0100010 |
| 1023 | // SRLXi 218 shift_right(rs1) fill w/ 0 sa=rs2[5:0] sh_sel=1000100 |
| 1024 | // SRAXi 218 shift_right(rs1) w/ sext sa=rs2[5:0] sh_sel=1010100 |
| 1025 | // |
| 1026 | // VIS |
| 1027 | // EDGE8 70 Eight 8-bit Edge |
| 1028 | // EDGE8N 70 Eight 8-bit Edge; no CC |
| 1029 | // EDGE8L 70 Eight 8-bit Edge; Little-Endian |
| 1030 | // EDGE8LN 70 Eight 8-bit Edge; no CC; Little-Endian |
| 1031 | // EDGE16 70 Four 16-bit Edge |
| 1032 | // EDGE16N 70 Four 16-bit Edge; no CC |
| 1033 | // EDGE16L 70 Four 16-bit Edge; Little-Endian |
| 1034 | // EDGE16LN 70 Four 16-bit Edge; no CC; Little-Endian |
| 1035 | // EDGE32 70 Two 32-bit Edge |
| 1036 | // EDGE32N 70 Two 32-bit Edge; no CC |
| 1037 | // EDGE32L 70 Two 32-bit Edge; Little-Endian |
| 1038 | // EDGE32LN 70 Two 32-bit Edge; no CC; Little-Endian |
| 1039 | // |
| 1040 | // |
| 1041 | // ARRAY8 74 Convert 8-bit 3-D addres to blocked byte address |
| 1042 | // ARRAY16 74 Convert 16-bit 3-D addres to blocked byte address |
| 1043 | // ARRAY32 74 Convert 32-bit 3-D addres to blocked byte address |
| 1044 | // |
| 1045 | // |
| 1046 | // ALIGNADDRESS 55 RD = rs1 + rs2; clip low 3 bits; GSR <- low 3 bits |
| 1047 | // ALIGNADDRESS-little RD = rs1 + rs2; clip low 3 bits; GSR <- ~low 3 bits |
| 1048 | // BMASK 55 RD = rs1 + rs2; clip low 3 bits; GSR <- low 32 bits |
| 1049 | |
| 1050 | |
| 1051 | |
| 1052 | // fixscan start: |
| 1053 | assign edp_scanin = scan_in ; |
| 1054 | assign ect_scanin = edp_scanout ; |
| 1055 | assign ecc_scanin = ect_scanout ; |
| 1056 | assign rml_scanin = ecc_scanout ; |
| 1057 | assign irf_scanin = rml_scanout ; |
| 1058 | assign scan_out = irf_scanout ; |
| 1059 | |
| 1060 | assign ect_wmr_scanin = wmr_scan_in ; |
| 1061 | assign rml_wmr_scanin = ect_wmr_scanout ; |
| 1062 | assign wmr_scan_out = rml_wmr_scanout ; |
| 1063 | // fixscan end: |
| 1064 | endmodule |
| 1065 | |