| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: exu_ect_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module exu_ect_ctl ( |
| 36 | l2clk, |
| 37 | scan_in, |
| 38 | wmr_scan_in, |
| 39 | tcu_pce_ov, |
| 40 | spc_aclk, |
| 41 | spc_bclk, |
| 42 | spc_aclk_wmr, |
| 43 | tcu_scan_en, |
| 44 | dec_tid_p, |
| 45 | dec_inst_rs1_vld_p, |
| 46 | dec_inst_rs2_vld_p, |
| 47 | dec_inst_rs3_vld_p, |
| 48 | dec_inst_rs1_p, |
| 49 | dec_inst_rs2_p, |
| 50 | dec_inst_rs3_p, |
| 51 | dec_inst_rd_d, |
| 52 | dec_inst_d, |
| 53 | dec_decode_d, |
| 54 | dec_thread_group, |
| 55 | dec_valid_e, |
| 56 | tlu_itlb_bypass_e, |
| 57 | dec_flush_m, |
| 58 | dec_flush_b, |
| 59 | fgu_exu_icc_fx5, |
| 60 | fgu_exu_xcc_fx5, |
| 61 | fgu_exu_cc_vld_fx5, |
| 62 | fgu_result_tid_fx5, |
| 63 | fgu_irf_w_addr_fx5, |
| 64 | fgu_exu_w_vld_fx5, |
| 65 | lsu_exu_ld_b, |
| 66 | lsu_exu_rd_m, |
| 67 | lsu_exu_tid_m, |
| 68 | lsu_exu_ld_vld_w, |
| 69 | tlu_flush_exu_b, |
| 70 | tlu_ccr, |
| 71 | tlu_ccr_cwp_valid, |
| 72 | tlu_ccr_cwp_tid, |
| 73 | tlu_pstate_am, |
| 74 | lsu_exu_pmen, |
| 75 | spc_core_running_status, |
| 76 | mbi_run, |
| 77 | mbi_addr, |
| 78 | mbi_irf_write_en, |
| 79 | edp_rng_in_ff, |
| 80 | edp_rng_in_ff_b56, |
| 81 | edp_rng_in_ff_b57, |
| 82 | rml_rng_wt_ccr_ctl, |
| 83 | edp_br_flag_e, |
| 84 | exu_rs1_data_e, |
| 85 | exu_rs2_data_e, |
| 86 | edp_add_cout64_e, |
| 87 | edp_add_data_e_b63, |
| 88 | edp_add_data_e_b31, |
| 89 | edp_add_data_e_b1, |
| 90 | edp_add_data_e_b0, |
| 91 | edp_add_zdetect_e_, |
| 92 | edp_sub_cout64_e, |
| 93 | edp_sub_data_e_b63, |
| 94 | edp_sub_data_e_b31, |
| 95 | edp_sub_zdetect_e_, |
| 96 | edp_logical_data_e_b63, |
| 97 | edp_logical_data_e_b31, |
| 98 | edp_lg_zdetect_e, |
| 99 | edp_address_m, |
| 100 | edp_rd_ff_m, |
| 101 | exu_ecc_m, |
| 102 | rml_test_valid_d, |
| 103 | fgu_fld_fcc_fx3, |
| 104 | lsu_fgu_fld_tid_b, |
| 105 | fgu_fld_fcc_vld_fx3, |
| 106 | lsu_fgu_fld_vld_w, |
| 107 | fgu_cmp_fcc_fx3, |
| 108 | fgu_cmp_fcc_tid_fx2, |
| 109 | fgu_cmp_fcc_vld_fx3, |
| 110 | dec_pick_d, |
| 111 | exu_mdp_mux_sel_e, |
| 112 | exu_ms_icc_e, |
| 113 | exu_gsr_vld_m, |
| 114 | exu_cmov_true_m, |
| 115 | exu_lsu_va_error_m, |
| 116 | exu_misalign_m, |
| 117 | exu_oor_va_m, |
| 118 | exu_tcc_m, |
| 119 | exu_tof_m, |
| 120 | exu_ccr0, |
| 121 | exu_ccr1, |
| 122 | exu_ccr2, |
| 123 | exu_ccr3, |
| 124 | ect_mbist_sel, |
| 125 | ect_rs1_early_sel_d, |
| 126 | ect_rs2_early_sel_d, |
| 127 | ect_rs3_early_sel_d, |
| 128 | ect_rs2_imm_sel_d, |
| 129 | ect_rs1_late_sel_d, |
| 130 | ect_rs2_late_sel_d, |
| 131 | ect_rs3_late_sel_d, |
| 132 | ect_logic_sel_d, |
| 133 | ect_shift_sel_d, |
| 134 | ect_br_taken_z0_e, |
| 135 | ect_br_taken_z1_e, |
| 136 | ect_alignaddress_little_e, |
| 137 | ect_as_clip_e_, |
| 138 | ect_as_cin_e, |
| 139 | ect_array_sel_e, |
| 140 | ect_edge_lmask_e, |
| 141 | ect_edge_lrmask_e, |
| 142 | ect_pstate_am_e, |
| 143 | ect_rm_early_sel_e, |
| 144 | ect_rm_late_sel_e, |
| 145 | ect_store_mux_sel_e, |
| 146 | ect_tid_lth_e, |
| 147 | ect_rs1_addr_e, |
| 148 | ect_rs2_addr_e, |
| 149 | ect_rs3_addr_e, |
| 150 | ect_rs1_valid_e, |
| 151 | ect_rs2_valid_e, |
| 152 | ect_rs3_valid_e, |
| 153 | ect_two_cycle_m, |
| 154 | ect_rd_lth_w, |
| 155 | ect_rd_lth_w2, |
| 156 | ect_tid_lth_w, |
| 157 | ect_tid_lth_w2, |
| 158 | ect_valid_lth_w, |
| 159 | ect_valid_in_w2, |
| 160 | ect_yreg_wr_w, |
| 161 | ect_rng_ccr_data, |
| 162 | ect_misaligned_error_m, |
| 163 | ect_ex_emb_clken, |
| 164 | ect_tg_clken, |
| 165 | scan_out, |
| 166 | wmr_scan_out); |
| 167 | wire pce_ov; |
| 168 | wire stop; |
| 169 | wire siclk; |
| 170 | wire soclk; |
| 171 | wire se; |
| 172 | wire l1clk; |
| 173 | wire l1clk_pm1; |
| 174 | wire ex_dw1_clken; |
| 175 | wire l1clk_pm2; |
| 176 | wire tg_active; |
| 177 | wire i_pwr0_lth_scanin; |
| 178 | wire i_pwr0_lth_scanout; |
| 179 | wire [2:0] lsu_exu_tid_b; |
| 180 | wire pmen_lth_; |
| 181 | wire tg_active_lth; |
| 182 | wire mbi_run_lth; |
| 183 | wire [2:2] tid_lth_w2; |
| 184 | wire i_pwr1_lth_scanin; |
| 185 | wire i_pwr1_lth_scanout; |
| 186 | wire pwr_m; |
| 187 | wire pwr_b; |
| 188 | wire pwr_w; |
| 189 | wire pwr_e; |
| 190 | wire pwr_w_p1; |
| 191 | wire i_mbist_lth_scanin; |
| 192 | wire i_mbist_lth_scanout; |
| 193 | wire mbi_irf_write_en_p1; |
| 194 | wire [6:0] mbi_addr_p1; |
| 195 | wire as_cin_d; |
| 196 | wire as_cin_set_d; |
| 197 | wire as_cin_ccr0_d; |
| 198 | wire ccr_byp_data_b0; |
| 199 | wire as_cin_ccr1_d; |
| 200 | wire wrxx_d; |
| 201 | wire wrxx_raw_d; |
| 202 | wire rs1_m_cmp; |
| 203 | wire rs1_b_cmp; |
| 204 | wire rs1_w_cmp; |
| 205 | wire rs1_w2_cmp; |
| 206 | wire rs1_w_plus1_cmp; |
| 207 | wire branch_d; |
| 208 | wire rs1_e_cmp; |
| 209 | wire rs1_l_cmp; |
| 210 | wire rs1_byp_early; |
| 211 | wire rs2_imm_sel7_d; |
| 212 | wire rs2_imm_sel6_d; |
| 213 | wire rs2_imm_sel5_d; |
| 214 | wire rs2_imm_sel4_d; |
| 215 | wire rs2_imm_sel3_d; |
| 216 | wire rs2_imm_sel2_d; |
| 217 | wire rs2_imm_sel1_d; |
| 218 | wire rs2_imm_sel0_d; |
| 219 | wire rs2_m_cmp; |
| 220 | wire rs2_b_cmp; |
| 221 | wire rs2_w_cmp; |
| 222 | wire rs2_w2_cmp; |
| 223 | wire rs2_w_plus1_cmp; |
| 224 | wire rs2_imm_data_d; |
| 225 | wire rs2_e_cmp; |
| 226 | wire rs2_l_cmp; |
| 227 | wire rs2_byp_early; |
| 228 | wire rs3_m_cmp; |
| 229 | wire rs3_b_cmp; |
| 230 | wire rs3_w_cmp; |
| 231 | wire rs3_w2_cmp; |
| 232 | wire rs3_w_plus1_cmp; |
| 233 | wire rs1_late_sel4_d; |
| 234 | wire rs3_e_cmp; |
| 235 | wire rs3_l_cmp; |
| 236 | wire rs3_byp_early; |
| 237 | wire [31:5] i; |
| 238 | wire as_subtract_d; |
| 239 | wire as_cc_d; |
| 240 | wire tas_cc_d; |
| 241 | wire tas_tv_d; |
| 242 | wire logic_sel3_d; |
| 243 | wire logic_sel2_d; |
| 244 | wire logic_sel1_d; |
| 245 | wire logic_sel0_d; |
| 246 | wire lg_cc_d; |
| 247 | wire shift_sel6_d; |
| 248 | wire shift_sel5_d; |
| 249 | wire shift_sel4_d; |
| 250 | wire shift_sel3_d; |
| 251 | wire shift_sel2_d; |
| 252 | wire shift_sel1_d; |
| 253 | wire shift_sel0_d; |
| 254 | wire edgele_d; |
| 255 | wire edge08_d; |
| 256 | wire edge16_d; |
| 257 | wire edge32_d; |
| 258 | wire array08_d; |
| 259 | wire array16_d; |
| 260 | wire call_d; |
| 261 | wire mov_cond_d; |
| 262 | wire bmask_d; |
| 263 | wire alignaddress_d; |
| 264 | wire alignaddress_little_d; |
| 265 | wire mux_mdp_sel0_d; |
| 266 | wire mux_mdp_sel1_d; |
| 267 | wire mux_mdp_sel2_d; |
| 268 | wire mux_mdp_sel3_d; |
| 269 | wire mux_mdp_sel4_d; |
| 270 | wire mux_mdp_sel5_d; |
| 271 | wire tcc_d; |
| 272 | wire address_d; |
| 273 | wire exu_op_d; |
| 274 | wire rm_late_sel0_d; |
| 275 | wire rm_late_sel1_d; |
| 276 | wire rm_late_sel2_d; |
| 277 | wire rm_early_sel0_d; |
| 278 | wire rm_early_sel1_d; |
| 279 | wire rm_early_sel2_d; |
| 280 | wire rm_early_sel4_d; |
| 281 | wire misalign_d; |
| 282 | wire ls_special_sel_d; |
| 283 | wire cmov_d; |
| 284 | wire regop_d; |
| 285 | wire specbr_d; |
| 286 | wire callclass_d; |
| 287 | wire movcc_d; |
| 288 | wire movr_d; |
| 289 | wire br_or_tcc_d; |
| 290 | wire bcc_d; |
| 291 | wire bpcc_d; |
| 292 | wire fmov_d; |
| 293 | wire imov_d; |
| 294 | wire fp_d; |
| 295 | wire two_cycle_d; |
| 296 | wire i_estage_lth_scanin; |
| 297 | wire i_estage_lth_scanout; |
| 298 | wire address_e; |
| 299 | wire branch_e; |
| 300 | wire ls_special_sel_e; |
| 301 | wire two_cycle_e; |
| 302 | wire rm_early_sel34; |
| 303 | wire as_subtract_e; |
| 304 | wire as_cc_e; |
| 305 | wire lg_cc_e; |
| 306 | wire misalign_e; |
| 307 | wire mov_cond_e; |
| 308 | wire tas_cc_e; |
| 309 | wire tas_tv_e; |
| 310 | wire tcc_e; |
| 311 | wire bmask_e; |
| 312 | wire alignaddress_e; |
| 313 | wire edge08_e; |
| 314 | wire edge16_e; |
| 315 | wire edge32_e; |
| 316 | wire edgele_e; |
| 317 | wire [1:0] gsr_vld_e_in; |
| 318 | wire address_e_in; |
| 319 | wire br_special_sel_e; |
| 320 | wire two_cycle_e_in; |
| 321 | wire i_mstage_lth_scanin; |
| 322 | wire i_mstage_lth_scanout; |
| 323 | wire address_m; |
| 324 | wire ls_special_sel_m; |
| 325 | wire br_special_sel_m; |
| 326 | wire fgu_valid_b; |
| 327 | wire lsu_valid_w2; |
| 328 | wire lsu_exu_ld_w; |
| 329 | wire valid_in_d; |
| 330 | wire valid_in_e; |
| 331 | wire valid_out_e; |
| 332 | wire valid_in_m; |
| 333 | wire valid_lth_m; |
| 334 | wire address_error_m; |
| 335 | wire valid_in_b; |
| 336 | wire valid_lth_b; |
| 337 | wire tof_b; |
| 338 | wire misalign_b; |
| 339 | wire [1:0] ect_tid_in_b; |
| 340 | wire [1:0] tid_lth_b; |
| 341 | wire [4:0] rd_in_d; |
| 342 | wire [4:0] inst_rs3_d; |
| 343 | wire [4:0] rd_in_m; |
| 344 | wire [4:0] rd_lth_m; |
| 345 | wire [4:0] ect_rd_in_b; |
| 346 | wire [4:0] rd_lth_b; |
| 347 | wire rs1_valid_d; |
| 348 | wire rs1_rd_en_d; |
| 349 | wire rs2_valid_d; |
| 350 | wire rs2_rd_en_d; |
| 351 | wire rs3_valid_d; |
| 352 | wire rs3_rd_en_d; |
| 353 | wire ren_lth_scanin; |
| 354 | wire ren_lth_scanout; |
| 355 | wire rs_lth_scanin; |
| 356 | wire rs_lth_scanout; |
| 357 | wire [4:0] inst_rs1_d; |
| 358 | wire [4:0] inst_rs2_d; |
| 359 | wire i_byp_lth_scanin; |
| 360 | wire i_byp_lth_scanout; |
| 361 | wire [1:0] tid_lth_d; |
| 362 | wire [4:0] rd_lth_e; |
| 363 | wire movcc_true_e; |
| 364 | wire [1:0] tid_lth_m; |
| 365 | wire [4:0] lsu_exu_rd_b; |
| 366 | wire valid_lth_e; |
| 367 | wire valid_lth_w_plus1; |
| 368 | wire [1:0] tid_lth_w_plus1; |
| 369 | wire [4:0] rd_lth_w_plus1; |
| 370 | wire valid_lth_w2_plus1; |
| 371 | wire [1:0] tid_lth_w2_plus1; |
| 372 | wire [4:0] rd_lth_w2_plus1; |
| 373 | wire dec_cmov_z00_e; |
| 374 | wire dec_cmov_z01_e; |
| 375 | wire dec_cmov_z10_e; |
| 376 | wire tas_tv_overflow_e; |
| 377 | wire misalign_error_e; |
| 378 | wire raw_valid_out_e; |
| 379 | wire rs1_w2_plus1_cmp; |
| 380 | wire rs2_w2_plus1_cmp; |
| 381 | wire rs3_w2_plus1_cmp; |
| 382 | wire [7:0] lg_cc; |
| 383 | wire [7:0] as_cc; |
| 384 | wire [7:0] ccr_data_e; |
| 385 | wire [7:0] ccr_data_b; |
| 386 | wire fgu_ccr_valid_b; |
| 387 | wire [7:0] ccr_data_lth_b; |
| 388 | wire ccr_valid_in_d; |
| 389 | wire ccr_valid_in_e; |
| 390 | wire ccr_valid_out_e; |
| 391 | wire ccr_valid_in_m; |
| 392 | wire ccr_valid_lth_m; |
| 393 | wire ccr_valid_in_b; |
| 394 | wire ccr_valid_lth_b; |
| 395 | wire wr_ccr_w_tid0; |
| 396 | wire ccr_valid_lth_w; |
| 397 | wire wr_ccr_w_tid1; |
| 398 | wire wr_ccr_w_tid2; |
| 399 | wire wr_ccr_w_tid3; |
| 400 | wire wr_ccr_tlu0; |
| 401 | wire wr_ccr_tlu1; |
| 402 | wire wr_ccr_tlu2; |
| 403 | wire wr_ccr_tlu3; |
| 404 | wire wr_ccr_asi0; |
| 405 | wire [1:0] rng_tid; |
| 406 | wire wr_ccr_asi1; |
| 407 | wire wr_ccr_asi2; |
| 408 | wire wr_ccr_asi3; |
| 409 | wire [7:0] arch_ccr_tid0_in; |
| 410 | wire [7:0] ccr_data_lth_w; |
| 411 | wire [7:0] arch_ccr_tid0_lth; |
| 412 | wire [7:0] arch_ccr_tid1_in; |
| 413 | wire [7:0] arch_ccr_tid1_lth; |
| 414 | wire [7:0] arch_ccr_tid2_in; |
| 415 | wire [7:0] arch_ccr_tid2_lth; |
| 416 | wire [7:0] arch_ccr_tid3_in; |
| 417 | wire [7:0] arch_ccr_tid3_lth; |
| 418 | wire i_ccr_pipe_lth_scanin; |
| 419 | wire i_ccr_pipe_lth_scanout; |
| 420 | wire [7:0] ccr_data_lth_m; |
| 421 | wire ccr_valid_lth_e; |
| 422 | wire i_ccr_arch_lth_wmr_scanin; |
| 423 | wire i_ccr_arch_lth_wmr_scanout; |
| 424 | wire ccr_e_cmp; |
| 425 | wire ccr_m_cmp; |
| 426 | wire ccr_b_cmp; |
| 427 | wire ccr_w_cmp; |
| 428 | wire ccr_sel_e; |
| 429 | wire ccr_sel_m; |
| 430 | wire ccr_sel_b; |
| 431 | wire ccr_sel_w; |
| 432 | wire ccr_sel_a0; |
| 433 | wire ccr_sel_a1; |
| 434 | wire ccr_sel_a2; |
| 435 | wire ccr_sel_a3; |
| 436 | wire [7:0] exu_ccr_byp_data0; |
| 437 | wire [7:0] exu_ccr_byp_data1; |
| 438 | wire ccr_byp_data_b1; |
| 439 | wire ccr_byp_data_b3; |
| 440 | wire trap_taken_e; |
| 441 | wire tcc_taken_e; |
| 442 | wire trap_taken_m_lth; |
| 443 | wire ms_icc_in; |
| 444 | wire tas_tv_overflow_m_in; |
| 445 | wire tas_tv_overflow_m_lth; |
| 446 | wire normal_va_hole_m_; |
| 447 | wire special_ls_va_hole_m_; |
| 448 | wire special_br_va_hole_m_; |
| 449 | wire va_hole_m; |
| 450 | wire pstate_am_m; |
| 451 | wire itlb_bypass_m; |
| 452 | wire misalign_error_m_in; |
| 453 | wire pstate_am_d; |
| 454 | wire i_tlu_lth_scanin; |
| 455 | wire i_tlu_lth_scanout; |
| 456 | wire yreg_mwr_valid_em3_in; |
| 457 | wire yreg_mwr_valid_em2_in; |
| 458 | wire yreg_mwr_valid_em2_lth; |
| 459 | wire yreg_mwr_valid_em1_in; |
| 460 | wire yreg_mwr_valid_em1_lth; |
| 461 | wire yreg_mwr_valid_e_in; |
| 462 | wire yreg_mwr_valid_e_lth; |
| 463 | wire yreg_mwr_valid_m_in; |
| 464 | wire yreg_mwr_valid_m_lth; |
| 465 | wire yreg_swr_valid_e_in; |
| 466 | wire yreg_swr_valid_m_in; |
| 467 | wire yreg_swr_valid_m_lth; |
| 468 | wire yreg_wr_valid_b_in; |
| 469 | wire yreg_mwr_valid_b_lth; |
| 470 | wire yreg_swr_valid_b_lth; |
| 471 | wire i_yreg_mpipe_lth_scanin; |
| 472 | wire i_yreg_mpipe_lth_scanout; |
| 473 | wire i_yreg_spipe_lth_scanin; |
| 474 | wire i_yreg_spipe_lth_scanout; |
| 475 | wire [7:0] lmask_e; |
| 476 | wire [7:0] rmask_e; |
| 477 | wire [7:0] lrmask_e; |
| 478 | wire [7:0] lmask_le8; |
| 479 | wire [7:0] lmask_le16; |
| 480 | wire [7:0] lmask_le32; |
| 481 | wire [7:0] lrmask_le8; |
| 482 | wire [7:0] lrmask_le16; |
| 483 | wire [7:0] lrmask_le32; |
| 484 | wire [2:0] cctype_d; |
| 485 | wire [3:0] brcond_d; |
| 486 | wire fgu_tid_ff_scanin; |
| 487 | wire fgu_tid_ff_scanout; |
| 488 | wire [2:0] fgu_cmp_fcc_tid_fx3; |
| 489 | wire [2:0] fgu_fld_fcc_tid_fx3; |
| 490 | wire [3:0] fcc_cw_valid; |
| 491 | wire sel_ct0; |
| 492 | wire sel_ct1; |
| 493 | wire sel_ct2; |
| 494 | wire sel_ct3; |
| 495 | wire [3:0] fcc_cw_t0; |
| 496 | wire [3:0] fcc_cw_t1; |
| 497 | wire [3:0] fcc_cw_t2; |
| 498 | wire [3:0] fcc_cw_t3; |
| 499 | wire [1:0] fcc_lw_valid; |
| 500 | wire sel_lt0; |
| 501 | wire sel_lt1; |
| 502 | wire sel_lt2; |
| 503 | wire sel_lt3; |
| 504 | wire [1:0] fcc_lw_t0; |
| 505 | wire [1:0] fcc_lw_t1; |
| 506 | wire [1:0] fcc_lw_t2; |
| 507 | wire [1:0] fcc_lw_t3; |
| 508 | wire [7:0] t0_data_in; |
| 509 | wire [7:0] t0_hold_in; |
| 510 | wire [7:0] fcc_t0_d; |
| 511 | wire [7:0] fcc_nxt_t0; |
| 512 | wire fcc_t0_ff_wmr_scanin; |
| 513 | wire fcc_t0_ff_wmr_scanout; |
| 514 | wire [7:0] t1_data_in; |
| 515 | wire [7:0] t1_hold_in; |
| 516 | wire [7:0] fcc_t1_d; |
| 517 | wire [7:0] fcc_nxt_t1; |
| 518 | wire fcc_t1_ff_wmr_scanin; |
| 519 | wire fcc_t1_ff_wmr_scanout; |
| 520 | wire [7:0] t2_data_in; |
| 521 | wire [7:0] t2_hold_in; |
| 522 | wire [7:0] fcc_t2_d; |
| 523 | wire [7:0] fcc_nxt_t2; |
| 524 | wire fcc_t2_ff_wmr_scanin; |
| 525 | wire fcc_t2_ff_wmr_scanout; |
| 526 | wire [7:0] t3_data_in; |
| 527 | wire [7:0] t3_hold_in; |
| 528 | wire [7:0] fcc_t3_d; |
| 529 | wire [7:0] fcc_nxt_t3; |
| 530 | wire fcc_t3_ff_wmr_scanin; |
| 531 | wire fcc_t3_ff_wmr_scanout; |
| 532 | wire [7:0] fcc_d; |
| 533 | wire use_fcc0_d; |
| 534 | wire use_fcc1_d; |
| 535 | wire use_fcc2_d; |
| 536 | wire use_fcc3_d; |
| 537 | wire [1:0] curr_fcc_d; |
| 538 | wire [3:0] fcc_dec_d; |
| 539 | wire fcce_ff_scanin; |
| 540 | wire fcce_ff_scanout; |
| 541 | wire [3:0] fcc_dec_e; |
| 542 | wire brcond_e_reg_scanin; |
| 543 | wire brcond_e_reg_scanout; |
| 544 | wire [3:0] br_cond_e; |
| 545 | wire use_xcc_d; |
| 546 | wire [7:0] ccr_byp_data; |
| 547 | wire [3:0] cc_d; |
| 548 | wire ccreg_e_scanin; |
| 549 | wire ccreg_e_scanout; |
| 550 | wire [3:0] cc_e; |
| 551 | wire [3:0] brcond_e; |
| 552 | wire ltz_e; |
| 553 | wire [7:0] cc_breval_e; |
| 554 | wire cc_eval0; |
| 555 | wire cc_eval1; |
| 556 | wire [7:0] fp_breval_e; |
| 557 | wire fp_eval0; |
| 558 | wire fp_eval1; |
| 559 | wire cctype_reg_scanin; |
| 560 | wire cctype_reg_scanout; |
| 561 | wire [2:2] cctype_e; |
| 562 | wire fpcond_mvbr_e; |
| 563 | wire cc_eval; |
| 564 | wire cond_true_e; |
| 565 | wire misc_ff_scanin; |
| 566 | wire misc_ff_scanout; |
| 567 | wire callclass_e; |
| 568 | wire specbr_e; |
| 569 | wire cmov_e; |
| 570 | wire regop_e; |
| 571 | wire r_eval1; |
| 572 | wire r_eval0; |
| 573 | wire final_cond_true_z0_e; |
| 574 | wire final_cond_true_z1_e; |
| 575 | wire spares_scanin; |
| 576 | wire spares_scanout; |
| 577 | |
| 578 | |
| 579 | // *** Global Inputs *** |
| 580 | |
| 581 | input l2clk; |
| 582 | input scan_in; |
| 583 | input wmr_scan_in; |
| 584 | input tcu_pce_ov; // scan signals |
| 585 | input spc_aclk; |
| 586 | input spc_bclk; |
| 587 | input spc_aclk_wmr; |
| 588 | input tcu_scan_en; |
| 589 | |
| 590 | input [1:0] dec_tid_p; |
| 591 | |
| 592 | input dec_inst_rs1_vld_p; |
| 593 | input dec_inst_rs2_vld_p; |
| 594 | input dec_inst_rs3_vld_p; |
| 595 | input [4:0] dec_inst_rs1_p; // window operations must be taken into account |
| 596 | input [4:0] dec_inst_rs2_p; |
| 597 | input [4:0] dec_inst_rs3_p; |
| 598 | input [4:0] dec_inst_rd_d; |
| 599 | input [31:5] dec_inst_d; |
| 600 | input dec_decode_d; // Instruction and TID are valid |
| 601 | input dec_thread_group; // Static Signal : Tie UP or DOWN where cloning occurs |
| 602 | |
| 603 | input dec_valid_e; // inst is truly valid at e (annul) |
| 604 | input tlu_itlb_bypass_e; // Ignore Address Out-Of-Range |
| 605 | |
| 606 | input dec_flush_m; |
| 607 | input dec_flush_b; |
| 608 | |
| 609 | input [3:0] fgu_exu_icc_fx5; // FGU int icc cond code {N,Z,V,C} |
| 610 | input [1:0] fgu_exu_xcc_fx5; // FGU int xcc cond code {N,Z} |
| 611 | input fgu_exu_cc_vld_fx5; // FGU int icc/xcc cond code valid |
| 612 | input [1:0] fgu_result_tid_fx5; |
| 613 | input [4:0] fgu_irf_w_addr_fx5; |
| 614 | input fgu_exu_w_vld_fx5; |
| 615 | |
| 616 | input lsu_exu_ld_b; |
| 617 | input [4:0] lsu_exu_rd_m; |
| 618 | input [2:0] lsu_exu_tid_m; |
| 619 | input lsu_exu_ld_vld_w; |
| 620 | |
| 621 | input tlu_flush_exu_b; // EXU to flush instr in B stage |
| 622 | input [7:0] tlu_ccr; |
| 623 | input tlu_ccr_cwp_valid; |
| 624 | input [1:0] tlu_ccr_cwp_tid; |
| 625 | input [3:0] tlu_pstate_am; // 32-bit addressing mode if = 1 |
| 626 | |
| 627 | input lsu_exu_pmen; // Power Management : Master Enable |
| 628 | input [3:0] spc_core_running_status; // Power Management : Thread active |
| 629 | |
| 630 | input mbi_run; // MBIST |
| 631 | input [6:0] mbi_addr; // MBIST |
| 632 | input mbi_irf_write_en; // MBIST |
| 633 | |
| 634 | |
| 635 | // *** Local Inputs *** |
| 636 | |
| 637 | input [7:0] edp_rng_in_ff; // ASI Ring : In data flopped |
| 638 | input edp_rng_in_ff_b56; |
| 639 | input edp_rng_in_ff_b57; |
| 640 | input rml_rng_wt_ccr_ctl; |
| 641 | |
| 642 | input [1:0] edp_br_flag_e; // [1] : RS1 negative; [0] : RS1 zero; |
| 643 | input [63:0] exu_rs1_data_e; |
| 644 | input [63:0] exu_rs2_data_e; |
| 645 | |
| 646 | input edp_add_cout64_e; |
| 647 | input edp_add_data_e_b63; |
| 648 | input edp_add_data_e_b31; |
| 649 | input edp_add_data_e_b1; |
| 650 | input edp_add_data_e_b0; |
| 651 | input [1:0] edp_add_zdetect_e_; |
| 652 | |
| 653 | input edp_sub_cout64_e; |
| 654 | input edp_sub_data_e_b63; |
| 655 | input edp_sub_data_e_b31; |
| 656 | input [1:0] edp_sub_zdetect_e_; |
| 657 | |
| 658 | input edp_logical_data_e_b63; |
| 659 | input edp_logical_data_e_b31; |
| 660 | input [1:0] edp_lg_zdetect_e; |
| 661 | |
| 662 | input [63:47] edp_address_m; |
| 663 | input [63:47] edp_rd_ff_m; |
| 664 | |
| 665 | input exu_ecc_m; |
| 666 | |
| 667 | input rml_test_valid_d; |
| 668 | |
| 669 | |
| 670 | // *** DEC_CCR Inputs *** |
| 671 | |
| 672 | input [7:0] fgu_fld_fcc_fx3; // fcc's from the fgu |
| 673 | input [2:0] lsu_fgu_fld_tid_b; |
| 674 | input [1:0] fgu_fld_fcc_vld_fx3; |
| 675 | input lsu_fgu_fld_vld_w; // Float load valid |
| 676 | |
| 677 | input [1:0] fgu_cmp_fcc_fx3; // fcc's from the fgu |
| 678 | input [2:0] fgu_cmp_fcc_tid_fx2; |
| 679 | input [3:0] fgu_cmp_fcc_vld_fx3; |
| 680 | |
| 681 | input [3:0] dec_pick_d; // which stand is valid at d |
| 682 | |
| 683 | |
| 684 | // *** Global Outputs *** |
| 685 | |
| 686 | output [5:0] exu_mdp_mux_sel_e; // To MDP |
| 687 | output exu_ms_icc_e; |
| 688 | |
| 689 | output [1:0] exu_gsr_vld_m; |
| 690 | output exu_cmov_true_m; |
| 691 | |
| 692 | output exu_lsu_va_error_m; // To LSU : Address Out of Range |
| 693 | |
| 694 | output exu_misalign_m; // To TLU : Misaligned address for Jump,Return |
| 695 | output exu_oor_va_m; // To TLU : Address Out of Range |
| 696 | output exu_tcc_m; // To TLU : Trap taken |
| 697 | output exu_tof_m; // To TLU : Tagged Add TV with overflow |
| 698 | |
| 699 | output [7:0] exu_ccr0; // To TLU : Architected CCR |
| 700 | output [7:0] exu_ccr1; // To TLU : Architected CCR |
| 701 | output [7:0] exu_ccr2; // To TLU : Architected CCR |
| 702 | output [7:0] exu_ccr3; // To TLU : Architected CCR |
| 703 | |
| 704 | |
| 705 | // *** Local Outputs *** |
| 706 | |
| 707 | output ect_mbist_sel; |
| 708 | |
| 709 | output [4:0] ect_rs1_early_sel_d; |
| 710 | output [4:0] ect_rs2_early_sel_d; |
| 711 | output [4:0] ect_rs3_early_sel_d; |
| 712 | output [7:0] ect_rs2_imm_sel_d; |
| 713 | output [3:0] ect_rs1_late_sel_d; |
| 714 | output [3:0] ect_rs2_late_sel_d; |
| 715 | output [3:0] ect_rs3_late_sel_d; |
| 716 | output [3:0] ect_logic_sel_d; |
| 717 | output [6:0] ect_shift_sel_d; |
| 718 | |
| 719 | output ect_br_taken_z0_e; |
| 720 | output ect_br_taken_z1_e; |
| 721 | output ect_alignaddress_little_e; |
| 722 | output ect_as_clip_e_; // ALIGNADDRESS clipping of bit [2:0] |
| 723 | output ect_as_cin_e; |
| 724 | output [1:0] ect_array_sel_e; |
| 725 | output [7:0] ect_edge_lmask_e; |
| 726 | output [7:0] ect_edge_lrmask_e; |
| 727 | output ect_pstate_am_e; |
| 728 | output [5:0] ect_rm_early_sel_e; |
| 729 | output [2:0] ect_rm_late_sel_e; // [0] : Sub; [1] : Add; [2] : Shift; Def : Early Mux |
| 730 | output ect_store_mux_sel_e; |
| 731 | output [1:0] ect_tid_lth_e; |
| 732 | |
| 733 | output [4:0] ect_rs1_addr_e; |
| 734 | output [4:0] ect_rs2_addr_e; |
| 735 | output [4:0] ect_rs3_addr_e; |
| 736 | output ect_rs1_valid_e; // Allow ECC checking on RS1 |
| 737 | output ect_rs2_valid_e; // Allow ECC checking on RS2 |
| 738 | output ect_rs3_valid_e; // Allow ECC checking on RS3 |
| 739 | output ect_two_cycle_m; // Allow ECC checking on 2nd cycle of CASA+STD |
| 740 | |
| 741 | output [4:0] ect_rd_lth_w; |
| 742 | output [4:0] ect_rd_lth_w2; |
| 743 | output [1:0] ect_tid_lth_w; |
| 744 | output [1:0] ect_tid_lth_w2; |
| 745 | output ect_valid_lth_w; |
| 746 | output ect_valid_in_w2; |
| 747 | |
| 748 | output ect_yreg_wr_w; |
| 749 | output [7:0] ect_rng_ccr_data; |
| 750 | |
| 751 | output ect_misaligned_error_m; // To RML : assert when last 2 bit of address is non "00" |
| 752 | |
| 753 | output ect_ex_emb_clken; // Power Management |
| 754 | output ect_tg_clken; // Power Management |
| 755 | |
| 756 | |
| 757 | output scan_out; |
| 758 | output wmr_scan_out; |
| 759 | |
| 760 | |
| 761 | // scan renames |
| 762 | assign pce_ov = tcu_pce_ov; |
| 763 | assign stop = 1'b0; |
| 764 | assign siclk = spc_aclk; |
| 765 | assign soclk = spc_bclk; |
| 766 | assign se = tcu_scan_en; |
| 767 | // end scan |
| 768 | |
| 769 | |
| 770 | |
| 771 | //!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : Power Management !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! |
| 772 | |
| 773 | |
| 774 | exu_ect_ctl_l1clkhdr_ctl_macro clkgen ( |
| 775 | .l2clk( l2clk ), |
| 776 | .l1en ( 1'b1 ), |
| 777 | .l1clk( l1clk ), |
| 778 | .pce_ov(pce_ov), |
| 779 | .stop(stop), |
| 780 | .se(se)); |
| 781 | |
| 782 | |
| 783 | exu_ect_ctl_l1clkhdr_ctl_macro clkgen_pm1 ( |
| 784 | .l2clk( l2clk ), |
| 785 | .l1en ( ect_tg_clken ), |
| 786 | .l1clk( l1clk_pm1 ), |
| 787 | .pce_ov(pce_ov), |
| 788 | .stop(stop), |
| 789 | .se(se)); |
| 790 | |
| 791 | |
| 792 | exu_ect_ctl_l1clkhdr_ctl_macro clkgen_pm2 ( |
| 793 | .l2clk( l2clk ), |
| 794 | .l1en ( ex_dw1_clken ), |
| 795 | .l1clk( l1clk_pm2 ), |
| 796 | .pce_ov(pce_ov), |
| 797 | .stop(stop), |
| 798 | .se(se)); |
| 799 | |
| 800 | |
| 801 | assign tg_active = (spc_core_running_status[3:0] != 4'b0000); |
| 802 | |
| 803 | exu_ect_ctl_msff_ctl_macro__width_5 i_pwr0_lth ( |
| 804 | .scan_in(i_pwr0_lth_scanin), |
| 805 | .scan_out(i_pwr0_lth_scanout), |
| 806 | .l1clk( l1clk ), |
| 807 | .din ({~lsu_exu_pmen , tg_active , mbi_run , lsu_exu_tid_m[2] , lsu_exu_tid_b[2]} ), |
| 808 | .dout ({pmen_lth_ , tg_active_lth , mbi_run_lth , lsu_exu_tid_b[2] , tid_lth_w2[2]} ), |
| 809 | .siclk(siclk), |
| 810 | .soclk(soclk)); |
| 811 | |
| 812 | |
| 813 | exu_ect_ctl_msff_ctl_macro__width_5 i_pwr1_lth ( |
| 814 | .scan_in(i_pwr1_lth_scanin), |
| 815 | .scan_out(i_pwr1_lth_scanout), |
| 816 | .l1clk( l1clk_pm1 ), |
| 817 | .din ({dec_decode_d , dec_valid_e , pwr_m , pwr_b , pwr_w} ), |
| 818 | .dout ({pwr_e , pwr_m , pwr_b , pwr_w , pwr_w_p1} ), |
| 819 | .siclk(siclk), |
| 820 | .soclk(soclk)); |
| 821 | |
| 822 | |
| 823 | assign ect_tg_clken = pmen_lth_ | tg_active_lth | mbi_run_lth; |
| 824 | assign ect_ex_emb_clken = pmen_lth_ | mbi_run_lth | pwr_e | pwr_m | pwr_b; |
| 825 | assign ex_dw1_clken = pmen_lth_ | mbi_run_lth | dec_decode_d | pwr_e | pwr_m | pwr_b | pwr_w | pwr_w_p1; |
| 826 | |
| 827 | assign ect_mbist_sel = mbi_run_lth; |
| 828 | |
| 829 | |
| 830 | exu_ect_ctl_msff_ctl_macro__width_8 i_mbist_lth ( |
| 831 | .scan_in(i_mbist_lth_scanin), |
| 832 | .scan_out(i_mbist_lth_scanout), |
| 833 | .l1clk( l1clk_pm1 ), |
| 834 | .din ({mbi_irf_write_en , mbi_addr[6:0]} ), |
| 835 | .dout ({mbi_irf_write_en_p1 , mbi_addr_p1[6:0]} ), |
| 836 | .siclk(siclk), |
| 837 | .soclk(soclk)); |
| 838 | |
| 839 | |
| 840 | //!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End : Power Management !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! |
| 841 | |
| 842 | |
| 843 | |
| 844 | |
| 845 | //!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : Decode !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! |
| 846 | |
| 847 | // *** WARNING : Full decodes used until unit is functional - then use espresso |
| 848 | |
| 849 | |
| 850 | // assign inst[29:25] = dec_inst_d[29:25]; |
| 851 | |
| 852 | |
| 853 | // *** ADD/SUB *** |
| 854 | |
| 855 | // assign d_add = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_0000); |
| 856 | // assign d_addcc = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_0000); |
| 857 | // assign d_addc = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_1000); |
| 858 | // assign d_addccc = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_1000); |
| 859 | |
| 860 | // assign d_sub = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_0100); |
| 861 | // assign d_subcc = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_0100); |
| 862 | // assign d_subc = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_1100); |
| 863 | // assign d_subccc = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_1100); |
| 864 | |
| 865 | // assign d_taddcc = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0000); // pg 234 : Tagged Add |
| 866 | // assign d_taddcctv = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0010); // pg 234 : Tagged Add |
| 867 | // assign d_tsubcc = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0001); // pg 235 : Tagged Sub |
| 868 | // assign d_tsubcctv = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0011); // pg 235 : Tagged Sub |
| 869 | |
| 870 | // assign d_save = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_1100); // pg 214 : Save |
| 871 | // assign d_restore = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_1101); // pg 214 : Restore |
| 872 | |
| 873 | // assign add_d = d_add | d_addcc | d_addc | d_addccc | d_taddcc | d_taddcctv | bmask_d | alignaddress_d | alignaddress_little_d; |
| 874 | // assign sub_d = d_sub | d_subcc | d_subc | d_subccc | d_tsubcc | d_tsubcctv; |
| 875 | // assign addsub_d = add_d | sub_d | bmask_d | alignaddress_d | alignaddress_little_d; |
| 876 | |
| 877 | // assign as_subtract_d = sub_d | edge_d; |
| 878 | |
| 879 | // assign as_cc_d = d_addcc | d_addccc | d_subcc | d_subccc | d_taddcc | d_taddcctv | d_tsubcc | d_tsubcctv | edge_cc_d; |
| 880 | // assign tas_cc_d = d_taddcc | d_taddcctv | d_tsubcc | d_tsubcctv; |
| 881 | // assign tas_tv_d = d_taddcctv | d_tsubcctv; |
| 882 | |
| 883 | // assign as_cin_d = ((d_sub | d_subcc ) ) | |
| 884 | // ((d_tsubcc | d_tsubcctv) ) | |
| 885 | // ( edge_d ) | |
| 886 | // ((d_subc | d_subccc ) & ~ccr_byp_data_b0) | |
| 887 | // ((d_addc | d_addccc ) & ccr_byp_data_b0); |
| 888 | |
| 889 | assign as_cin_d = as_cin_set_d | |
| 890 | (as_cin_ccr0_d & ~ccr_byp_data_b0) | |
| 891 | (as_cin_ccr1_d & ccr_byp_data_b0); |
| 892 | |
| 893 | |
| 894 | |
| 895 | // *** LOGICAL |
| 896 | |
| 897 | // assign d_and = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_0001); |
| 898 | // assign d_andcc = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_0001); |
| 899 | // assign d_andn = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_0101); |
| 900 | // assign d_andncc = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_0101); |
| 901 | // assign d_or = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_0010); |
| 902 | // assign d_orcc = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_0010); |
| 903 | // assign d_orn = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_0110); |
| 904 | // assign d_orncc = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_0110); |
| 905 | // assign d_xor = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_0011); |
| 906 | // assign d_xorcc = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_0011); |
| 907 | // assign d_xorn = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_0111); |
| 908 | // assign d_xorncc = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_0111); |
| 909 | |
| 910 | // assign logic_rs2_d = sethi_d | mov_cond_d; |
| 911 | |
| 912 | // assign logic_d = d_and | d_andcc | d_andn | d_andncc | d_or | d_orcc | d_orn | d_orncc | d_xor | d_xorcc | d_xorn | d_xorncc | logic_rs2_d; |
| 913 | // assign logic_sel_d[3] = d_and | d_andcc | d_or | d_orcc | d_orn | d_orncc | d_xorn | d_xorncc | logic_rs2_d | casa_d; |
| 914 | // assign logic_sel_d[2] = d_andn | d_andncc | d_or | d_orcc | d_orn | d_orncc | d_xor | d_xorcc | casa_d; |
| 915 | // assign logic_sel_d[1] = d_or | d_orcc | d_xor | d_xorcc | logic_rs2_d; |
| 916 | // assign logic_sel_d[0] = d_orn | d_orncc | d_xorn | d_xorncc ; |
| 917 | |
| 918 | // assign lg_cc_d = d_andcc | d_andncc | d_orcc | d_orncc | d_xorcc | d_xorncc; |
| 919 | |
| 920 | |
| 921 | // *** SHIFT *** |
| 922 | |
| 923 | // assign d_sll = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0101) & (inst[12] == 1'b0); |
| 924 | // assign d_srl = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0110) & (inst[12] == 1'b0); |
| 925 | // assign d_sra = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0111) & (inst[12] == 1'b0); |
| 926 | // assign d_sllx = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0101) & (inst[12] == 1'b1); |
| 927 | // assign d_srlx = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0110) & (inst[12] == 1'b1); |
| 928 | // assign d_srax = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0111) & (inst[12] == 1'b1); |
| 929 | |
| 930 | // assign shift_d = d_sll | d_srl | d_sra | d_sllx | d_srlx | d_srax; |
| 931 | // assign shift_sel_d[6] = d_srl | d_sra | d_srlx | d_srax; |
| 932 | // assign shift_sel_d[5] = d_sll | d_sllx ; |
| 933 | // assign shift_sel_d[4] = d_srax; |
| 934 | // assign shift_sel_d[3] = d_sra ; |
| 935 | // assign shift_sel_d[2] = d_srlx | d_srax; |
| 936 | // assign shift_sel_d[1] = d_sllx ; |
| 937 | // assign shift_sel_d[0] = d_sll | d_srl | d_sra ; |
| 938 | |
| 939 | |
| 940 | // *** EDGE *** |
| 941 | |
| 942 | // assign d_edge8 = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_0000); // VIS pg. 70 |
| 943 | // assign d_edge8n = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_0001); // VIS pg. 70 |
| 944 | // assign d_edge8l = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_0010); // VIS pg. 70 |
| 945 | // assign d_edge8ln = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_0011); // VIS pg. 70 |
| 946 | // assign d_edge16 = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_0100); // VIS pg. 70 |
| 947 | // assign d_edge16n = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_0101); // VIS pg. 70 |
| 948 | // assign d_edge16l = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_0110); // VIS pg. 70 |
| 949 | // assign d_edge16ln = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_0111); // VIS pg. 70 |
| 950 | // assign d_edge32 = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_1000); // VIS pg. 70 |
| 951 | // assign d_edge32n = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_1001); // VIS pg. 70 |
| 952 | // assign d_edge32l = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_1010); // VIS pg. 70 |
| 953 | // assign d_edge32ln = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_1011); // VIS pg. 70 |
| 954 | |
| 955 | // assign edge08_d = d_edge8 | d_edge8n | d_edge8l | d_edge8ln; |
| 956 | // assign edge16_d = d_edge16 | d_edge16n | d_edge16l | d_edge16ln; |
| 957 | // assign edge32_d = d_edge32 | d_edge32n | d_edge32l | d_edge32ln; |
| 958 | // assign edge_d = edge08_d | edge16_d | edge32_d; |
| 959 | // assign edgele_d = d_edge8l | d_edge8ln | d_edge16l | d_edge16ln | d_edge32l | d_edge32ln; |
| 960 | |
| 961 | // assign edge_cc_d = d_edge8 | d_edge8l | d_edge16 | d_edge16l | d_edge32 | d_edge32l; |
| 962 | |
| 963 | |
| 964 | // *** ARRAY *** |
| 965 | |
| 966 | // assign array08_d = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0001_0000); // VIS pg. 74 |
| 967 | // assign array16_d = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0001_0010); // VIS pg. 74 |
| 968 | // assign array32_d = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0001_0100); // VIS pg. 74 |
| 969 | |
| 970 | // assign array_d = array08_d | array16_d | array32_d; |
| 971 | |
| 972 | |
| 973 | // *** BRANCH *** |
| 974 | |
| 975 | // assign bpr_d = (inst[31:30] == 2'b00) & (inst[28] == 1'b0) & (inst[24:22] == 3'b011); // pg 136 : sign_ext{[21:20],[13:0]} |
| 976 | // assign bicc_d = (inst[31:30] == 2'b00) & (inst[24:22] == 3'b010); // pg 144 : sign_ext{[21:0]} |
| 977 | // assign bpcc_d = (inst[31:30] == 2'b00) & (inst[24:22] == 3'b001); // pg 146 : sign_ext{[18:0]} |
| 978 | // assign call_d = (inst[31:30] == 2'b01); // pg 149 : sign_ext{[29:0]} |
| 979 | // assign fbfcc_d = (inst[31:30] == 2'b00) & (inst[24:22] == 3'b110); // pg 138 : sign_ext{[21:0]} |
| 980 | // assign fbpfcc_d = (inst[31:30] == 2'b00) & (inst[24:22] == 3'b101); // pg 141 : sign_ext{[18:0]} |
| 981 | |
| 982 | // assign branch_d = bpr_d | bicc_d | bpcc_d | call_d | fbfcc_d | fbpfcc_d; |
| 983 | |
| 984 | |
| 985 | // *** Conditional Move *** |
| 986 | |
| 987 | // assign fmovcc_d = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0101) & (inst[18] == 1'b0); // pg 185 : Move FP on Condition Code |
| 988 | // assign fmovr_d = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0101) & (inst[13] == 1'b0); // pg 189 : Move FP on Integer reg |
| 989 | // assign movcc_d = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_1100); // pg 189 : Move Int on Condition Code |
| 990 | // assign movr_d = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_1111); // pg 189 : Move Int on Integer reg |
| 991 | |
| 992 | // assign mov_cond_d = movcc_d | movr_d; |
| 993 | |
| 994 | // *** LOAD & STORE *** |
| 995 | |
| 996 | // assign d_ldf = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_0000); // pg 171 : Load Floating Point |
| 997 | // assign d_lddf = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_0011); // pg 171 : Load Floating Point |
| 998 | // assign d_ldqf = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_0010); // pg 171 : Load Floating Point |
| 999 | // assign d_ldfsr = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_0001); // pg 171 : Load Floating Point |
| 1000 | // assign d_ldxfsr = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_0001); // pg 171 : Load Floating Point |
| 1001 | |
| 1002 | // assign d_ldfa = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b11_0000); // pg 173 : Load Floating Point from Alternate Space |
| 1003 | // assign d_lddfa = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b11_0011); // pg 173 : Load Floating Point from Alternate Space |
| 1004 | // assign d_ldqfa = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b11_0010); // pg 173 : Load Floating Point from Alternate Space |
| 1005 | |
| 1006 | // assign d_ldsb = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_1001); // pg 175 : Load Integer |
| 1007 | // assign d_ldsh = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_1010); // pg 175 : Load Integer |
| 1008 | // assign d_ldsw = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_1000); // pg 175 : Load Integer |
| 1009 | // assign d_ldub = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_0001); // pg 175 : Load Integer |
| 1010 | // assign d_lduh = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_0010); // pg 175 : Load Integer |
| 1011 | // assign d_lduw = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_0000); // pg 175 : Load Integer |
| 1012 | // assign d_ldx = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_1011); // pg 175 : Load Integer |
| 1013 | // assign d_ldd = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_0011); // pg 175 : Load Integer |
| 1014 | |
| 1015 | // assign d_ldsba = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_1001); // pg 177 : Load Integer from Alternate Space |
| 1016 | // assign d_ldsha = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_1010); // pg 177 : Load Integer from Alternate Space |
| 1017 | // assign d_ldswa = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_1000); // pg 177 : Load Integer from Alternate Space |
| 1018 | // assign d_lduba = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_0001); // pg 177 : Load Integer from Alternate Space |
| 1019 | // assign d_lduha = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_0010); // pg 177 : Load Integer from Alternate Space |
| 1020 | // assign d_lduwa = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_0000); // pg 177 : Load Integer from Alternate Space |
| 1021 | // assign d_ldxa = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_1011); // pg 177 : Load Integer from Alternate Space |
| 1022 | // assign d_ldda = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_0011); // pg 177 : Load Integer from Alternate Space |
| 1023 | |
| 1024 | // assign d_ldstub = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_1101); // pg 179 : Load-Store |
| 1025 | // assign d_ldstuba = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_1101); // pg 180 : Load-Store from Alternate Space |
| 1026 | |
| 1027 | // assign d_prefetch = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_1101); // pg 203 : Prefetch Data |
| 1028 | // assign d_prefetcha = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b11_1101); // pg 203 : Prefetch Data from Alternate Space |
| 1029 | |
| 1030 | |
| 1031 | // assign load_d = d_ldf | d_lddf | d_ldfsr | d_ldxfsr | |
| 1032 | // d_ldfa | d_lddfa | |
| 1033 | // d_ldsb | d_ldsh | d_ldsw | d_ldub | d_lduh | d_lduw | d_ldx | d_ldd | |
| 1034 | // d_ldsba | d_ldsha | d_ldswa | d_lduba | d_lduha | d_lduwa | d_ldxa | d_ldda | |
| 1035 | // d_ldstub | d_ldstuba | |
| 1036 | // d_prefetch | d_prefetcha; |
| 1037 | |
| 1038 | // assign int_load_d = d_ldsb | d_ldsh | d_ldsw | d_ldub | d_lduh | d_lduw | d_ldx | d_ldd | |
| 1039 | // d_ldsba | d_ldsha | d_ldswa | d_lduba | d_lduha | d_lduwa | d_ldxa | d_ldda | |
| 1040 | // d_ldstub | d_ldstuba; |
| 1041 | |
| 1042 | |
| 1043 | // assign d_stf = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_0100); // pg 222 : Store Floating Point |
| 1044 | // assign d_stdf = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_0111); // pg 222 : Store Floating Point |
| 1045 | // assign d_stqf = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_0110); // pg 222 : Store Floating Point |
| 1046 | // assign d_stfsr = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_0101); // pg 222 : Store Floating Point |
| 1047 | // assign d_stxfsr = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_0101); // pg 222 : Store Floating Point |
| 1048 | |
| 1049 | // assign d_stfa = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b11_0100); // pg 224 : Store Floating Point from Alternate Space |
| 1050 | // assign d_stdfa = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b11_0111); // pg 224 : Store Floating Point from Alternate Space |
| 1051 | // assign d_stqfa = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b11_0110); // pg 224 : Store Floating Point from Alternate Space |
| 1052 | |
| 1053 | // assign d_stb = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_0101); // pg 226 : Store Integer |
| 1054 | // assign d_sth = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_0110); // pg 226 : Store Integer |
| 1055 | // assign d_stw = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_0100); // pg 226 : Store Integer |
| 1056 | // assign d_stx = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_1110); // pg 226 : Store Integer |
| 1057 | // assign d_std = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_0111); // pg 226 : Store Integer |
| 1058 | |
| 1059 | // assign d_stba = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_0101); // pg 226 : Store Integer from Alternate Space |
| 1060 | // assign d_stha = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_0110); // pg 226 : Store Integer from Alternate Space |
| 1061 | // assign d_stwa = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_0100); // pg 226 : Store Integer from Alternate Space |
| 1062 | // assign d_stxa = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_1110); // pg 226 : Store Integer from Alternate Space |
| 1063 | // assign d_stda = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_0111); // pg 226 : Store Integer from Alternate Space |
| 1064 | |
| 1065 | // assign d_swap = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_1111); // pg 231 : Swap Register with Memory |
| 1066 | // assign d_swapa = (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_1111); // pg 232 : Swap Register with Alt Space Memory |
| 1067 | |
| 1068 | |
| 1069 | // assign casa_d =((inst[31:30] == 2'b11) & (inst[24:19] == 6'b11_1100))| // pg 150 : Compare and Swap |
| 1070 | // ((inst[31:30] == 2'b11) & (inst[24:19] == 6'b11_1110)); // pg 150 : Compare and Swap |
| 1071 | |
| 1072 | |
| 1073 | // assign store_d = d_stf | d_stdf | d_stfsr | d_stxfsr | |
| 1074 | // d_stfa | d_stdfa | |
| 1075 | // d_stb | d_sth | d_stw | d_stx | d_std | |
| 1076 | // d_stba | d_stha | d_stwa | d_stxa | d_stda | |
| 1077 | // d_swap | d_swapa; |
| 1078 | |
| 1079 | |
| 1080 | // *** VIS *** |
| 1081 | |
| 1082 | // assign bmask_d = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:5] == 9'b0_0001_1001); |
| 1083 | // assign alignaddress_d = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:5] == 9'b0_0001_1000); |
| 1084 | // assign alignaddress_little_d = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:5] == 9'b0_0001_1010); |
| 1085 | |
| 1086 | |
| 1087 | |
| 1088 | // *** FGU *** |
| 1089 | |
| 1090 | // assign d_udiv = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_1110); // pg 152 : Unsigned Integer Division |
| 1091 | // assign d_sdiv = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_1111); // pg 152 : Signed Integer Division |
| 1092 | // assign d_udivcc = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_1110); // pg 152 : Unsigned Integer Division |
| 1093 | // assign d_sdivcc = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_1111); // pg 152 : Signed Integer Division |
| 1094 | |
| 1095 | // assign d_mulx = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_1001); // pg 196 : Multiply (signed or unsigned) |
| 1096 | // assign d_sdivx = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_1101); // pg 196 : Signed Divide |
| 1097 | // assign d_udivx = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_1101); // pg 196 : Unsigned Divide |
| 1098 | |
| 1099 | // assign d_umul = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_1010); // pg 197 : Unsigned Integer Multiply |
| 1100 | // assign d_smul = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_1011); // pg 197 : Signed Integer Multiply |
| 1101 | // assign d_umulcc = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_1010); // pg 197 : Unsigned Integer Multiply |
| 1102 | // assign d_smulcc = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_1011); // pg 197 : Signed Integer Multiply |
| 1103 | |
| 1104 | // assign d_mulscc = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0100); // pg 199 : Multiply Step |
| 1105 | |
| 1106 | // assign d_popc = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_1110); // pg 202 : Population Count |
| 1107 | |
| 1108 | // assign int_to_fgu_d = d_udiv | d_sdiv | d_udivcc | d_sdivcc | |
| 1109 | // d_mulx | d_sdivx | d_udivx | |
| 1110 | // d_umul | d_smul | d_umulcc | d_smulcc | |
| 1111 | // d_mulscc | d_popc; |
| 1112 | |
| 1113 | // assign mux_mdp_sel_d[0] = d_smul | d_smulcc; |
| 1114 | // assign mux_mdp_sel_d[1] = d_umul | d_umulcc; |
| 1115 | // assign mux_mdp_sel_d[2] = d_udiv | d_sdiv | d_udivcc | d_sdivcc; |
| 1116 | // assign mux_mdp_sel_d[3] = d_mulscc; |
| 1117 | // assign mux_mdp_sel_d[4] = d_sdiv | d_sdivcc | d_smul | d_smulcc; |
| 1118 | // assign mux_mdp_sel_d[5] = d_udiv | d_udivcc | d_umul | d_umulcc | d_mulscc; |
| 1119 | |
| 1120 | |
| 1121 | |
| 1122 | // *** MISC *** |
| 1123 | |
| 1124 | // assign jmpl_d = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_1000); |
| 1125 | // assign return_d = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_1001); |
| 1126 | // assign sethi_d = (inst[31:30] == 2'b00) & (inst[24:22] == 3'b10_0 ); |
| 1127 | // assign sir_d = (inst[31:30] == 2'b10) & (inst[29:14] == 16'b01111_11_0000_00000); // pg 220 |
| 1128 | // assign tcc_d = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_1010); // pg 237 : Trap on Integer Condition |
| 1129 | // assign d_wrpr = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0010); // pg 239 : Write Privileged Register |
| 1130 | // assign d_wry = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0000); // pg 241 : Write State Register |
| 1131 | // assign d_wrhpr = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0011); // |
| 1132 | // assign wrxx_d = (d_wrpr | d_wry | d_wrhpr) & dec_decode_d; |
| 1133 | assign wrxx_d = wrxx_raw_d & dec_decode_d; |
| 1134 | |
| 1135 | // assign address_d = branch_d | load_d | store_d | return_d | casa_d; |
| 1136 | |
| 1137 | // assign exu_op_d = logic_d | shift_d | add_d | sub_d | jmpl_d | edge_d | array_d; |
| 1138 | |
| 1139 | |
| 1140 | |
| 1141 | // *** Operand Selects *** |
| 1142 | |
| 1143 | assign ect_rs1_early_sel_d[0] = rs1_m_cmp; |
| 1144 | assign ect_rs1_early_sel_d[1] = rs1_b_cmp; |
| 1145 | assign ect_rs1_early_sel_d[2] = rs1_w_cmp; |
| 1146 | assign ect_rs1_early_sel_d[3] = rs1_w2_cmp; |
| 1147 | assign ect_rs1_early_sel_d[4] = rs1_w_plus1_cmp; |
| 1148 | |
| 1149 | assign ect_rs1_late_sel_d[0] = branch_d; // PC |
| 1150 | assign ect_rs1_late_sel_d[1] = rs1_e_cmp; // E Stage Bypass |
| 1151 | assign ect_rs1_late_sel_d[2] = rs1_l_cmp & ~rs1_m_cmp; // Load Bypass |
| 1152 | assign ect_rs1_late_sel_d[3] = rs1_byp_early; |
| 1153 | |
| 1154 | // assign ect_rs2_imm_sel_d[0] = bpr_d; // immediate BPr = {[21:20],[13:0]} |
| 1155 | // assign ect_rs2_imm_sel_d[1] = bicc_d | fbfcc_d; // immediate disp22 |
| 1156 | // assign ect_rs2_imm_sel_d[2] = bpcc_d | fbpfcc_d; // immediate disp19 |
| 1157 | // assign ect_rs2_imm_sel_d[3] = call_d; // immediate disp30 |
| 1158 | // assign ect_rs2_imm_sel_d[4] = sethi_d; // IMM22 |
| 1159 | // assign ect_rs2_imm_sel_d[5] = movcc_d; // SIMM11 |
| 1160 | // assign ect_rs2_imm_sel_d[6] = movr_d; // SIMM10 |
| 1161 | // assign ect_rs2_imm_sel_d[7] = rs2_imm13_data_d; // SIMM13 |
| 1162 | assign ect_rs2_imm_sel_d[7:0] = {rs2_imm_sel7_d,rs2_imm_sel6_d,rs2_imm_sel5_d,rs2_imm_sel4_d,rs2_imm_sel3_d,rs2_imm_sel2_d,rs2_imm_sel1_d,rs2_imm_sel0_d}; |
| 1163 | |
| 1164 | |
| 1165 | assign ect_rs2_early_sel_d[0] = rs2_m_cmp; |
| 1166 | assign ect_rs2_early_sel_d[1] = rs2_b_cmp; |
| 1167 | assign ect_rs2_early_sel_d[2] = rs2_w_cmp; |
| 1168 | assign ect_rs2_early_sel_d[3] = rs2_w2_cmp; |
| 1169 | assign ect_rs2_early_sel_d[4] = rs2_w_plus1_cmp; |
| 1170 | |
| 1171 | // assign rs2_imm13_data_d = (d_save | d_restore | logic_d | add_d | sub_d | shift_d | load_d | store_d | jmpl_d | |
| 1172 | // return_d | sir_d | tcc_d | d_wrpr | d_wrhpr | d_wry | int_to_fgu_d) & inst[13]; |
| 1173 | |
| 1174 | // assign rs2_imm_data_d = branch_d | sethi_d | rs2_imm13_data_d; |
| 1175 | |
| 1176 | |
| 1177 | assign ect_rs2_late_sel_d[0] = rs2_imm_data_d; // Immediate |
| 1178 | assign ect_rs2_late_sel_d[1] = rs2_e_cmp; // E Stage Bypass |
| 1179 | assign ect_rs2_late_sel_d[2] = rs2_l_cmp & ~rs2_m_cmp; // Load Bypass |
| 1180 | assign ect_rs2_late_sel_d[3] = rs2_byp_early; |
| 1181 | |
| 1182 | |
| 1183 | assign ect_rs3_early_sel_d[0] = rs3_m_cmp; |
| 1184 | assign ect_rs3_early_sel_d[1] = rs3_b_cmp; |
| 1185 | assign ect_rs3_early_sel_d[2] = rs3_w_cmp; |
| 1186 | assign ect_rs3_early_sel_d[3] = rs3_w2_cmp; |
| 1187 | assign ect_rs3_early_sel_d[4] = rs3_w_plus1_cmp; |
| 1188 | |
| 1189 | assign ect_rs3_late_sel_d[0] = rs1_late_sel4_d & dec_decode_d & ~rml_test_valid_d; // call_d | jmpl_d |
| 1190 | assign ect_rs3_late_sel_d[1] = rs3_e_cmp & ~rml_test_valid_d; |
| 1191 | assign ect_rs3_late_sel_d[2] = rs3_l_cmp & ~rs3_m_cmp & ~rml_test_valid_d; |
| 1192 | assign ect_rs3_late_sel_d[3] = rs3_byp_early & ~rml_test_valid_d; |
| 1193 | |
| 1194 | |
| 1195 | // *** RESULT MUX *** |
| 1196 | |
| 1197 | // assign rm_late_sel_d[0] = sub_d; |
| 1198 | // assign rm_late_sel_d[1] = add_d | tcc_d | load_d | store_d | return_d | bpr_d | bicc_d | bpcc_d | fbfcc_d | fbpfcc_d; |
| 1199 | // assign rm_late_sel_d[2] = shift_d; |
| 1200 | |
| 1201 | // assign rm_early_sel_d[0] = logic_d | casa_d; |
| 1202 | // assign rm_early_sel_d[1] = array_d; |
| 1203 | // assign rm_early_sel_d[2] = edge_d; |
| 1204 | // assign rm_early_sel_d[3] = d_mulscc; |
| 1205 | // assign rm_early_sel_d[4] = call_d | jmpl_d; |
| 1206 | |
| 1207 | |
| 1208 | |
| 1209 | |
| 1210 | |
| 1211 | |
| 1212 | |
| 1213 | |
| 1214 | // The ESPRESSO code below was generated from the EXU's "decode" file using the following command : |
| 1215 | // |
| 1216 | // ~rg131678/perl/n2decode -i decode -exu > decode.out |
| 1217 | // |
| 1218 | |
| 1219 | assign i[31:5] = dec_inst_d[31:5]; |
| 1220 | |
| 1221 | // --- autogenerated by n2decode view=exu Tue Aug 16 16:43:11 CDT 2005 |
| 1222 | |
| 1223 | assign as_subtract_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[12]&!i[11] |
| 1224 | &!i[10]&!i[9]) | (i[31]&!i[30]&i[24]&!i[23]&!i[22]&!i[21]&i[19]) | ( |
| 1225 | i[31]&!i[30]&!i[24]&i[21]&!i[20]&!i[19]); |
| 1226 | |
| 1227 | assign as_cc_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[11]&!i[10]&!i[9] |
| 1228 | &!i[5]) | (i[31]&!i[30]&!i[24]&i[23]&!i[20]&!i[19]) | (i[31]&!i[30] |
| 1229 | &i[24]&!i[23]&!i[22]&!i[21]); |
| 1230 | |
| 1231 | assign tas_cc_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&!i[21]); |
| 1232 | |
| 1233 | assign tas_tv_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&!i[21]&i[20]); |
| 1234 | |
| 1235 | assign as_cin_set_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[12]&!i[11] |
| 1236 | &!i[10]&!i[9]) | (i[31]&!i[30]&i[24]&!i[23]&!i[22]&!i[21]&i[19]) | ( |
| 1237 | i[31]&!i[30]&!i[24]&!i[22]&i[21]&!i[20]&!i[19]); |
| 1238 | |
| 1239 | assign as_cin_ccr0_d = (i[31]&!i[24]&i[22]&i[21]&!i[20]&!i[19]); |
| 1240 | |
| 1241 | assign as_cin_ccr1_d = (i[31]&!i[30]&!i[24]&i[22]&!i[21]&!i[20]&!i[19]); |
| 1242 | |
| 1243 | assign logic_sel3_d = (i[31]&i[24]&i[23]&i[21]&i[20]&i[19]&!i[13]&i[12]&i[11] |
| 1244 | &!i[10]&!i[9]) | (i[31]&i[30]&i[24]&i[22]&!i[19]) | (i[31]&!i[30] |
| 1245 | &!i[24]&!i[22]&!i[21]&!i[20]&i[19]) | (i[31]&!i[30]&!i[24]&!i[22] |
| 1246 | &i[21]&i[20]) | (i[31]&i[24]&!i[23]&i[22]&i[21]&!i[20]&!i[19]) | ( |
| 1247 | i[31]&i[24]&i[22]&i[21]&i[20]&i[19]) | (i[31]&!i[30]&!i[24]&!i[22] |
| 1248 | &i[20]&!i[19]) | (!i[31]&!i[30]&!i[23]&!i[22]); |
| 1249 | |
| 1250 | assign logic_sel2_d = (i[31]&i[24]&i[23]&i[21]&i[20]&i[19]&!i[13]&i[12]&i[11] |
| 1251 | &!i[10]&!i[9]) | (i[31]&!i[30]&!i[24]&!i[22]&i[21]&!i[20]&i[19]) | ( |
| 1252 | i[31]&i[30]&i[24]&i[22]&!i[19]) | (i[31]&!i[30]&!i[24]&!i[22]&!i[21] |
| 1253 | &i[20]) | (i[31]&!i[30]&!i[24]&!i[22]&i[20]&!i[19]); |
| 1254 | |
| 1255 | assign logic_sel1_d = (i[31]&i[24]&!i[23]&i[22]&i[21]&!i[20]&!i[19]) | (i[31] |
| 1256 | &i[24]&i[22]&i[21]&i[20]&i[19]) | (i[31]&!i[30]&!i[24]&!i[22]&!i[21] |
| 1257 | &i[20]) | (!i[31]&!i[30]&!i[23]&!i[22]); |
| 1258 | |
| 1259 | assign logic_sel0_d = (i[31]&!i[30]&!i[24]&!i[22]&i[21]&i[20]); |
| 1260 | |
| 1261 | assign lg_cc_d = (i[31]&!i[30]&!i[24]&i[23]&!i[20]&i[19]) | (i[31]&!i[30]&!i[24] |
| 1262 | &i[23]&!i[22]&i[20]); |
| 1263 | |
| 1264 | assign shift_sel6_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&i[21]&i[20]&i[12]) | ( |
| 1265 | i[31]&!i[30]&i[24]&!i[23]&!i[22]&i[21]&i[19]&i[12]); |
| 1266 | |
| 1267 | assign shift_sel5_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&i[21]&i[20]); |
| 1268 | |
| 1269 | assign shift_sel4_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&i[21]&!i[20]&i[19]); |
| 1270 | |
| 1271 | assign shift_sel3_d = (i[31]&!i[30]&i[24]&!i[22]&i[21]&i[20]&i[19]&i[12]); |
| 1272 | |
| 1273 | assign shift_sel2_d = (i[31]&!i[30]&i[24]&!i[22]&i[21]&i[20]&i[19]&!i[12]); |
| 1274 | |
| 1275 | assign shift_sel1_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&i[21]&i[20]&i[12]); |
| 1276 | |
| 1277 | assign shift_sel0_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&i[21]&!i[20]&i[19]&i[12]); |
| 1278 | |
| 1279 | assign edgele_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[11]&!i[10] |
| 1280 | &!i[9]&i[6]); |
| 1281 | |
| 1282 | assign edge08_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[12]&!i[10] |
| 1283 | &!i[9]&!i[8]&!i[7]); |
| 1284 | |
| 1285 | assign edge16_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[10]&!i[9]&!i[8] |
| 1286 | &i[7]); |
| 1287 | |
| 1288 | assign edge32_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[11]&!i[10] |
| 1289 | &!i[9]&i[8]); |
| 1290 | |
| 1291 | assign array08_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&!i[11]&i[9]&!i[8]&!i[7] |
| 1292 | &!i[6]&!i[5]); |
| 1293 | |
| 1294 | assign array16_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&!i[11]&!i[10]&i[9] |
| 1295 | &!i[8]&i[6]); |
| 1296 | |
| 1297 | assign call_d = (!i[31]&i[30]); |
| 1298 | |
| 1299 | assign branch_d = (!i[31]&i[23]) | (!i[31]&i[22]) | (!i[31]&i[30]); |
| 1300 | |
| 1301 | assign mov_cond_d = (i[31]&i[24]&i[22]&i[21]&i[20]&i[19]) | (i[31]&i[24]&!i[23] |
| 1302 | &i[22]&i[21]&!i[20]&!i[19]); |
| 1303 | |
| 1304 | assign bmask_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&!i[10]&i[9]&i[8]&i[5]); |
| 1305 | |
| 1306 | assign alignaddress_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&!i[10]&i[9]&i[8] |
| 1307 | &!i[6]&!i[5]); |
| 1308 | |
| 1309 | assign alignaddress_little_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&!i[10] |
| 1310 | &i[9]&i[8]&i[6]); |
| 1311 | |
| 1312 | assign mux_mdp_sel0_d = (i[31]&!i[30]&!i[24]&i[22]&!i[21]&i[20]&i[19]); |
| 1313 | |
| 1314 | assign mux_mdp_sel1_d = (i[31]&!i[30]&!i[24]&i[22]&!i[21]&i[20]&!i[19]); |
| 1315 | |
| 1316 | assign mux_mdp_sel2_d = (i[31]&!i[30]&!i[24]&i[22]&i[21]&i[20]); |
| 1317 | |
| 1318 | assign mux_mdp_sel3_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&i[21]&!i[20]&!i[19]); |
| 1319 | |
| 1320 | assign mux_mdp_sel4_d = (i[31]&!i[30]&!i[24]&i[22]&i[20]&i[19]); |
| 1321 | |
| 1322 | assign mux_mdp_sel5_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&i[21]&!i[20]&!i[19]) | ( |
| 1323 | i[31]&!i[30]&!i[24]&i[22]&i[20]&!i[19]); |
| 1324 | |
| 1325 | assign tcc_d = (!i[30]&i[24]&i[23]&i[22]&!i[21]&i[20]&!i[19]); |
| 1326 | |
| 1327 | assign wrxx_raw_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[20]&i[19]) | (i[31]&!i[30] |
| 1328 | &i[24]&i[23]&!i[22]&!i[21]&!i[19]); |
| 1329 | |
| 1330 | assign address_d = (i[30]&i[22]&!i[19]) | (i[30]&!i[22]&i[19]) | (i[30]&!i[20] |
| 1331 | &!i[19]) | (!i[31]&i[22]) | (!i[31]&i[23]) | (i[24]&i[23]&i[22]&!i[21] |
| 1332 | &!i[20]) | (i[30]&!i[24]) | (!i[31]&i[30]); |
| 1333 | |
| 1334 | assign exu_op_d = (i[31]&!i[30]&!i[22]&i[21]&i[20]&!i[12]&!i[11]&!i[10]) | ( |
| 1335 | i[31]&i[24]&i[23]&i[22]&!i[21]&!i[20]&!i[19]) | (i[31]&i[24]&i[22] |
| 1336 | &i[21]&i[20]&i[19]) | (i[31]&!i[23]&i[22]&i[21]&!i[20]&!i[19]) | ( |
| 1337 | !i[30]&!i[23]&!i[22]&i[19]) | (i[31]&!i[30]&!i[24]&!i[20]&!i[19]) | ( |
| 1338 | !i[30]&!i[23]&!i[22]&i[20]) | (i[31]&!i[30]&!i[24]&!i[22]) | (!i[30] |
| 1339 | &!i[23]&!i[22]&!i[21]) | (!i[31]&!i[30]&!i[23]&!i[22]); |
| 1340 | |
| 1341 | assign rs1_late_sel4_d = (i[24]&i[23]&i[22]&!i[21]&!i[20]&!i[19]) | (!i[31] |
| 1342 | &i[30]); |
| 1343 | |
| 1344 | assign rs2_imm_sel0_d = (!i[31]&!i[30]&i[23]&i[22]); |
| 1345 | |
| 1346 | assign rs2_imm_sel1_d = (!i[31]&!i[30]&i[23]&!i[22]); |
| 1347 | |
| 1348 | assign rs2_imm_sel2_d = (!i[31]&!i[30]&!i[23]&i[22]); |
| 1349 | |
| 1350 | assign rs2_imm_sel3_d = (!i[31]&i[30]); |
| 1351 | |
| 1352 | assign rs2_imm_sel4_d = (!i[31]&!i[30]&!i[23]&!i[22]); |
| 1353 | |
| 1354 | assign rs2_imm_sel5_d = (i[31]&i[24]&!i[23]&i[22]&i[21]&!i[20]&!i[19]); |
| 1355 | |
| 1356 | assign rs2_imm_sel6_d = (i[31]&i[24]&i[22]&i[21]&i[20]&i[19]); |
| 1357 | |
| 1358 | assign rs2_imm_sel7_d = (i[31]&!i[23]&i[22]&i[21]&i[20]&!i[19]&i[13]) | (i[31] |
| 1359 | &!i[30]&i[23]&!i[21]&!i[19]&i[13]) | (i[31]&i[22]&i[21]&!i[20]&i[19] |
| 1360 | &i[13]) | (!i[30]&i[24]&i[23]&i[22]&!i[20]&i[13]) | (i[31]&!i[22] |
| 1361 | &i[20]&i[19]&i[13]) | (i[31]&i[30]&!i[22]&!i[20]&i[13]) | (i[31] |
| 1362 | &!i[30]&!i[23]&!i[22]&i[13]) | (i[31]&!i[24]&i[13]); |
| 1363 | |
| 1364 | assign rs2_imm_data_d = (i[23]&i[22]&!i[21]&!i[19]&i[13]) | (!i[23]&!i[22]&i[19] |
| 1365 | &i[13]) | (!i[30]&i[23]&i[22]&!i[20]&i[13]) | (!i[30]&!i[22]&i[20] |
| 1366 | &i[13]) | (!i[22]&!i[20]&!i[19]&i[13]) | (!i[30]&!i[23]&i[21]&i[13]) | ( |
| 1367 | i[30]&i[19]&i[13]) | (!i[31]) | (!i[24]&i[13]); |
| 1368 | |
| 1369 | assign rm_late_sel0_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&!i[21]&i[19]) | ( |
| 1370 | i[31]&!i[30]&!i[24]&i[21]&!i[20]&!i[19]); |
| 1371 | |
| 1372 | assign rm_late_sel1_d = (i[31]&i[30]&!i[20]&i[19]) | (i[31]&i[30]&i[19]&i[13]) | ( |
| 1373 | !i[30]&i[24]&i[23]&i[22]&!i[21]&i[20]&!i[19]) | (i[31]&i[30]&i[19] |
| 1374 | &!i[12]) | (!i[30]&!i[24]&!i[21]&!i[20]&!i[19]) | (!i[30]&i[23]&i[22] |
| 1375 | &!i[21]&!i[20]&i[19]) | (i[31]&i[30]&i[19]&!i[11]) | (i[31]&i[30] |
| 1376 | &i[19]&i[10]) | (i[31]&i[30]&i[19]&i[9]) | (!i[30]&i[24]&i[23]&!i[22] |
| 1377 | &i[21]&!i[10]&i[9]&i[8]) | (i[31]&i[30]&!i[23]&i[19]) | (!i[31]&!i[30] |
| 1378 | &i[22]) | (!i[31]&!i[30]&i[23]) | (i[31]&i[30]&!i[24]) | (i[31]&!i[30] |
| 1379 | &i[24]&!i[23]&!i[22]&!i[21]&!i[19]) | (i[31]&i[30]&!i[22]&!i[20]) | ( |
| 1380 | i[31]&i[30]&!i[21]&i[19]); |
| 1381 | |
| 1382 | assign rm_late_sel2_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&i[21]&i[20]) | (i[31] |
| 1383 | &!i[30]&i[24]&!i[23]&!i[22]&i[21]&i[19]); |
| 1384 | |
| 1385 | assign rm_early_sel0_d = (i[31]&i[24]&i[23]&i[21]&i[20]&i[19]&!i[13]&i[12]&i[11] |
| 1386 | &!i[10]&!i[9]) | (i[31]&i[30]&i[24]&i[22]&!i[19]) | (i[31]&!i[30] |
| 1387 | &!i[24]&!i[22]&i[19]) | (i[31]&i[24]&!i[23]&i[22]&i[21]&!i[20]&!i[19]) | ( |
| 1388 | i[31]&i[24]&i[22]&i[21]&i[20]&i[19]) | (i[31]&!i[30]&!i[24]&!i[22] |
| 1389 | &i[20]) | (!i[31]&!i[30]&!i[23]&!i[22]); |
| 1390 | |
| 1391 | assign rm_early_sel1_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&!i[11]&!i[10] |
| 1392 | &i[9]&!i[8]); |
| 1393 | |
| 1394 | assign rm_early_sel2_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&i[21]&!i[20]&!i[19]); |
| 1395 | |
| 1396 | assign rm_early_sel4_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[12] |
| 1397 | &!i[11]&!i[10]&!i[9]); |
| 1398 | |
| 1399 | assign misalign_d = (!i[30]&i[24]&i[23]&i[22]&!i[21]&!i[20]); |
| 1400 | |
| 1401 | assign ls_special_sel_d = (i[31]&i[24]&i[23]&i[21]&i[20]&i[19]&!i[13]&i[12] |
| 1402 | &i[11]&!i[10]&!i[9]) | (i[31]&i[30]&i[24]&i[22]&!i[19]); |
| 1403 | |
| 1404 | assign cmov_d = (i[31]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[9]&!i[5]) | ( |
| 1405 | i[31]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[9]&!i[6]) | (i[31] |
| 1406 | &i[24]&!i[23]&i[22]&i[21]&!i[20]&!i[19]) | (i[31]&i[24]&i[22]&i[21] |
| 1407 | &i[20]&i[19]); |
| 1408 | |
| 1409 | assign regop_d = (i[31]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[9]&i[7]&!i[5]) | ( |
| 1410 | i[31]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[9]&i[7]&!i[6]) | ( |
| 1411 | !i[31]&!i[30]&i[23]&i[22]) | (i[31]&i[24]&i[22]&i[21]&i[20]&i[19]); |
| 1412 | |
| 1413 | assign specbr_d = (!i[31]&!i[30]&i[23]) | (!i[31]&!i[30]&i[22]); |
| 1414 | |
| 1415 | assign callclass_d = (i[24]&i[23]&i[22]&!i[21]&!i[20]) | (!i[31]&i[30]); |
| 1416 | |
| 1417 | assign movcc_d = (i[31]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[9]&!i[7]&!i[5]) | ( |
| 1418 | i[31]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[9]&!i[7]&!i[6]) | ( |
| 1419 | i[31]&i[24]&!i[23]&i[22]&i[21]&!i[20]&!i[19]); |
| 1420 | |
| 1421 | assign movr_d = (i[31]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[9]&i[7]&!i[5]) | ( |
| 1422 | i[31]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[9]&i[7]&!i[6]) | ( |
| 1423 | i[31]&i[24]&i[22]&i[21]&i[20]&i[19]); |
| 1424 | |
| 1425 | assign br_or_tcc_d = (!i[30]&i[24]&i[23]&i[22]&!i[21]&i[20]&!i[19]) | (!i[31] |
| 1426 | &!i[30]&i[23]) | (!i[31]&!i[30]&i[22]); |
| 1427 | |
| 1428 | assign bcc_d = (!i[31]&!i[30]&i[23]&!i[22]); |
| 1429 | |
| 1430 | assign bpcc_d = (!i[31]&!i[30]&!i[23]&i[22]); |
| 1431 | |
| 1432 | assign fmov_d = (i[31]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[9]&!i[7]&!i[5]) | ( |
| 1433 | i[31]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[9]&!i[7]&!i[6]) | ( |
| 1434 | !i[30]&i[24]&i[23]&i[22]&!i[21]&i[20]&!i[19]); |
| 1435 | |
| 1436 | assign imov_d = (i[31]&i[24]&!i[23]&i[22]&i[21]&!i[20]&!i[19]); |
| 1437 | |
| 1438 | assign fp_d = (!i[31]&!i[30]&i[24]&i[23]) | (!i[31]&!i[30]&i[24]&i[22]); |
| 1439 | |
| 1440 | assign two_cycle_d = (i[31]&i[30]&i[24]&i[22]&!i[19]) | (i[31]&i[30]&!i[24] |
| 1441 | &!i[22]&i[21]&i[20]&i[19]); |
| 1442 | |
| 1443 | // end autogeneration |
| 1444 | |
| 1445 | |
| 1446 | |
| 1447 | // *** Embed DECODE.OUT above here *** |
| 1448 | |
| 1449 | assign ect_logic_sel_d[3:0] = {logic_sel3_d,logic_sel2_d,logic_sel1_d,logic_sel0_d}; |
| 1450 | assign ect_shift_sel_d[6:0] = {shift_sel6_d,shift_sel5_d,shift_sel4_d,shift_sel3_d,shift_sel2_d,shift_sel1_d,shift_sel0_d}; |
| 1451 | |
| 1452 | |
| 1453 | exu_ect_ctl_msff_ctl_macro__width_37 i_estage_lth ( |
| 1454 | .scan_in(i_estage_lth_scanin), |
| 1455 | .scan_out(i_estage_lth_scanout), |
| 1456 | .l1clk( l1clk_pm2 ), |
| 1457 | .din ({address_d , |
| 1458 | branch_d , |
| 1459 | ls_special_sel_d , |
| 1460 | two_cycle_d , |
| 1461 | (~mux_mdp_sel5_d & ~mux_mdp_sel4_d),mux_mdp_sel4_d,mux_mdp_sel3_d,mux_mdp_sel2_d,mux_mdp_sel1_d,mux_mdp_sel0_d, |
| 1462 | rm_early_sel4_d,rs1_late_sel4_d,rm_early_sel2_d,rm_early_sel1_d,rm_early_sel0_d, |
| 1463 | rm_late_sel2_d,rm_late_sel1_d,rm_late_sel0_d, |
| 1464 | as_cin_d , |
| 1465 | as_subtract_d , |
| 1466 | as_cc_d,lg_cc_d , |
| 1467 | misalign_d , |
| 1468 | mov_cond_d , |
| 1469 | tas_cc_d,tas_tv_d , |
| 1470 | tcc_d , |
| 1471 | wrxx_d , |
| 1472 | bmask_d,alignaddress_d,alignaddress_little_d , |
| 1473 | array16_d,array08_d , |
| 1474 | edge08_d,edge16_d,edge32_d ,edgele_d }), |
| 1475 | .dout ({address_e , |
| 1476 | branch_e , |
| 1477 | ls_special_sel_e , |
| 1478 | two_cycle_e , |
| 1479 | exu_mdp_mux_sel_e[5:0] , |
| 1480 | ect_rm_early_sel_e[5],rm_early_sel34,ect_rm_early_sel_e[2:0], |
| 1481 | ect_rm_late_sel_e[2:0] , |
| 1482 | ect_as_cin_e , |
| 1483 | as_subtract_e , |
| 1484 | as_cc_e,lg_cc_e , |
| 1485 | misalign_e , |
| 1486 | mov_cond_e , |
| 1487 | tas_cc_e,tas_tv_e , |
| 1488 | tcc_e , |
| 1489 | ect_store_mux_sel_e , |
| 1490 | bmask_e,alignaddress_e,ect_alignaddress_little_e , |
| 1491 | ect_array_sel_e[1:0] , |
| 1492 | edge08_e,edge16_e,edge32_e ,edgele_e }), |
| 1493 | .siclk(siclk), |
| 1494 | .soclk(soclk)); |
| 1495 | |
| 1496 | |
| 1497 | assign ect_rm_early_sel_e[3] = rm_early_sel34 & ~ect_pstate_am_e; |
| 1498 | assign ect_rm_early_sel_e[4] = rm_early_sel34 & ect_pstate_am_e; |
| 1499 | |
| 1500 | assign ect_as_clip_e_ = ~(alignaddress_e | ect_alignaddress_little_e); |
| 1501 | |
| 1502 | |
| 1503 | assign gsr_vld_e_in[1] = dec_valid_e & (alignaddress_e | ect_alignaddress_little_e); |
| 1504 | assign gsr_vld_e_in[0] = dec_valid_e & bmask_e; |
| 1505 | |
| 1506 | assign address_e_in = address_e & dec_valid_e; |
| 1507 | |
| 1508 | assign br_special_sel_e = branch_e & exu_rs1_data_e[47]; |
| 1509 | |
| 1510 | assign two_cycle_e_in = dec_valid_e & two_cycle_e; |
| 1511 | |
| 1512 | exu_ect_ctl_msff_ctl_macro__width_6 i_mstage_lth ( |
| 1513 | .scan_in(i_mstage_lth_scanin), |
| 1514 | .scan_out(i_mstage_lth_scanout), |
| 1515 | .l1clk( l1clk_pm2 ), |
| 1516 | .din ({gsr_vld_e_in[1:0] , address_e_in , ls_special_sel_e , br_special_sel_e , two_cycle_e_in} ), |
| 1517 | .dout ({exu_gsr_vld_m[1:0] , address_m , ls_special_sel_m , br_special_sel_m , ect_two_cycle_m} ), |
| 1518 | .siclk(siclk), |
| 1519 | .soclk(soclk)); |
| 1520 | |
| 1521 | |
| 1522 | //!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End : Decode !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! |
| 1523 | |
| 1524 | |
| 1525 | |
| 1526 | |
| 1527 | |
| 1528 | //!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : Bypass !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! |
| 1529 | |
| 1530 | |
| 1531 | assign fgu_valid_b = fgu_exu_w_vld_fx5 & ~(fgu_irf_w_addr_fx5[4:0] == 5'b00000); |
| 1532 | assign lsu_valid_w2 = lsu_exu_ld_w & (dec_thread_group == tid_lth_w2[2]) & ~(ect_rd_lth_w2[4:0] == 5'b00000); |
| 1533 | assign ect_valid_in_w2 = lsu_exu_ld_vld_w & (dec_thread_group == tid_lth_w2[2]) & ~(ect_rd_lth_w2[4:0] == 5'b00000) & ~ect_mbist_sel; |
| 1534 | |
| 1535 | |
| 1536 | // *** Valids *** |
| 1537 | |
| 1538 | |
| 1539 | assign valid_in_d = (exu_op_d & ~(dec_inst_d[29:25] == 5'b00000)) | call_d; // see SPARC v9, page 30. |
| 1540 | assign valid_in_e = valid_out_e; |
| 1541 | assign valid_in_m = valid_lth_m & ~dec_flush_m & ~exu_ecc_m & ~address_error_m; |
| 1542 | assign valid_in_b = (valid_lth_b & ~dec_flush_b & ~tlu_flush_exu_b & ~tof_b & ~misalign_b & ~ect_mbist_sel) | |
| 1543 | (fgu_valid_b & ~ect_mbist_sel) | |
| 1544 | mbi_irf_write_en_p1; |
| 1545 | |
| 1546 | |
| 1547 | |
| 1548 | // *** Tid *** |
| 1549 | |
| 1550 | assign ect_tid_in_b[1:0]= ({2{~ect_mbist_sel & fgu_exu_w_vld_fx5}} & fgu_result_tid_fx5[1:0]) | |
| 1551 | ({2{~ect_mbist_sel & ~fgu_exu_w_vld_fx5}} & tid_lth_b[1:0] ) | |
| 1552 | ({2{ ect_mbist_sel }} & mbi_addr_p1[6:5] ); |
| 1553 | |
| 1554 | // *** RD *** |
| 1555 | assign rd_in_d[4:0] = ({5{~two_cycle_e_in}} & dec_inst_rd_d[4:0]) | |
| 1556 | ({5{ two_cycle_e_in}} & inst_rs3_d[4:0] ); |
| 1557 | |
| 1558 | assign rd_in_m[4:0] = rd_lth_m[4:0]; |
| 1559 | |
| 1560 | assign ect_rd_in_b[4:0] = ({5{~ect_mbist_sel & fgu_valid_b}} & fgu_irf_w_addr_fx5[4:0]) | |
| 1561 | ({5{~ect_mbist_sel & ~fgu_valid_b}} & rd_lth_b[4:0] ) | |
| 1562 | ({5{ ect_mbist_sel }} & mbi_addr_p1[4:0] ); |
| 1563 | |
| 1564 | |
| 1565 | assign rs1_valid_d = (ect_rs1_late_sel_d[3:1] == 3'b000 ) & rs1_rd_en_d & ~two_cycle_e_in; |
| 1566 | assign rs2_valid_d = (ect_rs2_late_sel_d[3:0] == 4'b0000) & rs2_rd_en_d & ~two_cycle_e_in; |
| 1567 | assign rs3_valid_d = (ect_rs3_late_sel_d[3:1] == 3'b000 ) & rs3_rd_en_d; |
| 1568 | |
| 1569 | exu_ect_ctl_msff_ctl_macro__width_6 ren_lth ( |
| 1570 | .scan_in(ren_lth_scanin), |
| 1571 | .scan_out(ren_lth_scanout), |
| 1572 | .l1clk( l1clk_pm1 ), |
| 1573 | .din ({dec_inst_rs1_vld_p , dec_inst_rs2_vld_p , dec_inst_rs3_vld_p , |
| 1574 | rs1_valid_d , rs2_valid_d , rs3_valid_d }), |
| 1575 | .dout ({rs1_rd_en_d , rs2_rd_en_d , rs3_rd_en_d , |
| 1576 | ect_rs1_valid_e , ect_rs2_valid_e , ect_rs3_valid_e }), |
| 1577 | .siclk(siclk), |
| 1578 | .soclk(soclk)); |
| 1579 | |
| 1580 | |
| 1581 | |
| 1582 | |
| 1583 | exu_ect_ctl_msff_ctl_macro__width_15 rs_lth ( |
| 1584 | .scan_in(rs_lth_scanin), |
| 1585 | .scan_out(rs_lth_scanout), |
| 1586 | .l1clk( l1clk_pm1 ), |
| 1587 | .din ({dec_inst_rs1_p[4:0] , dec_inst_rs2_p[4:0] , dec_inst_rs3_p[4:0]} ), |
| 1588 | .dout ({ inst_rs1_d[4:0] , inst_rs2_d[4:0] , inst_rs3_d[4:0]} ), |
| 1589 | .siclk(siclk), |
| 1590 | .soclk(soclk)); |
| 1591 | |
| 1592 | |
| 1593 | exu_ect_ctl_msff_ctl_macro__width_76 i_byp_lth ( |
| 1594 | .scan_in(i_byp_lth_scanin), |
| 1595 | .scan_out(i_byp_lth_scanout), |
| 1596 | .l1clk( l1clk_pm1 ), |
| 1597 | .din ({ dec_tid_p[1:0] , |
| 1598 | valid_in_d , tid_lth_d[1:0] , rd_in_d[4:0] , inst_rs1_d[4:0] , inst_rs2_d[4:0] , |
| 1599 | valid_in_e , ect_tid_lth_e[1:0] , rd_lth_e[4:0] , movcc_true_e , |
| 1600 | valid_in_m , tid_lth_m[1:0] , rd_in_m[4:0] , |
| 1601 | valid_in_b , ect_tid_in_b[1:0] , ect_rd_in_b[4:0] , |
| 1602 | ect_valid_lth_w , ect_tid_lth_w[1:0] , ect_rd_lth_w[4:0] , |
| 1603 | lsu_exu_tid_m[1:0] , lsu_exu_rd_m[4:0] , |
| 1604 | lsu_exu_tid_b[1:0] , lsu_exu_rd_b[4:0] , lsu_exu_ld_b , |
| 1605 | ect_valid_in_w2 , ect_tid_lth_w2[1:0] , ect_rd_lth_w2[4:0] }), |
| 1606 | .dout ({ tid_lth_d[1:0] , |
| 1607 | valid_lth_e , ect_tid_lth_e[1:0] , rd_lth_e[4:0] , ect_rs1_addr_e[4:0] , ect_rs2_addr_e[4:0] , |
| 1608 | valid_lth_m , tid_lth_m[1:0] , rd_lth_m[4:0] , exu_cmov_true_m , |
| 1609 | valid_lth_b , tid_lth_b[1:0] , rd_lth_b[4:0] , |
| 1610 | ect_valid_lth_w , ect_tid_lth_w[1:0] , ect_rd_lth_w[4:0] , |
| 1611 | valid_lth_w_plus1 , tid_lth_w_plus1[1:0] , rd_lth_w_plus1[4:0], |
| 1612 | lsu_exu_tid_b[1:0] , lsu_exu_rd_b[4:0] , |
| 1613 | ect_tid_lth_w2[1:0] , ect_rd_lth_w2[4:0] , lsu_exu_ld_w , |
| 1614 | valid_lth_w2_plus1, tid_lth_w2_plus1[1:0] , rd_lth_w2_plus1[4:0]}), |
| 1615 | .siclk(siclk), |
| 1616 | .soclk(soclk)); |
| 1617 | |
| 1618 | |
| 1619 | assign ect_rs3_addr_e[4:0] = rd_lth_e[4:0]; |
| 1620 | |
| 1621 | |
| 1622 | // M, B, W, and W2 priority built into the PGPE mux in the datapath |
| 1623 | |
| 1624 | // ZN RS1 zero RS1 negative |
| 1625 | assign movcc_true_e = (dec_cmov_z00_e & ~edp_br_flag_e[0] & ~edp_br_flag_e[1]) | |
| 1626 | (dec_cmov_z01_e & ~edp_br_flag_e[0] & edp_br_flag_e[1]) | |
| 1627 | (dec_cmov_z10_e & edp_br_flag_e[0] & ~edp_br_flag_e[1]); |
| 1628 | |
| 1629 | assign valid_out_e = valid_lth_e & dec_valid_e & ~(mov_cond_e & ~movcc_true_e) & ~tas_tv_overflow_e & ~misalign_error_e; |
| 1630 | assign raw_valid_out_e = valid_lth_e & dec_valid_e & ~(mov_cond_e & ~movcc_true_e); |
| 1631 | |
| 1632 | assign rs1_e_cmp = raw_valid_out_e & (ect_tid_lth_e[1:0] == tid_lth_d[1:0]) & (rd_lth_e[4:0] == inst_rs1_d[4:0]); |
| 1633 | assign rs1_m_cmp = valid_lth_m & ( tid_lth_m[1:0] == tid_lth_d[1:0]) & (rd_lth_m[4:0] == inst_rs1_d[4:0]); |
| 1634 | assign rs1_b_cmp = valid_lth_b & ( tid_lth_b[1:0] == tid_lth_d[1:0]) & (rd_lth_b[4:0] == inst_rs1_d[4:0]); |
| 1635 | assign rs1_w_cmp = ect_valid_lth_w & (ect_tid_lth_w[1:0] == tid_lth_d[1:0]) & (ect_rd_lth_w[4:0] == inst_rs1_d[4:0]); |
| 1636 | assign rs1_w2_cmp = lsu_valid_w2 & (ect_tid_lth_w2[1:0] == tid_lth_d[1:0]) & (ect_rd_lth_w2[4:0] == inst_rs1_d[4:0]); |
| 1637 | assign rs1_w_plus1_cmp = valid_lth_w_plus1 & ( tid_lth_w_plus1[1:0] == tid_lth_d[1:0]) & (rd_lth_w_plus1[4:0] == inst_rs1_d[4:0]); |
| 1638 | assign rs1_w2_plus1_cmp = valid_lth_w2_plus1 & ( tid_lth_w2_plus1[1:0] == tid_lth_d[1:0]) & (rd_lth_w2_plus1[4:0] == inst_rs1_d[4:0]); |
| 1639 | |
| 1640 | assign rs2_e_cmp = raw_valid_out_e & (ect_tid_lth_e[1:0] == tid_lth_d[1:0]) & (rd_lth_e[4:0] == inst_rs2_d[4:0]); |
| 1641 | assign rs2_m_cmp = valid_lth_m & ( tid_lth_m[1:0] == tid_lth_d[1:0]) & (rd_lth_m[4:0] == inst_rs2_d[4:0]); |
| 1642 | assign rs2_b_cmp = valid_lth_b & ( tid_lth_b[1:0] == tid_lth_d[1:0]) & (rd_lth_b[4:0] == inst_rs2_d[4:0]); |
| 1643 | assign rs2_w_cmp = ect_valid_lth_w & (ect_tid_lth_w[1:0] == tid_lth_d[1:0]) & (ect_rd_lth_w[4:0] == inst_rs2_d[4:0]); |
| 1644 | assign rs2_w2_cmp = lsu_valid_w2 & (ect_tid_lth_w2[1:0] == tid_lth_d[1:0]) & (ect_rd_lth_w2[4:0] == inst_rs2_d[4:0]); |
| 1645 | assign rs2_w_plus1_cmp = valid_lth_w_plus1 & ( tid_lth_w_plus1[1:0] == tid_lth_d[1:0]) & (rd_lth_w_plus1[4:0] == inst_rs2_d[4:0]); |
| 1646 | assign rs2_w2_plus1_cmp = valid_lth_w2_plus1 & ( tid_lth_w2_plus1[1:0] == tid_lth_d[1:0]) & (rd_lth_w2_plus1[4:0] == inst_rs2_d[4:0]); |
| 1647 | |
| 1648 | assign rs3_e_cmp = raw_valid_out_e & (ect_tid_lth_e[1:0] == tid_lth_d[1:0]) & (rd_lth_e[4:0] == inst_rs3_d[4:0]); |
| 1649 | assign rs3_m_cmp = valid_lth_m & ( tid_lth_m[1:0] == tid_lth_d[1:0]) & (rd_lth_m[4:0] == inst_rs3_d[4:0]); |
| 1650 | assign rs3_b_cmp = valid_lth_b & ( tid_lth_b[1:0] == tid_lth_d[1:0]) & (rd_lth_b[4:0] == inst_rs3_d[4:0]); |
| 1651 | assign rs3_w_cmp = ect_valid_lth_w & (ect_tid_lth_w[1:0] == tid_lth_d[1:0]) & (ect_rd_lth_w[4:0] == inst_rs3_d[4:0]); |
| 1652 | assign rs3_w2_cmp = lsu_valid_w2 & (ect_tid_lth_w2[1:0] == tid_lth_d[1:0]) & (ect_rd_lth_w2[4:0] == inst_rs3_d[4:0]); |
| 1653 | assign rs3_w_plus1_cmp = valid_lth_w_plus1 & ( tid_lth_w_plus1[1:0] == tid_lth_d[1:0]) & (rd_lth_w_plus1[4:0] == inst_rs3_d[4:0]); |
| 1654 | assign rs3_w2_plus1_cmp = valid_lth_w2_plus1 & ( tid_lth_w2_plus1[1:0] == tid_lth_d[1:0]) & (rd_lth_w2_plus1[4:0] == inst_rs3_d[4:0]); |
| 1655 | |
| 1656 | |
| 1657 | assign rs1_l_cmp = lsu_exu_ld_b & |
| 1658 | (lsu_exu_tid_b[2:0] == {dec_thread_group,tid_lth_d[1:0]}) & |
| 1659 | (lsu_exu_rd_b[4:0] == inst_rs1_d[4:0] ) & |
| 1660 | ~(lsu_exu_rd_b[4:0] == 5'b00000 ); |
| 1661 | |
| 1662 | assign rs2_l_cmp = lsu_exu_ld_b & |
| 1663 | (lsu_exu_tid_b[2:0] == {dec_thread_group,tid_lth_d[1:0]}) & |
| 1664 | (lsu_exu_rd_b[4:0] == inst_rs2_d[4:0] ) & |
| 1665 | ~(lsu_exu_rd_b[4:0] == 5'b00000 ); |
| 1666 | |
| 1667 | assign rs3_l_cmp = lsu_exu_ld_b & |
| 1668 | (lsu_exu_tid_b[2:0] == {dec_thread_group,tid_lth_d[1:0]}) & |
| 1669 | (lsu_exu_rd_b[4:0] == inst_rs3_d[4:0] ) & |
| 1670 | ~(lsu_exu_rd_b[4:0] == 5'b00000 ); |
| 1671 | |
| 1672 | assign rs1_byp_early = rs1_m_cmp | rs1_b_cmp | rs1_w_cmp | rs1_w2_cmp | rs1_w_plus1_cmp | rs1_w2_plus1_cmp; |
| 1673 | assign rs2_byp_early = rs2_m_cmp | rs2_b_cmp | rs2_w_cmp | rs2_w2_cmp | rs2_w_plus1_cmp | rs2_w2_plus1_cmp; |
| 1674 | assign rs3_byp_early = rs3_m_cmp | rs3_b_cmp | rs3_w_cmp | rs3_w2_cmp | rs3_w_plus1_cmp | rs3_w2_plus1_cmp; |
| 1675 | |
| 1676 | |
| 1677 | |
| 1678 | //!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End : Bypass !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! |
| 1679 | |
| 1680 | |
| 1681 | |
| 1682 | |
| 1683 | //!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : Flags !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! |
| 1684 | |
| 1685 | |
| 1686 | // *** E Stage Flag generation *** |
| 1687 | |
| 1688 | assign lg_cc[7] = edp_logical_data_e_b63; // N |
| 1689 | assign lg_cc[6] = edp_lg_zdetect_e[1] & edp_lg_zdetect_e[0]; // Z : [63:0] == 0 |
| 1690 | assign lg_cc[5] = 1'b0; // V : always 0 |
| 1691 | assign lg_cc[4] = 1'b0; // C : always 0 |
| 1692 | |
| 1693 | assign lg_cc[3] = edp_logical_data_e_b31; // N |
| 1694 | assign lg_cc[2] = edp_lg_zdetect_e[0]; // Z : [31:0] == 0 |
| 1695 | assign lg_cc[1] = 1'b0; // V : always 0 |
| 1696 | assign lg_cc[0] = 1'b0; // C : always 0 |
| 1697 | |
| 1698 | |
| 1699 | assign as_cc[7] = ( ~as_subtract_e & edp_add_data_e_b63 ) | // N |
| 1700 | ( as_subtract_e & edp_sub_data_e_b63 ); |
| 1701 | assign as_cc[6] = ( ~as_subtract_e & ~edp_add_zdetect_e_[1] & ~edp_add_zdetect_e_[0]) | // Z : [63:0] == 0 |
| 1702 | ( as_subtract_e & ~edp_sub_zdetect_e_[1] & ~edp_sub_zdetect_e_[0]); |
| 1703 | assign as_cc[5] = ( ~as_subtract_e & ~exu_rs1_data_e[63] & ~exu_rs2_data_e[63] & edp_add_data_e_b63 ) | // V |
| 1704 | ( ~as_subtract_e & exu_rs1_data_e[63] & exu_rs2_data_e[63] & ~edp_add_data_e_b63 ) | |
| 1705 | ( as_subtract_e & ~exu_rs1_data_e[63] & exu_rs2_data_e[63] & edp_sub_data_e_b63 ) | |
| 1706 | ( as_subtract_e & exu_rs1_data_e[63] & ~exu_rs2_data_e[63] & ~edp_sub_data_e_b63 ); |
| 1707 | assign as_cc[4] = ( ~as_subtract_e & edp_add_cout64_e ) | // C |
| 1708 | ( as_subtract_e & ~edp_sub_cout64_e ); |
| 1709 | |
| 1710 | assign as_cc[3] = ( ~as_subtract_e & edp_add_data_e_b31 ) | // N |
| 1711 | ( as_subtract_e & edp_sub_data_e_b31 ); |
| 1712 | assign as_cc[2] = ( ~as_subtract_e & ~edp_add_zdetect_e_[0]) | // Z : [31:0] == 0 |
| 1713 | ( as_subtract_e & ~edp_sub_zdetect_e_[0]); |
| 1714 | assign as_cc[1] = ( ~as_subtract_e & ~exu_rs1_data_e[31] & ~exu_rs2_data_e[31] & edp_add_data_e_b31 ) | // V |
| 1715 | ( ~as_subtract_e & exu_rs1_data_e[31] & exu_rs2_data_e[31] & ~edp_add_data_e_b31 ) | |
| 1716 | ( as_subtract_e & ~exu_rs1_data_e[31] & exu_rs2_data_e[31] & edp_sub_data_e_b31 ) | |
| 1717 | ( as_subtract_e & exu_rs1_data_e[31] & ~exu_rs2_data_e[31] & ~edp_sub_data_e_b31 ) | |
| 1718 | ( tas_cc_e & ( exu_rs1_data_e[0] | exu_rs2_data_e[0]) ) | |
| 1719 | ( tas_cc_e & ( exu_rs1_data_e[1] | exu_rs2_data_e[1]) ); |
| 1720 | assign as_cc[0] = ( ~as_subtract_e & ( exu_rs1_data_e[31] & exu_rs2_data_e[31]) ) | // C |
| 1721 | ( ~as_subtract_e & ( exu_rs1_data_e[31] | exu_rs2_data_e[31]) & ~edp_add_data_e_b31 ) | |
| 1722 | ( as_subtract_e & (~exu_rs1_data_e[31] & exu_rs2_data_e[31]) ) | |
| 1723 | ( as_subtract_e & (~exu_rs1_data_e[31] | exu_rs2_data_e[31]) & edp_sub_data_e_b31 ); |
| 1724 | |
| 1725 | |
| 1726 | assign ccr_data_e[7:0] = ({8{as_cc_e }} & as_cc[7:0] ) | |
| 1727 | ({8{lg_cc_e }} & lg_cc[7:0] ); |
| 1728 | |
| 1729 | |
| 1730 | assign ccr_data_b[7:0] = ({8{~fgu_ccr_valid_b}} & ccr_data_lth_b[7:0] ) | |
| 1731 | ({8{ fgu_ccr_valid_b}} & {fgu_exu_xcc_fx5[1:0],2'b00,fgu_exu_icc_fx5[3:0]}); |
| 1732 | |
| 1733 | assign fgu_ccr_valid_b = fgu_exu_cc_vld_fx5 & fgu_exu_w_vld_fx5; |
| 1734 | |
| 1735 | assign ccr_valid_in_d = (as_cc_d | lg_cc_d); |
| 1736 | assign ccr_valid_in_e = ccr_valid_out_e; |
| 1737 | assign ccr_valid_in_m = ccr_valid_lth_m & ~dec_flush_m & ~exu_ecc_m & ~address_error_m; |
| 1738 | assign ccr_valid_in_b = (ccr_valid_lth_b & ~dec_flush_b & ~tlu_flush_exu_b & ~tof_b & ~misalign_b) | fgu_ccr_valid_b; |
| 1739 | |
| 1740 | |
| 1741 | |
| 1742 | assign wr_ccr_w_tid0 = ccr_valid_lth_w & (ect_tid_lth_w[1:0] == 2'b00); |
| 1743 | assign wr_ccr_w_tid1 = ccr_valid_lth_w & (ect_tid_lth_w[1:0] == 2'b01); |
| 1744 | assign wr_ccr_w_tid2 = ccr_valid_lth_w & (ect_tid_lth_w[1:0] == 2'b10); |
| 1745 | assign wr_ccr_w_tid3 = ccr_valid_lth_w & (ect_tid_lth_w[1:0] == 2'b11); |
| 1746 | |
| 1747 | assign wr_ccr_tlu0 = tlu_ccr_cwp_valid & (tlu_ccr_cwp_tid[1:0] == 2'b00); |
| 1748 | assign wr_ccr_tlu1 = tlu_ccr_cwp_valid & (tlu_ccr_cwp_tid[1:0] == 2'b01); |
| 1749 | assign wr_ccr_tlu2 = tlu_ccr_cwp_valid & (tlu_ccr_cwp_tid[1:0] == 2'b10); |
| 1750 | assign wr_ccr_tlu3 = tlu_ccr_cwp_valid & (tlu_ccr_cwp_tid[1:0] == 2'b11); |
| 1751 | |
| 1752 | assign wr_ccr_asi0 = rml_rng_wt_ccr_ctl & (rng_tid[1:0] == 2'b00); |
| 1753 | assign wr_ccr_asi1 = rml_rng_wt_ccr_ctl & (rng_tid[1:0] == 2'b01); |
| 1754 | assign wr_ccr_asi2 = rml_rng_wt_ccr_ctl & (rng_tid[1:0] == 2'b10); |
| 1755 | assign wr_ccr_asi3 = rml_rng_wt_ccr_ctl & (rng_tid[1:0] == 2'b11); |
| 1756 | |
| 1757 | |
| 1758 | assign arch_ccr_tid0_in[7:0] = ({8{ wr_ccr_w_tid0 }} & ccr_data_lth_w[7:0] ) | |
| 1759 | ({8{ wr_ccr_tlu0 }} & tlu_ccr[7:0] ) | |
| 1760 | ({8{ wr_ccr_asi0}} & edp_rng_in_ff[7:0] ) | |
| 1761 | ({8{~wr_ccr_w_tid0 & ~wr_ccr_tlu0 & ~wr_ccr_asi0}} & arch_ccr_tid0_lth[7:0]); |
| 1762 | |
| 1763 | |
| 1764 | assign arch_ccr_tid1_in[7:0] = ({8{ wr_ccr_w_tid1 }} & ccr_data_lth_w[7:0] ) | |
| 1765 | ({8{ wr_ccr_tlu1 }} & tlu_ccr[7:0] ) | |
| 1766 | ({8{ wr_ccr_asi1}} & edp_rng_in_ff[7:0] ) | |
| 1767 | ({8{~wr_ccr_w_tid1 & ~wr_ccr_tlu1 & ~wr_ccr_asi1}} & arch_ccr_tid1_lth[7:0]); |
| 1768 | |
| 1769 | |
| 1770 | assign arch_ccr_tid2_in[7:0] = ({8{ wr_ccr_w_tid2 }} & ccr_data_lth_w[7:0] ) | |
| 1771 | ({8{ wr_ccr_tlu2 }} & tlu_ccr[7:0] ) | |
| 1772 | ({8{ wr_ccr_asi2}} & edp_rng_in_ff[7:0] ) | |
| 1773 | ({8{~wr_ccr_w_tid2 & ~wr_ccr_tlu2 & ~wr_ccr_asi2}} & arch_ccr_tid2_lth[7:0]); |
| 1774 | |
| 1775 | |
| 1776 | assign arch_ccr_tid3_in[7:0] = ({8{ wr_ccr_w_tid3 }} & ccr_data_lth_w[7:0] ) | |
| 1777 | ({8{ wr_ccr_tlu3 }} & tlu_ccr[7:0] ) | |
| 1778 | ({8{ wr_ccr_asi3}} & edp_rng_in_ff[7:0] ) | |
| 1779 | ({8{~wr_ccr_w_tid3 & ~wr_ccr_tlu3 & ~wr_ccr_asi3}} & arch_ccr_tid3_lth[7:0]); |
| 1780 | |
| 1781 | |
| 1782 | exu_ect_ctl_msff_ctl_macro__width_28 i_ccr_pipe_lth ( |
| 1783 | .scan_in(i_ccr_pipe_lth_scanin), |
| 1784 | .scan_out(i_ccr_pipe_lth_scanout), |
| 1785 | .l1clk( l1clk_pm1 ), |
| 1786 | .din ({ ccr_valid_in_d , |
| 1787 | ccr_valid_in_e , ccr_data_e[7:0] , |
| 1788 | ccr_valid_in_m , ccr_data_lth_m[7:0] , |
| 1789 | ccr_valid_in_b , ccr_data_b[7:0] }), |
| 1790 | .dout ({ ccr_valid_lth_e , |
| 1791 | ccr_valid_lth_m , ccr_data_lth_m[7:0] , |
| 1792 | ccr_valid_lth_b , ccr_data_lth_b[7:0] , |
| 1793 | ccr_valid_lth_w , ccr_data_lth_w[7:0] }), |
| 1794 | .siclk(siclk), |
| 1795 | .soclk(soclk)); |
| 1796 | |
| 1797 | |
| 1798 | exu_ect_ctl_msff_ctl_macro__width_32 i_ccr_arch_lth ( // FS:wmr_protect |
| 1799 | .scan_in(i_ccr_arch_lth_wmr_scanin), |
| 1800 | .scan_out(i_ccr_arch_lth_wmr_scanout), |
| 1801 | .siclk(spc_aclk_wmr), |
| 1802 | .l1clk( l1clk_pm1 ), |
| 1803 | .din ({arch_ccr_tid0_in[7:0] , arch_ccr_tid1_in[7:0] , arch_ccr_tid2_in[7:0] , arch_ccr_tid3_in[7:0] }), |
| 1804 | .dout ({arch_ccr_tid0_lth[7:0], arch_ccr_tid1_lth[7:0], arch_ccr_tid2_lth[7:0], arch_ccr_tid3_lth[7:0] }), |
| 1805 | .soclk(soclk)); |
| 1806 | |
| 1807 | |
| 1808 | assign ccr_valid_out_e = ccr_valid_lth_e & dec_valid_e & ~tas_tv_overflow_e; |
| 1809 | |
| 1810 | assign ccr_e_cmp = ccr_valid_lth_e & (tid_lth_d[1:0] == ect_tid_lth_e[1:0]); |
| 1811 | assign ccr_m_cmp = ccr_valid_lth_m & (tid_lth_d[1:0] == tid_lth_m[1:0]); |
| 1812 | assign ccr_b_cmp = ccr_valid_lth_b & (tid_lth_d[1:0] == tid_lth_b[1:0]); |
| 1813 | assign ccr_w_cmp = ccr_valid_lth_w & (tid_lth_d[1:0] == ect_tid_lth_w[1:0]); |
| 1814 | |
| 1815 | assign ccr_sel_e = ccr_e_cmp; |
| 1816 | assign ccr_sel_m = ccr_m_cmp; |
| 1817 | assign ccr_sel_b = ~ccr_m_cmp & ccr_b_cmp; |
| 1818 | assign ccr_sel_w = ~ccr_m_cmp & ~ccr_b_cmp & ccr_w_cmp; |
| 1819 | assign ccr_sel_a0 = ~ccr_m_cmp & ~ccr_b_cmp & ~ccr_w_cmp & (tid_lth_d[1:0] == 2'b00); |
| 1820 | assign ccr_sel_a1 = ~ccr_m_cmp & ~ccr_b_cmp & ~ccr_w_cmp & (tid_lth_d[1:0] == 2'b01); |
| 1821 | assign ccr_sel_a2 = ~ccr_m_cmp & ~ccr_b_cmp & ~ccr_w_cmp & (tid_lth_d[1:0] == 2'b10); |
| 1822 | assign ccr_sel_a3 = ~ccr_m_cmp & ~ccr_b_cmp & ~ccr_w_cmp & (tid_lth_d[1:0] == 2'b11); |
| 1823 | |
| 1824 | assign exu_ccr_byp_data0[7:0] = ({8{ ccr_sel_m }} & ccr_data_lth_m[7:0] ) | |
| 1825 | ({8{ ccr_sel_b }} & ccr_data_lth_b[7:0] ) | |
| 1826 | ({8{ ccr_sel_w }} & ccr_data_lth_w[7:0] ) | |
| 1827 | ({8{ ccr_sel_a0}} & arch_ccr_tid0_lth[7:0]) | |
| 1828 | ({8{ ccr_sel_a1}} & arch_ccr_tid1_lth[7:0]) | |
| 1829 | ({8{ ccr_sel_a2}} & arch_ccr_tid2_lth[7:0]) | |
| 1830 | ({8{ ccr_sel_a3}} & arch_ccr_tid3_lth[7:0]); |
| 1831 | |
| 1832 | assign exu_ccr_byp_data1[7:0] = ({8{ ccr_sel_e }} & ccr_data_e[7:0] ) | |
| 1833 | ({8{~ccr_sel_e & ccr_sel_m }} & ccr_data_lth_m[7:0] ) | |
| 1834 | ({8{~ccr_sel_e & ccr_sel_b }} & ccr_data_lth_b[7:0] ) | |
| 1835 | ({8{~ccr_sel_e & ccr_sel_w }} & ccr_data_lth_w[7:0] ) | |
| 1836 | ({8{~ccr_sel_e & ccr_sel_a0}} & arch_ccr_tid0_lth[7:0]) | |
| 1837 | ({8{~ccr_sel_e & ccr_sel_a1}} & arch_ccr_tid1_lth[7:0]) | |
| 1838 | ({8{~ccr_sel_e & ccr_sel_a2}} & arch_ccr_tid2_lth[7:0]) | |
| 1839 | ({8{~ccr_sel_e & ccr_sel_a3}} & arch_ccr_tid3_lth[7:0]); |
| 1840 | |
| 1841 | assign ccr_byp_data_b0 = ( {~dec_valid_e} & exu_ccr_byp_data0[0]) | |
| 1842 | ( { dec_valid_e} & exu_ccr_byp_data1[0]); |
| 1843 | |
| 1844 | assign ccr_byp_data_b1 = ( {~dec_valid_e} & exu_ccr_byp_data0[1]) | |
| 1845 | ( { dec_valid_e} & exu_ccr_byp_data1[1]); |
| 1846 | |
| 1847 | assign ccr_byp_data_b3 = ( {~dec_valid_e} & exu_ccr_byp_data0[3]) | |
| 1848 | ( { dec_valid_e} & exu_ccr_byp_data1[3]); |
| 1849 | |
| 1850 | |
| 1851 | |
| 1852 | assign exu_ccr0[7:0] = arch_ccr_tid0_lth[7:0]; |
| 1853 | assign exu_ccr1[7:0] = arch_ccr_tid1_lth[7:0]; |
| 1854 | assign exu_ccr2[7:0] = arch_ccr_tid2_lth[7:0]; |
| 1855 | assign exu_ccr3[7:0] = arch_ccr_tid3_lth[7:0]; |
| 1856 | |
| 1857 | assign ect_rng_ccr_data[7:0] = ({8{rng_tid[1:0] == 2'b00}} & arch_ccr_tid0_lth[7:0]) | |
| 1858 | ({8{rng_tid[1:0] == 2'b01}} & arch_ccr_tid1_lth[7:0]) | |
| 1859 | ({8{rng_tid[1:0] == 2'b10}} & arch_ccr_tid2_lth[7:0]) | |
| 1860 | ({8{rng_tid[1:0] == 2'b11}} & arch_ccr_tid3_lth[7:0]); |
| 1861 | |
| 1862 | |
| 1863 | assign trap_taken_e = dec_valid_e & tcc_e & tcc_taken_e; |
| 1864 | |
| 1865 | assign exu_tcc_m = trap_taken_m_lth; |
| 1866 | |
| 1867 | |
| 1868 | // pg. 199 Multiply Step -> CCR.icc.n XOR CCR.icc.v |
| 1869 | |
| 1870 | assign ms_icc_in = ccr_byp_data_b3 ^ ccr_byp_data_b1; |
| 1871 | |
| 1872 | assign tas_tv_overflow_e = (dec_valid_e & tas_tv_e & as_cc[1]); // Tagged Add TV with overflow |
| 1873 | assign tas_tv_overflow_m_in = tas_tv_overflow_m_lth & ~dec_flush_m; |
| 1874 | assign exu_tof_m = tas_tv_overflow_m_lth; |
| 1875 | |
| 1876 | |
| 1877 | assign normal_va_hole_m_ = edp_address_m[63:48] == {16{edp_address_m[47]}}; |
| 1878 | assign special_ls_va_hole_m_ = edp_rd_ff_m[63:48] == {16{edp_rd_ff_m[47]}}; |
| 1879 | assign special_br_va_hole_m_ = ((edp_address_m[63:48] == 16'h0001) & ~edp_address_m[47]) | |
| 1880 | ((edp_address_m[63:48] == 16'h0000) & edp_address_m[47]); |
| 1881 | |
| 1882 | assign va_hole_m = ( ls_special_sel_m & ~special_ls_va_hole_m_) | |
| 1883 | ( br_special_sel_m & ~special_br_va_hole_m_) | |
| 1884 | (~ls_special_sel_m & ~br_special_sel_m & ~normal_va_hole_m_ ); |
| 1885 | |
| 1886 | assign exu_lsu_va_error_m = (va_hole_m & address_m & ~pstate_am_m ); |
| 1887 | assign exu_oor_va_m = (va_hole_m & address_m ); |
| 1888 | assign address_error_m = (va_hole_m & address_m & ~pstate_am_m & ~itlb_bypass_m); |
| 1889 | |
| 1890 | |
| 1891 | assign misalign_error_e = misalign_e & dec_valid_e & (edp_add_data_e_b1 | edp_add_data_e_b0); |
| 1892 | |
| 1893 | assign misalign_error_m_in = ect_misaligned_error_m & ~dec_flush_m; |
| 1894 | assign exu_misalign_m = ect_misaligned_error_m; |
| 1895 | |
| 1896 | assign pstate_am_d = (tlu_pstate_am[0] & (tid_lth_d[1:0] == 2'b00)) | |
| 1897 | (tlu_pstate_am[1] & (tid_lth_d[1:0] == 2'b01)) | |
| 1898 | (tlu_pstate_am[2] & (tid_lth_d[1:0] == 2'b10)) | |
| 1899 | (tlu_pstate_am[3] & (tid_lth_d[1:0] == 2'b11)); |
| 1900 | |
| 1901 | |
| 1902 | exu_ect_ctl_msff_ctl_macro__width_9 i_tlu_lth ( |
| 1903 | .scan_in(i_tlu_lth_scanin), |
| 1904 | .scan_out(i_tlu_lth_scanout), |
| 1905 | .l1clk( l1clk_pm2 ), |
| 1906 | .din ({trap_taken_e , |
| 1907 | ms_icc_in , |
| 1908 | tas_tv_overflow_e , |
| 1909 | tas_tv_overflow_m_in , |
| 1910 | misalign_error_e , |
| 1911 | misalign_error_m_in , |
| 1912 | pstate_am_d , |
| 1913 | ect_pstate_am_e , |
| 1914 | tlu_itlb_bypass_e }), |
| 1915 | .dout ({trap_taken_m_lth , |
| 1916 | exu_ms_icc_e , |
| 1917 | tas_tv_overflow_m_lth , |
| 1918 | tof_b , |
| 1919 | ect_misaligned_error_m , |
| 1920 | misalign_b , |
| 1921 | ect_pstate_am_e , |
| 1922 | pstate_am_m , |
| 1923 | itlb_bypass_m }), |
| 1924 | .siclk(siclk), |
| 1925 | .soclk(soclk)); |
| 1926 | |
| 1927 | |
| 1928 | |
| 1929 | //!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End : Flags !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! |
| 1930 | |
| 1931 | |
| 1932 | |
| 1933 | |
| 1934 | //!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : Y Register !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! |
| 1935 | |
| 1936 | assign yreg_mwr_valid_em3_in = dec_valid_e & (exu_mdp_mux_sel_e[0] | exu_mdp_mux_sel_e[1]); // UMUL(cc), SMUL(cc) |
| 1937 | assign yreg_mwr_valid_em2_in = yreg_mwr_valid_em2_lth & ~dec_flush_m & ~exu_ecc_m; |
| 1938 | assign yreg_mwr_valid_em1_in = yreg_mwr_valid_em1_lth & ~dec_flush_b & ~tlu_flush_exu_b; |
| 1939 | assign yreg_mwr_valid_e_in = yreg_mwr_valid_e_lth; |
| 1940 | assign yreg_mwr_valid_m_in = yreg_mwr_valid_m_lth; |
| 1941 | |
| 1942 | assign yreg_swr_valid_e_in = dec_valid_e & exu_mdp_mux_sel_e[3]; // MULScc |
| 1943 | assign yreg_swr_valid_m_in = yreg_swr_valid_m_lth & ~dec_flush_m & ~exu_ecc_m; |
| 1944 | |
| 1945 | assign yreg_wr_valid_b_in = yreg_mwr_valid_b_lth | |
| 1946 | (yreg_swr_valid_b_lth & ~dec_flush_b & ~tlu_flush_exu_b); |
| 1947 | |
| 1948 | |
| 1949 | exu_ect_ctl_msff_ctl_macro__width_5 i_yreg_mpipe_lth ( |
| 1950 | .scan_in(i_yreg_mpipe_lth_scanin), |
| 1951 | .scan_out(i_yreg_mpipe_lth_scanout), |
| 1952 | .l1clk( l1clk_pm1 ), |
| 1953 | .din ({yreg_mwr_valid_em3_in , yreg_mwr_valid_em2_in , yreg_mwr_valid_em1_in , yreg_mwr_valid_e_in , yreg_mwr_valid_m_in }), |
| 1954 | .dout ({yreg_mwr_valid_em2_lth , yreg_mwr_valid_em1_lth , yreg_mwr_valid_e_lth , yreg_mwr_valid_m_lth , yreg_mwr_valid_b_lth}), |
| 1955 | .siclk(siclk), |
| 1956 | .soclk(soclk)); |
| 1957 | |
| 1958 | exu_ect_ctl_msff_ctl_macro__width_5 i_yreg_spipe_lth ( |
| 1959 | .scan_in(i_yreg_spipe_lth_scanin), |
| 1960 | .scan_out(i_yreg_spipe_lth_scanout), |
| 1961 | .l1clk( l1clk_pm1 ), |
| 1962 | .din ({yreg_swr_valid_e_in , yreg_swr_valid_m_in , yreg_wr_valid_b_in , edp_rng_in_ff_b57,edp_rng_in_ff_b56} ), |
| 1963 | .dout ({yreg_swr_valid_m_lth , yreg_swr_valid_b_lth , ect_yreg_wr_w , rng_tid[1:0]} ), |
| 1964 | .siclk(siclk), |
| 1965 | .soclk(soclk)); |
| 1966 | |
| 1967 | |
| 1968 | //!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End : Y Register !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! |
| 1969 | |
| 1970 | |
| 1971 | |
| 1972 | //!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : Edge !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! |
| 1973 | |
| 1974 | // Edge Mask Specification |
| 1975 | // |
| 1976 | // Big-endian Little-endian |
| 1977 | // |
| 1978 | // Edge Size A2..A0 Left Edge Right Edge Left Edge Right Edge |
| 1979 | // --------- ------ --------- ---------- --------- ---------- |
| 1980 | // 8 000 1111_1111 1000_0000 1111_1111 0000_0001 |
| 1981 | // 8 001 0111_1111 1100_0000 1111_1110 0000_0011 |
| 1982 | // 8 010 0011_1111 1110_0000 1111_1100 0000_0111 |
| 1983 | // 8 011 0001_1111 1111_0000 1111_1000 0000_1111 |
| 1984 | // 8 100 0000_1111 1111_1000 1111_0000 0001_1111 |
| 1985 | // 8 101 0000_0111 1111_1100 1110_0000 0011_1111 |
| 1986 | // 8 110 0000_0011 1111_1110 1100_0000 0111_1111 |
| 1987 | // 8 111 0000_0001 1111_1111 1000_0000 1111_1111 |
| 1988 | // |
| 1989 | // 16 00x 1111 1000 1111 0001 |
| 1990 | // 16 01x 0111 1100 1110 0011 |
| 1991 | // 16 10x 0011 1110 1100 0111 |
| 1992 | // 16 11x 0001 1111 1000 1111 |
| 1993 | // |
| 1994 | // 32 0xx 11 10 11 01 |
| 1995 | // 32 1xx 01 11 10 11 |
| 1996 | |
| 1997 | |
| 1998 | |
| 1999 | // Algorithm |
| 2000 | // |
| 2001 | // 1. The left edge is computed from the 3 least significant bits of RS1 and |
| 2002 | // the right edge is computed from the 3 least significant bits of RS2. |
| 2003 | // |
| 2004 | // 2. If 32-bit address masking is disabled (PSTATE.AM == 0, 64-bit addressing) and |
| 2005 | // the (RS1[63:3] == RS2[63:3]), then RD = right edge mask ANDed with the left edge mask. |
| 2006 | // |
| 2007 | // OR |
| 2008 | // |
| 2009 | // If 32-bit address masking is enabled (PSTATE.AM == 1, 32-bit addressing) and |
| 2010 | // the (RS1[31:3] == RS2[31:3]), then RD = right edge mask ANDed with the left edge mask. |
| 2011 | // |
| 2012 | // 3. Otherwise, RD = left edge mask. |
| 2013 | |
| 2014 | |
| 2015 | // Format : |
| 2016 | // |
| 2017 | // 31:30 29:25 24:19 18:14 13:05 04:00 |
| 2018 | // ----- ----- ------ ----- ----- ----- |
| 2019 | // 10 rd 110110 rs1 opf rs2 |
| 2020 | // |
| 2021 | // |
| 2022 | // OPCODE opf comment |
| 2023 | // -------- ----------- ---------------------------- |
| 2024 | // edge8 0 0000 0000 |
| 2025 | // edge8N 0 0000 0001 no icc,xcc update; |
| 2026 | // edge8L 0 0000 0010 Little-Endian |
| 2027 | // edge8LN 0 0000 0011 no icc,xcc update; Little-Endian |
| 2028 | // edge16 0 0000 0100 |
| 2029 | // edge16N 0 0000 0101 no icc,xcc update; |
| 2030 | // edge16L 0 0000 0110 Little-Endian |
| 2031 | // edge16LN 0 0000 0111 no icc,xcc update; Little-Endian |
| 2032 | // edge32 0 0000 1000 |
| 2033 | // edge32N 0 0000 1001 no icc,xcc update; |
| 2034 | // edge32L 0 0000 1010 Little-Endian |
| 2035 | // edge32LN 0 0000 1011 no icc,xcc update; Little-Endian |
| 2036 | |
| 2037 | |
| 2038 | |
| 2039 | // E0: XOR rs1 rs2 for eq det. Also take pstate_am into account |
| 2040 | // assign zdet_in_e[63:32] = {32{~ect_pstate_am_e}} & (exu_rs1_data_e[63:32] ^ exu_rs2_data_e[63:32]); |
| 2041 | // assign zdet_in_e[31:3] = exu_rs1_data_e[31:3] ^ exu_rs2_data_e[31:3]; |
| 2042 | |
| 2043 | // assign neq_zdet_e = | zdet_in_e[63:3]; |
| 2044 | // assign neq_zdet_e = ~(( edp_rs1_x_rs2_cmp_e[1] & edp_rs1_x_rs2_cmp_e[0]) | |
| 2045 | // ( ect_pstate_am_e & edp_rs1_x_rs2_cmp_e[0])); |
| 2046 | |
| 2047 | |
| 2048 | // *** Generate left mask *** |
| 2049 | // EDGE8 EDGE16 EDGE32 |
| 2050 | assign lmask_e[7] = edge08_e & ~exu_rs1_data_e[2] & ~exu_rs1_data_e[1] & ~exu_rs1_data_e[0] ; // 000 |
| 2051 | |
| 2052 | assign lmask_e[6] = edge08_e & ~exu_rs1_data_e[2] & ~exu_rs1_data_e[1] ; // 000 001 |
| 2053 | |
| 2054 | assign lmask_e[5] = (edge08_e & ~exu_rs1_data_e[2] & ~exu_rs1_data_e[1] ) | // 000 001 |
| 2055 | (edge08_e & ~exu_rs1_data_e[2] & ~exu_rs1_data_e[0]); // 010 |
| 2056 | |
| 2057 | assign lmask_e[4] = edge08_e & ~exu_rs1_data_e[2] ; // 000 001 010 011 |
| 2058 | |
| 2059 | assign lmask_e[3] = (edge08_e & ~exu_rs1_data_e[2] ) | // 000 001 010 011 |
| 2060 | (edge08_e & ~exu_rs1_data_e[1] & ~exu_rs1_data_e[0]) | // 100 |
| 2061 | (edge16_e & ~exu_rs1_data_e[2] & ~exu_rs1_data_e[1] ); // 00x |
| 2062 | |
| 2063 | assign lmask_e[2] = (edge08_e & ~exu_rs1_data_e[2] ) | // 000 001 010 011 |
| 2064 | (edge08_e & ~exu_rs1_data_e[1] ) | // 100 101 |
| 2065 | (edge16_e & ~exu_rs1_data_e[2] ); // 00x 01x |
| 2066 | |
| 2067 | assign lmask_e[1] = (edge08_e & ~exu_rs1_data_e[2] ) | // 000 001 010 011 |
| 2068 | (edge08_e & ~exu_rs1_data_e[1] ) | // 100 101 |
| 2069 | (edge08_e & ~exu_rs1_data_e[0]) | // 110 |
| 2070 | (edge16_e & ~exu_rs1_data_e[2] ) | // 00x 01x |
| 2071 | (edge16_e & ~exu_rs1_data_e[1] ) | // 10x |
| 2072 | (edge32_e & ~exu_rs1_data_e[2] ); // 0xx |
| 2073 | |
| 2074 | assign lmask_e[0] = 1'b1; |
| 2075 | |
| 2076 | |
| 2077 | |
| 2078 | // *** Generate right mask *** |
| 2079 | // EDGE8 EDGE16 EDGE32 |
| 2080 | assign rmask_e[7] = 1'b1; |
| 2081 | |
| 2082 | assign rmask_e[6] = (edge08_e & exu_rs2_data_e[2] ) | // 100 101 110 111 |
| 2083 | (edge08_e & exu_rs2_data_e[1] ) | // 010 011 |
| 2084 | (edge08_e & exu_rs2_data_e[0]); // 001 |
| 2085 | |
| 2086 | assign rmask_e[5] = (edge08_e & exu_rs2_data_e[2] ) | // 100 101 110 111 |
| 2087 | (edge08_e & exu_rs2_data_e[1] ); // 010 011 |
| 2088 | |
| 2089 | assign rmask_e[4] = (edge08_e & exu_rs2_data_e[2] ) | // 100 101 110 111 |
| 2090 | (edge08_e & exu_rs2_data_e[1] & exu_rs2_data_e[0]); // 011 |
| 2091 | |
| 2092 | assign rmask_e[3] = (edge08_e & exu_rs2_data_e[2] ) | // 100 101 110 111 |
| 2093 | edge16_e ; // 00x 01x 10x 11x |
| 2094 | |
| 2095 | assign rmask_e[2] = (edge08_e & exu_rs2_data_e[2] & exu_rs2_data_e[1] ) | // 110 111 |
| 2096 | (edge08_e & exu_rs2_data_e[2] & exu_rs2_data_e[0]) | // 101 |
| 2097 | (edge16_e & exu_rs2_data_e[2] ) | // 10x 11x |
| 2098 | (edge16_e & exu_rs2_data_e[1] ); // 01x |
| 2099 | |
| 2100 | assign rmask_e[1] = (edge08_e & exu_rs2_data_e[2] & exu_rs2_data_e[1] ) | // 110 111 |
| 2101 | (edge16_e & exu_rs2_data_e[2] ) | // 10x 11x |
| 2102 | edge32_e ; // 0xx 1xx |
| 2103 | |
| 2104 | assign rmask_e[0] = (edge08_e & exu_rs2_data_e[2] & exu_rs2_data_e[1] & exu_rs2_data_e[0]) | // 111 |
| 2105 | (edge16_e & exu_rs2_data_e[2] & exu_rs2_data_e[1] ) | // 11x |
| 2106 | (edge32_e & exu_rs2_data_e[2] ); // 1xx |
| 2107 | |
| 2108 | |
| 2109 | |
| 2110 | assign lrmask_e[7:0] = lmask_e[7:0] & rmask_e[7:0]; |
| 2111 | |
| 2112 | assign lmask_le8[7:0] = { lmask_e[0], lmask_e[1], lmask_e[2], lmask_e[3], lmask_e[4], lmask_e[5], lmask_e[6], lmask_e[7]}; |
| 2113 | assign lmask_le16[7:0] = { 1'b0 , 1'b0 , 1'b0 , 1'b0 , lmask_e[0], lmask_e[1], lmask_e[2], lmask_e[3]}; |
| 2114 | assign lmask_le32[7:0] = { 1'b0 , 1'b0 , 1'b0 , 1'b0 , 1'b0 , 1'b0 , lmask_e[0], lmask_e[1]}; |
| 2115 | |
| 2116 | assign lrmask_le8[7:0] = {lrmask_e[0], lrmask_e[1], lrmask_e[2], lrmask_e[3], lrmask_e[4], lrmask_e[5], lrmask_e[6], lrmask_e[7]}; |
| 2117 | assign lrmask_le16[7:0] = { 1'b0 , 1'b0 , 1'b0 , 1'b0 , lrmask_e[0], lrmask_e[1], lrmask_e[2], lrmask_e[3]}; |
| 2118 | assign lrmask_le32[7:0] = { 1'b0 , 1'b0 , 1'b0 , 1'b0 , 1'b0 , 1'b0 , lrmask_e[0], lrmask_e[1]}; |
| 2119 | |
| 2120 | |
| 2121 | assign ect_edge_lmask_e[7:0] = ({8{~edgele_e }} & lmask_e[7:0] ) | |
| 2122 | ({8{ edgele_e & edge08_e}} & lmask_le8[7:0] ) | |
| 2123 | ({8{ edgele_e & edge16_e}} & lmask_le16[7:0] ) | |
| 2124 | ({8{ edgele_e & edge32_e}} & lmask_le32[7:0] ); |
| 2125 | |
| 2126 | assign ect_edge_lrmask_e[7:0] = ({8{~edgele_e }} & lrmask_e[7:0] ) | |
| 2127 | ({8{ edgele_e & edge08_e}} & lrmask_le8[7:0] ) | |
| 2128 | ({8{ edgele_e & edge16_e}} & lrmask_le16[7:0]) | |
| 2129 | ({8{ edgele_e & edge32_e}} & lrmask_le32[7:0]); |
| 2130 | |
| 2131 | |
| 2132 | // assign ect_edge_res_e[7:0] = ({8{ neq_zdet_e}} & lmask_endian_e[7:0] ) | |
| 2133 | // ({8{~neq_zdet_e}} & lrmask_endian_e[7:0]); |
| 2134 | |
| 2135 | |
| 2136 | //!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End : Edge !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! |
| 2137 | |
| 2138 | |
| 2139 | //!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : DEC_CCR_CTL !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! |
| 2140 | |
| 2141 | // Description: Condition code resolution logic |
| 2142 | // |
| 2143 | |
| 2144 | |
| 2145 | //------------------ |
| 2146 | // CC Logic for BCC |
| 2147 | //------------------ |
| 2148 | // Choose appropriate CCs |
| 2149 | // |
| 2150 | // cctype is 3 bits |
| 2151 | // 10X icc |
| 2152 | // 11X xcc |
| 2153 | // 000 fcc0 |
| 2154 | // 001 fcc1 |
| 2155 | // 010 fcc2 |
| 2156 | // 011 fcc3 |
| 2157 | |
| 2158 | assign cctype_d[2:0] = ({3{imov_d}} & {i[18], i[12:11]} ) | |
| 2159 | ({3{fmov_d}} & {i[13] | tcc_d, i[12:11]}) | |
| 2160 | ({3{bpcc_d}} & {~fp_d, i[21:20]} ) | |
| 2161 | ({3{bcc_d}} & {~fp_d, 2'b00} ); |
| 2162 | |
| 2163 | assign brcond_d[3:0] = ({4{movcc_d}} & i[17:14] ) | |
| 2164 | ({4{movr_d}} & {1'b0,i[12:10]}) | |
| 2165 | ({4{br_or_tcc_d}} & i[28:25] ); |
| 2166 | |
| 2167 | |
| 2168 | // cctype is 3 bits |
| 2169 | // 10X icc |
| 2170 | // 11X xcc |
| 2171 | // 000 fcc0 |
| 2172 | // 001 fcc1 |
| 2173 | // 010 fcc2 |
| 2174 | // 011 fcc3 |
| 2175 | |
| 2176 | |
| 2177 | |
| 2178 | exu_ect_ctl_msff_ctl_macro__width_6 fgu_tid_ff ( |
| 2179 | .scan_in(fgu_tid_ff_scanin), |
| 2180 | .scan_out(fgu_tid_ff_scanout), |
| 2181 | .l1clk(l1clk), |
| 2182 | .din ({fgu_cmp_fcc_tid_fx2[2:0] , lsu_fgu_fld_tid_b[2:0]}), |
| 2183 | .dout ({fgu_cmp_fcc_tid_fx3[2:0] , fgu_fld_fcc_tid_fx3[2:0]}), |
| 2184 | .siclk(siclk), |
| 2185 | .soclk(soclk) |
| 2186 | ); |
| 2187 | |
| 2188 | |
| 2189 | |
| 2190 | // fcc data |
| 2191 | |
| 2192 | // modeled this after N1, it assumes the data is available 1 cycle earlier than POR |
| 2193 | |
| 2194 | assign fcc_cw_valid[3:0] = fgu_cmp_fcc_vld_fx3[3:0]; |
| 2195 | |
| 2196 | assign sel_ct0 = (fgu_cmp_fcc_tid_fx3[2:0] == {dec_thread_group,2'b00}); |
| 2197 | assign sel_ct1 = (fgu_cmp_fcc_tid_fx3[2:0] == {dec_thread_group,2'b01}); |
| 2198 | assign sel_ct2 = (fgu_cmp_fcc_tid_fx3[2:0] == {dec_thread_group,2'b10}); |
| 2199 | assign sel_ct3 = (fgu_cmp_fcc_tid_fx3[2:0] == {dec_thread_group,2'b11}); |
| 2200 | |
| 2201 | assign fcc_cw_t0[3:0] = {4{sel_ct0}} & fcc_cw_valid[3:0]; |
| 2202 | assign fcc_cw_t1[3:0] = {4{sel_ct1}} & fcc_cw_valid[3:0]; |
| 2203 | assign fcc_cw_t2[3:0] = {4{sel_ct2}} & fcc_cw_valid[3:0]; |
| 2204 | assign fcc_cw_t3[3:0] = {4{sel_ct3}} & fcc_cw_valid[3:0]; |
| 2205 | |
| 2206 | assign fcc_lw_valid[1:0] = {2{lsu_fgu_fld_vld_w}} & fgu_fld_fcc_vld_fx3[1:0]; |
| 2207 | |
| 2208 | assign sel_lt0 = (fgu_fld_fcc_tid_fx3[2:0] == {dec_thread_group,2'b00}); |
| 2209 | assign sel_lt1 = (fgu_fld_fcc_tid_fx3[2:0] == {dec_thread_group,2'b01}); |
| 2210 | assign sel_lt2 = (fgu_fld_fcc_tid_fx3[2:0] == {dec_thread_group,2'b10}); |
| 2211 | assign sel_lt3 = (fgu_fld_fcc_tid_fx3[2:0] == {dec_thread_group,2'b11}); |
| 2212 | |
| 2213 | assign fcc_lw_t0[1:0] = {2{sel_lt0}} & fcc_lw_valid[1:0]; |
| 2214 | assign fcc_lw_t1[1:0] = {2{sel_lt1}} & fcc_lw_valid[1:0]; |
| 2215 | assign fcc_lw_t2[1:0] = {2{sel_lt2}} & fcc_lw_valid[1:0]; |
| 2216 | assign fcc_lw_t3[1:0] = {2{sel_lt3}} & fcc_lw_valid[1:0]; |
| 2217 | |
| 2218 | |
| 2219 | assign t0_data_in[7:0] = { |
| 2220 | ({2{fcc_lw_t0[1]}} & fgu_fld_fcc_fx3[7:6]) | ({2{fcc_cw_t0[3]}} & fgu_cmp_fcc_fx3[1:0]), |
| 2221 | ({2{fcc_lw_t0[1]}} & fgu_fld_fcc_fx3[5:4]) | ({2{fcc_cw_t0[2]}} & fgu_cmp_fcc_fx3[1:0]), |
| 2222 | ({2{fcc_lw_t0[1]}} & fgu_fld_fcc_fx3[3:2]) | ({2{fcc_cw_t0[1]}} & fgu_cmp_fcc_fx3[1:0]), |
| 2223 | ({2{fcc_lw_t0[0]}} & fgu_fld_fcc_fx3[1:0]) | ({2{fcc_cw_t0[0]}} & fgu_cmp_fcc_fx3[1:0]) |
| 2224 | }; |
| 2225 | assign t0_hold_in[7:0] = { |
| 2226 | {2{~fcc_lw_t0[1] & ~fcc_cw_t0[3]}} & fcc_t0_d[7:6], |
| 2227 | {2{~fcc_lw_t0[1] & ~fcc_cw_t0[2]}} & fcc_t0_d[5:4], |
| 2228 | {2{~fcc_lw_t0[1] & ~fcc_cw_t0[1]}} & fcc_t0_d[3:2], |
| 2229 | {2{~fcc_lw_t0[0] & ~fcc_cw_t0[0]}} & fcc_t0_d[1:0] |
| 2230 | }; |
| 2231 | |
| 2232 | assign fcc_nxt_t0[7:0] = t0_data_in[7:0] | t0_hold_in[7:0]; |
| 2233 | |
| 2234 | exu_ect_ctl_msff_ctl_macro__width_8 fcc_t0_ff ( // FS:wmr_protect |
| 2235 | .scan_in(fcc_t0_ff_wmr_scanin), |
| 2236 | .scan_out(fcc_t0_ff_wmr_scanout), |
| 2237 | .siclk(spc_aclk_wmr), |
| 2238 | .l1clk(l1clk_pm1), |
| 2239 | .din (fcc_nxt_t0[7:0]), |
| 2240 | .dout (fcc_t0_d[7:0]), |
| 2241 | .soclk(soclk) |
| 2242 | ); |
| 2243 | |
| 2244 | assign t1_data_in[7:0] = { |
| 2245 | ({2{fcc_lw_t1[1]}} & fgu_fld_fcc_fx3[7:6]) | ({2{fcc_cw_t1[3]}} & fgu_cmp_fcc_fx3[1:0]), |
| 2246 | ({2{fcc_lw_t1[1]}} & fgu_fld_fcc_fx3[5:4]) | ({2{fcc_cw_t1[2]}} & fgu_cmp_fcc_fx3[1:0]), |
| 2247 | ({2{fcc_lw_t1[1]}} & fgu_fld_fcc_fx3[3:2]) | ({2{fcc_cw_t1[1]}} & fgu_cmp_fcc_fx3[1:0]), |
| 2248 | ({2{fcc_lw_t1[0]}} & fgu_fld_fcc_fx3[1:0]) | ({2{fcc_cw_t1[0]}} & fgu_cmp_fcc_fx3[1:0]) |
| 2249 | }; |
| 2250 | assign t1_hold_in[7:0] = { |
| 2251 | {2{~fcc_lw_t1[1] & ~fcc_cw_t1[3]}} & fcc_t1_d[7:6], |
| 2252 | {2{~fcc_lw_t1[1] & ~fcc_cw_t1[2]}} & fcc_t1_d[5:4], |
| 2253 | {2{~fcc_lw_t1[1] & ~fcc_cw_t1[1]}} & fcc_t1_d[3:2], |
| 2254 | {2{~fcc_lw_t1[0] & ~fcc_cw_t1[0]}} & fcc_t1_d[1:0] |
| 2255 | }; |
| 2256 | |
| 2257 | assign fcc_nxt_t1[7:0] = t1_data_in[7:0] | t1_hold_in[7:0]; |
| 2258 | |
| 2259 | exu_ect_ctl_msff_ctl_macro__width_8 fcc_t1_ff ( // FS:wmr_protect |
| 2260 | .scan_in(fcc_t1_ff_wmr_scanin), |
| 2261 | .scan_out(fcc_t1_ff_wmr_scanout), |
| 2262 | .siclk(spc_aclk_wmr), |
| 2263 | .l1clk(l1clk_pm1), |
| 2264 | .din (fcc_nxt_t1[7:0]), |
| 2265 | .dout (fcc_t1_d[7:0]), |
| 2266 | .soclk(soclk) |
| 2267 | ); |
| 2268 | |
| 2269 | assign t2_data_in[7:0] = { |
| 2270 | ({2{fcc_lw_t2[1]}} & fgu_fld_fcc_fx3[7:6]) | ({2{fcc_cw_t2[3]}} & fgu_cmp_fcc_fx3[1:0]), |
| 2271 | ({2{fcc_lw_t2[1]}} & fgu_fld_fcc_fx3[5:4]) | ({2{fcc_cw_t2[2]}} & fgu_cmp_fcc_fx3[1:0]), |
| 2272 | ({2{fcc_lw_t2[1]}} & fgu_fld_fcc_fx3[3:2]) | ({2{fcc_cw_t2[1]}} & fgu_cmp_fcc_fx3[1:0]), |
| 2273 | ({2{fcc_lw_t2[0]}} & fgu_fld_fcc_fx3[1:0]) | ({2{fcc_cw_t2[0]}} & fgu_cmp_fcc_fx3[1:0]) |
| 2274 | }; |
| 2275 | assign t2_hold_in[7:0] = { |
| 2276 | {2{~fcc_lw_t2[1] & ~fcc_cw_t2[3]}} & fcc_t2_d[7:6], |
| 2277 | {2{~fcc_lw_t2[1] & ~fcc_cw_t2[2]}} & fcc_t2_d[5:4], |
| 2278 | {2{~fcc_lw_t2[1] & ~fcc_cw_t2[1]}} & fcc_t2_d[3:2], |
| 2279 | {2{~fcc_lw_t2[0] & ~fcc_cw_t2[0]}} & fcc_t2_d[1:0] |
| 2280 | }; |
| 2281 | |
| 2282 | assign fcc_nxt_t2[7:0] = t2_data_in[7:0] | t2_hold_in[7:0]; |
| 2283 | |
| 2284 | exu_ect_ctl_msff_ctl_macro__width_8 fcc_t2_ff ( // FS:wmr_protect |
| 2285 | .scan_in(fcc_t2_ff_wmr_scanin), |
| 2286 | .scan_out(fcc_t2_ff_wmr_scanout), |
| 2287 | .siclk(spc_aclk_wmr), |
| 2288 | .l1clk(l1clk_pm1), |
| 2289 | .din (fcc_nxt_t2[7:0]), |
| 2290 | .dout (fcc_t2_d[7:0]), |
| 2291 | .soclk(soclk) |
| 2292 | ); |
| 2293 | |
| 2294 | assign t3_data_in[7:0] = { |
| 2295 | ({2{fcc_lw_t3[1]}} & fgu_fld_fcc_fx3[7:6]) | ({2{fcc_cw_t3[3]}} & fgu_cmp_fcc_fx3[1:0]), |
| 2296 | ({2{fcc_lw_t3[1]}} & fgu_fld_fcc_fx3[5:4]) | ({2{fcc_cw_t3[2]}} & fgu_cmp_fcc_fx3[1:0]), |
| 2297 | ({2{fcc_lw_t3[1]}} & fgu_fld_fcc_fx3[3:2]) | ({2{fcc_cw_t3[1]}} & fgu_cmp_fcc_fx3[1:0]), |
| 2298 | ({2{fcc_lw_t3[0]}} & fgu_fld_fcc_fx3[1:0]) | ({2{fcc_cw_t3[0]}} & fgu_cmp_fcc_fx3[1:0]) |
| 2299 | }; |
| 2300 | assign t3_hold_in[7:0] = { |
| 2301 | {2{~fcc_lw_t3[1] & ~fcc_cw_t3[3]}} & fcc_t3_d[7:6], |
| 2302 | {2{~fcc_lw_t3[1] & ~fcc_cw_t3[2]}} & fcc_t3_d[5:4], |
| 2303 | {2{~fcc_lw_t3[1] & ~fcc_cw_t3[1]}} & fcc_t3_d[3:2], |
| 2304 | {2{~fcc_lw_t3[0] & ~fcc_cw_t3[0]}} & fcc_t3_d[1:0] |
| 2305 | }; |
| 2306 | |
| 2307 | assign fcc_nxt_t3[7:0] = t3_data_in[7:0] | t3_hold_in[7:0]; |
| 2308 | |
| 2309 | exu_ect_ctl_msff_ctl_macro__width_8 fcc_t3_ff ( // FS:wmr_protect |
| 2310 | .scan_in(fcc_t3_ff_wmr_scanin), |
| 2311 | .scan_out(fcc_t3_ff_wmr_scanout), |
| 2312 | .siclk(spc_aclk_wmr), |
| 2313 | .l1clk(l1clk_pm1), |
| 2314 | .din (fcc_nxt_t3[7:0]), |
| 2315 | .dout (fcc_t3_d[7:0]), |
| 2316 | .soclk(soclk) |
| 2317 | ); |
| 2318 | |
| 2319 | |
| 2320 | // use current tid to pick the right thread |
| 2321 | |
| 2322 | // 0in value -var dec_pick_d[3:0] -val 0 1 2 4 8 |
| 2323 | |
| 2324 | assign fcc_d[7:0] = ({8{dec_pick_d[0]}} & fcc_t0_d[7:0]) | |
| 2325 | ({8{dec_pick_d[1]}} & fcc_t1_d[7:0]) | |
| 2326 | ({8{dec_pick_d[2]}} & fcc_t2_d[7:0]) | |
| 2327 | ({8{dec_pick_d[3]}} & fcc_t3_d[7:0]); |
| 2328 | |
| 2329 | //--------------------------- |
| 2330 | // FCC Logic |
| 2331 | //-------------------------- |
| 2332 | // choose current fcc |
| 2333 | assign use_fcc0_d = ~cctype_d[1] & ~cctype_d[0]; |
| 2334 | assign use_fcc1_d = ~cctype_d[1] & cctype_d[0]; |
| 2335 | assign use_fcc2_d = cctype_d[1] & ~cctype_d[0]; |
| 2336 | assign use_fcc3_d = cctype_d[1] & cctype_d[0]; |
| 2337 | |
| 2338 | assign curr_fcc_d[1:0] = ({2{use_fcc0_d}} & fcc_d[1:0]) | |
| 2339 | ({2{use_fcc1_d}} & fcc_d[3:2]) | |
| 2340 | ({2{use_fcc2_d}} & fcc_d[5:4]) | |
| 2341 | ({2{use_fcc3_d}} & fcc_d[7:6]); |
| 2342 | |
| 2343 | // decode to make next step easier |
| 2344 | assign fcc_dec_d[0] = ~curr_fcc_d[1] & ~curr_fcc_d[0]; |
| 2345 | assign fcc_dec_d[1] = ~curr_fcc_d[1] & curr_fcc_d[0]; |
| 2346 | assign fcc_dec_d[2] = curr_fcc_d[1] & ~curr_fcc_d[0]; |
| 2347 | assign fcc_dec_d[3] = curr_fcc_d[1] & curr_fcc_d[0]; |
| 2348 | |
| 2349 | exu_ect_ctl_msff_ctl_macro__width_4 fcce_ff ( |
| 2350 | .scan_in(fcce_ff_scanin), |
| 2351 | .scan_out(fcce_ff_scanout), |
| 2352 | .l1clk(l1clk_pm1), |
| 2353 | .din (fcc_dec_d[3:0]), |
| 2354 | .dout (fcc_dec_e[3:0]), |
| 2355 | .siclk(siclk), |
| 2356 | .soclk(soclk) |
| 2357 | ); |
| 2358 | |
| 2359 | exu_ect_ctl_msff_ctl_macro__width_4 brcond_e_reg ( |
| 2360 | .scan_in(brcond_e_reg_scanin), |
| 2361 | .scan_out(brcond_e_reg_scanout), |
| 2362 | .l1clk(l1clk_pm1), |
| 2363 | .din (brcond_d[3:0]), |
| 2364 | .dout (br_cond_e[3:0]), |
| 2365 | .siclk(siclk), |
| 2366 | .soclk(soclk) |
| 2367 | ); |
| 2368 | |
| 2369 | assign use_xcc_d = cctype_d[2] & cctype_d[1]; |
| 2370 | |
| 2371 | |
| 2372 | assign ccr_byp_data[7:0] = dec_valid_e ? exu_ccr_byp_data1[7:0] : |
| 2373 | exu_ccr_byp_data0[7:0]; |
| 2374 | |
| 2375 | // mux between xcc and icc |
| 2376 | assign cc_d[3:0] = use_xcc_d ? ccr_byp_data[7:4] : // xcc |
| 2377 | ccr_byp_data[3:0]; // icc |
| 2378 | |
| 2379 | exu_ect_ctl_msff_ctl_macro__width_4 ccreg_e ( |
| 2380 | .scan_in(ccreg_e_scanin), |
| 2381 | .scan_out(ccreg_e_scanout), |
| 2382 | .l1clk(l1clk_pm1), |
| 2383 | .din (cc_d[3:0]), |
| 2384 | .dout (cc_e[3:0]), |
| 2385 | .siclk(siclk), |
| 2386 | .soclk(soclk) |
| 2387 | ); |
| 2388 | |
| 2389 | // Branch Type Decode |
| 2390 | assign brcond_e[0] = ~br_cond_e[1] & ~br_cond_e[0]; |
| 2391 | assign brcond_e[1] = ~br_cond_e[1] & br_cond_e[0]; |
| 2392 | assign brcond_e[2] = br_cond_e[1] & ~br_cond_e[0]; |
| 2393 | assign brcond_e[3] = br_cond_e[1] & br_cond_e[0]; |
| 2394 | |
| 2395 | // Evaluate potential integer CC branches |
| 2396 | assign ltz_e = (cc_e[3] ^ cc_e[1]); |
| 2397 | |
| 2398 | assign cc_breval_e[0] = 1'b0; // BPN |
| 2399 | assign cc_breval_e[1] = cc_e[2]; // BPE |
| 2400 | assign cc_breval_e[2] = cc_e[2] | ltz_e; // BPLE |
| 2401 | assign cc_breval_e[3] = ltz_e; // BPL |
| 2402 | assign cc_breval_e[4] = cc_e[2] | cc_e[0]; // BPLEU |
| 2403 | assign cc_breval_e[5] = cc_e[0]; // BPCS |
| 2404 | assign cc_breval_e[6] = cc_e[3]; // BPNEG |
| 2405 | assign cc_breval_e[7] = cc_e[1]; // BPVS |
| 2406 | |
| 2407 | // mux to choose right condition |
| 2408 | assign cc_eval0 = cc_breval_e[0] & brcond_e[0] | |
| 2409 | cc_breval_e[1] & brcond_e[1] | |
| 2410 | cc_breval_e[2] & brcond_e[2] | |
| 2411 | cc_breval_e[3] & brcond_e[3]; |
| 2412 | |
| 2413 | assign cc_eval1 = cc_breval_e[4] & brcond_e[0] | |
| 2414 | cc_breval_e[5] & brcond_e[1] | |
| 2415 | cc_breval_e[6] & brcond_e[2] | |
| 2416 | cc_breval_e[7] & brcond_e[3]; |
| 2417 | |
| 2418 | // Evaluate FP CC branches |
| 2419 | assign fp_breval_e[0] = 1'b0; // FBN / A |
| 2420 | assign fp_breval_e[1] = ~fcc_dec_e[0]; // FBNE / E |
| 2421 | assign fp_breval_e[2] = fcc_dec_e[1] | fcc_dec_e[2]; // FBLG / UE |
| 2422 | assign fp_breval_e[3] = fcc_dec_e[1] | fcc_dec_e[3]; // FBUL / GE |
| 2423 | assign fp_breval_e[4] = fcc_dec_e[1]; // FBL / UGE |
| 2424 | assign fp_breval_e[5] = fcc_dec_e[3] | fcc_dec_e[2]; // FBUG / LE |
| 2425 | assign fp_breval_e[6] = fcc_dec_e[2]; // FBG / ULE |
| 2426 | assign fp_breval_e[7] = fcc_dec_e[3]; // FBU / O |
| 2427 | |
| 2428 | assign fp_eval0 = fp_breval_e[0] & brcond_e[0] | |
| 2429 | fp_breval_e[1] & brcond_e[1] | |
| 2430 | fp_breval_e[2] & brcond_e[2] | |
| 2431 | fp_breval_e[3] & brcond_e[3]; |
| 2432 | |
| 2433 | assign fp_eval1 = fp_breval_e[4] & brcond_e[0] | |
| 2434 | fp_breval_e[5] & brcond_e[1] | |
| 2435 | fp_breval_e[6] & brcond_e[2] | |
| 2436 | fp_breval_e[7] & brcond_e[3]; |
| 2437 | |
| 2438 | |
| 2439 | exu_ect_ctl_msff_ctl_macro__width_1 cctype_reg ( |
| 2440 | .scan_in(cctype_reg_scanin), |
| 2441 | .scan_out(cctype_reg_scanout), |
| 2442 | .l1clk(l1clk_pm1), |
| 2443 | .din (cctype_d[2]), |
| 2444 | .dout (cctype_e[2]), |
| 2445 | .siclk(siclk), |
| 2446 | .soclk(soclk) |
| 2447 | ); |
| 2448 | |
| 2449 | assign fpcond_mvbr_e = ~cctype_e[2]; |
| 2450 | |
| 2451 | // merge eval0, eval1 and fp condition codes |
| 2452 | assign cc_eval = (~fpcond_mvbr_e & ~br_cond_e[2] & cc_eval0) | |
| 2453 | (~fpcond_mvbr_e & br_cond_e[2] & cc_eval1) | |
| 2454 | ( fpcond_mvbr_e & ~br_cond_e[2] & fp_eval0) | |
| 2455 | ( fpcond_mvbr_e & br_cond_e[2] & fp_eval1); |
| 2456 | |
| 2457 | // invert branch condition if this is an inverted br type |
| 2458 | assign cond_true_e = cc_eval ^ br_cond_e[3]; |
| 2459 | |
| 2460 | exu_ect_ctl_msff_ctl_macro__width_4 misc_ff ( |
| 2461 | .scan_in(misc_ff_scanin), |
| 2462 | .scan_out(misc_ff_scanout), |
| 2463 | .l1clk(l1clk_pm1), |
| 2464 | .din ({callclass_d , specbr_d , cmov_d , regop_d}), |
| 2465 | .dout ({callclass_e , specbr_e , cmov_e , regop_e}), |
| 2466 | .siclk(siclk), |
| 2467 | .soclk(soclk) |
| 2468 | ); |
| 2469 | |
| 2470 | //-------------- |
| 2471 | // For BRZ |
| 2472 | // ------------- |
| 2473 | // Calculate Cond Assuming Z=1 And Z=0. Then Mux |
| 2474 | assign r_eval1 = (edp_br_flag_e[1] | ~br_cond_e[1] | ~br_cond_e[0]) ^ br_cond_e[2]; |
| 2475 | |
| 2476 | assign r_eval0 = (edp_br_flag_e[1] & br_cond_e[1]) ^ br_cond_e[2]; |
| 2477 | |
| 2478 | |
| 2479 | // Evaluate Final Branch condition |
| 2480 | // 3:1 mux |
| 2481 | |
| 2482 | assign final_cond_true_z0_e = (~regop_e & cond_true_e) | |
| 2483 | ( regop_e & r_eval0 ); |
| 2484 | |
| 2485 | assign final_cond_true_z1_e = (~regop_e & cond_true_e) | |
| 2486 | ( regop_e & r_eval1 ); |
| 2487 | |
| 2488 | // valid_e takes annul into account |
| 2489 | |
| 2490 | |
| 2491 | // 0in value -var {callclass_e & dec_valid_e,cmov_e & dec_valid_e,tcc_e & dec_valid_e} -val 0 1 2 4 |
| 2492 | |
| 2493 | assign ect_br_taken_z0_e = (callclass_e | (specbr_e & final_cond_true_z0_e)); |
| 2494 | assign ect_br_taken_z1_e = (callclass_e | (specbr_e & final_cond_true_z1_e)); |
| 2495 | |
| 2496 | |
| 2497 | // 3 cases for {zero,neg} are 00, 01, 10 (11 illegal) |
| 2498 | |
| 2499 | assign dec_cmov_z00_e = cmov_e & ((~regop_e & cond_true_e) | (regop_e & br_cond_e[2])); // 00 case |
| 2500 | |
| 2501 | assign dec_cmov_z01_e = cmov_e & ((~regop_e & cond_true_e) | (regop_e & (br_cond_e[1] ^ br_cond_e[2]))); // 01 case |
| 2502 | |
| 2503 | assign dec_cmov_z10_e = cmov_e & ((~regop_e & cond_true_e) | (regop_e & ((~br_cond_e[1] | ~br_cond_e[0]) ^ br_cond_e[2]))); // 10 case |
| 2504 | |
| 2505 | |
| 2506 | assign tcc_taken_e = (tcc_e & final_cond_true_z0_e & ~edp_br_flag_e[0]) | |
| 2507 | (tcc_e & final_cond_true_z1_e & edp_br_flag_e[0]); |
| 2508 | |
| 2509 | |
| 2510 | //!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End : DEC_CCR_CTL !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! |
| 2511 | |
| 2512 | |
| 2513 | exu_ect_ctl_spare_ctl_macro__num_6 spares ( |
| 2514 | .scan_in(spares_scanin), |
| 2515 | .scan_out(spares_scanout), |
| 2516 | .l1clk (l1clk), |
| 2517 | .siclk(siclk), |
| 2518 | .soclk(soclk)); |
| 2519 | |
| 2520 | |
| 2521 | supply0 vss; |
| 2522 | supply1 vdd; |
| 2523 | |
| 2524 | // fixscan start: |
| 2525 | assign i_pwr0_lth_scanin = scan_in ; |
| 2526 | assign i_pwr1_lth_scanin = i_pwr0_lth_scanout ; |
| 2527 | assign i_mbist_lth_scanin = i_pwr1_lth_scanout ; |
| 2528 | assign i_estage_lth_scanin = i_mbist_lth_scanout ; |
| 2529 | assign i_mstage_lth_scanin = i_estage_lth_scanout ; |
| 2530 | assign ren_lth_scanin = i_mstage_lth_scanout ; |
| 2531 | assign rs_lth_scanin = ren_lth_scanout ; |
| 2532 | assign i_byp_lth_scanin = rs_lth_scanout ; |
| 2533 | assign i_ccr_pipe_lth_scanin = i_byp_lth_scanout ; |
| 2534 | assign i_tlu_lth_scanin = i_ccr_pipe_lth_scanout ; |
| 2535 | assign i_yreg_mpipe_lth_scanin = i_tlu_lth_scanout ; |
| 2536 | assign i_yreg_spipe_lth_scanin = i_yreg_mpipe_lth_scanout ; |
| 2537 | assign fgu_tid_ff_scanin = i_yreg_spipe_lth_scanout ; |
| 2538 | assign fcce_ff_scanin = fgu_tid_ff_scanout ; |
| 2539 | assign brcond_e_reg_scanin = fcce_ff_scanout ; |
| 2540 | assign ccreg_e_scanin = brcond_e_reg_scanout ; |
| 2541 | assign cctype_reg_scanin = ccreg_e_scanout ; |
| 2542 | assign misc_ff_scanin = cctype_reg_scanout ; |
| 2543 | assign spares_scanin = misc_ff_scanout ; |
| 2544 | assign scan_out = spares_scanout ; |
| 2545 | |
| 2546 | assign i_ccr_arch_lth_wmr_scanin = wmr_scan_in ; |
| 2547 | assign fcc_t0_ff_wmr_scanin = i_ccr_arch_lth_wmr_scanout; |
| 2548 | assign fcc_t1_ff_wmr_scanin = fcc_t0_ff_wmr_scanout ; |
| 2549 | assign fcc_t2_ff_wmr_scanin = fcc_t1_ff_wmr_scanout ; |
| 2550 | assign fcc_t3_ff_wmr_scanin = fcc_t2_ff_wmr_scanout ; |
| 2551 | assign wmr_scan_out = fcc_t3_ff_wmr_scanout ; |
| 2552 | // fixscan end: |
| 2553 | endmodule |
| 2554 | |
| 2555 | |
| 2556 | |
| 2557 | |
| 2558 | |
| 2559 | |
| 2560 | // any PARAMS parms go into naming of macro |
| 2561 | |
| 2562 | module exu_ect_ctl_l1clkhdr_ctl_macro ( |
| 2563 | l2clk, |
| 2564 | l1en, |
| 2565 | pce_ov, |
| 2566 | stop, |
| 2567 | se, |
| 2568 | l1clk); |
| 2569 | |
| 2570 | |
| 2571 | input l2clk; |
| 2572 | input l1en; |
| 2573 | input pce_ov; |
| 2574 | input stop; |
| 2575 | input se; |
| 2576 | output l1clk; |
| 2577 | |
| 2578 | |
| 2579 | |
| 2580 | |
| 2581 | |
| 2582 | cl_sc1_l1hdr_8x c_0 ( |
| 2583 | |
| 2584 | |
| 2585 | .l2clk(l2clk), |
| 2586 | .pce(l1en), |
| 2587 | .l1clk(l1clk), |
| 2588 | .se(se), |
| 2589 | .pce_ov(pce_ov), |
| 2590 | .stop(stop) |
| 2591 | ); |
| 2592 | |
| 2593 | |
| 2594 | |
| 2595 | endmodule |
| 2596 | |
| 2597 | |
| 2598 | |
| 2599 | |
| 2600 | |
| 2601 | |
| 2602 | |
| 2603 | |
| 2604 | |
| 2605 | |
| 2606 | |
| 2607 | |
| 2608 | |
| 2609 | // any PARAMS parms go into naming of macro |
| 2610 | |
| 2611 | module exu_ect_ctl_msff_ctl_macro__width_5 ( |
| 2612 | din, |
| 2613 | l1clk, |
| 2614 | scan_in, |
| 2615 | siclk, |
| 2616 | soclk, |
| 2617 | dout, |
| 2618 | scan_out); |
| 2619 | wire [4:0] fdin; |
| 2620 | wire [3:0] so; |
| 2621 | |
| 2622 | input [4:0] din; |
| 2623 | input l1clk; |
| 2624 | input scan_in; |
| 2625 | |
| 2626 | |
| 2627 | input siclk; |
| 2628 | input soclk; |
| 2629 | |
| 2630 | output [4:0] dout; |
| 2631 | output scan_out; |
| 2632 | assign fdin[4:0] = din[4:0]; |
| 2633 | |
| 2634 | |
| 2635 | |
| 2636 | |
| 2637 | |
| 2638 | |
| 2639 | dff #(5) d0_0 ( |
| 2640 | .l1clk(l1clk), |
| 2641 | .siclk(siclk), |
| 2642 | .soclk(soclk), |
| 2643 | .d(fdin[4:0]), |
| 2644 | .si({scan_in,so[3:0]}), |
| 2645 | .so({so[3:0],scan_out}), |
| 2646 | .q(dout[4:0]) |
| 2647 | ); |
| 2648 | |
| 2649 | |
| 2650 | |
| 2651 | |
| 2652 | |
| 2653 | |
| 2654 | |
| 2655 | |
| 2656 | |
| 2657 | |
| 2658 | |
| 2659 | |
| 2660 | endmodule |
| 2661 | |
| 2662 | |
| 2663 | |
| 2664 | |
| 2665 | |
| 2666 | |
| 2667 | |
| 2668 | |
| 2669 | |
| 2670 | |
| 2671 | |
| 2672 | |
| 2673 | |
| 2674 | // any PARAMS parms go into naming of macro |
| 2675 | |
| 2676 | module exu_ect_ctl_msff_ctl_macro__width_8 ( |
| 2677 | din, |
| 2678 | l1clk, |
| 2679 | scan_in, |
| 2680 | siclk, |
| 2681 | soclk, |
| 2682 | dout, |
| 2683 | scan_out); |
| 2684 | wire [7:0] fdin; |
| 2685 | wire [6:0] so; |
| 2686 | |
| 2687 | input [7:0] din; |
| 2688 | input l1clk; |
| 2689 | input scan_in; |
| 2690 | |
| 2691 | |
| 2692 | input siclk; |
| 2693 | input soclk; |
| 2694 | |
| 2695 | output [7:0] dout; |
| 2696 | output scan_out; |
| 2697 | assign fdin[7:0] = din[7:0]; |
| 2698 | |
| 2699 | |
| 2700 | |
| 2701 | |
| 2702 | |
| 2703 | |
| 2704 | dff #(8) d0_0 ( |
| 2705 | .l1clk(l1clk), |
| 2706 | .siclk(siclk), |
| 2707 | .soclk(soclk), |
| 2708 | .d(fdin[7:0]), |
| 2709 | .si({scan_in,so[6:0]}), |
| 2710 | .so({so[6:0],scan_out}), |
| 2711 | .q(dout[7:0]) |
| 2712 | ); |
| 2713 | |
| 2714 | |
| 2715 | |
| 2716 | |
| 2717 | |
| 2718 | |
| 2719 | |
| 2720 | |
| 2721 | |
| 2722 | |
| 2723 | |
| 2724 | |
| 2725 | endmodule |
| 2726 | |
| 2727 | |
| 2728 | |
| 2729 | |
| 2730 | |
| 2731 | |
| 2732 | |
| 2733 | |
| 2734 | |
| 2735 | |
| 2736 | |
| 2737 | |
| 2738 | |
| 2739 | // any PARAMS parms go into naming of macro |
| 2740 | |
| 2741 | module exu_ect_ctl_msff_ctl_macro__width_37 ( |
| 2742 | din, |
| 2743 | l1clk, |
| 2744 | scan_in, |
| 2745 | siclk, |
| 2746 | soclk, |
| 2747 | dout, |
| 2748 | scan_out); |
| 2749 | wire [36:0] fdin; |
| 2750 | wire [35:0] so; |
| 2751 | |
| 2752 | input [36:0] din; |
| 2753 | input l1clk; |
| 2754 | input scan_in; |
| 2755 | |
| 2756 | |
| 2757 | input siclk; |
| 2758 | input soclk; |
| 2759 | |
| 2760 | output [36:0] dout; |
| 2761 | output scan_out; |
| 2762 | assign fdin[36:0] = din[36:0]; |
| 2763 | |
| 2764 | |
| 2765 | |
| 2766 | |
| 2767 | |
| 2768 | |
| 2769 | dff #(37) d0_0 ( |
| 2770 | .l1clk(l1clk), |
| 2771 | .siclk(siclk), |
| 2772 | .soclk(soclk), |
| 2773 | .d(fdin[36:0]), |
| 2774 | .si({scan_in,so[35:0]}), |
| 2775 | .so({so[35:0],scan_out}), |
| 2776 | .q(dout[36:0]) |
| 2777 | ); |
| 2778 | |
| 2779 | |
| 2780 | |
| 2781 | |
| 2782 | |
| 2783 | |
| 2784 | |
| 2785 | |
| 2786 | |
| 2787 | |
| 2788 | |
| 2789 | |
| 2790 | endmodule |
| 2791 | |
| 2792 | |
| 2793 | |
| 2794 | |
| 2795 | |
| 2796 | |
| 2797 | |
| 2798 | |
| 2799 | |
| 2800 | |
| 2801 | |
| 2802 | |
| 2803 | |
| 2804 | // any PARAMS parms go into naming of macro |
| 2805 | |
| 2806 | module exu_ect_ctl_msff_ctl_macro__width_6 ( |
| 2807 | din, |
| 2808 | l1clk, |
| 2809 | scan_in, |
| 2810 | siclk, |
| 2811 | soclk, |
| 2812 | dout, |
| 2813 | scan_out); |
| 2814 | wire [5:0] fdin; |
| 2815 | wire [4:0] so; |
| 2816 | |
| 2817 | input [5:0] din; |
| 2818 | input l1clk; |
| 2819 | input scan_in; |
| 2820 | |
| 2821 | |
| 2822 | input siclk; |
| 2823 | input soclk; |
| 2824 | |
| 2825 | output [5:0] dout; |
| 2826 | output scan_out; |
| 2827 | assign fdin[5:0] = din[5:0]; |
| 2828 | |
| 2829 | |
| 2830 | |
| 2831 | |
| 2832 | |
| 2833 | |
| 2834 | dff #(6) d0_0 ( |
| 2835 | .l1clk(l1clk), |
| 2836 | .siclk(siclk), |
| 2837 | .soclk(soclk), |
| 2838 | .d(fdin[5:0]), |
| 2839 | .si({scan_in,so[4:0]}), |
| 2840 | .so({so[4:0],scan_out}), |
| 2841 | .q(dout[5:0]) |
| 2842 | ); |
| 2843 | |
| 2844 | |
| 2845 | |
| 2846 | |
| 2847 | |
| 2848 | |
| 2849 | |
| 2850 | |
| 2851 | |
| 2852 | |
| 2853 | |
| 2854 | |
| 2855 | endmodule |
| 2856 | |
| 2857 | |
| 2858 | |
| 2859 | |
| 2860 | |
| 2861 | |
| 2862 | |
| 2863 | |
| 2864 | |
| 2865 | |
| 2866 | |
| 2867 | |
| 2868 | |
| 2869 | // any PARAMS parms go into naming of macro |
| 2870 | |
| 2871 | module exu_ect_ctl_msff_ctl_macro__width_15 ( |
| 2872 | din, |
| 2873 | l1clk, |
| 2874 | scan_in, |
| 2875 | siclk, |
| 2876 | soclk, |
| 2877 | dout, |
| 2878 | scan_out); |
| 2879 | wire [14:0] fdin; |
| 2880 | wire [13:0] so; |
| 2881 | |
| 2882 | input [14:0] din; |
| 2883 | input l1clk; |
| 2884 | input scan_in; |
| 2885 | |
| 2886 | |
| 2887 | input siclk; |
| 2888 | input soclk; |
| 2889 | |
| 2890 | output [14:0] dout; |
| 2891 | output scan_out; |
| 2892 | assign fdin[14:0] = din[14:0]; |
| 2893 | |
| 2894 | |
| 2895 | |
| 2896 | |
| 2897 | |
| 2898 | |
| 2899 | dff #(15) d0_0 ( |
| 2900 | .l1clk(l1clk), |
| 2901 | .siclk(siclk), |
| 2902 | .soclk(soclk), |
| 2903 | .d(fdin[14:0]), |
| 2904 | .si({scan_in,so[13:0]}), |
| 2905 | .so({so[13:0],scan_out}), |
| 2906 | .q(dout[14:0]) |
| 2907 | ); |
| 2908 | |
| 2909 | |
| 2910 | |
| 2911 | |
| 2912 | |
| 2913 | |
| 2914 | |
| 2915 | |
| 2916 | |
| 2917 | |
| 2918 | |
| 2919 | |
| 2920 | endmodule |
| 2921 | |
| 2922 | |
| 2923 | |
| 2924 | |
| 2925 | |
| 2926 | |
| 2927 | |
| 2928 | |
| 2929 | |
| 2930 | |
| 2931 | |
| 2932 | |
| 2933 | |
| 2934 | // any PARAMS parms go into naming of macro |
| 2935 | |
| 2936 | module exu_ect_ctl_msff_ctl_macro__width_76 ( |
| 2937 | din, |
| 2938 | l1clk, |
| 2939 | scan_in, |
| 2940 | siclk, |
| 2941 | soclk, |
| 2942 | dout, |
| 2943 | scan_out); |
| 2944 | wire [75:0] fdin; |
| 2945 | wire [74:0] so; |
| 2946 | |
| 2947 | input [75:0] din; |
| 2948 | input l1clk; |
| 2949 | input scan_in; |
| 2950 | |
| 2951 | |
| 2952 | input siclk; |
| 2953 | input soclk; |
| 2954 | |
| 2955 | output [75:0] dout; |
| 2956 | output scan_out; |
| 2957 | assign fdin[75:0] = din[75:0]; |
| 2958 | |
| 2959 | |
| 2960 | |
| 2961 | |
| 2962 | |
| 2963 | |
| 2964 | dff #(76) d0_0 ( |
| 2965 | .l1clk(l1clk), |
| 2966 | .siclk(siclk), |
| 2967 | .soclk(soclk), |
| 2968 | .d(fdin[75:0]), |
| 2969 | .si({scan_in,so[74:0]}), |
| 2970 | .so({so[74:0],scan_out}), |
| 2971 | .q(dout[75:0]) |
| 2972 | ); |
| 2973 | |
| 2974 | |
| 2975 | |
| 2976 | |
| 2977 | |
| 2978 | |
| 2979 | |
| 2980 | |
| 2981 | |
| 2982 | |
| 2983 | |
| 2984 | |
| 2985 | endmodule |
| 2986 | |
| 2987 | |
| 2988 | |
| 2989 | |
| 2990 | |
| 2991 | |
| 2992 | |
| 2993 | |
| 2994 | |
| 2995 | |
| 2996 | |
| 2997 | |
| 2998 | |
| 2999 | // any PARAMS parms go into naming of macro |
| 3000 | |
| 3001 | module exu_ect_ctl_msff_ctl_macro__width_28 ( |
| 3002 | din, |
| 3003 | l1clk, |
| 3004 | scan_in, |
| 3005 | siclk, |
| 3006 | soclk, |
| 3007 | dout, |
| 3008 | scan_out); |
| 3009 | wire [27:0] fdin; |
| 3010 | wire [26:0] so; |
| 3011 | |
| 3012 | input [27:0] din; |
| 3013 | input l1clk; |
| 3014 | input scan_in; |
| 3015 | |
| 3016 | |
| 3017 | input siclk; |
| 3018 | input soclk; |
| 3019 | |
| 3020 | output [27:0] dout; |
| 3021 | output scan_out; |
| 3022 | assign fdin[27:0] = din[27:0]; |
| 3023 | |
| 3024 | |
| 3025 | |
| 3026 | |
| 3027 | |
| 3028 | |
| 3029 | dff #(28) d0_0 ( |
| 3030 | .l1clk(l1clk), |
| 3031 | .siclk(siclk), |
| 3032 | .soclk(soclk), |
| 3033 | .d(fdin[27:0]), |
| 3034 | .si({scan_in,so[26:0]}), |
| 3035 | .so({so[26:0],scan_out}), |
| 3036 | .q(dout[27:0]) |
| 3037 | ); |
| 3038 | |
| 3039 | |
| 3040 | |
| 3041 | |
| 3042 | |
| 3043 | |
| 3044 | |
| 3045 | |
| 3046 | |
| 3047 | |
| 3048 | |
| 3049 | |
| 3050 | endmodule |
| 3051 | |
| 3052 | |
| 3053 | |
| 3054 | |
| 3055 | |
| 3056 | |
| 3057 | |
| 3058 | |
| 3059 | |
| 3060 | |
| 3061 | |
| 3062 | |
| 3063 | |
| 3064 | // any PARAMS parms go into naming of macro |
| 3065 | |
| 3066 | module exu_ect_ctl_msff_ctl_macro__width_32 ( |
| 3067 | din, |
| 3068 | l1clk, |
| 3069 | scan_in, |
| 3070 | siclk, |
| 3071 | soclk, |
| 3072 | dout, |
| 3073 | scan_out); |
| 3074 | wire [31:0] fdin; |
| 3075 | wire [30:0] so; |
| 3076 | |
| 3077 | input [31:0] din; |
| 3078 | input l1clk; |
| 3079 | input scan_in; |
| 3080 | |
| 3081 | |
| 3082 | input siclk; |
| 3083 | input soclk; |
| 3084 | |
| 3085 | output [31:0] dout; |
| 3086 | output scan_out; |
| 3087 | assign fdin[31:0] = din[31:0]; |
| 3088 | |
| 3089 | |
| 3090 | |
| 3091 | |
| 3092 | |
| 3093 | |
| 3094 | dff #(32) d0_0 ( |
| 3095 | .l1clk(l1clk), |
| 3096 | .siclk(siclk), |
| 3097 | .soclk(soclk), |
| 3098 | .d(fdin[31:0]), |
| 3099 | .si({scan_in,so[30:0]}), |
| 3100 | .so({so[30:0],scan_out}), |
| 3101 | .q(dout[31:0]) |
| 3102 | ); |
| 3103 | |
| 3104 | |
| 3105 | |
| 3106 | |
| 3107 | |
| 3108 | |
| 3109 | |
| 3110 | |
| 3111 | |
| 3112 | |
| 3113 | |
| 3114 | |
| 3115 | endmodule |
| 3116 | |
| 3117 | |
| 3118 | |
| 3119 | |
| 3120 | |
| 3121 | |
| 3122 | |
| 3123 | |
| 3124 | |
| 3125 | |
| 3126 | |
| 3127 | |
| 3128 | |
| 3129 | // any PARAMS parms go into naming of macro |
| 3130 | |
| 3131 | module exu_ect_ctl_msff_ctl_macro__width_9 ( |
| 3132 | din, |
| 3133 | l1clk, |
| 3134 | scan_in, |
| 3135 | siclk, |
| 3136 | soclk, |
| 3137 | dout, |
| 3138 | scan_out); |
| 3139 | wire [8:0] fdin; |
| 3140 | wire [7:0] so; |
| 3141 | |
| 3142 | input [8:0] din; |
| 3143 | input l1clk; |
| 3144 | input scan_in; |
| 3145 | |
| 3146 | |
| 3147 | input siclk; |
| 3148 | input soclk; |
| 3149 | |
| 3150 | output [8:0] dout; |
| 3151 | output scan_out; |
| 3152 | assign fdin[8:0] = din[8:0]; |
| 3153 | |
| 3154 | |
| 3155 | |
| 3156 | |
| 3157 | |
| 3158 | |
| 3159 | dff #(9) d0_0 ( |
| 3160 | .l1clk(l1clk), |
| 3161 | .siclk(siclk), |
| 3162 | .soclk(soclk), |
| 3163 | .d(fdin[8:0]), |
| 3164 | .si({scan_in,so[7:0]}), |
| 3165 | .so({so[7:0],scan_out}), |
| 3166 | .q(dout[8:0]) |
| 3167 | ); |
| 3168 | |
| 3169 | |
| 3170 | |
| 3171 | |
| 3172 | |
| 3173 | |
| 3174 | |
| 3175 | |
| 3176 | |
| 3177 | |
| 3178 | |
| 3179 | |
| 3180 | endmodule |
| 3181 | |
| 3182 | |
| 3183 | |
| 3184 | |
| 3185 | |
| 3186 | |
| 3187 | |
| 3188 | |
| 3189 | |
| 3190 | |
| 3191 | |
| 3192 | |
| 3193 | |
| 3194 | // any PARAMS parms go into naming of macro |
| 3195 | |
| 3196 | module exu_ect_ctl_msff_ctl_macro__width_4 ( |
| 3197 | din, |
| 3198 | l1clk, |
| 3199 | scan_in, |
| 3200 | siclk, |
| 3201 | soclk, |
| 3202 | dout, |
| 3203 | scan_out); |
| 3204 | wire [3:0] fdin; |
| 3205 | wire [2:0] so; |
| 3206 | |
| 3207 | input [3:0] din; |
| 3208 | input l1clk; |
| 3209 | input scan_in; |
| 3210 | |
| 3211 | |
| 3212 | input siclk; |
| 3213 | input soclk; |
| 3214 | |
| 3215 | output [3:0] dout; |
| 3216 | output scan_out; |
| 3217 | assign fdin[3:0] = din[3:0]; |
| 3218 | |
| 3219 | |
| 3220 | |
| 3221 | |
| 3222 | |
| 3223 | |
| 3224 | dff #(4) d0_0 ( |
| 3225 | .l1clk(l1clk), |
| 3226 | .siclk(siclk), |
| 3227 | .soclk(soclk), |
| 3228 | .d(fdin[3:0]), |
| 3229 | .si({scan_in,so[2:0]}), |
| 3230 | .so({so[2:0],scan_out}), |
| 3231 | .q(dout[3:0]) |
| 3232 | ); |
| 3233 | |
| 3234 | |
| 3235 | |
| 3236 | |
| 3237 | |
| 3238 | |
| 3239 | |
| 3240 | |
| 3241 | |
| 3242 | |
| 3243 | |
| 3244 | |
| 3245 | endmodule |
| 3246 | |
| 3247 | |
| 3248 | |
| 3249 | |
| 3250 | |
| 3251 | |
| 3252 | |
| 3253 | |
| 3254 | |
| 3255 | |
| 3256 | |
| 3257 | |
| 3258 | |
| 3259 | // any PARAMS parms go into naming of macro |
| 3260 | |
| 3261 | module exu_ect_ctl_msff_ctl_macro__width_1 ( |
| 3262 | din, |
| 3263 | l1clk, |
| 3264 | scan_in, |
| 3265 | siclk, |
| 3266 | soclk, |
| 3267 | dout, |
| 3268 | scan_out); |
| 3269 | wire [0:0] fdin; |
| 3270 | |
| 3271 | input [0:0] din; |
| 3272 | input l1clk; |
| 3273 | input scan_in; |
| 3274 | |
| 3275 | |
| 3276 | input siclk; |
| 3277 | input soclk; |
| 3278 | |
| 3279 | output [0:0] dout; |
| 3280 | output scan_out; |
| 3281 | assign fdin[0:0] = din[0:0]; |
| 3282 | |
| 3283 | |
| 3284 | |
| 3285 | |
| 3286 | |
| 3287 | |
| 3288 | dff #(1) d0_0 ( |
| 3289 | .l1clk(l1clk), |
| 3290 | .siclk(siclk), |
| 3291 | .soclk(soclk), |
| 3292 | .d(fdin[0:0]), |
| 3293 | .si(scan_in), |
| 3294 | .so(scan_out), |
| 3295 | .q(dout[0:0]) |
| 3296 | ); |
| 3297 | |
| 3298 | |
| 3299 | |
| 3300 | |
| 3301 | |
| 3302 | |
| 3303 | |
| 3304 | |
| 3305 | |
| 3306 | |
| 3307 | |
| 3308 | |
| 3309 | endmodule |
| 3310 | |
| 3311 | |
| 3312 | |
| 3313 | |
| 3314 | |
| 3315 | |
| 3316 | |
| 3317 | |
| 3318 | |
| 3319 | // Description: Spare gate macro for control blocks |
| 3320 | // |
| 3321 | // Param num controls the number of times the macro is added |
| 3322 | // flops=0 can be used to use only combination spare logic |
| 3323 | |
| 3324 | |
| 3325 | module exu_ect_ctl_spare_ctl_macro__num_6 ( |
| 3326 | l1clk, |
| 3327 | scan_in, |
| 3328 | siclk, |
| 3329 | soclk, |
| 3330 | scan_out); |
| 3331 | wire si_0; |
| 3332 | wire so_0; |
| 3333 | wire spare0_flop_unused; |
| 3334 | wire spare0_buf_32x_unused; |
| 3335 | wire spare0_nand3_8x_unused; |
| 3336 | wire spare0_inv_8x_unused; |
| 3337 | wire spare0_aoi22_4x_unused; |
| 3338 | wire spare0_buf_8x_unused; |
| 3339 | wire spare0_oai22_4x_unused; |
| 3340 | wire spare0_inv_16x_unused; |
| 3341 | wire spare0_nand2_16x_unused; |
| 3342 | wire spare0_nor3_4x_unused; |
| 3343 | wire spare0_nand2_8x_unused; |
| 3344 | wire spare0_buf_16x_unused; |
| 3345 | wire spare0_nor2_16x_unused; |
| 3346 | wire spare0_inv_32x_unused; |
| 3347 | wire si_1; |
| 3348 | wire so_1; |
| 3349 | wire spare1_flop_unused; |
| 3350 | wire spare1_buf_32x_unused; |
| 3351 | wire spare1_nand3_8x_unused; |
| 3352 | wire spare1_inv_8x_unused; |
| 3353 | wire spare1_aoi22_4x_unused; |
| 3354 | wire spare1_buf_8x_unused; |
| 3355 | wire spare1_oai22_4x_unused; |
| 3356 | wire spare1_inv_16x_unused; |
| 3357 | wire spare1_nand2_16x_unused; |
| 3358 | wire spare1_nor3_4x_unused; |
| 3359 | wire spare1_nand2_8x_unused; |
| 3360 | wire spare1_buf_16x_unused; |
| 3361 | wire spare1_nor2_16x_unused; |
| 3362 | wire spare1_inv_32x_unused; |
| 3363 | wire si_2; |
| 3364 | wire so_2; |
| 3365 | wire spare2_flop_unused; |
| 3366 | wire spare2_buf_32x_unused; |
| 3367 | wire spare2_nand3_8x_unused; |
| 3368 | wire spare2_inv_8x_unused; |
| 3369 | wire spare2_aoi22_4x_unused; |
| 3370 | wire spare2_buf_8x_unused; |
| 3371 | wire spare2_oai22_4x_unused; |
| 3372 | wire spare2_inv_16x_unused; |
| 3373 | wire spare2_nand2_16x_unused; |
| 3374 | wire spare2_nor3_4x_unused; |
| 3375 | wire spare2_nand2_8x_unused; |
| 3376 | wire spare2_buf_16x_unused; |
| 3377 | wire spare2_nor2_16x_unused; |
| 3378 | wire spare2_inv_32x_unused; |
| 3379 | wire si_3; |
| 3380 | wire so_3; |
| 3381 | wire spare3_flop_unused; |
| 3382 | wire spare3_buf_32x_unused; |
| 3383 | wire spare3_nand3_8x_unused; |
| 3384 | wire spare3_inv_8x_unused; |
| 3385 | wire spare3_aoi22_4x_unused; |
| 3386 | wire spare3_buf_8x_unused; |
| 3387 | wire spare3_oai22_4x_unused; |
| 3388 | wire spare3_inv_16x_unused; |
| 3389 | wire spare3_nand2_16x_unused; |
| 3390 | wire spare3_nor3_4x_unused; |
| 3391 | wire spare3_nand2_8x_unused; |
| 3392 | wire spare3_buf_16x_unused; |
| 3393 | wire spare3_nor2_16x_unused; |
| 3394 | wire spare3_inv_32x_unused; |
| 3395 | wire si_4; |
| 3396 | wire so_4; |
| 3397 | wire spare4_flop_unused; |
| 3398 | wire spare4_buf_32x_unused; |
| 3399 | wire spare4_nand3_8x_unused; |
| 3400 | wire spare4_inv_8x_unused; |
| 3401 | wire spare4_aoi22_4x_unused; |
| 3402 | wire spare4_buf_8x_unused; |
| 3403 | wire spare4_oai22_4x_unused; |
| 3404 | wire spare4_inv_16x_unused; |
| 3405 | wire spare4_nand2_16x_unused; |
| 3406 | wire spare4_nor3_4x_unused; |
| 3407 | wire spare4_nand2_8x_unused; |
| 3408 | wire spare4_buf_16x_unused; |
| 3409 | wire spare4_nor2_16x_unused; |
| 3410 | wire spare4_inv_32x_unused; |
| 3411 | wire si_5; |
| 3412 | wire so_5; |
| 3413 | wire spare5_flop_unused; |
| 3414 | wire spare5_buf_32x_unused; |
| 3415 | wire spare5_nand3_8x_unused; |
| 3416 | wire spare5_inv_8x_unused; |
| 3417 | wire spare5_aoi22_4x_unused; |
| 3418 | wire spare5_buf_8x_unused; |
| 3419 | wire spare5_oai22_4x_unused; |
| 3420 | wire spare5_inv_16x_unused; |
| 3421 | wire spare5_nand2_16x_unused; |
| 3422 | wire spare5_nor3_4x_unused; |
| 3423 | wire spare5_nand2_8x_unused; |
| 3424 | wire spare5_buf_16x_unused; |
| 3425 | wire spare5_nor2_16x_unused; |
| 3426 | wire spare5_inv_32x_unused; |
| 3427 | |
| 3428 | |
| 3429 | input l1clk; |
| 3430 | input scan_in; |
| 3431 | input siclk; |
| 3432 | input soclk; |
| 3433 | output scan_out; |
| 3434 | |
| 3435 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), |
| 3436 | .siclk(siclk), |
| 3437 | .soclk(soclk), |
| 3438 | .si(si_0), |
| 3439 | .so(so_0), |
| 3440 | .d(1'b0), |
| 3441 | .q(spare0_flop_unused)); |
| 3442 | assign si_0 = scan_in; |
| 3443 | |
| 3444 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), |
| 3445 | .out(spare0_buf_32x_unused)); |
| 3446 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), |
| 3447 | .in1(1'b1), |
| 3448 | .in2(1'b1), |
| 3449 | .out(spare0_nand3_8x_unused)); |
| 3450 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), |
| 3451 | .out(spare0_inv_8x_unused)); |
| 3452 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), |
| 3453 | .in01(1'b1), |
| 3454 | .in10(1'b1), |
| 3455 | .in11(1'b1), |
| 3456 | .out(spare0_aoi22_4x_unused)); |
| 3457 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), |
| 3458 | .out(spare0_buf_8x_unused)); |
| 3459 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), |
| 3460 | .in01(1'b1), |
| 3461 | .in10(1'b1), |
| 3462 | .in11(1'b1), |
| 3463 | .out(spare0_oai22_4x_unused)); |
| 3464 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), |
| 3465 | .out(spare0_inv_16x_unused)); |
| 3466 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), |
| 3467 | .in1(1'b1), |
| 3468 | .out(spare0_nand2_16x_unused)); |
| 3469 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), |
| 3470 | .in1(1'b0), |
| 3471 | .in2(1'b0), |
| 3472 | .out(spare0_nor3_4x_unused)); |
| 3473 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), |
| 3474 | .in1(1'b1), |
| 3475 | .out(spare0_nand2_8x_unused)); |
| 3476 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), |
| 3477 | .out(spare0_buf_16x_unused)); |
| 3478 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), |
| 3479 | .in1(1'b0), |
| 3480 | .out(spare0_nor2_16x_unused)); |
| 3481 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), |
| 3482 | .out(spare0_inv_32x_unused)); |
| 3483 | |
| 3484 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), |
| 3485 | .siclk(siclk), |
| 3486 | .soclk(soclk), |
| 3487 | .si(si_1), |
| 3488 | .so(so_1), |
| 3489 | .d(1'b0), |
| 3490 | .q(spare1_flop_unused)); |
| 3491 | assign si_1 = so_0; |
| 3492 | |
| 3493 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), |
| 3494 | .out(spare1_buf_32x_unused)); |
| 3495 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), |
| 3496 | .in1(1'b1), |
| 3497 | .in2(1'b1), |
| 3498 | .out(spare1_nand3_8x_unused)); |
| 3499 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), |
| 3500 | .out(spare1_inv_8x_unused)); |
| 3501 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), |
| 3502 | .in01(1'b1), |
| 3503 | .in10(1'b1), |
| 3504 | .in11(1'b1), |
| 3505 | .out(spare1_aoi22_4x_unused)); |
| 3506 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), |
| 3507 | .out(spare1_buf_8x_unused)); |
| 3508 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), |
| 3509 | .in01(1'b1), |
| 3510 | .in10(1'b1), |
| 3511 | .in11(1'b1), |
| 3512 | .out(spare1_oai22_4x_unused)); |
| 3513 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), |
| 3514 | .out(spare1_inv_16x_unused)); |
| 3515 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), |
| 3516 | .in1(1'b1), |
| 3517 | .out(spare1_nand2_16x_unused)); |
| 3518 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), |
| 3519 | .in1(1'b0), |
| 3520 | .in2(1'b0), |
| 3521 | .out(spare1_nor3_4x_unused)); |
| 3522 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), |
| 3523 | .in1(1'b1), |
| 3524 | .out(spare1_nand2_8x_unused)); |
| 3525 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), |
| 3526 | .out(spare1_buf_16x_unused)); |
| 3527 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), |
| 3528 | .in1(1'b0), |
| 3529 | .out(spare1_nor2_16x_unused)); |
| 3530 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), |
| 3531 | .out(spare1_inv_32x_unused)); |
| 3532 | |
| 3533 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), |
| 3534 | .siclk(siclk), |
| 3535 | .soclk(soclk), |
| 3536 | .si(si_2), |
| 3537 | .so(so_2), |
| 3538 | .d(1'b0), |
| 3539 | .q(spare2_flop_unused)); |
| 3540 | assign si_2 = so_1; |
| 3541 | |
| 3542 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), |
| 3543 | .out(spare2_buf_32x_unused)); |
| 3544 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), |
| 3545 | .in1(1'b1), |
| 3546 | .in2(1'b1), |
| 3547 | .out(spare2_nand3_8x_unused)); |
| 3548 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), |
| 3549 | .out(spare2_inv_8x_unused)); |
| 3550 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), |
| 3551 | .in01(1'b1), |
| 3552 | .in10(1'b1), |
| 3553 | .in11(1'b1), |
| 3554 | .out(spare2_aoi22_4x_unused)); |
| 3555 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), |
| 3556 | .out(spare2_buf_8x_unused)); |
| 3557 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), |
| 3558 | .in01(1'b1), |
| 3559 | .in10(1'b1), |
| 3560 | .in11(1'b1), |
| 3561 | .out(spare2_oai22_4x_unused)); |
| 3562 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), |
| 3563 | .out(spare2_inv_16x_unused)); |
| 3564 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), |
| 3565 | .in1(1'b1), |
| 3566 | .out(spare2_nand2_16x_unused)); |
| 3567 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), |
| 3568 | .in1(1'b0), |
| 3569 | .in2(1'b0), |
| 3570 | .out(spare2_nor3_4x_unused)); |
| 3571 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), |
| 3572 | .in1(1'b1), |
| 3573 | .out(spare2_nand2_8x_unused)); |
| 3574 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), |
| 3575 | .out(spare2_buf_16x_unused)); |
| 3576 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), |
| 3577 | .in1(1'b0), |
| 3578 | .out(spare2_nor2_16x_unused)); |
| 3579 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), |
| 3580 | .out(spare2_inv_32x_unused)); |
| 3581 | |
| 3582 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), |
| 3583 | .siclk(siclk), |
| 3584 | .soclk(soclk), |
| 3585 | .si(si_3), |
| 3586 | .so(so_3), |
| 3587 | .d(1'b0), |
| 3588 | .q(spare3_flop_unused)); |
| 3589 | assign si_3 = so_2; |
| 3590 | |
| 3591 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), |
| 3592 | .out(spare3_buf_32x_unused)); |
| 3593 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), |
| 3594 | .in1(1'b1), |
| 3595 | .in2(1'b1), |
| 3596 | .out(spare3_nand3_8x_unused)); |
| 3597 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), |
| 3598 | .out(spare3_inv_8x_unused)); |
| 3599 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), |
| 3600 | .in01(1'b1), |
| 3601 | .in10(1'b1), |
| 3602 | .in11(1'b1), |
| 3603 | .out(spare3_aoi22_4x_unused)); |
| 3604 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), |
| 3605 | .out(spare3_buf_8x_unused)); |
| 3606 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), |
| 3607 | .in01(1'b1), |
| 3608 | .in10(1'b1), |
| 3609 | .in11(1'b1), |
| 3610 | .out(spare3_oai22_4x_unused)); |
| 3611 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), |
| 3612 | .out(spare3_inv_16x_unused)); |
| 3613 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), |
| 3614 | .in1(1'b1), |
| 3615 | .out(spare3_nand2_16x_unused)); |
| 3616 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), |
| 3617 | .in1(1'b0), |
| 3618 | .in2(1'b0), |
| 3619 | .out(spare3_nor3_4x_unused)); |
| 3620 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), |
| 3621 | .in1(1'b1), |
| 3622 | .out(spare3_nand2_8x_unused)); |
| 3623 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), |
| 3624 | .out(spare3_buf_16x_unused)); |
| 3625 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), |
| 3626 | .in1(1'b0), |
| 3627 | .out(spare3_nor2_16x_unused)); |
| 3628 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), |
| 3629 | .out(spare3_inv_32x_unused)); |
| 3630 | |
| 3631 | cl_sc1_msff_8x spare4_flop (.l1clk(l1clk), |
| 3632 | .siclk(siclk), |
| 3633 | .soclk(soclk), |
| 3634 | .si(si_4), |
| 3635 | .so(so_4), |
| 3636 | .d(1'b0), |
| 3637 | .q(spare4_flop_unused)); |
| 3638 | assign si_4 = so_3; |
| 3639 | |
| 3640 | cl_u1_buf_32x spare4_buf_32x (.in(1'b1), |
| 3641 | .out(spare4_buf_32x_unused)); |
| 3642 | cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1), |
| 3643 | .in1(1'b1), |
| 3644 | .in2(1'b1), |
| 3645 | .out(spare4_nand3_8x_unused)); |
| 3646 | cl_u1_inv_8x spare4_inv_8x (.in(1'b1), |
| 3647 | .out(spare4_inv_8x_unused)); |
| 3648 | cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1), |
| 3649 | .in01(1'b1), |
| 3650 | .in10(1'b1), |
| 3651 | .in11(1'b1), |
| 3652 | .out(spare4_aoi22_4x_unused)); |
| 3653 | cl_u1_buf_8x spare4_buf_8x (.in(1'b1), |
| 3654 | .out(spare4_buf_8x_unused)); |
| 3655 | cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1), |
| 3656 | .in01(1'b1), |
| 3657 | .in10(1'b1), |
| 3658 | .in11(1'b1), |
| 3659 | .out(spare4_oai22_4x_unused)); |
| 3660 | cl_u1_inv_16x spare4_inv_16x (.in(1'b1), |
| 3661 | .out(spare4_inv_16x_unused)); |
| 3662 | cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1), |
| 3663 | .in1(1'b1), |
| 3664 | .out(spare4_nand2_16x_unused)); |
| 3665 | cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0), |
| 3666 | .in1(1'b0), |
| 3667 | .in2(1'b0), |
| 3668 | .out(spare4_nor3_4x_unused)); |
| 3669 | cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1), |
| 3670 | .in1(1'b1), |
| 3671 | .out(spare4_nand2_8x_unused)); |
| 3672 | cl_u1_buf_16x spare4_buf_16x (.in(1'b1), |
| 3673 | .out(spare4_buf_16x_unused)); |
| 3674 | cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0), |
| 3675 | .in1(1'b0), |
| 3676 | .out(spare4_nor2_16x_unused)); |
| 3677 | cl_u1_inv_32x spare4_inv_32x (.in(1'b1), |
| 3678 | .out(spare4_inv_32x_unused)); |
| 3679 | |
| 3680 | cl_sc1_msff_8x spare5_flop (.l1clk(l1clk), |
| 3681 | .siclk(siclk), |
| 3682 | .soclk(soclk), |
| 3683 | .si(si_5), |
| 3684 | .so(so_5), |
| 3685 | .d(1'b0), |
| 3686 | .q(spare5_flop_unused)); |
| 3687 | assign si_5 = so_4; |
| 3688 | |
| 3689 | cl_u1_buf_32x spare5_buf_32x (.in(1'b1), |
| 3690 | .out(spare5_buf_32x_unused)); |
| 3691 | cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1), |
| 3692 | .in1(1'b1), |
| 3693 | .in2(1'b1), |
| 3694 | .out(spare5_nand3_8x_unused)); |
| 3695 | cl_u1_inv_8x spare5_inv_8x (.in(1'b1), |
| 3696 | .out(spare5_inv_8x_unused)); |
| 3697 | cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1), |
| 3698 | .in01(1'b1), |
| 3699 | .in10(1'b1), |
| 3700 | .in11(1'b1), |
| 3701 | .out(spare5_aoi22_4x_unused)); |
| 3702 | cl_u1_buf_8x spare5_buf_8x (.in(1'b1), |
| 3703 | .out(spare5_buf_8x_unused)); |
| 3704 | cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1), |
| 3705 | .in01(1'b1), |
| 3706 | .in10(1'b1), |
| 3707 | .in11(1'b1), |
| 3708 | .out(spare5_oai22_4x_unused)); |
| 3709 | cl_u1_inv_16x spare5_inv_16x (.in(1'b1), |
| 3710 | .out(spare5_inv_16x_unused)); |
| 3711 | cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1), |
| 3712 | .in1(1'b1), |
| 3713 | .out(spare5_nand2_16x_unused)); |
| 3714 | cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0), |
| 3715 | .in1(1'b0), |
| 3716 | .in2(1'b0), |
| 3717 | .out(spare5_nor3_4x_unused)); |
| 3718 | cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1), |
| 3719 | .in1(1'b1), |
| 3720 | .out(spare5_nand2_8x_unused)); |
| 3721 | cl_u1_buf_16x spare5_buf_16x (.in(1'b1), |
| 3722 | .out(spare5_buf_16x_unused)); |
| 3723 | cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0), |
| 3724 | .in1(1'b0), |
| 3725 | .out(spare5_nor2_16x_unused)); |
| 3726 | cl_u1_inv_32x spare5_inv_32x (.in(1'b1), |
| 3727 | .out(spare5_inv_32x_unused)); |
| 3728 | assign scan_out = so_5; |
| 3729 | |
| 3730 | |
| 3731 | |
| 3732 | endmodule |
| 3733 | |