| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: fgu_fad_dp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module fgu_fad_dp ( |
| 36 | dec_frf_r2_addr_d, |
| 37 | dec_frf_r1_32b_d, |
| 38 | dec_frf_r2_32b_d, |
| 39 | dec_frf_r1_odd32b_d, |
| 40 | dec_frf_r2_odd32b_d, |
| 41 | fgu_fld_fcc_fx3, |
| 42 | lsu_fgu_fld_data_b, |
| 43 | lsu_fgu_fld_addr_b, |
| 44 | lsu_fgu_fld_vld_w, |
| 45 | lsu_fgu_fld_b, |
| 46 | lsu_fgu_fld_tid_b, |
| 47 | lsu_fgu_fld_32b_b, |
| 48 | lsu_fgu_fld_odd32b_b, |
| 49 | lsu_fgu_fsr_load_b, |
| 50 | fgu_lsu_fst_data_fx1, |
| 51 | exu_fgu_rs1_e, |
| 52 | exu_fgu_rs2_e, |
| 53 | fac_frf_r1_addr_e, |
| 54 | fac_tid_e, |
| 55 | fac_aman_fmt_sel_e, |
| 56 | fac_bman_fmt_sel_e, |
| 57 | fac_fst_fmt_sel_fx1, |
| 58 | fac_exu_src_e, |
| 59 | fac_w1_addr_fb, |
| 60 | fac_fpd_addr_fb, |
| 61 | fac_w1_32b_fb, |
| 62 | fac_fpd_32b_fb, |
| 63 | fac_w1_odd32b_fb, |
| 64 | fac_fpd_odd32b_fb, |
| 65 | fac_w1_tid_fb, |
| 66 | fac_fpd_tid_fb, |
| 67 | fac_fsr0_sel_fw, |
| 68 | fac_fsr1_sel_fw, |
| 69 | fac_fsr2_sel_fw, |
| 70 | fac_fsr3_sel_fw, |
| 71 | fac_fsr4_sel_fw, |
| 72 | fac_fsr5_sel_fw, |
| 73 | fac_fsr6_sel_fw, |
| 74 | fac_fsr7_sel_fw, |
| 75 | main_clken, |
| 76 | asi_clken, |
| 77 | coreon_clken, |
| 78 | fad_w2_addr_fw1_b4, |
| 79 | fad_w2_tid_fw1, |
| 80 | fad_w2_vld_fw1, |
| 81 | fpc_w1_vld_fb, |
| 82 | fpc_w1_ul_vld_fb, |
| 83 | fpc_fsr_w1_result_fw, |
| 84 | fpc_fsr_w2_result_fw, |
| 85 | fpc_fpd_exp_res, |
| 86 | fpc_fpd_sign_res, |
| 87 | fpc_fpd_const_sel, |
| 88 | fpc_fcc_fw, |
| 89 | fpc_fpd_ieee_trap_fb, |
| 90 | fpc_fpd_unfin_fb, |
| 91 | fad_gsr_imirnd_fx1, |
| 92 | frf_r1_data_e, |
| 93 | frf_r2_data_e, |
| 94 | fad_w1_tid_fw, |
| 95 | fad_w1_vld_fw, |
| 96 | fad_w2_result_fw, |
| 97 | fad_w2_addr_fw, |
| 98 | fad_w2_tid_fw, |
| 99 | fad_w2_vld_fw, |
| 100 | fad_nombi_w2_result_fw, |
| 101 | fad_r1_byp_hit_fx1, |
| 102 | fad_r2_byp_hit_fx1, |
| 103 | fad_i_parity_2e_fx1, |
| 104 | fad_i_parity_2o_fx1, |
| 105 | fad_i_parity_1e_fx1, |
| 106 | fad_i_parity_1o_fx1, |
| 107 | fpf_w1_result_fb, |
| 108 | fad_rs1_fmt_fx1, |
| 109 | fad_rs2_fmt_fx1, |
| 110 | fad_rs1_fx1, |
| 111 | fad_rs2_fx1, |
| 112 | fad_r1_odd32b_fx1, |
| 113 | fad_fsr_rd_fx1, |
| 114 | fad_fsr_tem_fx1, |
| 115 | fad_fsr_ns_fx1, |
| 116 | fdd_result_rep0, |
| 117 | fdc_finish_fltd_early_rep0, |
| 118 | fdc_finish_flts_early_rep0, |
| 119 | fgd_rngl_cdbus_3f, |
| 120 | l2clk, |
| 121 | scan_in, |
| 122 | spc_aclk_wmr, |
| 123 | wmr_scan_in, |
| 124 | lb_scan_en_wmr, |
| 125 | tcu_pce_ov, |
| 126 | spc_aclk, |
| 127 | spc_bclk, |
| 128 | tcu_scan_en, |
| 129 | tcu_se_scancollar_out, |
| 130 | mbi_run, |
| 131 | mbi_frf_write_en, |
| 132 | fac_mbist_addr_1f, |
| 133 | fec_mbist_wdata_1f, |
| 134 | fec_mbist_wdata_3f, |
| 135 | fad_mbist_cmp64_fx1, |
| 136 | scan_out, |
| 137 | wmr_scan_out, |
| 138 | fgu_rngl_cdbus); |
| 139 | wire stop; |
| 140 | wire se; |
| 141 | wire pce_ov; |
| 142 | wire siclk; |
| 143 | wire soclk; |
| 144 | wire e_01_scanin; |
| 145 | wire e_01_scanout; |
| 146 | wire [1:0] fpd_vld_fb; |
| 147 | wire r1_odd32b_e; |
| 148 | wire [4:0] r2_addr_e; |
| 149 | wire r1_byp_hit_e; |
| 150 | wire r2_byp_hit_e; |
| 151 | wire w2_32b_fw; |
| 152 | wire w2_odd32b_fw; |
| 153 | wire [3:0] w2_addr_fw1; |
| 154 | wire [1:0] fpd_vld_fw; |
| 155 | wire [4:0] w1_addr_fw; |
| 156 | wire w1_32b_fw; |
| 157 | wire w1_odd32b_fw; |
| 158 | wire w1_ul_vld_fw; |
| 159 | wire w2_32b_fw1; |
| 160 | wire w2_odd32b_fw1; |
| 161 | wire div_finish_flts_fb; |
| 162 | wire div_finish_fltd_fb; |
| 163 | wire mbist_run_1f; |
| 164 | wire mbist_frf_write_en_1f; |
| 165 | wire [4:0] aman_fmt_sel_fx1; |
| 166 | wire [4:0] bman_fmt_sel_fx1; |
| 167 | wire e_01_extra_scanin; |
| 168 | wire e_01_extra_scanout; |
| 169 | wire [4:0] w2_addr_fb; |
| 170 | wire [2:0] w2_tid_fb; |
| 171 | wire w2_32b_fb; |
| 172 | wire w2_odd32b_fb; |
| 173 | wire [1:0] pre_fld_vld_fb; |
| 174 | wire fld_fw; |
| 175 | wire r1_32b_e; |
| 176 | wire r2_32b_e; |
| 177 | wire r2_odd32b_e; |
| 178 | wire [4:0] w2_addr_fw; |
| 179 | wire [2:0] w2_tid_fw; |
| 180 | wire [1:0] pre_fld_vld_fw; |
| 181 | wire fld_fw1; |
| 182 | wire q2_r1_32b_e; |
| 183 | wire q2_r1_odd32b_e; |
| 184 | wire q3_r2_32b_e; |
| 185 | wire q3_r2_odd32b_e; |
| 186 | wire q6_r1_32b_e; |
| 187 | wire q6_r1_odd32b_e; |
| 188 | wire q7_r2_32b_e; |
| 189 | wire q7_r2_odd32b_e; |
| 190 | wire q8_r2_32b_e; |
| 191 | wire q8_r2_odd32b_e; |
| 192 | wire q9_r1_32b_e; |
| 193 | wire q9_r1_odd32b_e; |
| 194 | wire r1_w1_hit_fb; |
| 195 | wire r1_fld_hit_fb; |
| 196 | wire r1_w1_hit_fw; |
| 197 | wire r1_w2_hit_fw; |
| 198 | wire r1_w2_hit_fw1; |
| 199 | wire r2_w1_hit_fb; |
| 200 | wire r2_fld_hit_fb; |
| 201 | wire r2_w1_hit_fw; |
| 202 | wire r2_w2_hit_fw; |
| 203 | wire r2_w2_hit_fw1; |
| 204 | wire i1_r1_byp_hit_e; |
| 205 | wire i2_r1_byp_hit_e; |
| 206 | wire i1_r2_byp_hit_e; |
| 207 | wire i2_r2_byp_hit_e; |
| 208 | wire fx1_rs1byp_scanin; |
| 209 | wire fx1_rs1byp_scanout; |
| 210 | wire [63:0] w2_result_fw1; |
| 211 | wire [63:0] w1_result_fw; |
| 212 | wire fx1_rs2byp_scanin; |
| 213 | wire fx1_rs2byp_scanout; |
| 214 | wire [27:0] fsr0_fx1; |
| 215 | wire [11:0] fsr0_fttexc_merged_fw; |
| 216 | wire fx1_fsr0_wmr_scanin; |
| 217 | wire fx1_fsr0_wmr_scanout; |
| 218 | wire [27:0] ldfsr_data_fw; |
| 219 | wire [27:0] fsr1_fx1; |
| 220 | wire [11:0] fsr1_fttexc_merged_fw; |
| 221 | wire fx1_fsr1_wmr_scanin; |
| 222 | wire fx1_fsr1_wmr_scanout; |
| 223 | wire [27:0] fsr2_fx1; |
| 224 | wire [11:0] fsr2_fttexc_merged_fw; |
| 225 | wire fx1_fsr2_wmr_scanin; |
| 226 | wire fx1_fsr2_wmr_scanout; |
| 227 | wire [27:0] fsr3_fx1; |
| 228 | wire [11:0] fsr3_fttexc_merged_fw; |
| 229 | wire fx1_fsr3_wmr_scanin; |
| 230 | wire fx1_fsr3_wmr_scanout; |
| 231 | wire [27:0] fsr4_fx1; |
| 232 | wire [11:0] fsr4_fttexc_merged_fw; |
| 233 | wire fx1_fsr4_wmr_scanin; |
| 234 | wire fx1_fsr4_wmr_scanout; |
| 235 | wire [27:0] fsr5_fx1; |
| 236 | wire [11:0] fsr5_fttexc_merged_fw; |
| 237 | wire fx1_fsr5_wmr_scanin; |
| 238 | wire fx1_fsr5_wmr_scanout; |
| 239 | wire [27:0] fsr6_fx1; |
| 240 | wire [11:0] fsr6_fttexc_merged_fw; |
| 241 | wire fx1_fsr6_wmr_scanin; |
| 242 | wire fx1_fsr6_wmr_scanout; |
| 243 | wire [27:0] fsr7_fx1; |
| 244 | wire [11:0] fsr7_fttexc_merged_fw; |
| 245 | wire fx1_fsr7_wmr_scanin; |
| 246 | wire fx1_fsr7_wmr_scanout; |
| 247 | wire flop_rng1_4f_scanin; |
| 248 | wire flop_rng1_4f_scanout; |
| 249 | wire [62:0] rngl_cdbus_4f; |
| 250 | wire flop_rng0_4f_scanin; |
| 251 | wire flop_rng0_4f_scanout; |
| 252 | wire fx1_fsr_scanin; |
| 253 | wire fx1_fsr_scanout; |
| 254 | wire [1:0] fsr_ftt_fx1; |
| 255 | wire [4:0] fsr_aexc_fx1; |
| 256 | wire [4:0] fsr_cexc_fx1; |
| 257 | wire [1:0] fsr_fcc3_fx1; |
| 258 | wire [1:0] fsr_fcc2_fx1; |
| 259 | wire [1:0] fsr_fcc1_fx1; |
| 260 | wire [1:0] fsr_fcc0_fx1; |
| 261 | wire [63:0] rs1_fmt_fx1; |
| 262 | wire [63:0] rs2_fmt_fx1; |
| 263 | wire [63:0] fst_data_fx1; |
| 264 | wire [1:0] pre_fpd_vld_fb; |
| 265 | wire fpd_trap_fb; |
| 266 | wire lsu_fgu_fld_32b_b_; |
| 267 | wire lsu_fgu_fld_odd32b_b_; |
| 268 | wire lsu_fgu_fsr_load_b_; |
| 269 | wire fpd_trap_fb_; |
| 270 | wire fac_fpd_odd32b_fb_; |
| 271 | wire fld_w2_even_en_fb; |
| 272 | wire fld_w2_odd_en_fb; |
| 273 | wire mbist_run_1f_; |
| 274 | wire div_finish_flts_even_fb; |
| 275 | wire div_finish_flts_odd_fb; |
| 276 | wire fpd_vld_odd32b_fb; |
| 277 | wire [62:11] q_fdd_result_rep0; |
| 278 | wire [63:0] w2_result_fb; |
| 279 | wire fw_w2data_scanin; |
| 280 | wire fw_w2data_scanout; |
| 281 | wire fw_w1_scanin; |
| 282 | wire fw_w1_scanout; |
| 283 | wire fw_ldfsr_scanin; |
| 284 | wire fw_ldfsr_scanout; |
| 285 | wire [2:0] i_w2_tid_fw; |
| 286 | wire [4:0] i_w2_addr_fw; |
| 287 | wire fw1_w2data_scanin; |
| 288 | wire fw1_w2data_scanout; |
| 289 | |
| 290 | |
| 291 | |
| 292 | // ---------------------------------------------------------------------------- |
| 293 | // Interface with DEC |
| 294 | // ---------------------------------------------------------------------------- |
| 295 | |
| 296 | input [4:0] dec_frf_r2_addr_d; |
| 297 | input dec_frf_r1_32b_d; |
| 298 | input dec_frf_r2_32b_d; |
| 299 | input dec_frf_r1_odd32b_d; |
| 300 | input dec_frf_r2_odd32b_d; |
| 301 | |
| 302 | output [7:0] fgu_fld_fcc_fx3; // ldfsr fcc data {fcc3[1:0], fcc2[1:0], fcc1[1:0], fcc0[1:0]} |
| 303 | |
| 304 | // ---------------------------------------------------------------------------- |
| 305 | // Interface with LSU |
| 306 | // ---------------------------------------------------------------------------- |
| 307 | |
| 308 | input [63:0] lsu_fgu_fld_data_b; |
| 309 | input [4:0] lsu_fgu_fld_addr_b; |
| 310 | input lsu_fgu_fld_vld_w; |
| 311 | input lsu_fgu_fld_b; |
| 312 | input [2:0] lsu_fgu_fld_tid_b; |
| 313 | input lsu_fgu_fld_32b_b; |
| 314 | input lsu_fgu_fld_odd32b_b; |
| 315 | input lsu_fgu_fsr_load_b; |
| 316 | |
| 317 | output [63:0] fgu_lsu_fst_data_fx1; |
| 318 | |
| 319 | // ---------------------------------------------------------------------------- |
| 320 | // Interface with EXU |
| 321 | // ---------------------------------------------------------------------------- |
| 322 | |
| 323 | input [63:0] exu_fgu_rs1_e; |
| 324 | input [63:0] exu_fgu_rs2_e; |
| 325 | |
| 326 | // ---------------------------------------------------------------------------- |
| 327 | // Interface with FAC |
| 328 | // ---------------------------------------------------------------------------- |
| 329 | |
| 330 | input [4:0] fac_frf_r1_addr_e; |
| 331 | input [2:0] fac_tid_e; |
| 332 | input [4:0] fac_aman_fmt_sel_e; // aop mantissa format mux select |
| 333 | input [4:0] fac_bman_fmt_sel_e; // bop mantissa format mux select |
| 334 | input [3:0] fac_fst_fmt_sel_fx1; // store format mux select |
| 335 | input fac_exu_src_e; |
| 336 | |
| 337 | input [4:0] fac_w1_addr_fb; // FRF w1 write addr |
| 338 | input [4:0] fac_fpd_addr_fb; // FRF w2 write addr (div/sqrt) |
| 339 | input fac_w1_32b_fb; // FRF w1 is 32-bit dest |
| 340 | input fac_fpd_32b_fb; // FRF w2 is 32-bit dest (div/sqrt) |
| 341 | input fac_w1_odd32b_fb; // FRF w1 is odd 32-bit dest (32 LSBs) |
| 342 | input fac_fpd_odd32b_fb; // FRF w2 is odd 32-bit dest (32 LSBs) (div/sqrt) |
| 343 | |
| 344 | input [2:0] fac_w1_tid_fb; // FRF w1 TID |
| 345 | input [2:0] fac_fpd_tid_fb; // FRF w2 TID (div/sqrt) |
| 346 | |
| 347 | input [5:0] fac_fsr0_sel_fw; |
| 348 | input [5:0] fac_fsr1_sel_fw; |
| 349 | input [5:0] fac_fsr2_sel_fw; |
| 350 | input [5:0] fac_fsr3_sel_fw; |
| 351 | input [5:0] fac_fsr4_sel_fw; |
| 352 | input [5:0] fac_fsr5_sel_fw; |
| 353 | input [5:0] fac_fsr6_sel_fw; |
| 354 | input [5:0] fac_fsr7_sel_fw; |
| 355 | |
| 356 | input main_clken; // main clken |
| 357 | input asi_clken; // asi clken: controls ASI ring stage flops in fgd/fad |
| 358 | input coreon_clken; // controls all "free running" flops |
| 359 | |
| 360 | output fad_w2_addr_fw1_b4; // FRF w2 write addr (LSU->FRF path, |
| 361 | output [2:0] fad_w2_tid_fw1; // FRF w2 write TID delayed to fw1) |
| 362 | output [1:0] fad_w2_vld_fw1; // FRF w2 write valid (qualified) |
| 363 | |
| 364 | // ---------------------------------------------------------------------------- |
| 365 | // Interface with FPC |
| 366 | // ---------------------------------------------------------------------------- |
| 367 | |
| 368 | input [1:0] fpc_w1_vld_fb; // FRF w1 write valid (qualified), [63:32],[31:0] |
| 369 | input fpc_w1_ul_vld_fb; // FRF w1 write valid (qualified), upper or lower |
| 370 | input [11:0] fpc_fsr_w1_result_fw; // FSR w1 write data {ftt,aexc,cexc} |
| 371 | input [11:0] fpc_fsr_w2_result_fw; // FSR w2 write data {ftt,aexc,cexc} |
| 372 | input [10:0] fpc_fpd_exp_res; // FPD exponent result |
| 373 | input fpc_fpd_sign_res; // FPD sign result |
| 374 | input [1:0] fpc_fpd_const_sel; // 10=ones frac, 01=fdd frac, 00=zero frac |
| 375 | input [1:0] fpc_fcc_fw; |
| 376 | input fpc_fpd_ieee_trap_fb; |
| 377 | input fpc_fpd_unfin_fb; |
| 378 | |
| 379 | // ---------------------------------------------------------------------------- |
| 380 | // Interface with FSD |
| 381 | // ---------------------------------------------------------------------------- |
| 382 | |
| 383 | output [2:0] fad_gsr_imirnd_fx1; // {GSR.im,GSR.irnd[1:0]} |
| 384 | |
| 385 | // ---------------------------------------------------------------------------- |
| 386 | // Interface with FRF |
| 387 | // ---------------------------------------------------------------------------- |
| 388 | |
| 389 | input [63:0] frf_r1_data_e; // FRF rs1 read data |
| 390 | input [63:0] frf_r2_data_e; // FRF rs2 read data |
| 391 | |
| 392 | output [2:0] fad_w1_tid_fw; // FRF w1 write TID |
| 393 | output [1:0] fad_w1_vld_fw; // FRF w1 write valid (qualified) |
| 394 | |
| 395 | output [63:0] fad_w2_result_fw; // FRF w2 write data for FRF |
| 396 | output [4:0] fad_w2_addr_fw; // FRF w2 write addr |
| 397 | output [2:0] fad_w2_tid_fw; // FRF w2 write TID (LSU->FRF path, |
| 398 | output [1:0] fad_w2_vld_fw; // FRF w2 write valid delayed to fw) |
| 399 | |
| 400 | // ---------------------------------------------------------------------------- |
| 401 | // Interface with FEC |
| 402 | // ---------------------------------------------------------------------------- |
| 403 | |
| 404 | output [63:0] fad_nombi_w2_result_fw; // FRF w2 write data w/out mbist data muxed in |
| 405 | output fad_r1_byp_hit_fx1; // r1 is bypass data |
| 406 | output fad_r2_byp_hit_fx1; // r2 is bypass data |
| 407 | output fad_i_parity_2e_fx1; // partial ECC check (parity portion), rs2 even |
| 408 | output fad_i_parity_2o_fx1; // partial ECC check (parity portion), rs2 odd |
| 409 | output fad_i_parity_1e_fx1; // partial ECC check (parity portion), rs1 even |
| 410 | output fad_i_parity_1o_fx1; // partial ECC check (parity portion), rs1 odd |
| 411 | |
| 412 | // ---------------------------------------------------------------------------- |
| 413 | // Interface with FPF |
| 414 | // ---------------------------------------------------------------------------- |
| 415 | |
| 416 | input [63:0] fpf_w1_result_fb; // FPX result |
| 417 | output [63:0] fad_rs1_fmt_fx1; // rs1 formatted |
| 418 | output [63:0] fad_rs2_fmt_fx1; // rs2 formatted |
| 419 | output [63:0] fad_rs1_fx1; // rs1 unformatted |
| 420 | output [63:0] fad_rs2_fx1; // rs2 unformatted |
| 421 | output fad_r1_odd32b_fx1; |
| 422 | |
| 423 | output [1:0] fad_fsr_rd_fx1; |
| 424 | output [4:0] fad_fsr_tem_fx1; |
| 425 | output fad_fsr_ns_fx1; |
| 426 | |
| 427 | // ---------------------------------------------------------------------------- |
| 428 | // Interface with FDD |
| 429 | // ---------------------------------------------------------------------------- |
| 430 | |
| 431 | input [62:11] fdd_result_rep0; // FDD result |
| 432 | |
| 433 | // ---------------------------------------------------------------------------- |
| 434 | // Interface with FDC |
| 435 | // ---------------------------------------------------------------------------- |
| 436 | |
| 437 | input fdc_finish_fltd_early_rep0; |
| 438 | input fdc_finish_flts_early_rep0; |
| 439 | |
| 440 | // ---------------------------------------------------------------------------- |
| 441 | // Interface with FGD |
| 442 | // ---------------------------------------------------------------------------- |
| 443 | |
| 444 | input [62:0] fgd_rngl_cdbus_3f; |
| 445 | |
| 446 | // ---------------------------------------------------------------------------- |
| 447 | // Global Signals |
| 448 | // ---------------------------------------------------------------------------- |
| 449 | |
| 450 | input l2clk; // clock input |
| 451 | input scan_in; |
| 452 | input spc_aclk_wmr; |
| 453 | input wmr_scan_in; |
| 454 | input lb_scan_en_wmr; |
| 455 | input tcu_pce_ov; // scan signals |
| 456 | input spc_aclk; |
| 457 | input spc_bclk; |
| 458 | input tcu_scan_en; |
| 459 | input tcu_se_scancollar_out; |
| 460 | input mbi_run; // MBIST |
| 461 | input mbi_frf_write_en; // MBIST |
| 462 | input [7:0] fac_mbist_addr_1f; // MBIST |
| 463 | input [7:0] fec_mbist_wdata_1f; // MBIST |
| 464 | input [7:0] fec_mbist_wdata_3f; // MBIST |
| 465 | |
| 466 | output fad_mbist_cmp64_fx1; // MBIST |
| 467 | output scan_out; |
| 468 | output wmr_scan_out; |
| 469 | output [62:0] fgu_rngl_cdbus; // ASI local ring |
| 470 | |
| 471 | // scan renames |
| 472 | assign stop = 1'b0; |
| 473 | // end scan |
| 474 | |
| 475 | fgu_fad_dp_buff_macro__dbuff_32x__rep_1__width_4 test_rep0 ( |
| 476 | .din ({tcu_scan_en, tcu_pce_ov, spc_aclk, spc_bclk}), |
| 477 | .dout({se, pce_ov, siclk, soclk }) |
| 478 | ); |
| 479 | |
| 480 | |
| 481 | // ---------------------------------------------------------------------------- |
| 482 | // E stage |
| 483 | // ---------------------------------------------------------------------------- |
| 484 | |
| 485 | fgu_fad_dp_msff_macro__width_47 e_01 ( |
| 486 | .scan_in(e_01_scanin), |
| 487 | .scan_out(e_01_scanout), |
| 488 | .clk (l2clk), |
| 489 | .en (main_clken), |
| 490 | .din ({fad_w2_vld_fw[1:0], |
| 491 | fad_w2_addr_fw[3:0], |
| 492 | fpd_vld_fb[1:0], |
| 493 | fac_w1_addr_fb[4:0], |
| 494 | fac_w1_32b_fb, |
| 495 | fac_w1_odd32b_fb, |
| 496 | fac_w1_tid_fb[2:0], |
| 497 | fpc_w1_vld_fb[1:0], |
| 498 | fpc_w1_ul_vld_fb, |
| 499 | r1_odd32b_e, |
| 500 | r2_addr_e[1:0], |
| 501 | r2_addr_e[4], |
| 502 | r1_byp_hit_e, |
| 503 | r2_byp_hit_e, |
| 504 | fad_w2_addr_fw[4], |
| 505 | fad_w2_tid_fw[2:0], |
| 506 | w2_32b_fw, |
| 507 | w2_odd32b_fw, |
| 508 | fdc_finish_flts_early_rep0, |
| 509 | fdc_finish_fltd_early_rep0, |
| 510 | mbi_run, |
| 511 | mbi_frf_write_en, |
| 512 | fac_aman_fmt_sel_e[4:0], |
| 513 | fac_bman_fmt_sel_e[4:0]}), |
| 514 | .dout({fad_w2_vld_fw1[1:0], |
| 515 | w2_addr_fw1[3:0], |
| 516 | fpd_vld_fw[1:0], |
| 517 | w1_addr_fw[4:0], |
| 518 | w1_32b_fw, |
| 519 | w1_odd32b_fw, |
| 520 | fad_w1_tid_fw[2:0], |
| 521 | fad_w1_vld_fw[1:0], |
| 522 | w1_ul_vld_fw, |
| 523 | fad_r1_odd32b_fx1, |
| 524 | fad_gsr_imirnd_fx1[2:0], |
| 525 | fad_r1_byp_hit_fx1, |
| 526 | fad_r2_byp_hit_fx1, |
| 527 | fad_w2_addr_fw1_b4, |
| 528 | fad_w2_tid_fw1[2:0], |
| 529 | w2_32b_fw1, |
| 530 | w2_odd32b_fw1, |
| 531 | div_finish_flts_fb, |
| 532 | div_finish_fltd_fb, |
| 533 | mbist_run_1f, |
| 534 | mbist_frf_write_en_1f, |
| 535 | aman_fmt_sel_fx1[4:0], |
| 536 | bman_fmt_sel_fx1[4:0]}), |
| 537 | .se(se), |
| 538 | .siclk(siclk), |
| 539 | .soclk(soclk), |
| 540 | .pce_ov(pce_ov), |
| 541 | .stop(stop) |
| 542 | ); |
| 543 | |
| 544 | fgu_fad_dp_msff_macro__width_23 e_01_extra ( |
| 545 | .scan_in(e_01_extra_scanin), |
| 546 | .scan_out(e_01_extra_scanout), |
| 547 | .clk (l2clk), |
| 548 | .en (coreon_clken), |
| 549 | .din ({dec_frf_r2_addr_d[4:0], // requires free running clk or dec_fgu_decode_d en |
| 550 | dec_frf_r1_32b_d, // requires free running clk or dec_fgu_decode_d en |
| 551 | dec_frf_r2_32b_d, // requires free running clk or dec_fgu_decode_d en |
| 552 | dec_frf_r1_odd32b_d, // requires free running clk or dec_fgu_decode_d en |
| 553 | dec_frf_r2_odd32b_d, // requires free running clk or dec_fgu_decode_d en |
| 554 | w2_addr_fb[4:0], // requires free running clk |
| 555 | w2_tid_fb[2:0], // requires free running clk |
| 556 | w2_32b_fb, // requires free running clk |
| 557 | w2_odd32b_fb, // requires free running clk |
| 558 | pre_fld_vld_fb[1:0], // requires free running clk |
| 559 | lsu_fgu_fld_b, // requires free running clk |
| 560 | fld_fw}), // requires free running clk |
| 561 | .dout({ r2_addr_e[4:0], |
| 562 | r1_32b_e, |
| 563 | r2_32b_e, |
| 564 | r1_odd32b_e, |
| 565 | r2_odd32b_e, |
| 566 | w2_addr_fw[4:0], |
| 567 | w2_tid_fw[2:0], |
| 568 | w2_32b_fw, |
| 569 | w2_odd32b_fw, |
| 570 | pre_fld_vld_fw[1:0], |
| 571 | fld_fw, |
| 572 | fld_fw1}), |
| 573 | .se(se), |
| 574 | .siclk(siclk), |
| 575 | .soclk(soclk), |
| 576 | .pce_ov(pce_ov), |
| 577 | .stop(stop) |
| 578 | ); |
| 579 | |
| 580 | // ------------------------------------ |
| 581 | // Bypass detection |
| 582 | // |
| 583 | // ten compares total: |
| 584 | // r1_e == w1_fb |
| 585 | // r1_e == fld_fb |
| 586 | // r1_e == w1_fw |
| 587 | // r1_e == w2_fw |
| 588 | // r1_e == w2_fw1 |
| 589 | // r2_e == w1_fb |
| 590 | // r2_e == fld_fb |
| 591 | // r2_e == w1_fw |
| 592 | // r2_e == w2_fw |
| 593 | // r2_e == w2_fw1 |
| 594 | // ------------------------------------ |
| 595 | |
| 596 | // SP->DP bypass is not supported (evil-twin) |
| 597 | // DP->SP bypass is supported only for a DP load bypassing to a SP arith. |
| 598 | // DP arith. bypassing to SP arith. isn't supported due to IFU considerations. |
| 599 | // |
| 600 | // If 64b result and 32b source then "32b" and "odd32b" signals are don't care, |
| 601 | // force the source "32b" and "odd32b" signals to zero to match the 64b result's |
| 602 | // "32b" and "odd32b" signals |
| 603 | |
| 604 | fgu_fad_dp_and_macro__ports_2__width_2 and_q2 ( |
| 605 | .din0({lsu_fgu_fld_32b_b, lsu_fgu_fld_32b_b}), |
| 606 | .din1({ r1_32b_e, r1_odd32b_e }), |
| 607 | .dout({q2_r1_32b_e, q2_r1_odd32b_e }) |
| 608 | ); |
| 609 | |
| 610 | fgu_fad_dp_and_macro__ports_2__width_2 and_q3 ( |
| 611 | .din0({lsu_fgu_fld_32b_b, lsu_fgu_fld_32b_b}), |
| 612 | .din1({ r2_32b_e, r2_odd32b_e }), |
| 613 | .dout({q3_r2_32b_e, q3_r2_odd32b_e }) |
| 614 | ); |
| 615 | |
| 616 | fgu_fad_dp_and_macro__ports_2__width_2 and_q6 ( |
| 617 | .din0({w2_32b_fw, w2_32b_fw }), |
| 618 | .din1({ r1_32b_e, r1_odd32b_e}), |
| 619 | .dout({q6_r1_32b_e, q6_r1_odd32b_e}) |
| 620 | ); |
| 621 | |
| 622 | fgu_fad_dp_and_macro__ports_2__width_2 and_q7 ( |
| 623 | .din0({w2_32b_fw, w2_32b_fw }), |
| 624 | .din1({ r2_32b_e, r2_odd32b_e}), |
| 625 | .dout({q7_r2_32b_e, q7_r2_odd32b_e}) |
| 626 | ); |
| 627 | |
| 628 | fgu_fad_dp_and_macro__ports_2__width_2 and_q8 ( |
| 629 | .din0({w2_32b_fw1, w2_32b_fw1 }), |
| 630 | .din1({ r2_32b_e, r2_odd32b_e}), |
| 631 | .dout({q8_r2_32b_e, q8_r2_odd32b_e}) |
| 632 | ); |
| 633 | |
| 634 | fgu_fad_dp_and_macro__ports_2__width_2 and_q9 ( |
| 635 | .din0({w2_32b_fw1, w2_32b_fw1 }), |
| 636 | .din1({ r1_32b_e, r1_odd32b_e}), |
| 637 | .dout({q9_r1_32b_e, q9_r1_odd32b_e}) |
| 638 | ); |
| 639 | |
| 640 | fgu_fad_dp_cmp_macro__width_12 cmp_r1a ( |
| 641 | .din0({fac_frf_r1_addr_e[4:0], |
| 642 | fac_tid_e[2:0], |
| 643 | r1_32b_e, |
| 644 | r1_odd32b_e, |
| 645 | 1'b1, |
| 646 | mbist_run_1f}), |
| 647 | .din1({fac_w1_addr_fb[4:0], |
| 648 | fac_w1_tid_fb[2:0], |
| 649 | fac_w1_32b_fb, |
| 650 | fac_w1_odd32b_fb, |
| 651 | fpc_w1_ul_vld_fb, |
| 652 | 1'b0}), |
| 653 | .dout(r1_w1_hit_fb) |
| 654 | ); |
| 655 | |
| 656 | fgu_fad_dp_cmp_macro__width_12 cmp_r1b ( |
| 657 | .din0({fac_frf_r1_addr_e[4:0], |
| 658 | fac_tid_e[2:0], |
| 659 | q2_r1_32b_e, |
| 660 | q2_r1_odd32b_e, |
| 661 | 1'b1, |
| 662 | mbist_run_1f}), |
| 663 | .din1({lsu_fgu_fld_addr_b[4:0], |
| 664 | lsu_fgu_fld_tid_b[2:0], |
| 665 | lsu_fgu_fld_32b_b, |
| 666 | lsu_fgu_fld_odd32b_b, |
| 667 | lsu_fgu_fld_b, // load fsr is serializing, can't cause a fld_hit |
| 668 | 1'b0}), |
| 669 | .dout(r1_fld_hit_fb) |
| 670 | ); |
| 671 | |
| 672 | fgu_fad_dp_cmp_macro__width_12 cmp_r1c ( |
| 673 | .din0({fac_frf_r1_addr_e[4:0], |
| 674 | fac_tid_e[2:0], |
| 675 | r1_32b_e, |
| 676 | r1_odd32b_e, |
| 677 | 1'b1, |
| 678 | mbist_run_1f}), |
| 679 | .din1({w1_addr_fw[4:0], |
| 680 | fad_w1_tid_fw[2:0], |
| 681 | w1_32b_fw, |
| 682 | w1_odd32b_fw, |
| 683 | w1_ul_vld_fw, |
| 684 | 1'b0}), |
| 685 | .dout(r1_w1_hit_fw) |
| 686 | ); |
| 687 | |
| 688 | fgu_fad_dp_cmp_macro__width_12 cmp_r1d ( |
| 689 | .din0({fac_frf_r1_addr_e[4:0], |
| 690 | fac_tid_e[2:0], |
| 691 | q6_r1_32b_e, |
| 692 | q6_r1_odd32b_e, |
| 693 | 1'b1, |
| 694 | mbist_run_1f}), |
| 695 | .din1({fad_w2_addr_fw[4:0], |
| 696 | fad_w2_tid_fw[2:0], |
| 697 | w2_32b_fw, |
| 698 | w2_odd32b_fw, |
| 699 | fld_fw, // load fsr is serializing, can't cause a fld_hit |
| 700 | 1'b0}), |
| 701 | .dout(r1_w2_hit_fw) |
| 702 | ); |
| 703 | |
| 704 | fgu_fad_dp_cmp_macro__width_12 cmp_r1e ( |
| 705 | .din0({fac_frf_r1_addr_e[4:0], |
| 706 | fac_tid_e[2:0], |
| 707 | q9_r1_32b_e, |
| 708 | q9_r1_odd32b_e, |
| 709 | 1'b1, |
| 710 | mbist_run_1f}), |
| 711 | .din1({fad_w2_addr_fw1_b4, w2_addr_fw1[3:0], |
| 712 | fad_w2_tid_fw1[2:0], |
| 713 | w2_32b_fw1, |
| 714 | w2_odd32b_fw1, |
| 715 | fld_fw1, // load fsr is serializing, can't cause a fld_hit |
| 716 | 1'b0}), |
| 717 | .dout(r1_w2_hit_fw1) |
| 718 | ); |
| 719 | |
| 720 | fgu_fad_dp_cmp_macro__width_12 cmp_r2a ( |
| 721 | .din0({r2_addr_e[4:0], |
| 722 | fac_tid_e[2:0], |
| 723 | r2_32b_e, |
| 724 | r2_odd32b_e, |
| 725 | 1'b1, |
| 726 | 1'b0}), |
| 727 | .din1({fac_w1_addr_fb[4:0], |
| 728 | fac_w1_tid_fb[2:0], |
| 729 | fac_w1_32b_fb, |
| 730 | fac_w1_odd32b_fb, |
| 731 | fpc_w1_ul_vld_fb, |
| 732 | 1'b0}), |
| 733 | .dout(r2_w1_hit_fb) |
| 734 | ); |
| 735 | |
| 736 | fgu_fad_dp_cmp_macro__width_12 cmp_r2b ( |
| 737 | .din0({r2_addr_e[4:0], |
| 738 | fac_tid_e[2:0], |
| 739 | q3_r2_32b_e, |
| 740 | q3_r2_odd32b_e, |
| 741 | 1'b1, |
| 742 | 1'b0}), |
| 743 | .din1({lsu_fgu_fld_addr_b[4:0], |
| 744 | lsu_fgu_fld_tid_b[2:0], |
| 745 | lsu_fgu_fld_32b_b, |
| 746 | lsu_fgu_fld_odd32b_b, |
| 747 | lsu_fgu_fld_b, // load fsr is serializing, can't cause a fld_hit |
| 748 | 1'b0}), |
| 749 | .dout(r2_fld_hit_fb) |
| 750 | ); |
| 751 | |
| 752 | fgu_fad_dp_cmp_macro__width_12 cmp_r2c ( |
| 753 | .din0({r2_addr_e[4:0], |
| 754 | fac_tid_e[2:0], |
| 755 | r2_32b_e, |
| 756 | r2_odd32b_e, |
| 757 | 1'b1, |
| 758 | 1'b0}), |
| 759 | .din1({w1_addr_fw[4:0], |
| 760 | fad_w1_tid_fw[2:0], |
| 761 | w1_32b_fw, |
| 762 | w1_odd32b_fw, |
| 763 | w1_ul_vld_fw, |
| 764 | 1'b0}), |
| 765 | .dout(r2_w1_hit_fw) |
| 766 | ); |
| 767 | |
| 768 | fgu_fad_dp_cmp_macro__width_12 cmp_r2d ( |
| 769 | .din0({r2_addr_e[4:0], |
| 770 | fac_tid_e[2:0], |
| 771 | q7_r2_32b_e, |
| 772 | q7_r2_odd32b_e, |
| 773 | 1'b1, |
| 774 | 1'b0}), |
| 775 | .din1({fad_w2_addr_fw[4:0], |
| 776 | fad_w2_tid_fw[2:0], |
| 777 | w2_32b_fw, |
| 778 | w2_odd32b_fw, |
| 779 | fld_fw, // load fsr is serializing, can't cause a fld_hit |
| 780 | 1'b0}), |
| 781 | .dout(r2_w2_hit_fw) |
| 782 | ); |
| 783 | |
| 784 | fgu_fad_dp_cmp_macro__width_12 cmp_r2e ( |
| 785 | .din0({r2_addr_e[4:0], |
| 786 | fac_tid_e[2:0], |
| 787 | q8_r2_32b_e, |
| 788 | q8_r2_odd32b_e, |
| 789 | 1'b1, |
| 790 | 1'b0}), |
| 791 | .din1({fad_w2_addr_fw1_b4, w2_addr_fw1[3:0], |
| 792 | fad_w2_tid_fw1[2:0], |
| 793 | w2_32b_fw1, |
| 794 | w2_odd32b_fw1, |
| 795 | fld_fw1, // load fsr is serializing, can't cause a fld_hit |
| 796 | 1'b0}), |
| 797 | .dout(r2_w2_hit_fw1) |
| 798 | ); |
| 799 | |
| 800 | fgu_fad_dp_nor_macro__ports_3__width_4 rs_vld0 ( |
| 801 | .din0({r1_fld_hit_fb, r1_w2_hit_fw1, r2_fld_hit_fb, r2_w2_hit_fw1 }), |
| 802 | .din1({r1_w1_hit_fb, r1_w1_hit_fw, r2_w1_hit_fb, r2_w1_hit_fw }), |
| 803 | .din2({r1_w2_hit_fw, 1'b0, r2_w2_hit_fw, 1'b0 }), |
| 804 | .dout({i1_r1_byp_hit_e, i2_r1_byp_hit_e, i1_r2_byp_hit_e, i2_r2_byp_hit_e}) |
| 805 | ); |
| 806 | |
| 807 | fgu_fad_dp_nand_macro__ports_2__width_2 rs_vld1 ( |
| 808 | .din0({i1_r1_byp_hit_e, i1_r2_byp_hit_e}), |
| 809 | .din1({i2_r1_byp_hit_e, i2_r2_byp_hit_e}), |
| 810 | .dout({r1_byp_hit_e, r2_byp_hit_e }) |
| 811 | ); |
| 812 | |
| 813 | // ------------------------------------ |
| 814 | // Bypass muxes |
| 815 | // ------------------------------------ |
| 816 | |
| 817 | fgu_fad_dp_msff_macro__dmux_4x__mux_aope__ports_7__width_64 fx1_rs1byp ( |
| 818 | .scan_in(fx1_rs1byp_scanin), |
| 819 | .scan_out(fx1_rs1byp_scanout), |
| 820 | .se (tcu_se_scancollar_out), |
| 821 | .clk (l2clk), |
| 822 | .en (main_clken), |
| 823 | .din0(exu_fgu_rs1_e[63:0]), |
| 824 | .din1(lsu_fgu_fld_data_b[63:0]), |
| 825 | .din2(fpf_w1_result_fb[63:0]), |
| 826 | .din3(fad_nombi_w2_result_fw[63:0]), |
| 827 | .din4(w2_result_fw1[63:0]), |
| 828 | .din5(w1_result_fw[63:0]), |
| 829 | .din6(frf_r1_data_e[63:0]), // functional or MBIST read data |
| 830 | .sel0(fac_exu_src_e), |
| 831 | .sel1(r1_fld_hit_fb), |
| 832 | .sel2(r1_w1_hit_fb), |
| 833 | .sel3(r1_w2_hit_fw), |
| 834 | .sel4(r1_w2_hit_fw1), |
| 835 | .sel5(r1_w1_hit_fw), |
| 836 | .dout(fad_rs1_fx1[63:0]), |
| 837 | .siclk(siclk), |
| 838 | .soclk(soclk), |
| 839 | .pce_ov(pce_ov), |
| 840 | .stop(stop) |
| 841 | ); |
| 842 | |
| 843 | fgu_fad_dp_cmp_macro__width_64 cmp_mbist ( |
| 844 | .din0({8{fec_mbist_wdata_3f[7:0]}}), |
| 845 | .din1(fad_rs1_fx1[63:0]), |
| 846 | .dout(fad_mbist_cmp64_fx1) |
| 847 | ); |
| 848 | |
| 849 | fgu_fad_dp_msff_macro__dmux_4x__mux_aope__ports_7__width_64 fx1_rs2byp ( |
| 850 | .scan_in(fx1_rs2byp_scanin), |
| 851 | .scan_out(fx1_rs2byp_scanout), |
| 852 | .se (tcu_se_scancollar_out), |
| 853 | .clk (l2clk), |
| 854 | .en (main_clken), |
| 855 | .din0(exu_fgu_rs2_e[63:0]), |
| 856 | .din1(lsu_fgu_fld_data_b[63:0]), |
| 857 | .din2(fpf_w1_result_fb[63:0]), |
| 858 | .din3(fad_nombi_w2_result_fw[63:0]), |
| 859 | .din4(w2_result_fw1[63:0]), |
| 860 | .din5(w1_result_fw[63:0]), |
| 861 | .din6(frf_r2_data_e[63:0]), |
| 862 | .sel0(fac_exu_src_e), |
| 863 | .sel1(r2_fld_hit_fb), |
| 864 | .sel2(r2_w1_hit_fb), |
| 865 | .sel3(r2_w2_hit_fw), |
| 866 | .sel4(r2_w2_hit_fw1), |
| 867 | .sel5(r2_w1_hit_fw), |
| 868 | .dout(fad_rs2_fx1[63:0]), |
| 869 | .siclk(siclk), |
| 870 | .soclk(soclk), |
| 871 | .pce_ov(pce_ov), |
| 872 | .stop(stop) |
| 873 | ); |
| 874 | |
| 875 | // ------------------------------------ |
| 876 | // Begin ECC check for rs1/rs2 here, complete it in FEC |
| 877 | // ------------------------------------ |
| 878 | |
| 879 | fgu_fad_dp_prty_macro__width_32 ecc_parity_2e ( |
| 880 | .din (fad_rs2_fx1[63:32]), |
| 881 | .dout(fad_i_parity_2e_fx1) |
| 882 | ); |
| 883 | |
| 884 | fgu_fad_dp_prty_macro__width_32 ecc_parity_2o ( |
| 885 | .din (fad_rs2_fx1[31:0]), |
| 886 | .dout(fad_i_parity_2o_fx1) |
| 887 | ); |
| 888 | |
| 889 | fgu_fad_dp_prty_macro__width_32 ecc_parity_1e ( |
| 890 | .din (fad_rs1_fx1[63:32]), |
| 891 | .dout(fad_i_parity_1e_fx1) |
| 892 | ); |
| 893 | |
| 894 | fgu_fad_dp_prty_macro__width_32 ecc_parity_1o ( |
| 895 | .din (fad_rs1_fx1[31:0]), |
| 896 | .dout(fad_i_parity_1o_fx1) |
| 897 | ); |
| 898 | |
| 899 | // ------------------------------------ |
| 900 | // FSR w1,w2,hold mux/flop, threads 0-7 |
| 901 | // ------------------------------------ |
| 902 | |
| 903 | // ---------- |
| 904 | // FSR tid0 |
| 905 | // ---------- |
| 906 | |
| 907 | fgu_fad_dp_mux_macro__mux_aonpe__ports_3__stack_32l__width_12 fsr0_in ( |
| 908 | .din0(fpc_fsr_w1_result_fw[11:0]), // w1 {ftt,aexc,cexc} |
| 909 | .din1(fpc_fsr_w2_result_fw[11:0]), // fdiv/fsqrt {ftt,aexc,cexc} |
| 910 | .din2({2'b0, fsr0_fx1[17:13], 5'b0}), // accrued aexc |
| 911 | .sel0(fac_fsr0_sel_fw[4]), |
| 912 | .sel1(fac_fsr0_sel_fw[5]), |
| 913 | .sel2(1'b1), |
| 914 | .dout(fsr0_fttexc_merged_fw[11:0]) |
| 915 | ); |
| 916 | |
| 917 | fgu_fad_dp_msff_macro__mux_aodec__ports_8__stack_32l__width_28 fx1_fsr0 ( // FS:wmr_protect |
| 918 | .scan_in(fx1_fsr0_wmr_scanin), |
| 919 | .scan_out(fx1_fsr0_wmr_scanout), |
| 920 | .siclk(spc_aclk_wmr), |
| 921 | .se(lb_scan_en_wmr), |
| 922 | .clk (l2clk), |
| 923 | .en (fac_fsr0_sel_fw[3]), |
| 924 | .din0({ldfsr_data_fw[27:26], // LDFSR: rd |
| 925 | ldfsr_data_fw[25:21], // tem |
| 926 | ldfsr_data_fw[20], // ns |
| 927 | fsr0_fx1[19:18], // ftt |
| 928 | ldfsr_data_fw[17:8], // aexc,cexc |
| 929 | fsr0_fx1[7:6], // fcc3 |
| 930 | fsr0_fx1[5:4], // fcc2 |
| 931 | fsr0_fx1[3:2], // fcc1 |
| 932 | ldfsr_data_fw[1:0]}), // fcc0 |
| 933 | .din1({ldfsr_data_fw[27:26], // LDXFSR: rd |
| 934 | ldfsr_data_fw[25:21], // tem |
| 935 | ldfsr_data_fw[20], // ns |
| 936 | fsr0_fx1[19:18], // ftt |
| 937 | ldfsr_data_fw[17:8], // aexc,cexc |
| 938 | ldfsr_data_fw[7:6], // fcc3 |
| 939 | ldfsr_data_fw[5:4], // fcc2 |
| 940 | ldfsr_data_fw[3:2], // fcc1 |
| 941 | ldfsr_data_fw[1:0]}), // fcc0 |
| 942 | .din2({fsr0_fx1[27:26], // ST(X)FSR: rd |
| 943 | fsr0_fx1[25:21], // tem |
| 944 | fsr0_fx1[20], // ns |
| 945 | fsr0_fttexc_merged_fw[11:10], // ftt |
| 946 | fsr0_fx1[17:8], // aexc,cexc |
| 947 | fsr0_fx1[7:6], // fcc3 |
| 948 | fsr0_fx1[5:4], // fcc2 |
| 949 | fsr0_fx1[3:2], // fcc1 |
| 950 | fsr0_fx1[1:0]}), // fcc0 |
| 951 | .din3({fsr0_fx1[27:26], // FCMP(E) fcc0: rd |
| 952 | fsr0_fx1[25:21], // tem |
| 953 | fsr0_fx1[20], // ns |
| 954 | fsr0_fttexc_merged_fw[11:10], // ftt |
| 955 | fsr0_fttexc_merged_fw[9:0], // aexc,cexc |
| 956 | fsr0_fx1[7:6], // fcc3 |
| 957 | fsr0_fx1[5:4], // fcc2 |
| 958 | fsr0_fx1[3:2], // fcc1 |
| 959 | fpc_fcc_fw[1:0]}), // fcc0 |
| 960 | .din4({fsr0_fx1[27:26], // FCMP(E) fcc1: rd |
| 961 | fsr0_fx1[25:21], // tem |
| 962 | fsr0_fx1[20], // ns |
| 963 | fsr0_fttexc_merged_fw[11:10], // ftt |
| 964 | fsr0_fttexc_merged_fw[9:0], // aexc,cexc |
| 965 | fsr0_fx1[7:6], // fcc3 |
| 966 | fsr0_fx1[5:4], // fcc2 |
| 967 | fpc_fcc_fw[1:0], // fcc1 |
| 968 | fsr0_fx1[1:0]}), // fcc0 |
| 969 | .din5({fsr0_fx1[27:26], // FCMP(E) fcc2: rd |
| 970 | fsr0_fx1[25:21], // tem |
| 971 | fsr0_fx1[20], // ns |
| 972 | fsr0_fttexc_merged_fw[11:10], // ftt |
| 973 | fsr0_fttexc_merged_fw[9:0], // aexc,cexc |
| 974 | fsr0_fx1[7:6], // fcc3 |
| 975 | fpc_fcc_fw[1:0], // fcc2 |
| 976 | fsr0_fx1[3:2], // fcc1 |
| 977 | fsr0_fx1[1:0]}), // fcc0 |
| 978 | .din6({fsr0_fx1[27:26], // FCMP(E) fcc3: rd |
| 979 | fsr0_fx1[25:21], // tem |
| 980 | fsr0_fx1[20], // ns |
| 981 | fsr0_fttexc_merged_fw[11:10], // ftt |
| 982 | fsr0_fttexc_merged_fw[9:0], // aexc,cexc |
| 983 | fpc_fcc_fw[1:0], // fcc3 |
| 984 | fsr0_fx1[5:4], // fcc2 |
| 985 | fsr0_fx1[3:2], // fcc1 |
| 986 | fsr0_fx1[1:0]}), // fcc0 |
| 987 | .din7({fsr0_fx1[27:26], // other FPop: rd |
| 988 | fsr0_fx1[25:21], // tem |
| 989 | fsr0_fx1[20], // ns |
| 990 | fsr0_fttexc_merged_fw[11:10], // ftt |
| 991 | fsr0_fttexc_merged_fw[9:0], // aexc,cexc |
| 992 | fsr0_fx1[7:6], // fcc3 |
| 993 | fsr0_fx1[5:4], // fcc2 |
| 994 | fsr0_fx1[3:2], // fcc1 |
| 995 | fsr0_fx1[1:0]}), // fcc0 |
| 996 | .sel (fac_fsr0_sel_fw[2:0]), |
| 997 | .dout(fsr0_fx1[27:0]), |
| 998 | .soclk(soclk), |
| 999 | .pce_ov(pce_ov), |
| 1000 | .stop(stop) |
| 1001 | ); |
| 1002 | |
| 1003 | // ---------- |
| 1004 | // FSR tid1 |
| 1005 | // ---------- |
| 1006 | |
| 1007 | fgu_fad_dp_mux_macro__mux_aonpe__ports_3__stack_32l__width_12 fsr1_in ( |
| 1008 | .din0(fpc_fsr_w1_result_fw[11:0]), // w1 {ftt,aexc,cexc} |
| 1009 | .din1(fpc_fsr_w2_result_fw[11:0]), // fdiv/fsqrt {ftt,aexc,cexc} |
| 1010 | .din2({2'b0, fsr1_fx1[17:13], 5'b0}), // accrued aexc |
| 1011 | .sel0(fac_fsr1_sel_fw[4]), |
| 1012 | .sel1(fac_fsr1_sel_fw[5]), |
| 1013 | .sel2(1'b1), |
| 1014 | .dout(fsr1_fttexc_merged_fw[11:0]) |
| 1015 | ); |
| 1016 | |
| 1017 | fgu_fad_dp_msff_macro__mux_aodec__ports_8__stack_32l__width_28 fx1_fsr1 ( // FS:wmr_protect |
| 1018 | .scan_in(fx1_fsr1_wmr_scanin), |
| 1019 | .scan_out(fx1_fsr1_wmr_scanout), |
| 1020 | .siclk(spc_aclk_wmr), |
| 1021 | .se(lb_scan_en_wmr), |
| 1022 | .clk (l2clk), |
| 1023 | .en (fac_fsr1_sel_fw[3]), |
| 1024 | .din0({ldfsr_data_fw[27:26], // LDFSR: rd |
| 1025 | ldfsr_data_fw[25:21], // tem |
| 1026 | ldfsr_data_fw[20], // ns |
| 1027 | fsr1_fx1[19:18], // ftt |
| 1028 | ldfsr_data_fw[17:8], // aexc,cexc |
| 1029 | fsr1_fx1[7:6], // fcc3 |
| 1030 | fsr1_fx1[5:4], // fcc2 |
| 1031 | fsr1_fx1[3:2], // fcc1 |
| 1032 | ldfsr_data_fw[1:0]}), // fcc0 |
| 1033 | .din1({ldfsr_data_fw[27:26], // LDXFSR: rd |
| 1034 | ldfsr_data_fw[25:21], // tem |
| 1035 | ldfsr_data_fw[20], // ns |
| 1036 | fsr1_fx1[19:18], // ftt |
| 1037 | ldfsr_data_fw[17:8], // aexc,cexc |
| 1038 | ldfsr_data_fw[7:6], // fcc3 |
| 1039 | ldfsr_data_fw[5:4], // fcc2 |
| 1040 | ldfsr_data_fw[3:2], // fcc1 |
| 1041 | ldfsr_data_fw[1:0]}), // fcc0 |
| 1042 | .din2({fsr1_fx1[27:26], // ST(X)FSR: rd |
| 1043 | fsr1_fx1[25:21], // tem |
| 1044 | fsr1_fx1[20], // ns |
| 1045 | fsr1_fttexc_merged_fw[11:10], // ftt |
| 1046 | fsr1_fx1[17:8], // aexc,cexc |
| 1047 | fsr1_fx1[7:6], // fcc3 |
| 1048 | fsr1_fx1[5:4], // fcc2 |
| 1049 | fsr1_fx1[3:2], // fcc1 |
| 1050 | fsr1_fx1[1:0]}), // fcc0 |
| 1051 | .din3({fsr1_fx1[27:26], // FCMP(E) fcc0: rd |
| 1052 | fsr1_fx1[25:21], // tem |
| 1053 | fsr1_fx1[20], // ns |
| 1054 | fsr1_fttexc_merged_fw[11:10], // ftt |
| 1055 | fsr1_fttexc_merged_fw[9:0], // aexc,cexc |
| 1056 | fsr1_fx1[7:6], // fcc3 |
| 1057 | fsr1_fx1[5:4], // fcc2 |
| 1058 | fsr1_fx1[3:2], // fcc1 |
| 1059 | fpc_fcc_fw[1:0]}), // fcc0 |
| 1060 | .din4({fsr1_fx1[27:26], // FCMP(E) fcc1: rd |
| 1061 | fsr1_fx1[25:21], // tem |
| 1062 | fsr1_fx1[20], // ns |
| 1063 | fsr1_fttexc_merged_fw[11:10], // ftt |
| 1064 | fsr1_fttexc_merged_fw[9:0], // aexc,cexc |
| 1065 | fsr1_fx1[7:6], // fcc3 |
| 1066 | fsr1_fx1[5:4], // fcc2 |
| 1067 | fpc_fcc_fw[1:0], // fcc1 |
| 1068 | fsr1_fx1[1:0]}), // fcc0 |
| 1069 | .din5({fsr1_fx1[27:26], // FCMP(E) fcc2: rd |
| 1070 | fsr1_fx1[25:21], // tem |
| 1071 | fsr1_fx1[20], // ns |
| 1072 | fsr1_fttexc_merged_fw[11:10], // ftt |
| 1073 | fsr1_fttexc_merged_fw[9:0], // aexc,cexc |
| 1074 | fsr1_fx1[7:6], // fcc3 |
| 1075 | fpc_fcc_fw[1:0], // fcc2 |
| 1076 | fsr1_fx1[3:2], // fcc1 |
| 1077 | fsr1_fx1[1:0]}), // fcc0 |
| 1078 | .din6({fsr1_fx1[27:26], // FCMP(E) fcc3: rd |
| 1079 | fsr1_fx1[25:21], // tem |
| 1080 | fsr1_fx1[20], // ns |
| 1081 | fsr1_fttexc_merged_fw[11:10], // ftt |
| 1082 | fsr1_fttexc_merged_fw[9:0], // aexc,cexc |
| 1083 | fpc_fcc_fw[1:0], // fcc3 |
| 1084 | fsr1_fx1[5:4], // fcc2 |
| 1085 | fsr1_fx1[3:2], // fcc1 |
| 1086 | fsr1_fx1[1:0]}), // fcc0 |
| 1087 | .din7({fsr1_fx1[27:26], // other FPop: rd |
| 1088 | fsr1_fx1[25:21], // tem |
| 1089 | fsr1_fx1[20], // ns |
| 1090 | fsr1_fttexc_merged_fw[11:10], // ftt |
| 1091 | fsr1_fttexc_merged_fw[9:0], // aexc,cexc |
| 1092 | fsr1_fx1[7:6], // fcc3 |
| 1093 | fsr1_fx1[5:4], // fcc2 |
| 1094 | fsr1_fx1[3:2], // fcc1 |
| 1095 | fsr1_fx1[1:0]}), // fcc0 |
| 1096 | .sel (fac_fsr1_sel_fw[2:0]), |
| 1097 | .dout(fsr1_fx1[27:0]), |
| 1098 | .soclk(soclk), |
| 1099 | .pce_ov(pce_ov), |
| 1100 | .stop(stop) |
| 1101 | ); |
| 1102 | |
| 1103 | // ---------- |
| 1104 | // FSR tid2 |
| 1105 | // ---------- |
| 1106 | |
| 1107 | fgu_fad_dp_mux_macro__mux_aonpe__ports_3__stack_32l__width_12 fsr2_in ( |
| 1108 | .din0(fpc_fsr_w1_result_fw[11:0]), // w1 {ftt,aexc,cexc} |
| 1109 | .din1(fpc_fsr_w2_result_fw[11:0]), // fdiv/fsqrt {ftt,aexc,cexc} |
| 1110 | .din2({2'b0, fsr2_fx1[17:13], 5'b0}), // accrued aexc |
| 1111 | .sel0(fac_fsr2_sel_fw[4]), |
| 1112 | .sel1(fac_fsr2_sel_fw[5]), |
| 1113 | .sel2(1'b1), |
| 1114 | .dout(fsr2_fttexc_merged_fw[11:0]) |
| 1115 | ); |
| 1116 | |
| 1117 | fgu_fad_dp_msff_macro__mux_aodec__ports_8__stack_32l__width_28 fx1_fsr2 ( // FS:wmr_protect |
| 1118 | .scan_in(fx1_fsr2_wmr_scanin), |
| 1119 | .scan_out(fx1_fsr2_wmr_scanout), |
| 1120 | .siclk(spc_aclk_wmr), |
| 1121 | .se(lb_scan_en_wmr), |
| 1122 | .clk (l2clk), |
| 1123 | .en (fac_fsr2_sel_fw[3]), |
| 1124 | .din0({ldfsr_data_fw[27:26], // LDFSR: rd |
| 1125 | ldfsr_data_fw[25:21], // tem |
| 1126 | ldfsr_data_fw[20], // ns |
| 1127 | fsr2_fx1[19:18], // ftt |
| 1128 | ldfsr_data_fw[17:8], // aexc,cexc |
| 1129 | fsr2_fx1[7:6], // fcc3 |
| 1130 | fsr2_fx1[5:4], // fcc2 |
| 1131 | fsr2_fx1[3:2], // fcc1 |
| 1132 | ldfsr_data_fw[1:0]}), // fcc0 |
| 1133 | .din1({ldfsr_data_fw[27:26], // LDXFSR: rd |
| 1134 | ldfsr_data_fw[25:21], // tem |
| 1135 | ldfsr_data_fw[20], // ns |
| 1136 | fsr2_fx1[19:18], // ftt |
| 1137 | ldfsr_data_fw[17:8], // aexc,cexc |
| 1138 | ldfsr_data_fw[7:6], // fcc3 |
| 1139 | ldfsr_data_fw[5:4], // fcc2 |
| 1140 | ldfsr_data_fw[3:2], // fcc1 |
| 1141 | ldfsr_data_fw[1:0]}), // fcc0 |
| 1142 | .din2({fsr2_fx1[27:26], // ST(X)FSR: rd |
| 1143 | fsr2_fx1[25:21], // tem |
| 1144 | fsr2_fx1[20], // ns |
| 1145 | fsr2_fttexc_merged_fw[11:10], // ftt |
| 1146 | fsr2_fx1[17:8], // aexc,cexc |
| 1147 | fsr2_fx1[7:6], // fcc3 |
| 1148 | fsr2_fx1[5:4], // fcc2 |
| 1149 | fsr2_fx1[3:2], // fcc1 |
| 1150 | fsr2_fx1[1:0]}), // fcc0 |
| 1151 | .din3({fsr2_fx1[27:26], // FCMP(E) fcc0: rd |
| 1152 | fsr2_fx1[25:21], // tem |
| 1153 | fsr2_fx1[20], // ns |
| 1154 | fsr2_fttexc_merged_fw[11:10], // ftt |
| 1155 | fsr2_fttexc_merged_fw[9:0], // aexc,cexc |
| 1156 | fsr2_fx1[7:6], // fcc3 |
| 1157 | fsr2_fx1[5:4], // fcc2 |
| 1158 | fsr2_fx1[3:2], // fcc1 |
| 1159 | fpc_fcc_fw[1:0]}), // fcc0 |
| 1160 | .din4({fsr2_fx1[27:26], // FCMP(E) fcc1: rd |
| 1161 | fsr2_fx1[25:21], // tem |
| 1162 | fsr2_fx1[20], // ns |
| 1163 | fsr2_fttexc_merged_fw[11:10], // ftt |
| 1164 | fsr2_fttexc_merged_fw[9:0], // aexc,cexc |
| 1165 | fsr2_fx1[7:6], // fcc3 |
| 1166 | fsr2_fx1[5:4], // fcc2 |
| 1167 | fpc_fcc_fw[1:0], // fcc1 |
| 1168 | fsr2_fx1[1:0]}), // fcc0 |
| 1169 | .din5({fsr2_fx1[27:26], // FCMP(E) fcc2: rd |
| 1170 | fsr2_fx1[25:21], // tem |
| 1171 | fsr2_fx1[20], // ns |
| 1172 | fsr2_fttexc_merged_fw[11:10], // ftt |
| 1173 | fsr2_fttexc_merged_fw[9:0], // aexc,cexc |
| 1174 | fsr2_fx1[7:6], // fcc3 |
| 1175 | fpc_fcc_fw[1:0], // fcc2 |
| 1176 | fsr2_fx1[3:2], // fcc1 |
| 1177 | fsr2_fx1[1:0]}), // fcc0 |
| 1178 | .din6({fsr2_fx1[27:26], // FCMP(E) fcc3: rd |
| 1179 | fsr2_fx1[25:21], // tem |
| 1180 | fsr2_fx1[20], // ns |
| 1181 | fsr2_fttexc_merged_fw[11:10], // ftt |
| 1182 | fsr2_fttexc_merged_fw[9:0], // aexc,cexc |
| 1183 | fpc_fcc_fw[1:0], // fcc3 |
| 1184 | fsr2_fx1[5:4], // fcc2 |
| 1185 | fsr2_fx1[3:2], // fcc1 |
| 1186 | fsr2_fx1[1:0]}), // fcc0 |
| 1187 | .din7({fsr2_fx1[27:26], // other FPop: rd |
| 1188 | fsr2_fx1[25:21], // tem |
| 1189 | fsr2_fx1[20], // ns |
| 1190 | fsr2_fttexc_merged_fw[11:10], // ftt |
| 1191 | fsr2_fttexc_merged_fw[9:0], // aexc,cexc |
| 1192 | fsr2_fx1[7:6], // fcc3 |
| 1193 | fsr2_fx1[5:4], // fcc2 |
| 1194 | fsr2_fx1[3:2], // fcc1 |
| 1195 | fsr2_fx1[1:0]}), // fcc0 |
| 1196 | .sel (fac_fsr2_sel_fw[2:0]), |
| 1197 | .dout(fsr2_fx1[27:0]), |
| 1198 | .soclk(soclk), |
| 1199 | .pce_ov(pce_ov), |
| 1200 | .stop(stop) |
| 1201 | ); |
| 1202 | |
| 1203 | // ---------- |
| 1204 | // FSR tid3 |
| 1205 | // ---------- |
| 1206 | |
| 1207 | fgu_fad_dp_mux_macro__mux_aonpe__ports_3__stack_32l__width_12 fsr3_in ( |
| 1208 | .din0(fpc_fsr_w1_result_fw[11:0]), // w1 {ftt,aexc,cexc} |
| 1209 | .din1(fpc_fsr_w2_result_fw[11:0]), // fdiv/fsqrt {ftt,aexc,cexc} |
| 1210 | .din2({2'b0, fsr3_fx1[17:13], 5'b0}), // accrued aexc |
| 1211 | .sel0(fac_fsr3_sel_fw[4]), |
| 1212 | .sel1(fac_fsr3_sel_fw[5]), |
| 1213 | .sel2(1'b1), |
| 1214 | .dout(fsr3_fttexc_merged_fw[11:0]) |
| 1215 | ); |
| 1216 | |
| 1217 | fgu_fad_dp_msff_macro__mux_aodec__ports_8__stack_32l__width_28 fx1_fsr3 ( // FS:wmr_protect |
| 1218 | .scan_in(fx1_fsr3_wmr_scanin), |
| 1219 | .scan_out(fx1_fsr3_wmr_scanout), |
| 1220 | .siclk(spc_aclk_wmr), |
| 1221 | .se(lb_scan_en_wmr), |
| 1222 | .clk (l2clk), |
| 1223 | .en (fac_fsr3_sel_fw[3]), |
| 1224 | .din0({ldfsr_data_fw[27:26], // LDFSR: rd |
| 1225 | ldfsr_data_fw[25:21], // tem |
| 1226 | ldfsr_data_fw[20], // ns |
| 1227 | fsr3_fx1[19:18], // ftt |
| 1228 | ldfsr_data_fw[17:8], // aexc,cexc |
| 1229 | fsr3_fx1[7:6], // fcc3 |
| 1230 | fsr3_fx1[5:4], // fcc2 |
| 1231 | fsr3_fx1[3:2], // fcc1 |
| 1232 | ldfsr_data_fw[1:0]}), // fcc0 |
| 1233 | .din1({ldfsr_data_fw[27:26], // LDXFSR: rd |
| 1234 | ldfsr_data_fw[25:21], // tem |
| 1235 | ldfsr_data_fw[20], // ns |
| 1236 | fsr3_fx1[19:18], // ftt |
| 1237 | ldfsr_data_fw[17:8], // aexc,cexc |
| 1238 | ldfsr_data_fw[7:6], // fcc3 |
| 1239 | ldfsr_data_fw[5:4], // fcc2 |
| 1240 | ldfsr_data_fw[3:2], // fcc1 |
| 1241 | ldfsr_data_fw[1:0]}), // fcc0 |
| 1242 | .din2({fsr3_fx1[27:26], // ST(X)FSR: rd |
| 1243 | fsr3_fx1[25:21], // tem |
| 1244 | fsr3_fx1[20], // ns |
| 1245 | fsr3_fttexc_merged_fw[11:10], // ftt |
| 1246 | fsr3_fx1[17:8], // aexc,cexc |
| 1247 | fsr3_fx1[7:6], // fcc3 |
| 1248 | fsr3_fx1[5:4], // fcc2 |
| 1249 | fsr3_fx1[3:2], // fcc1 |
| 1250 | fsr3_fx1[1:0]}), // fcc0 |
| 1251 | .din3({fsr3_fx1[27:26], // FCMP(E) fcc0: rd |
| 1252 | fsr3_fx1[25:21], // tem |
| 1253 | fsr3_fx1[20], // ns |
| 1254 | fsr3_fttexc_merged_fw[11:10], // ftt |
| 1255 | fsr3_fttexc_merged_fw[9:0], // aexc,cexc |
| 1256 | fsr3_fx1[7:6], // fcc3 |
| 1257 | fsr3_fx1[5:4], // fcc2 |
| 1258 | fsr3_fx1[3:2], // fcc1 |
| 1259 | fpc_fcc_fw[1:0]}), // fcc0 |
| 1260 | .din4({fsr3_fx1[27:26], // FCMP(E) fcc1: rd |
| 1261 | fsr3_fx1[25:21], // tem |
| 1262 | fsr3_fx1[20], // ns |
| 1263 | fsr3_fttexc_merged_fw[11:10], // ftt |
| 1264 | fsr3_fttexc_merged_fw[9:0], // aexc,cexc |
| 1265 | fsr3_fx1[7:6], // fcc3 |
| 1266 | fsr3_fx1[5:4], // fcc2 |
| 1267 | fpc_fcc_fw[1:0], // fcc1 |
| 1268 | fsr3_fx1[1:0]}), // fcc0 |
| 1269 | .din5({fsr3_fx1[27:26], // FCMP(E) fcc2: rd |
| 1270 | fsr3_fx1[25:21], // tem |
| 1271 | fsr3_fx1[20], // ns |
| 1272 | fsr3_fttexc_merged_fw[11:10], // ftt |
| 1273 | fsr3_fttexc_merged_fw[9:0], // aexc,cexc |
| 1274 | fsr3_fx1[7:6], // fcc3 |
| 1275 | fpc_fcc_fw[1:0], // fcc2 |
| 1276 | fsr3_fx1[3:2], // fcc1 |
| 1277 | fsr3_fx1[1:0]}), // fcc0 |
| 1278 | .din6({fsr3_fx1[27:26], // FCMP(E) fcc3: rd |
| 1279 | fsr3_fx1[25:21], // tem |
| 1280 | fsr3_fx1[20], // ns |
| 1281 | fsr3_fttexc_merged_fw[11:10], // ftt |
| 1282 | fsr3_fttexc_merged_fw[9:0], // aexc,cexc |
| 1283 | fpc_fcc_fw[1:0], // fcc3 |
| 1284 | fsr3_fx1[5:4], // fcc2 |
| 1285 | fsr3_fx1[3:2], // fcc1 |
| 1286 | fsr3_fx1[1:0]}), // fcc0 |
| 1287 | .din7({fsr3_fx1[27:26], // other FPop: rd |
| 1288 | fsr3_fx1[25:21], // tem |
| 1289 | fsr3_fx1[20], // ns |
| 1290 | fsr3_fttexc_merged_fw[11:10], // ftt |
| 1291 | fsr3_fttexc_merged_fw[9:0], // aexc,cexc |
| 1292 | fsr3_fx1[7:6], // fcc3 |
| 1293 | fsr3_fx1[5:4], // fcc2 |
| 1294 | fsr3_fx1[3:2], // fcc1 |
| 1295 | fsr3_fx1[1:0]}), // fcc0 |
| 1296 | .sel (fac_fsr3_sel_fw[2:0]), |
| 1297 | .dout(fsr3_fx1[27:0]), |
| 1298 | .soclk(soclk), |
| 1299 | .pce_ov(pce_ov), |
| 1300 | .stop(stop) |
| 1301 | ); |
| 1302 | |
| 1303 | // ---------- |
| 1304 | // FSR tid4 |
| 1305 | // ---------- |
| 1306 | |
| 1307 | fgu_fad_dp_mux_macro__mux_aonpe__ports_3__stack_32l__width_12 fsr4_in ( |
| 1308 | .din0(fpc_fsr_w1_result_fw[11:0]), // w1 {ftt,aexc,cexc} |
| 1309 | .din1(fpc_fsr_w2_result_fw[11:0]), // fdiv/fsqrt {ftt,aexc,cexc} |
| 1310 | .din2({2'b0, fsr4_fx1[17:13], 5'b0}), // accrued aexc |
| 1311 | .sel0(fac_fsr4_sel_fw[4]), |
| 1312 | .sel1(fac_fsr4_sel_fw[5]), |
| 1313 | .sel2(1'b1), |
| 1314 | .dout(fsr4_fttexc_merged_fw[11:0]) |
| 1315 | ); |
| 1316 | |
| 1317 | fgu_fad_dp_msff_macro__mux_aodec__ports_8__stack_32l__width_28 fx1_fsr4 ( // FS:wmr_protect |
| 1318 | .scan_in(fx1_fsr4_wmr_scanin), |
| 1319 | .scan_out(fx1_fsr4_wmr_scanout), |
| 1320 | .siclk(spc_aclk_wmr), |
| 1321 | .se(lb_scan_en_wmr), |
| 1322 | .clk (l2clk), |
| 1323 | .en (fac_fsr4_sel_fw[3]), |
| 1324 | .din0({ldfsr_data_fw[27:26], // LDFSR: rd |
| 1325 | ldfsr_data_fw[25:21], // tem |
| 1326 | ldfsr_data_fw[20], // ns |
| 1327 | fsr4_fx1[19:18], // ftt |
| 1328 | ldfsr_data_fw[17:8], // aexc,cexc |
| 1329 | fsr4_fx1[7:6], // fcc3 |
| 1330 | fsr4_fx1[5:4], // fcc2 |
| 1331 | fsr4_fx1[3:2], // fcc1 |
| 1332 | ldfsr_data_fw[1:0]}), // fcc0 |
| 1333 | .din1({ldfsr_data_fw[27:26], // LDXFSR: rd |
| 1334 | ldfsr_data_fw[25:21], // tem |
| 1335 | ldfsr_data_fw[20], // ns |
| 1336 | fsr4_fx1[19:18], // ftt |
| 1337 | ldfsr_data_fw[17:8], // aexc,cexc |
| 1338 | ldfsr_data_fw[7:6], // fcc3 |
| 1339 | ldfsr_data_fw[5:4], // fcc2 |
| 1340 | ldfsr_data_fw[3:2], // fcc1 |
| 1341 | ldfsr_data_fw[1:0]}), // fcc0 |
| 1342 | .din2({fsr4_fx1[27:26], // ST(X)FSR: rd |
| 1343 | fsr4_fx1[25:21], // tem |
| 1344 | fsr4_fx1[20], // ns |
| 1345 | fsr4_fttexc_merged_fw[11:10], // ftt |
| 1346 | fsr4_fx1[17:8], // aexc,cexc |
| 1347 | fsr4_fx1[7:6], // fcc3 |
| 1348 | fsr4_fx1[5:4], // fcc2 |
| 1349 | fsr4_fx1[3:2], // fcc1 |
| 1350 | fsr4_fx1[1:0]}), // fcc0 |
| 1351 | .din3({fsr4_fx1[27:26], // FCMP(E) fcc0: rd |
| 1352 | fsr4_fx1[25:21], // tem |
| 1353 | fsr4_fx1[20], // ns |
| 1354 | fsr4_fttexc_merged_fw[11:10], // ftt |
| 1355 | fsr4_fttexc_merged_fw[9:0], // aexc,cexc |
| 1356 | fsr4_fx1[7:6], // fcc3 |
| 1357 | fsr4_fx1[5:4], // fcc2 |
| 1358 | fsr4_fx1[3:2], // fcc1 |
| 1359 | fpc_fcc_fw[1:0]}), // fcc0 |
| 1360 | .din4({fsr4_fx1[27:26], // FCMP(E) fcc1: rd |
| 1361 | fsr4_fx1[25:21], // tem |
| 1362 | fsr4_fx1[20], // ns |
| 1363 | fsr4_fttexc_merged_fw[11:10], // ftt |
| 1364 | fsr4_fttexc_merged_fw[9:0], // aexc,cexc |
| 1365 | fsr4_fx1[7:6], // fcc3 |
| 1366 | fsr4_fx1[5:4], // fcc2 |
| 1367 | fpc_fcc_fw[1:0], // fcc1 |
| 1368 | fsr4_fx1[1:0]}), // fcc0 |
| 1369 | .din5({fsr4_fx1[27:26], // FCMP(E) fcc2: rd |
| 1370 | fsr4_fx1[25:21], // tem |
| 1371 | fsr4_fx1[20], // ns |
| 1372 | fsr4_fttexc_merged_fw[11:10], // ftt |
| 1373 | fsr4_fttexc_merged_fw[9:0], // aexc,cexc |
| 1374 | fsr4_fx1[7:6], // fcc3 |
| 1375 | fpc_fcc_fw[1:0], // fcc2 |
| 1376 | fsr4_fx1[3:2], // fcc1 |
| 1377 | fsr4_fx1[1:0]}), // fcc0 |
| 1378 | .din6({fsr4_fx1[27:26], // FCMP(E) fcc3: rd |
| 1379 | fsr4_fx1[25:21], // tem |
| 1380 | fsr4_fx1[20], // ns |
| 1381 | fsr4_fttexc_merged_fw[11:10], // ftt |
| 1382 | fsr4_fttexc_merged_fw[9:0], // aexc,cexc |
| 1383 | fpc_fcc_fw[1:0], // fcc3 |
| 1384 | fsr4_fx1[5:4], // fcc2 |
| 1385 | fsr4_fx1[3:2], // fcc1 |
| 1386 | fsr4_fx1[1:0]}), // fcc0 |
| 1387 | .din7({fsr4_fx1[27:26], // other FPop: rd |
| 1388 | fsr4_fx1[25:21], // tem |
| 1389 | fsr4_fx1[20], // ns |
| 1390 | fsr4_fttexc_merged_fw[11:10], // ftt |
| 1391 | fsr4_fttexc_merged_fw[9:0], // aexc,cexc |
| 1392 | fsr4_fx1[7:6], // fcc3 |
| 1393 | fsr4_fx1[5:4], // fcc2 |
| 1394 | fsr4_fx1[3:2], // fcc1 |
| 1395 | fsr4_fx1[1:0]}), // fcc0 |
| 1396 | .sel (fac_fsr4_sel_fw[2:0]), |
| 1397 | .dout(fsr4_fx1[27:0]), |
| 1398 | .soclk(soclk), |
| 1399 | .pce_ov(pce_ov), |
| 1400 | .stop(stop) |
| 1401 | ); |
| 1402 | |
| 1403 | // ---------- |
| 1404 | // FSR tid5 |
| 1405 | // ---------- |
| 1406 | |
| 1407 | fgu_fad_dp_mux_macro__mux_aonpe__ports_3__stack_32l__width_12 fsr5_in ( |
| 1408 | .din0(fpc_fsr_w1_result_fw[11:0]), // w1 {ftt,aexc,cexc} |
| 1409 | .din1(fpc_fsr_w2_result_fw[11:0]), // fdiv/fsqrt {ftt,aexc,cexc} |
| 1410 | .din2({2'b0, fsr5_fx1[17:13], 5'b0}), // accrued aexc |
| 1411 | .sel0(fac_fsr5_sel_fw[4]), |
| 1412 | .sel1(fac_fsr5_sel_fw[5]), |
| 1413 | .sel2(1'b1), |
| 1414 | .dout(fsr5_fttexc_merged_fw[11:0]) |
| 1415 | ); |
| 1416 | |
| 1417 | fgu_fad_dp_msff_macro__mux_aodec__ports_8__stack_32l__width_28 fx1_fsr5 ( // FS:wmr_protect |
| 1418 | .scan_in(fx1_fsr5_wmr_scanin), |
| 1419 | .scan_out(fx1_fsr5_wmr_scanout), |
| 1420 | .siclk(spc_aclk_wmr), |
| 1421 | .se(lb_scan_en_wmr), |
| 1422 | .clk (l2clk), |
| 1423 | .en (fac_fsr5_sel_fw[3]), |
| 1424 | .din0({ldfsr_data_fw[27:26], // LDFSR: rd |
| 1425 | ldfsr_data_fw[25:21], // tem |
| 1426 | ldfsr_data_fw[20], // ns |
| 1427 | fsr5_fx1[19:18], // ftt |
| 1428 | ldfsr_data_fw[17:8], // aexc,cexc |
| 1429 | fsr5_fx1[7:6], // fcc3 |
| 1430 | fsr5_fx1[5:4], // fcc2 |
| 1431 | fsr5_fx1[3:2], // fcc1 |
| 1432 | ldfsr_data_fw[1:0]}), // fcc0 |
| 1433 | .din1({ldfsr_data_fw[27:26], // LDXFSR: rd |
| 1434 | ldfsr_data_fw[25:21], // tem |
| 1435 | ldfsr_data_fw[20], // ns |
| 1436 | fsr5_fx1[19:18], // ftt |
| 1437 | ldfsr_data_fw[17:8], // aexc,cexc |
| 1438 | ldfsr_data_fw[7:6], // fcc3 |
| 1439 | ldfsr_data_fw[5:4], // fcc2 |
| 1440 | ldfsr_data_fw[3:2], // fcc1 |
| 1441 | ldfsr_data_fw[1:0]}), // fcc0 |
| 1442 | .din2({fsr5_fx1[27:26], // ST(X)FSR: rd |
| 1443 | fsr5_fx1[25:21], // tem |
| 1444 | fsr5_fx1[20], // ns |
| 1445 | fsr5_fttexc_merged_fw[11:10], // ftt |
| 1446 | fsr5_fx1[17:8], // aexc,cexc |
| 1447 | fsr5_fx1[7:6], // fcc3 |
| 1448 | fsr5_fx1[5:4], // fcc2 |
| 1449 | fsr5_fx1[3:2], // fcc1 |
| 1450 | fsr5_fx1[1:0]}), // fcc0 |
| 1451 | .din3({fsr5_fx1[27:26], // FCMP(E) fcc0: rd |
| 1452 | fsr5_fx1[25:21], // tem |
| 1453 | fsr5_fx1[20], // ns |
| 1454 | fsr5_fttexc_merged_fw[11:10], // ftt |
| 1455 | fsr5_fttexc_merged_fw[9:0], // aexc,cexc |
| 1456 | fsr5_fx1[7:6], // fcc3 |
| 1457 | fsr5_fx1[5:4], // fcc2 |
| 1458 | fsr5_fx1[3:2], // fcc1 |
| 1459 | fpc_fcc_fw[1:0]}), // fcc0 |
| 1460 | .din4({fsr5_fx1[27:26], // FCMP(E) fcc1: rd |
| 1461 | fsr5_fx1[25:21], // tem |
| 1462 | fsr5_fx1[20], // ns |
| 1463 | fsr5_fttexc_merged_fw[11:10], // ftt |
| 1464 | fsr5_fttexc_merged_fw[9:0], // aexc,cexc |
| 1465 | fsr5_fx1[7:6], // fcc3 |
| 1466 | fsr5_fx1[5:4], // fcc2 |
| 1467 | fpc_fcc_fw[1:0], // fcc1 |
| 1468 | fsr5_fx1[1:0]}), // fcc0 |
| 1469 | .din5({fsr5_fx1[27:26], // FCMP(E) fcc2: rd |
| 1470 | fsr5_fx1[25:21], // tem |
| 1471 | fsr5_fx1[20], // ns |
| 1472 | fsr5_fttexc_merged_fw[11:10], // ftt |
| 1473 | fsr5_fttexc_merged_fw[9:0], // aexc,cexc |
| 1474 | fsr5_fx1[7:6], // fcc3 |
| 1475 | fpc_fcc_fw[1:0], // fcc2 |
| 1476 | fsr5_fx1[3:2], // fcc1 |
| 1477 | fsr5_fx1[1:0]}), // fcc0 |
| 1478 | .din6({fsr5_fx1[27:26], // FCMP(E) fcc3: rd |
| 1479 | fsr5_fx1[25:21], // tem |
| 1480 | fsr5_fx1[20], // ns |
| 1481 | fsr5_fttexc_merged_fw[11:10], // ftt |
| 1482 | fsr5_fttexc_merged_fw[9:0], // aexc,cexc |
| 1483 | fpc_fcc_fw[1:0], // fcc3 |
| 1484 | fsr5_fx1[5:4], // fcc2 |
| 1485 | fsr5_fx1[3:2], // fcc1 |
| 1486 | fsr5_fx1[1:0]}), // fcc0 |
| 1487 | .din7({fsr5_fx1[27:26], // other FPop: rd |
| 1488 | fsr5_fx1[25:21], // tem |
| 1489 | fsr5_fx1[20], // ns |
| 1490 | fsr5_fttexc_merged_fw[11:10], // ftt |
| 1491 | fsr5_fttexc_merged_fw[9:0], // aexc,cexc |
| 1492 | fsr5_fx1[7:6], // fcc3 |
| 1493 | fsr5_fx1[5:4], // fcc2 |
| 1494 | fsr5_fx1[3:2], // fcc1 |
| 1495 | fsr5_fx1[1:0]}), // fcc0 |
| 1496 | .sel (fac_fsr5_sel_fw[2:0]), |
| 1497 | .dout(fsr5_fx1[27:0]), |
| 1498 | .soclk(soclk), |
| 1499 | .pce_ov(pce_ov), |
| 1500 | .stop(stop) |
| 1501 | ); |
| 1502 | |
| 1503 | // ---------- |
| 1504 | // FSR tid6 |
| 1505 | // ---------- |
| 1506 | |
| 1507 | fgu_fad_dp_mux_macro__mux_aonpe__ports_3__stack_32l__width_12 fsr6_in ( |
| 1508 | .din0(fpc_fsr_w1_result_fw[11:0]), // w1 {ftt,aexc,cexc} |
| 1509 | .din1(fpc_fsr_w2_result_fw[11:0]), // fdiv/fsqrt {ftt,aexc,cexc} |
| 1510 | .din2({2'b0, fsr6_fx1[17:13], 5'b0}), // accrued aexc |
| 1511 | .sel0(fac_fsr6_sel_fw[4]), |
| 1512 | .sel1(fac_fsr6_sel_fw[5]), |
| 1513 | .sel2(1'b1), |
| 1514 | .dout(fsr6_fttexc_merged_fw[11:0]) |
| 1515 | ); |
| 1516 | |
| 1517 | fgu_fad_dp_msff_macro__mux_aodec__ports_8__stack_32l__width_28 fx1_fsr6 ( // FS:wmr_protect |
| 1518 | .scan_in(fx1_fsr6_wmr_scanin), |
| 1519 | .scan_out(fx1_fsr6_wmr_scanout), |
| 1520 | .siclk(spc_aclk_wmr), |
| 1521 | .se(lb_scan_en_wmr), |
| 1522 | .clk (l2clk), |
| 1523 | .en (fac_fsr6_sel_fw[3]), |
| 1524 | .din0({ldfsr_data_fw[27:26], // LDFSR: rd |
| 1525 | ldfsr_data_fw[25:21], // tem |
| 1526 | ldfsr_data_fw[20], // ns |
| 1527 | fsr6_fx1[19:18], // ftt |
| 1528 | ldfsr_data_fw[17:8], // aexc,cexc |
| 1529 | fsr6_fx1[7:6], // fcc3 |
| 1530 | fsr6_fx1[5:4], // fcc2 |
| 1531 | fsr6_fx1[3:2], // fcc1 |
| 1532 | ldfsr_data_fw[1:0]}), // fcc0 |
| 1533 | .din1({ldfsr_data_fw[27:26], // LDXFSR: rd |
| 1534 | ldfsr_data_fw[25:21], // tem |
| 1535 | ldfsr_data_fw[20], // ns |
| 1536 | fsr6_fx1[19:18], // ftt |
| 1537 | ldfsr_data_fw[17:8], // aexc,cexc |
| 1538 | ldfsr_data_fw[7:6], // fcc3 |
| 1539 | ldfsr_data_fw[5:4], // fcc2 |
| 1540 | ldfsr_data_fw[3:2], // fcc1 |
| 1541 | ldfsr_data_fw[1:0]}), // fcc0 |
| 1542 | .din2({fsr6_fx1[27:26], // ST(X)FSR: rd |
| 1543 | fsr6_fx1[25:21], // tem |
| 1544 | fsr6_fx1[20], // ns |
| 1545 | fsr6_fttexc_merged_fw[11:10], // ftt |
| 1546 | fsr6_fx1[17:8], // aexc,cexc |
| 1547 | fsr6_fx1[7:6], // fcc3 |
| 1548 | fsr6_fx1[5:4], // fcc2 |
| 1549 | fsr6_fx1[3:2], // fcc1 |
| 1550 | fsr6_fx1[1:0]}), // fcc0 |
| 1551 | .din3({fsr6_fx1[27:26], // FCMP(E) fcc0: rd |
| 1552 | fsr6_fx1[25:21], // tem |
| 1553 | fsr6_fx1[20], // ns |
| 1554 | fsr6_fttexc_merged_fw[11:10], // ftt |
| 1555 | fsr6_fttexc_merged_fw[9:0], // aexc,cexc |
| 1556 | fsr6_fx1[7:6], // fcc3 |
| 1557 | fsr6_fx1[5:4], // fcc2 |
| 1558 | fsr6_fx1[3:2], // fcc1 |
| 1559 | fpc_fcc_fw[1:0]}), // fcc0 |
| 1560 | .din4({fsr6_fx1[27:26], // FCMP(E) fcc1: rd |
| 1561 | fsr6_fx1[25:21], // tem |
| 1562 | fsr6_fx1[20], // ns |
| 1563 | fsr6_fttexc_merged_fw[11:10], // ftt |
| 1564 | fsr6_fttexc_merged_fw[9:0], // aexc,cexc |
| 1565 | fsr6_fx1[7:6], // fcc3 |
| 1566 | fsr6_fx1[5:4], // fcc2 |
| 1567 | fpc_fcc_fw[1:0], // fcc1 |
| 1568 | fsr6_fx1[1:0]}), // fcc0 |
| 1569 | .din5({fsr6_fx1[27:26], // FCMP(E) fcc2: rd |
| 1570 | fsr6_fx1[25:21], // tem |
| 1571 | fsr6_fx1[20], // ns |
| 1572 | fsr6_fttexc_merged_fw[11:10], // ftt |
| 1573 | fsr6_fttexc_merged_fw[9:0], // aexc,cexc |
| 1574 | fsr6_fx1[7:6], // fcc3 |
| 1575 | fpc_fcc_fw[1:0], // fcc2 |
| 1576 | fsr6_fx1[3:2], // fcc1 |
| 1577 | fsr6_fx1[1:0]}), // fcc0 |
| 1578 | .din6({fsr6_fx1[27:26], // FCMP(E) fcc3: rd |
| 1579 | fsr6_fx1[25:21], // tem |
| 1580 | fsr6_fx1[20], // ns |
| 1581 | fsr6_fttexc_merged_fw[11:10], // ftt |
| 1582 | fsr6_fttexc_merged_fw[9:0], // aexc,cexc |
| 1583 | fpc_fcc_fw[1:0], // fcc3 |
| 1584 | fsr6_fx1[5:4], // fcc2 |
| 1585 | fsr6_fx1[3:2], // fcc1 |
| 1586 | fsr6_fx1[1:0]}), // fcc0 |
| 1587 | .din7({fsr6_fx1[27:26], // other FPop: rd |
| 1588 | fsr6_fx1[25:21], // tem |
| 1589 | fsr6_fx1[20], // ns |
| 1590 | fsr6_fttexc_merged_fw[11:10], // ftt |
| 1591 | fsr6_fttexc_merged_fw[9:0], // aexc,cexc |
| 1592 | fsr6_fx1[7:6], // fcc3 |
| 1593 | fsr6_fx1[5:4], // fcc2 |
| 1594 | fsr6_fx1[3:2], // fcc1 |
| 1595 | fsr6_fx1[1:0]}), // fcc0 |
| 1596 | .sel (fac_fsr6_sel_fw[2:0]), |
| 1597 | .dout(fsr6_fx1[27:0]), |
| 1598 | .soclk(soclk), |
| 1599 | .pce_ov(pce_ov), |
| 1600 | .stop(stop) |
| 1601 | ); |
| 1602 | |
| 1603 | // ---------- |
| 1604 | // FSR tid7 |
| 1605 | // ---------- |
| 1606 | |
| 1607 | fgu_fad_dp_mux_macro__mux_aonpe__ports_3__stack_32l__width_12 fsr7_in ( |
| 1608 | .din0(fpc_fsr_w1_result_fw[11:0]), // w1 {ftt,aexc,cexc} |
| 1609 | .din1(fpc_fsr_w2_result_fw[11:0]), // fdiv/fsqrt {ftt,aexc,cexc} |
| 1610 | .din2({2'b0, fsr7_fx1[17:13], 5'b0}), // accrued aexc |
| 1611 | .sel0(fac_fsr7_sel_fw[4]), |
| 1612 | .sel1(fac_fsr7_sel_fw[5]), |
| 1613 | .sel2(1'b1), |
| 1614 | .dout(fsr7_fttexc_merged_fw[11:0]) |
| 1615 | ); |
| 1616 | |
| 1617 | fgu_fad_dp_msff_macro__mux_aodec__ports_8__stack_32l__width_28 fx1_fsr7 ( // FS:wmr_protect |
| 1618 | .scan_in(fx1_fsr7_wmr_scanin), |
| 1619 | .scan_out(fx1_fsr7_wmr_scanout), |
| 1620 | .siclk(spc_aclk_wmr), |
| 1621 | .se(lb_scan_en_wmr), |
| 1622 | .clk (l2clk), |
| 1623 | .en (fac_fsr7_sel_fw[3]), |
| 1624 | .din0({ldfsr_data_fw[27:26], // LDFSR: rd |
| 1625 | ldfsr_data_fw[25:21], // tem |
| 1626 | ldfsr_data_fw[20], // ns |
| 1627 | fsr7_fx1[19:18], // ftt |
| 1628 | ldfsr_data_fw[17:8], // aexc,cexc |
| 1629 | fsr7_fx1[7:6], // fcc3 |
| 1630 | fsr7_fx1[5:4], // fcc2 |
| 1631 | fsr7_fx1[3:2], // fcc1 |
| 1632 | ldfsr_data_fw[1:0]}), // fcc0 |
| 1633 | .din1({ldfsr_data_fw[27:26], // LDXFSR: rd |
| 1634 | ldfsr_data_fw[25:21], // tem |
| 1635 | ldfsr_data_fw[20], // ns |
| 1636 | fsr7_fx1[19:18], // ftt |
| 1637 | ldfsr_data_fw[17:8], // aexc,cexc |
| 1638 | ldfsr_data_fw[7:6], // fcc3 |
| 1639 | ldfsr_data_fw[5:4], // fcc2 |
| 1640 | ldfsr_data_fw[3:2], // fcc1 |
| 1641 | ldfsr_data_fw[1:0]}), // fcc0 |
| 1642 | .din2({fsr7_fx1[27:26], // ST(X)FSR: rd |
| 1643 | fsr7_fx1[25:21], // tem |
| 1644 | fsr7_fx1[20], // ns |
| 1645 | fsr7_fttexc_merged_fw[11:10], // ftt |
| 1646 | fsr7_fx1[17:8], // aexc,cexc |
| 1647 | fsr7_fx1[7:6], // fcc3 |
| 1648 | fsr7_fx1[5:4], // fcc2 |
| 1649 | fsr7_fx1[3:2], // fcc1 |
| 1650 | fsr7_fx1[1:0]}), // fcc0 |
| 1651 | .din3({fsr7_fx1[27:26], // FCMP(E) fcc0: rd |
| 1652 | fsr7_fx1[25:21], // tem |
| 1653 | fsr7_fx1[20], // ns |
| 1654 | fsr7_fttexc_merged_fw[11:10], // ftt |
| 1655 | fsr7_fttexc_merged_fw[9:0], // aexc,cexc |
| 1656 | fsr7_fx1[7:6], // fcc3 |
| 1657 | fsr7_fx1[5:4], // fcc2 |
| 1658 | fsr7_fx1[3:2], // fcc1 |
| 1659 | fpc_fcc_fw[1:0]}), // fcc0 |
| 1660 | .din4({fsr7_fx1[27:26], // FCMP(E) fcc1: rd |
| 1661 | fsr7_fx1[25:21], // tem |
| 1662 | fsr7_fx1[20], // ns |
| 1663 | fsr7_fttexc_merged_fw[11:10], // ftt |
| 1664 | fsr7_fttexc_merged_fw[9:0], // aexc,cexc |
| 1665 | fsr7_fx1[7:6], // fcc3 |
| 1666 | fsr7_fx1[5:4], // fcc2 |
| 1667 | fpc_fcc_fw[1:0], // fcc1 |
| 1668 | fsr7_fx1[1:0]}), // fcc0 |
| 1669 | .din5({fsr7_fx1[27:26], // FCMP(E) fcc2: rd |
| 1670 | fsr7_fx1[25:21], // tem |
| 1671 | fsr7_fx1[20], // ns |
| 1672 | fsr7_fttexc_merged_fw[11:10], // ftt |
| 1673 | fsr7_fttexc_merged_fw[9:0], // aexc,cexc |
| 1674 | fsr7_fx1[7:6], // fcc3 |
| 1675 | fpc_fcc_fw[1:0], // fcc2 |
| 1676 | fsr7_fx1[3:2], // fcc1 |
| 1677 | fsr7_fx1[1:0]}), // fcc0 |
| 1678 | .din6({fsr7_fx1[27:26], // FCMP(E) fcc3: rd |
| 1679 | fsr7_fx1[25:21], // tem |
| 1680 | fsr7_fx1[20], // ns |
| 1681 | fsr7_fttexc_merged_fw[11:10], // ftt |
| 1682 | fsr7_fttexc_merged_fw[9:0], // aexc,cexc |
| 1683 | fpc_fcc_fw[1:0], // fcc3 |
| 1684 | fsr7_fx1[5:4], // fcc2 |
| 1685 | fsr7_fx1[3:2], // fcc1 |
| 1686 | fsr7_fx1[1:0]}), // fcc0 |
| 1687 | .din7({fsr7_fx1[27:26], // other FPop: rd |
| 1688 | fsr7_fx1[25:21], // tem |
| 1689 | fsr7_fx1[20], // ns |
| 1690 | fsr7_fttexc_merged_fw[11:10], // ftt |
| 1691 | fsr7_fttexc_merged_fw[9:0], // aexc,cexc |
| 1692 | fsr7_fx1[7:6], // fcc3 |
| 1693 | fsr7_fx1[5:4], // fcc2 |
| 1694 | fsr7_fx1[3:2], // fcc1 |
| 1695 | fsr7_fx1[1:0]}), // fcc0 |
| 1696 | .sel (fac_fsr7_sel_fw[2:0]), |
| 1697 | .dout(fsr7_fx1[27:0]), |
| 1698 | .soclk(soclk), |
| 1699 | .pce_ov(pce_ov), |
| 1700 | .stop(stop) |
| 1701 | ); |
| 1702 | |
| 1703 | // ---------------------------------------------------------------------------- |
| 1704 | // FGU ASI local ring datapath |
| 1705 | // ---------------------------------------------------------------------------- |
| 1706 | |
| 1707 | fgu_fad_dp_msff_macro__stack_32l__width_31 flop_rng1_4f ( |
| 1708 | .scan_in(flop_rng1_4f_scanin), |
| 1709 | .scan_out(flop_rng1_4f_scanout), |
| 1710 | .clk (l2clk), |
| 1711 | .en (asi_clken), |
| 1712 | .din (fgd_rngl_cdbus_3f[62:32]), |
| 1713 | .dout( rngl_cdbus_4f[62:32]), |
| 1714 | .se(se), |
| 1715 | .siclk(siclk), |
| 1716 | .soclk(soclk), |
| 1717 | .pce_ov(pce_ov), |
| 1718 | .stop(stop) |
| 1719 | ); |
| 1720 | |
| 1721 | fgu_fad_dp_msff_macro__stack_32l__width_32 flop_rng0_4f ( |
| 1722 | .scan_in(flop_rng0_4f_scanin), |
| 1723 | .scan_out(flop_rng0_4f_scanout), |
| 1724 | .clk (l2clk), |
| 1725 | .en (asi_clken), |
| 1726 | .din (fgd_rngl_cdbus_3f[31:0]), |
| 1727 | .dout( rngl_cdbus_4f[31:0]), |
| 1728 | .se(se), |
| 1729 | .siclk(siclk), |
| 1730 | .soclk(soclk), |
| 1731 | .pce_ov(pce_ov), |
| 1732 | .stop(stop) |
| 1733 | ); |
| 1734 | |
| 1735 | fgu_fad_dp_buff_macro__rep_1__stack_32l__width_31 buf_rng1 ( |
| 1736 | .din ( rngl_cdbus_4f[62:32]), |
| 1737 | .dout(fgu_rngl_cdbus[62:32]) |
| 1738 | ); |
| 1739 | |
| 1740 | fgu_fad_dp_buff_macro__rep_1__stack_32l__width_32 buf_rng0 ( |
| 1741 | .din ( rngl_cdbus_4f[31:0]), |
| 1742 | .dout(fgu_rngl_cdbus[31:0]) |
| 1743 | ); |
| 1744 | |
| 1745 | |
| 1746 | // ---------------------------------------------------------------------------- |
| 1747 | // FX1 stage |
| 1748 | // ---------------------------------------------------------------------------- |
| 1749 | |
| 1750 | // ------------------------------------ |
| 1751 | // FSR thread 0-7 mux |
| 1752 | // |
| 1753 | // ST(X)FSR has a presync. All preceeding instrs have completed |
| 1754 | // FW+1 before ST(X)FSR reaches FX1. |
| 1755 | // |
| 1756 | // LD(X)FSR has same presync as ST(X)FSR. LD(X)FSR update of the |
| 1757 | // architected FSR is available in FX4. Instrs following LD(X)FSR |
| 1758 | // are in E when LD(X)FSR is in FX4. |
| 1759 | // |
| 1760 | // As a result, the mux below can be a mux/flop and still allow |
| 1761 | // correct functionality. Making it a mux/flop helps storefmt timing |
| 1762 | // for the ST(X)FSR path. |
| 1763 | // ------------------------------------ |
| 1764 | |
| 1765 | fgu_fad_dp_msff_macro__mux_aodec__ports_8__stack_32l__width_28 fx1_fsr ( |
| 1766 | .scan_in(fx1_fsr_scanin), |
| 1767 | .scan_out(fx1_fsr_scanout), |
| 1768 | .clk (l2clk), |
| 1769 | .en (main_clken), |
| 1770 | .din0(fsr0_fx1[27:0]), |
| 1771 | .din1(fsr1_fx1[27:0]), |
| 1772 | .din2(fsr2_fx1[27:0]), |
| 1773 | .din3(fsr3_fx1[27:0]), |
| 1774 | .din4(fsr4_fx1[27:0]), |
| 1775 | .din5(fsr5_fx1[27:0]), |
| 1776 | .din6(fsr6_fx1[27:0]), |
| 1777 | .din7(fsr7_fx1[27:0]), |
| 1778 | .sel (fac_tid_e[2:0]), // ST(X)FSR is in E when mux is selecting the FSR. |
| 1779 | // Instr following LD(X)FSR is in E when mux is selecting the FSR. |
| 1780 | .dout({fad_fsr_rd_fx1[1:0], // LD(X)FSR update only |
| 1781 | fad_fsr_tem_fx1[4:0], // LD(X)FSR update only |
| 1782 | fad_fsr_ns_fx1, // LD(X)FSR update only |
| 1783 | fsr_ftt_fx1[1:0], // ST(X)FSR usage only |
| 1784 | fsr_aexc_fx1[4:0], // ST(X)FSR usage only |
| 1785 | fsr_cexc_fx1[4:0], // ST(X)FSR usage only |
| 1786 | fsr_fcc3_fx1[1:0], // STXFSR usage only |
| 1787 | fsr_fcc2_fx1[1:0], // STXFSR usage only |
| 1788 | fsr_fcc1_fx1[1:0], // STXFSR usage only |
| 1789 | fsr_fcc0_fx1[1:0]}), |
| 1790 | .se(se), |
| 1791 | .siclk(siclk), |
| 1792 | .soclk(soclk), |
| 1793 | .pce_ov(pce_ov), |
| 1794 | .stop(stop) // ST(X)FSR usage only |
| 1795 | ); |
| 1796 | |
| 1797 | // ------------------------------------ |
| 1798 | // Mantissa format muxes |
| 1799 | // ------------------------------------ |
| 1800 | |
| 1801 | fgu_fad_dp_mux_macro__mux_aonpe__ports_5__width_64 rs1fmt ( |
| 1802 | .din0({1'b1,fad_rs1_fx1[51:0], 11'b0}), // DP |
| 1803 | .din1({1'b1,fad_rs1_fx1[22:0], 40'b0}), // SP odd (rotate) |
| 1804 | .din2({1'b1,fad_rs1_fx1[54:32],40'b0}), // SP even |
| 1805 | .din3({fad_rs1_fx1[31:0], 32'b0}), // Word odd (rotate) |
| 1806 | .din4( fad_rs1_fx1[63:0] ), // Dblword, Word even |
| 1807 | // else: Const 64'b0 |
| 1808 | .sel0(aman_fmt_sel_fx1[0]), |
| 1809 | .sel1(aman_fmt_sel_fx1[1]), |
| 1810 | .sel2(aman_fmt_sel_fx1[2]), |
| 1811 | .sel3(aman_fmt_sel_fx1[3]), |
| 1812 | .sel4(aman_fmt_sel_fx1[4]), |
| 1813 | .dout(rs1_fmt_fx1[63:0]) |
| 1814 | ); |
| 1815 | |
| 1816 | fgu_fad_dp_buff_macro__width_64 buf_rs1fmt ( |
| 1817 | .din ( rs1_fmt_fx1[63:0]), |
| 1818 | .dout(fad_rs1_fmt_fx1[63:0]) |
| 1819 | ); |
| 1820 | |
| 1821 | fgu_fad_dp_mux_macro__mux_aonpe__ports_5__width_64 rs2fmt ( |
| 1822 | .din0({1'b1,fad_rs2_fx1[51:0], 11'b0}), // DP |
| 1823 | .din1({1'b1,fad_rs2_fx1[22:0], 40'b0}), // SP odd (rotate) |
| 1824 | .din2({1'b1,fad_rs2_fx1[54:32],40'b0}), // SP even |
| 1825 | .din3({fad_rs2_fx1[31:0], 32'b0}), // Word odd (rotate) |
| 1826 | .din4( fad_rs2_fx1[63:0] ), // Dblword, Word even |
| 1827 | .sel0(bman_fmt_sel_fx1[0]), |
| 1828 | .sel1(bman_fmt_sel_fx1[1]), |
| 1829 | .sel2(bman_fmt_sel_fx1[2]), |
| 1830 | .sel3(bman_fmt_sel_fx1[3]), |
| 1831 | .sel4(bman_fmt_sel_fx1[4]), |
| 1832 | .dout(rs2_fmt_fx1[63:0]) |
| 1833 | ); |
| 1834 | |
| 1835 | fgu_fad_dp_buff_macro__width_64 buf_rs2fmt ( |
| 1836 | .din ( rs2_fmt_fx1[63:0]), |
| 1837 | .dout(fad_rs2_fmt_fx1[63:0]) |
| 1838 | ); |
| 1839 | |
| 1840 | fgu_fad_dp_mux_macro__mux_aonpe__ports_4__width_64 storefmt ( |
| 1841 | .din0({fad_rs2_fx1[31:0], 32'b0}), // STF odd (rotate) |
| 1842 | .din1( fad_rs2_fx1[63:0] ), // STF even, STDF |
| 1843 | .din2({26'b0, |
| 1844 | fsr_fcc3_fx1[1:0], |
| 1845 | fsr_fcc2_fx1[1:0], |
| 1846 | fsr_fcc1_fx1[1:0], |
| 1847 | fad_fsr_rd_fx1[1:0], |
| 1848 | 2'b0, |
| 1849 | fad_fsr_tem_fx1[4:0], |
| 1850 | fad_fsr_ns_fx1, |
| 1851 | 2'b0, |
| 1852 | 3'b0, // FSR.ver = 3'b0 |
| 1853 | 1'b0, // FSR.ftt[2] = 1'b0 |
| 1854 | fsr_ftt_fx1[1:0], |
| 1855 | 2'b0, |
| 1856 | fsr_fcc0_fx1[1:0], |
| 1857 | fsr_aexc_fx1[4:0], |
| 1858 | fsr_cexc_fx1[4:0] |
| 1859 | }), // STXFSR |
| 1860 | .din3({fad_fsr_rd_fx1[1:0], |
| 1861 | 2'b0, |
| 1862 | fad_fsr_tem_fx1[4:0], |
| 1863 | fad_fsr_ns_fx1, |
| 1864 | 2'b0, |
| 1865 | 3'b0, // FSR.ver = 3'b0 |
| 1866 | 1'b0, // FSR.ftt[2] = 1'b0 |
| 1867 | fsr_ftt_fx1[1:0], |
| 1868 | 2'b0, |
| 1869 | fsr_fcc0_fx1[1:0], |
| 1870 | fsr_aexc_fx1[4:0], |
| 1871 | fsr_cexc_fx1[4:0], |
| 1872 | 32'b0 }), // STFSR |
| 1873 | .sel0(fac_fst_fmt_sel_fx1[0]), |
| 1874 | .sel1(fac_fst_fmt_sel_fx1[1]), |
| 1875 | .sel2(fac_fst_fmt_sel_fx1[2]), |
| 1876 | .sel3(fac_fst_fmt_sel_fx1[3]), |
| 1877 | .dout(fst_data_fx1[63:0]) // pwr mgmt: aomux free zeros |
| 1878 | ); |
| 1879 | |
| 1880 | fgu_fad_dp_buff_macro__rep_1__width_64 buf_storefmt ( |
| 1881 | .din ( fst_data_fx1[63:0]), |
| 1882 | .dout(fgu_lsu_fst_data_fx1[63:0]) |
| 1883 | ); |
| 1884 | |
| 1885 | |
| 1886 | // ---------------------------------------------------------------------------- |
| 1887 | // FB stage |
| 1888 | // ---------------------------------------------------------------------------- |
| 1889 | |
| 1890 | fgu_fad_dp_mux_macro__mux_aope__ports_3__width_12 w2addr ( |
| 1891 | .din0({fac_fpd_addr_fb[4:0], |
| 1892 | fac_fpd_tid_fb[2:0], |
| 1893 | fac_fpd_32b_fb, |
| 1894 | fac_fpd_odd32b_fb, |
| 1895 | pre_fpd_vld_fb[1:0]}), |
| 1896 | .din1({fac_fpd_addr_fb[4:0], |
| 1897 | fac_fpd_tid_fb[2:0], |
| 1898 | fac_fpd_32b_fb, |
| 1899 | fac_fpd_odd32b_fb, |
| 1900 | pre_fpd_vld_fb[1:0]}), |
| 1901 | .din2({lsu_fgu_fld_addr_b[4:0], |
| 1902 | lsu_fgu_fld_tid_b[2:0], |
| 1903 | lsu_fgu_fld_32b_b, |
| 1904 | lsu_fgu_fld_odd32b_b, |
| 1905 | 2'b0}), |
| 1906 | .sel0(div_finish_fltd_fb), |
| 1907 | .sel1(div_finish_flts_fb), |
| 1908 | .dout({w2_addr_fb[4:0], |
| 1909 | w2_tid_fb[2:0], |
| 1910 | w2_32b_fb, |
| 1911 | w2_odd32b_fb, |
| 1912 | fpd_vld_fb[1:0]}) |
| 1913 | ); |
| 1914 | |
| 1915 | fgu_fad_dp_inv_macro__width_5 inv_vld ( |
| 1916 | .din ({lsu_fgu_fld_32b_b, |
| 1917 | lsu_fgu_fld_odd32b_b, |
| 1918 | lsu_fgu_fsr_load_b, |
| 1919 | fpd_trap_fb, |
| 1920 | fac_fpd_odd32b_fb}), |
| 1921 | .dout({lsu_fgu_fld_32b_b_, |
| 1922 | lsu_fgu_fld_odd32b_b_, |
| 1923 | lsu_fgu_fsr_load_b_, |
| 1924 | fpd_trap_fb_, |
| 1925 | fac_fpd_odd32b_fb_}) |
| 1926 | ); |
| 1927 | |
| 1928 | fgu_fad_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 even_en_ld ( |
| 1929 | .din0(lsu_fgu_fld_32b_b ), |
| 1930 | .din1(lsu_fgu_fld_32b_b_ ), |
| 1931 | .sel0(lsu_fgu_fld_odd32b_b_), |
| 1932 | .sel1(1'b1 ), |
| 1933 | .dout(fld_w2_even_en_fb ) |
| 1934 | ); |
| 1935 | |
| 1936 | fgu_fad_dp_or_macro__ports_2__width_2 odd_en_ld ( |
| 1937 | .din0({lsu_fgu_fld_32b_b_, fpc_fpd_ieee_trap_fb }), |
| 1938 | .din1({lsu_fgu_fld_odd32b_b, fpc_fpd_unfin_fb }), |
| 1939 | .dout({fld_w2_odd_en_fb, fpd_trap_fb }) |
| 1940 | ); |
| 1941 | |
| 1942 | // 0in custom -fire ((|fad_w2_vld_fw[1:0]) & ($0in_delay((fpc_fpd_ieee_trap_fb | fpc_fpd_unfin_fb),1))) -message "FRF written during FP trap" |
| 1943 | |
| 1944 | // 0in custom -fire ((lsu_fgu_fld_vld_w & ($0in_delay((lsu_fgu_fsr_load_b & (|fpc_w1_vld_fb[1:0]) & (lsu_fgu_fld_tid_b[2:0]==fac_w1_tid_fb[2:0])),1))) | (lsu_fgu_fld_vld_w & ($0in_delay((lsu_fgu_fsr_load_b & (|fad_w1_vld_fw[1:0]) & (lsu_fgu_fld_tid_b[2:0]==fad_w1_tid_fw[2:0])),1)))) -message "LDFSR collision with FPop" |
| 1945 | |
| 1946 | fgu_fad_dp_and_macro__ports_3__width_2 and_vld ( |
| 1947 | .din0({fld_w2_even_en_fb, fld_w2_odd_en_fb }), |
| 1948 | .din1({lsu_fgu_fsr_load_b_, lsu_fgu_fsr_load_b_}), |
| 1949 | .din2({mbist_run_1f_, mbist_run_1f_ }), |
| 1950 | .dout({pre_fld_vld_fb[1], pre_fld_vld_fb[0] }) |
| 1951 | ); |
| 1952 | |
| 1953 | fgu_fad_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_2 fpd_vld ( |
| 1954 | .din0({div_finish_fltd_fb, div_finish_fltd_fb }), |
| 1955 | .din1({div_finish_flts_even_fb, div_finish_flts_odd_fb}), |
| 1956 | .sel0( fpd_trap_fb_), |
| 1957 | .sel1( fpd_trap_fb_), |
| 1958 | .dout({pre_fpd_vld_fb[1], pre_fpd_vld_fb[0] }) |
| 1959 | ); |
| 1960 | |
| 1961 | fgu_fad_dp_and_macro__ports_2__width_3 fpd_odd ( |
| 1962 | .din0({div_finish_flts_fb, div_finish_flts_fb, div_finish_flts_fb }), |
| 1963 | .din1({fac_fpd_odd32b_fb, fac_fpd_odd32b_fb, fac_fpd_odd32b_fb_ }), |
| 1964 | .dout({fpd_vld_odd32b_fb, div_finish_flts_odd_fb, div_finish_flts_even_fb}) |
| 1965 | ); |
| 1966 | |
| 1967 | fgu_fad_dp_mux_macro__mux_aonpe__ports_2__width_52 div_const ( |
| 1968 | .din0(fdd_result_rep0[62:11]), // FPD mantissa result |
| 1969 | .din1(52'hfffffffffffff), // FPD mantissa constant result for fdiv overflow (max or inf) |
| 1970 | .sel0(fpc_fpd_const_sel[0]), // Note: lack of sel0 or sel1 provides free zeros for aomux, |
| 1971 | .sel1(fpc_fpd_const_sel[1]), // fdiv underflow constant result is zero |
| 1972 | .dout(q_fdd_result_rep0[62:11]) |
| 1973 | ); |
| 1974 | |
| 1975 | fgu_fad_dp_mux_macro__mux_aope__ports_4__width_64 mux_w2data ( |
| 1976 | .din0({ fpc_fpd_sign_res, fpc_fpd_exp_res[10:0], q_fdd_result_rep0[62:11] }), // FPD result DP |
| 1977 | .din1({32'b0, fpc_fpd_sign_res, fpc_fpd_exp_res[7:0], q_fdd_result_rep0[62:40] }), // FPD result SP odd |
| 1978 | .din2({ fpc_fpd_sign_res, fpc_fpd_exp_res[7:0], q_fdd_result_rep0[62:40], 32'b0}), // FPD result SP even |
| 1979 | .din3(lsu_fgu_fld_data_b[63:0]), |
| 1980 | .sel0(div_finish_fltd_fb), |
| 1981 | .sel1(fpd_vld_odd32b_fb), |
| 1982 | .sel2(div_finish_flts_fb), |
| 1983 | .dout(w2_result_fb[63:0]) |
| 1984 | ); |
| 1985 | |
| 1986 | |
| 1987 | // ---------------------------------------------------------------------------- |
| 1988 | // FW stage |
| 1989 | // ---------------------------------------------------------------------------- |
| 1990 | |
| 1991 | fgu_fad_dp_msff_macro__width_64 fw_w2data ( |
| 1992 | .scan_in(fw_w2data_scanin), |
| 1993 | .scan_out(fw_w2data_scanout), |
| 1994 | .clk (l2clk), |
| 1995 | .en (coreon_clken), |
| 1996 | .din ( w2_result_fb[63:0]), // requires free running clk |
| 1997 | .dout(fad_nombi_w2_result_fw[63:0]), |
| 1998 | .se(se), |
| 1999 | .siclk(siclk), |
| 2000 | .soclk(soclk), |
| 2001 | .pce_ov(pce_ov), |
| 2002 | .stop(stop) |
| 2003 | ); |
| 2004 | |
| 2005 | fgu_fad_dp_msff_macro__width_64 fw_w1 ( |
| 2006 | .scan_in(fw_w1_scanin), |
| 2007 | .scan_out(fw_w1_scanout), |
| 2008 | .clk (l2clk), |
| 2009 | .en (main_clken), |
| 2010 | .din (fpf_w1_result_fb[63:0]), |
| 2011 | .dout( w1_result_fw[63:0]), |
| 2012 | .se(se), |
| 2013 | .siclk(siclk), |
| 2014 | .soclk(soclk), |
| 2015 | .pce_ov(pce_ov), |
| 2016 | .stop(stop) |
| 2017 | ); |
| 2018 | |
| 2019 | fgu_fad_dp_msff_macro__stack_32l__width_26 fw_ldfsr ( |
| 2020 | .scan_in(fw_ldfsr_scanin), |
| 2021 | .scan_out(fw_ldfsr_scanout), |
| 2022 | .clk (l2clk), |
| 2023 | .en (lsu_fgu_fld_b), |
| 2024 | .din ({lsu_fgu_fld_data_b[31:30], // requires free running clk or lsu_fgu_fld_b en |
| 2025 | lsu_fgu_fld_data_b[27:22], // requires free running clk or lsu_fgu_fld_b en |
| 2026 | lsu_fgu_fld_data_b[9:0], // requires free running clk or lsu_fgu_fld_b en |
| 2027 | lsu_fgu_fld_data_b[37:32], // requires free running clk or lsu_fgu_fld_b en |
| 2028 | lsu_fgu_fld_data_b[11:10]}), // requires free running clk or lsu_fgu_fld_b en |
| 2029 | .dout({ldfsr_data_fw[27:20], ldfsr_data_fw[17:0]}), |
| 2030 | .se(se), |
| 2031 | .siclk(siclk), |
| 2032 | .soclk(soclk), |
| 2033 | .pce_ov(pce_ov), |
| 2034 | .stop(stop) |
| 2035 | ); |
| 2036 | |
| 2037 | assign fgu_fld_fcc_fx3[7:0] = ldfsr_data_fw[7:0]; |
| 2038 | |
| 2039 | fgu_fad_dp_inv_macro__width_1 inv_mbist_run ( |
| 2040 | .din (mbist_run_1f), |
| 2041 | .dout(mbist_run_1f_) |
| 2042 | ); |
| 2043 | |
| 2044 | fgu_fad_dp_mux_macro__buffsel_none__mux_aonpe__ports_3__width_2 w2_vld ( |
| 2045 | .din0({pre_fld_vld_fw[1], pre_fld_vld_fw[0] }), // functional, pre qualified with mbist_run_1f_ |
| 2046 | .din1({fpd_vld_fw[1], fpd_vld_fw[0] }), // functional |
| 2047 | .din2({mbist_frf_write_en_1f, mbist_frf_write_en_1f}), // MBIST |
| 2048 | .sel0(lsu_fgu_fld_vld_w), |
| 2049 | .sel1(mbist_run_1f_), |
| 2050 | .sel2(mbist_run_1f), |
| 2051 | .dout({fad_w2_vld_fw[1], fad_w2_vld_fw[0] }) |
| 2052 | ); |
| 2053 | |
| 2054 | fgu_fad_dp_mux_macro__mux_pgpe__ports_2__width_64 mux_w2mbist1 ( |
| 2055 | .din0({8{fec_mbist_wdata_1f[7:0]}}), // MBIST |
| 2056 | .din1(fad_nombi_w2_result_fw[63:0]), // functional |
| 2057 | .sel0(mbist_run_1f), |
| 2058 | .dout(fad_w2_result_fw[63:0] ) |
| 2059 | ); |
| 2060 | |
| 2061 | fgu_fad_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_8 mux_w2mbist2 ( |
| 2062 | .din0({fac_mbist_addr_1f[7:5], fac_mbist_addr_1f[4:0]}), // MBIST |
| 2063 | .din1({w2_tid_fw[2:0], w2_addr_fw[4:0] }), // functional |
| 2064 | .sel0(mbist_run_1f), |
| 2065 | .sel1(mbist_run_1f_), |
| 2066 | .dout({i_w2_tid_fw[2:0], i_w2_addr_fw[4:0] }) |
| 2067 | ); |
| 2068 | |
| 2069 | fgu_fad_dp_buff_macro__width_8 buf_w2mbist2 ( |
| 2070 | .din ({ i_w2_tid_fw[2:0], i_w2_addr_fw[4:0]}), |
| 2071 | .dout({fad_w2_tid_fw[2:0], fad_w2_addr_fw[4:0]}) |
| 2072 | ); |
| 2073 | |
| 2074 | |
| 2075 | // ---------------------------------------------------------------------------- |
| 2076 | // FW1 stage |
| 2077 | // ---------------------------------------------------------------------------- |
| 2078 | |
| 2079 | fgu_fad_dp_msff_macro__minbuff_1__width_64 fw1_w2data ( |
| 2080 | .scan_in(fw1_w2data_scanin), |
| 2081 | .scan_out(fw1_w2data_scanout), |
| 2082 | .clk (l2clk), |
| 2083 | .en (main_clken), |
| 2084 | .din (fad_nombi_w2_result_fw[63:0]), |
| 2085 | .dout(w2_result_fw1[63:0]), |
| 2086 | .se(se), |
| 2087 | .siclk(siclk), |
| 2088 | .soclk(soclk), |
| 2089 | .pce_ov(pce_ov), |
| 2090 | .stop(stop) |
| 2091 | ); |
| 2092 | |
| 2093 | |
| 2094 | // fixscan start: |
| 2095 | assign e_01_scanin = scan_in ; |
| 2096 | assign e_01_extra_scanin = e_01_scanout ; |
| 2097 | assign fx1_rs1byp_scanin = e_01_extra_scanout ; |
| 2098 | assign fx1_rs2byp_scanin = fx1_rs1byp_scanout ; |
| 2099 | assign flop_rng1_4f_scanin = fx1_rs2byp_scanout ; |
| 2100 | assign flop_rng0_4f_scanin = flop_rng1_4f_scanout ; |
| 2101 | assign fx1_fsr_scanin = flop_rng0_4f_scanout ; |
| 2102 | assign fw_w2data_scanin = fx1_fsr_scanout ; |
| 2103 | assign fw_w1_scanin = fw_w2data_scanout ; |
| 2104 | assign fw_ldfsr_scanin = fw_w1_scanout ; |
| 2105 | assign fw1_w2data_scanin = fw_ldfsr_scanout ; |
| 2106 | assign scan_out = fw1_w2data_scanout ; |
| 2107 | |
| 2108 | assign fx1_fsr0_wmr_scanin = wmr_scan_in ; |
| 2109 | assign fx1_fsr1_wmr_scanin = fx1_fsr0_wmr_scanout ; |
| 2110 | assign fx1_fsr2_wmr_scanin = fx1_fsr1_wmr_scanout ; |
| 2111 | assign fx1_fsr3_wmr_scanin = fx1_fsr2_wmr_scanout ; |
| 2112 | assign fx1_fsr4_wmr_scanin = fx1_fsr3_wmr_scanout ; |
| 2113 | assign fx1_fsr5_wmr_scanin = fx1_fsr4_wmr_scanout ; |
| 2114 | assign fx1_fsr6_wmr_scanin = fx1_fsr5_wmr_scanout ; |
| 2115 | assign fx1_fsr7_wmr_scanin = fx1_fsr6_wmr_scanout ; |
| 2116 | assign wmr_scan_out = fx1_fsr7_wmr_scanout ; |
| 2117 | // fixscan end: |
| 2118 | endmodule // fgu_fad_dp |
| 2119 | |
| 2120 | |
| 2121 | |
| 2122 | // |
| 2123 | // buff macro |
| 2124 | // |
| 2125 | // |
| 2126 | |
| 2127 | |
| 2128 | |
| 2129 | |
| 2130 | |
| 2131 | module fgu_fad_dp_buff_macro__dbuff_32x__rep_1__width_4 ( |
| 2132 | din, |
| 2133 | dout); |
| 2134 | input [3:0] din; |
| 2135 | output [3:0] dout; |
| 2136 | |
| 2137 | |
| 2138 | |
| 2139 | |
| 2140 | |
| 2141 | |
| 2142 | buff #(4) d0_0 ( |
| 2143 | .in(din[3:0]), |
| 2144 | .out(dout[3:0]) |
| 2145 | ); |
| 2146 | |
| 2147 | |
| 2148 | |
| 2149 | |
| 2150 | |
| 2151 | |
| 2152 | |
| 2153 | |
| 2154 | endmodule |
| 2155 | |
| 2156 | |
| 2157 | |
| 2158 | |
| 2159 | |
| 2160 | |
| 2161 | |
| 2162 | |
| 2163 | |
| 2164 | // any PARAMS parms go into naming of macro |
| 2165 | |
| 2166 | module fgu_fad_dp_msff_macro__width_47 ( |
| 2167 | din, |
| 2168 | clk, |
| 2169 | en, |
| 2170 | se, |
| 2171 | scan_in, |
| 2172 | siclk, |
| 2173 | soclk, |
| 2174 | pce_ov, |
| 2175 | stop, |
| 2176 | dout, |
| 2177 | scan_out); |
| 2178 | wire l1clk; |
| 2179 | wire siclk_out; |
| 2180 | wire soclk_out; |
| 2181 | wire [45:0] so; |
| 2182 | |
| 2183 | input [46:0] din; |
| 2184 | |
| 2185 | |
| 2186 | input clk; |
| 2187 | input en; |
| 2188 | input se; |
| 2189 | input scan_in; |
| 2190 | input siclk; |
| 2191 | input soclk; |
| 2192 | input pce_ov; |
| 2193 | input stop; |
| 2194 | |
| 2195 | |
| 2196 | |
| 2197 | output [46:0] dout; |
| 2198 | |
| 2199 | |
| 2200 | output scan_out; |
| 2201 | |
| 2202 | |
| 2203 | |
| 2204 | |
| 2205 | cl_dp1_l1hdr_8x c0_0 ( |
| 2206 | .l2clk(clk), |
| 2207 | .pce(en), |
| 2208 | .aclk(siclk), |
| 2209 | .bclk(soclk), |
| 2210 | .l1clk(l1clk), |
| 2211 | .se(se), |
| 2212 | .pce_ov(pce_ov), |
| 2213 | .stop(stop), |
| 2214 | .siclk_out(siclk_out), |
| 2215 | .soclk_out(soclk_out) |
| 2216 | ); |
| 2217 | dff #(47) d0_0 ( |
| 2218 | .l1clk(l1clk), |
| 2219 | .siclk(siclk_out), |
| 2220 | .soclk(soclk_out), |
| 2221 | .d(din[46:0]), |
| 2222 | .si({scan_in,so[45:0]}), |
| 2223 | .so({so[45:0],scan_out}), |
| 2224 | .q(dout[46:0]) |
| 2225 | ); |
| 2226 | |
| 2227 | |
| 2228 | |
| 2229 | |
| 2230 | |
| 2231 | |
| 2232 | |
| 2233 | |
| 2234 | |
| 2235 | |
| 2236 | |
| 2237 | |
| 2238 | |
| 2239 | |
| 2240 | |
| 2241 | |
| 2242 | |
| 2243 | |
| 2244 | |
| 2245 | |
| 2246 | endmodule |
| 2247 | |
| 2248 | |
| 2249 | |
| 2250 | |
| 2251 | |
| 2252 | |
| 2253 | |
| 2254 | |
| 2255 | |
| 2256 | |
| 2257 | |
| 2258 | |
| 2259 | |
| 2260 | // any PARAMS parms go into naming of macro |
| 2261 | |
| 2262 | module fgu_fad_dp_msff_macro__width_23 ( |
| 2263 | din, |
| 2264 | clk, |
| 2265 | en, |
| 2266 | se, |
| 2267 | scan_in, |
| 2268 | siclk, |
| 2269 | soclk, |
| 2270 | pce_ov, |
| 2271 | stop, |
| 2272 | dout, |
| 2273 | scan_out); |
| 2274 | wire l1clk; |
| 2275 | wire siclk_out; |
| 2276 | wire soclk_out; |
| 2277 | wire [21:0] so; |
| 2278 | |
| 2279 | input [22:0] din; |
| 2280 | |
| 2281 | |
| 2282 | input clk; |
| 2283 | input en; |
| 2284 | input se; |
| 2285 | input scan_in; |
| 2286 | input siclk; |
| 2287 | input soclk; |
| 2288 | input pce_ov; |
| 2289 | input stop; |
| 2290 | |
| 2291 | |
| 2292 | |
| 2293 | output [22:0] dout; |
| 2294 | |
| 2295 | |
| 2296 | output scan_out; |
| 2297 | |
| 2298 | |
| 2299 | |
| 2300 | |
| 2301 | cl_dp1_l1hdr_8x c0_0 ( |
| 2302 | .l2clk(clk), |
| 2303 | .pce(en), |
| 2304 | .aclk(siclk), |
| 2305 | .bclk(soclk), |
| 2306 | .l1clk(l1clk), |
| 2307 | .se(se), |
| 2308 | .pce_ov(pce_ov), |
| 2309 | .stop(stop), |
| 2310 | .siclk_out(siclk_out), |
| 2311 | .soclk_out(soclk_out) |
| 2312 | ); |
| 2313 | dff #(23) d0_0 ( |
| 2314 | .l1clk(l1clk), |
| 2315 | .siclk(siclk_out), |
| 2316 | .soclk(soclk_out), |
| 2317 | .d(din[22:0]), |
| 2318 | .si({scan_in,so[21:0]}), |
| 2319 | .so({so[21:0],scan_out}), |
| 2320 | .q(dout[22:0]) |
| 2321 | ); |
| 2322 | |
| 2323 | |
| 2324 | |
| 2325 | |
| 2326 | |
| 2327 | |
| 2328 | |
| 2329 | |
| 2330 | |
| 2331 | |
| 2332 | |
| 2333 | |
| 2334 | |
| 2335 | |
| 2336 | |
| 2337 | |
| 2338 | |
| 2339 | |
| 2340 | |
| 2341 | |
| 2342 | endmodule |
| 2343 | |
| 2344 | |
| 2345 | |
| 2346 | |
| 2347 | |
| 2348 | |
| 2349 | |
| 2350 | |
| 2351 | |
| 2352 | // |
| 2353 | // and macro for ports = 2,3,4 |
| 2354 | // |
| 2355 | // |
| 2356 | |
| 2357 | |
| 2358 | |
| 2359 | |
| 2360 | |
| 2361 | module fgu_fad_dp_and_macro__ports_2__width_2 ( |
| 2362 | din0, |
| 2363 | din1, |
| 2364 | dout); |
| 2365 | input [1:0] din0; |
| 2366 | input [1:0] din1; |
| 2367 | output [1:0] dout; |
| 2368 | |
| 2369 | |
| 2370 | |
| 2371 | |
| 2372 | |
| 2373 | |
| 2374 | and2 #(2) d0_0 ( |
| 2375 | .in0(din0[1:0]), |
| 2376 | .in1(din1[1:0]), |
| 2377 | .out(dout[1:0]) |
| 2378 | ); |
| 2379 | |
| 2380 | |
| 2381 | |
| 2382 | |
| 2383 | |
| 2384 | |
| 2385 | |
| 2386 | |
| 2387 | |
| 2388 | endmodule |
| 2389 | |
| 2390 | |
| 2391 | |
| 2392 | |
| 2393 | |
| 2394 | // |
| 2395 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) |
| 2396 | // |
| 2397 | // |
| 2398 | |
| 2399 | |
| 2400 | |
| 2401 | |
| 2402 | |
| 2403 | module fgu_fad_dp_cmp_macro__width_12 ( |
| 2404 | din0, |
| 2405 | din1, |
| 2406 | dout); |
| 2407 | input [11:0] din0; |
| 2408 | input [11:0] din1; |
| 2409 | output dout; |
| 2410 | |
| 2411 | |
| 2412 | |
| 2413 | |
| 2414 | |
| 2415 | |
| 2416 | cmp #(12) m0_0 ( |
| 2417 | .in0(din0[11:0]), |
| 2418 | .in1(din1[11:0]), |
| 2419 | .out(dout) |
| 2420 | ); |
| 2421 | |
| 2422 | |
| 2423 | |
| 2424 | |
| 2425 | |
| 2426 | |
| 2427 | |
| 2428 | |
| 2429 | |
| 2430 | |
| 2431 | endmodule |
| 2432 | |
| 2433 | |
| 2434 | |
| 2435 | |
| 2436 | |
| 2437 | // |
| 2438 | // nor macro for ports = 2,3 |
| 2439 | // |
| 2440 | // |
| 2441 | |
| 2442 | |
| 2443 | |
| 2444 | |
| 2445 | |
| 2446 | module fgu_fad_dp_nor_macro__ports_3__width_4 ( |
| 2447 | din0, |
| 2448 | din1, |
| 2449 | din2, |
| 2450 | dout); |
| 2451 | input [3:0] din0; |
| 2452 | input [3:0] din1; |
| 2453 | input [3:0] din2; |
| 2454 | output [3:0] dout; |
| 2455 | |
| 2456 | |
| 2457 | |
| 2458 | |
| 2459 | |
| 2460 | |
| 2461 | nor3 #(4) d0_0 ( |
| 2462 | .in0(din0[3:0]), |
| 2463 | .in1(din1[3:0]), |
| 2464 | .in2(din2[3:0]), |
| 2465 | .out(dout[3:0]) |
| 2466 | ); |
| 2467 | |
| 2468 | |
| 2469 | |
| 2470 | |
| 2471 | |
| 2472 | |
| 2473 | |
| 2474 | endmodule |
| 2475 | |
| 2476 | |
| 2477 | |
| 2478 | |
| 2479 | |
| 2480 | // |
| 2481 | // nand macro for ports = 2,3,4 |
| 2482 | // |
| 2483 | // |
| 2484 | |
| 2485 | |
| 2486 | |
| 2487 | |
| 2488 | |
| 2489 | module fgu_fad_dp_nand_macro__ports_2__width_2 ( |
| 2490 | din0, |
| 2491 | din1, |
| 2492 | dout); |
| 2493 | input [1:0] din0; |
| 2494 | input [1:0] din1; |
| 2495 | output [1:0] dout; |
| 2496 | |
| 2497 | |
| 2498 | |
| 2499 | |
| 2500 | |
| 2501 | |
| 2502 | nand2 #(2) d0_0 ( |
| 2503 | .in0(din0[1:0]), |
| 2504 | .in1(din1[1:0]), |
| 2505 | .out(dout[1:0]) |
| 2506 | ); |
| 2507 | |
| 2508 | |
| 2509 | |
| 2510 | |
| 2511 | |
| 2512 | |
| 2513 | |
| 2514 | |
| 2515 | |
| 2516 | endmodule |
| 2517 | |
| 2518 | |
| 2519 | |
| 2520 | |
| 2521 | |
| 2522 | |
| 2523 | |
| 2524 | |
| 2525 | |
| 2526 | // any PARAMS parms go into naming of macro |
| 2527 | |
| 2528 | module fgu_fad_dp_msff_macro__dmux_4x__mux_aope__ports_7__width_64 ( |
| 2529 | din0, |
| 2530 | din1, |
| 2531 | din2, |
| 2532 | din3, |
| 2533 | din4, |
| 2534 | din5, |
| 2535 | din6, |
| 2536 | sel0, |
| 2537 | sel1, |
| 2538 | sel2, |
| 2539 | sel3, |
| 2540 | sel4, |
| 2541 | sel5, |
| 2542 | clk, |
| 2543 | en, |
| 2544 | se, |
| 2545 | scan_in, |
| 2546 | siclk, |
| 2547 | soclk, |
| 2548 | pce_ov, |
| 2549 | stop, |
| 2550 | dout, |
| 2551 | scan_out); |
| 2552 | wire psel0; |
| 2553 | wire psel1; |
| 2554 | wire psel2; |
| 2555 | wire psel3; |
| 2556 | wire psel4; |
| 2557 | wire psel5; |
| 2558 | wire psel6; |
| 2559 | wire [63:0] muxout; |
| 2560 | wire l1clk; |
| 2561 | wire siclk_out; |
| 2562 | wire soclk_out; |
| 2563 | wire [62:0] so; |
| 2564 | |
| 2565 | input [63:0] din0; |
| 2566 | input [63:0] din1; |
| 2567 | input [63:0] din2; |
| 2568 | input [63:0] din3; |
| 2569 | input [63:0] din4; |
| 2570 | input [63:0] din5; |
| 2571 | input [63:0] din6; |
| 2572 | input sel0; |
| 2573 | input sel1; |
| 2574 | input sel2; |
| 2575 | input sel3; |
| 2576 | input sel4; |
| 2577 | input sel5; |
| 2578 | |
| 2579 | |
| 2580 | input clk; |
| 2581 | input en; |
| 2582 | input se; |
| 2583 | input scan_in; |
| 2584 | input siclk; |
| 2585 | input soclk; |
| 2586 | input pce_ov; |
| 2587 | input stop; |
| 2588 | |
| 2589 | |
| 2590 | |
| 2591 | output [63:0] dout; |
| 2592 | |
| 2593 | |
| 2594 | output scan_out; |
| 2595 | |
| 2596 | |
| 2597 | |
| 2598 | |
| 2599 | cl_dp1_penc7_8x c1_0 ( |
| 2600 | .test(1'b1), |
| 2601 | .sel0(sel0), |
| 2602 | .sel1(sel1), |
| 2603 | .sel2(sel2), |
| 2604 | .sel3(sel3), |
| 2605 | .sel4(sel4), |
| 2606 | .sel5(sel5), |
| 2607 | .psel0(psel0), |
| 2608 | .psel1(psel1), |
| 2609 | .psel2(psel2), |
| 2610 | .psel3(psel3), |
| 2611 | .psel4(psel4), |
| 2612 | .psel5(psel5), |
| 2613 | .psel6(psel6) |
| 2614 | ); |
| 2615 | |
| 2616 | mux7s #(64) d1_0 ( |
| 2617 | .sel0(psel0), |
| 2618 | .sel1(psel1), |
| 2619 | .sel2(psel2), |
| 2620 | .sel3(psel3), |
| 2621 | .sel4(psel4), |
| 2622 | .sel5(psel5), |
| 2623 | .sel6(psel6), |
| 2624 | .in0(din0[63:0]), |
| 2625 | .in1(din1[63:0]), |
| 2626 | .in2(din2[63:0]), |
| 2627 | .in3(din3[63:0]), |
| 2628 | .in4(din4[63:0]), |
| 2629 | .in5(din5[63:0]), |
| 2630 | .in6(din6[63:0]), |
| 2631 | .dout(muxout[63:0]) |
| 2632 | ); |
| 2633 | cl_dp1_l1hdr_8x c0_0 ( |
| 2634 | .l2clk(clk), |
| 2635 | .pce(en), |
| 2636 | .aclk(siclk), |
| 2637 | .bclk(soclk), |
| 2638 | .l1clk(l1clk), |
| 2639 | .se(se), |
| 2640 | .pce_ov(pce_ov), |
| 2641 | .stop(stop), |
| 2642 | .siclk_out(siclk_out), |
| 2643 | .soclk_out(soclk_out) |
| 2644 | ); |
| 2645 | dff #(64) d0_0 ( |
| 2646 | .l1clk(l1clk), |
| 2647 | .siclk(siclk_out), |
| 2648 | .soclk(soclk_out), |
| 2649 | .d(muxout[63:0]), |
| 2650 | .si({scan_in,so[62:0]}), |
| 2651 | .so({so[62:0],scan_out}), |
| 2652 | .q(dout[63:0]) |
| 2653 | ); |
| 2654 | |
| 2655 | |
| 2656 | |
| 2657 | |
| 2658 | |
| 2659 | |
| 2660 | |
| 2661 | |
| 2662 | |
| 2663 | |
| 2664 | |
| 2665 | |
| 2666 | |
| 2667 | |
| 2668 | |
| 2669 | |
| 2670 | |
| 2671 | |
| 2672 | |
| 2673 | |
| 2674 | endmodule |
| 2675 | |
| 2676 | |
| 2677 | |
| 2678 | |
| 2679 | |
| 2680 | |
| 2681 | |
| 2682 | |
| 2683 | |
| 2684 | // |
| 2685 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) |
| 2686 | // |
| 2687 | // |
| 2688 | |
| 2689 | |
| 2690 | |
| 2691 | |
| 2692 | |
| 2693 | module fgu_fad_dp_cmp_macro__width_64 ( |
| 2694 | din0, |
| 2695 | din1, |
| 2696 | dout); |
| 2697 | input [63:0] din0; |
| 2698 | input [63:0] din1; |
| 2699 | output dout; |
| 2700 | |
| 2701 | |
| 2702 | |
| 2703 | |
| 2704 | |
| 2705 | |
| 2706 | cmp #(64) m0_0 ( |
| 2707 | .in0(din0[63:0]), |
| 2708 | .in1(din1[63:0]), |
| 2709 | .out(dout) |
| 2710 | ); |
| 2711 | |
| 2712 | |
| 2713 | |
| 2714 | |
| 2715 | |
| 2716 | |
| 2717 | |
| 2718 | |
| 2719 | |
| 2720 | |
| 2721 | endmodule |
| 2722 | |
| 2723 | |
| 2724 | |
| 2725 | |
| 2726 | |
| 2727 | // |
| 2728 | // parity macro (even parity) |
| 2729 | // |
| 2730 | // |
| 2731 | |
| 2732 | |
| 2733 | |
| 2734 | |
| 2735 | |
| 2736 | module fgu_fad_dp_prty_macro__width_32 ( |
| 2737 | din, |
| 2738 | dout); |
| 2739 | input [31:0] din; |
| 2740 | output dout; |
| 2741 | |
| 2742 | |
| 2743 | |
| 2744 | |
| 2745 | |
| 2746 | |
| 2747 | |
| 2748 | prty #(32) m0_0 ( |
| 2749 | .in(din[31:0]), |
| 2750 | .out(dout) |
| 2751 | ); |
| 2752 | |
| 2753 | |
| 2754 | |
| 2755 | |
| 2756 | |
| 2757 | |
| 2758 | |
| 2759 | |
| 2760 | |
| 2761 | |
| 2762 | endmodule |
| 2763 | |
| 2764 | |
| 2765 | |
| 2766 | |
| 2767 | |
| 2768 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2769 | // also for pass-gate with decoder |
| 2770 | |
| 2771 | |
| 2772 | |
| 2773 | |
| 2774 | |
| 2775 | // any PARAMS parms go into naming of macro |
| 2776 | |
| 2777 | module fgu_fad_dp_mux_macro__mux_aonpe__ports_3__stack_32l__width_12 ( |
| 2778 | din0, |
| 2779 | sel0, |
| 2780 | din1, |
| 2781 | sel1, |
| 2782 | din2, |
| 2783 | sel2, |
| 2784 | dout); |
| 2785 | wire buffout0; |
| 2786 | wire buffout1; |
| 2787 | wire buffout2; |
| 2788 | |
| 2789 | input [11:0] din0; |
| 2790 | input sel0; |
| 2791 | input [11:0] din1; |
| 2792 | input sel1; |
| 2793 | input [11:0] din2; |
| 2794 | input sel2; |
| 2795 | output [11:0] dout; |
| 2796 | |
| 2797 | |
| 2798 | |
| 2799 | |
| 2800 | |
| 2801 | cl_dp1_muxbuff3_8x c0_0 ( |
| 2802 | .in0(sel0), |
| 2803 | .in1(sel1), |
| 2804 | .in2(sel2), |
| 2805 | .out0(buffout0), |
| 2806 | .out1(buffout1), |
| 2807 | .out2(buffout2) |
| 2808 | ); |
| 2809 | mux3s #(12) d0_0 ( |
| 2810 | .sel0(buffout0), |
| 2811 | .sel1(buffout1), |
| 2812 | .sel2(buffout2), |
| 2813 | .in0(din0[11:0]), |
| 2814 | .in1(din1[11:0]), |
| 2815 | .in2(din2[11:0]), |
| 2816 | .dout(dout[11:0]) |
| 2817 | ); |
| 2818 | |
| 2819 | |
| 2820 | |
| 2821 | |
| 2822 | |
| 2823 | |
| 2824 | |
| 2825 | |
| 2826 | |
| 2827 | |
| 2828 | |
| 2829 | |
| 2830 | |
| 2831 | endmodule |
| 2832 | |
| 2833 | |
| 2834 | |
| 2835 | |
| 2836 | |
| 2837 | |
| 2838 | // any PARAMS parms go into naming of macro |
| 2839 | |
| 2840 | module fgu_fad_dp_msff_macro__mux_aodec__ports_8__stack_32l__width_28 ( |
| 2841 | din0, |
| 2842 | din1, |
| 2843 | din2, |
| 2844 | din3, |
| 2845 | din4, |
| 2846 | din5, |
| 2847 | din6, |
| 2848 | din7, |
| 2849 | sel, |
| 2850 | clk, |
| 2851 | en, |
| 2852 | se, |
| 2853 | scan_in, |
| 2854 | siclk, |
| 2855 | soclk, |
| 2856 | pce_ov, |
| 2857 | stop, |
| 2858 | dout, |
| 2859 | scan_out); |
| 2860 | wire psel0; |
| 2861 | wire psel1; |
| 2862 | wire psel2; |
| 2863 | wire psel3; |
| 2864 | wire psel4; |
| 2865 | wire psel5; |
| 2866 | wire psel6; |
| 2867 | wire psel7; |
| 2868 | wire [27:0] muxout; |
| 2869 | wire l1clk; |
| 2870 | wire siclk_out; |
| 2871 | wire soclk_out; |
| 2872 | wire [26:0] so; |
| 2873 | |
| 2874 | input [27:0] din0; |
| 2875 | input [27:0] din1; |
| 2876 | input [27:0] din2; |
| 2877 | input [27:0] din3; |
| 2878 | input [27:0] din4; |
| 2879 | input [27:0] din5; |
| 2880 | input [27:0] din6; |
| 2881 | input [27:0] din7; |
| 2882 | input [2:0] sel; |
| 2883 | |
| 2884 | |
| 2885 | input clk; |
| 2886 | input en; |
| 2887 | input se; |
| 2888 | input scan_in; |
| 2889 | input siclk; |
| 2890 | input soclk; |
| 2891 | input pce_ov; |
| 2892 | input stop; |
| 2893 | |
| 2894 | |
| 2895 | |
| 2896 | output [27:0] dout; |
| 2897 | |
| 2898 | |
| 2899 | output scan_out; |
| 2900 | |
| 2901 | |
| 2902 | |
| 2903 | |
| 2904 | cl_dp1_pdec8_8x c1_0 ( |
| 2905 | .test(1'b1), |
| 2906 | .sel0(sel[0]), |
| 2907 | .sel1(sel[1]), |
| 2908 | .sel2(sel[2]), |
| 2909 | .psel0(psel0), |
| 2910 | .psel1(psel1), |
| 2911 | .psel2(psel2), |
| 2912 | .psel3(psel3), |
| 2913 | .psel4(psel4), |
| 2914 | .psel5(psel5), |
| 2915 | .psel6(psel6), |
| 2916 | .psel7(psel7) |
| 2917 | ); |
| 2918 | |
| 2919 | mux8s #(28) d1_0 ( |
| 2920 | .sel0(psel0), |
| 2921 | .sel1(psel1), |
| 2922 | .sel2(psel2), |
| 2923 | .sel3(psel3), |
| 2924 | .sel4(psel4), |
| 2925 | .sel5(psel5), |
| 2926 | .sel6(psel6), |
| 2927 | .sel7(psel7), |
| 2928 | .in0(din0[27:0]), |
| 2929 | .in1(din1[27:0]), |
| 2930 | .in2(din2[27:0]), |
| 2931 | .in3(din3[27:0]), |
| 2932 | .in4(din4[27:0]), |
| 2933 | .in5(din5[27:0]), |
| 2934 | .in6(din6[27:0]), |
| 2935 | .in7(din7[27:0]), |
| 2936 | .dout(muxout[27:0]) |
| 2937 | ); |
| 2938 | cl_dp1_l1hdr_8x c0_0 ( |
| 2939 | .l2clk(clk), |
| 2940 | .pce(en), |
| 2941 | .aclk(siclk), |
| 2942 | .bclk(soclk), |
| 2943 | .l1clk(l1clk), |
| 2944 | .se(se), |
| 2945 | .pce_ov(pce_ov), |
| 2946 | .stop(stop), |
| 2947 | .siclk_out(siclk_out), |
| 2948 | .soclk_out(soclk_out) |
| 2949 | ); |
| 2950 | dff #(28) d0_0 ( |
| 2951 | .l1clk(l1clk), |
| 2952 | .siclk(siclk_out), |
| 2953 | .soclk(soclk_out), |
| 2954 | .d(muxout[27:0]), |
| 2955 | .si({scan_in,so[26:0]}), |
| 2956 | .so({so[26:0],scan_out}), |
| 2957 | .q(dout[27:0]) |
| 2958 | ); |
| 2959 | |
| 2960 | |
| 2961 | |
| 2962 | |
| 2963 | |
| 2964 | |
| 2965 | |
| 2966 | |
| 2967 | |
| 2968 | |
| 2969 | |
| 2970 | |
| 2971 | |
| 2972 | |
| 2973 | |
| 2974 | |
| 2975 | |
| 2976 | |
| 2977 | |
| 2978 | |
| 2979 | endmodule |
| 2980 | |
| 2981 | |
| 2982 | |
| 2983 | |
| 2984 | |
| 2985 | |
| 2986 | |
| 2987 | |
| 2988 | |
| 2989 | |
| 2990 | |
| 2991 | |
| 2992 | |
| 2993 | // any PARAMS parms go into naming of macro |
| 2994 | |
| 2995 | module fgu_fad_dp_msff_macro__stack_32l__width_31 ( |
| 2996 | din, |
| 2997 | clk, |
| 2998 | en, |
| 2999 | se, |
| 3000 | scan_in, |
| 3001 | siclk, |
| 3002 | soclk, |
| 3003 | pce_ov, |
| 3004 | stop, |
| 3005 | dout, |
| 3006 | scan_out); |
| 3007 | wire l1clk; |
| 3008 | wire siclk_out; |
| 3009 | wire soclk_out; |
| 3010 | wire [29:0] so; |
| 3011 | |
| 3012 | input [30:0] din; |
| 3013 | |
| 3014 | |
| 3015 | input clk; |
| 3016 | input en; |
| 3017 | input se; |
| 3018 | input scan_in; |
| 3019 | input siclk; |
| 3020 | input soclk; |
| 3021 | input pce_ov; |
| 3022 | input stop; |
| 3023 | |
| 3024 | |
| 3025 | |
| 3026 | output [30:0] dout; |
| 3027 | |
| 3028 | |
| 3029 | output scan_out; |
| 3030 | |
| 3031 | |
| 3032 | |
| 3033 | |
| 3034 | cl_dp1_l1hdr_8x c0_0 ( |
| 3035 | .l2clk(clk), |
| 3036 | .pce(en), |
| 3037 | .aclk(siclk), |
| 3038 | .bclk(soclk), |
| 3039 | .l1clk(l1clk), |
| 3040 | .se(se), |
| 3041 | .pce_ov(pce_ov), |
| 3042 | .stop(stop), |
| 3043 | .siclk_out(siclk_out), |
| 3044 | .soclk_out(soclk_out) |
| 3045 | ); |
| 3046 | dff #(31) d0_0 ( |
| 3047 | .l1clk(l1clk), |
| 3048 | .siclk(siclk_out), |
| 3049 | .soclk(soclk_out), |
| 3050 | .d(din[30:0]), |
| 3051 | .si({scan_in,so[29:0]}), |
| 3052 | .so({so[29:0],scan_out}), |
| 3053 | .q(dout[30:0]) |
| 3054 | ); |
| 3055 | |
| 3056 | |
| 3057 | |
| 3058 | |
| 3059 | |
| 3060 | |
| 3061 | |
| 3062 | |
| 3063 | |
| 3064 | |
| 3065 | |
| 3066 | |
| 3067 | |
| 3068 | |
| 3069 | |
| 3070 | |
| 3071 | |
| 3072 | |
| 3073 | |
| 3074 | |
| 3075 | endmodule |
| 3076 | |
| 3077 | |
| 3078 | |
| 3079 | |
| 3080 | |
| 3081 | |
| 3082 | |
| 3083 | |
| 3084 | |
| 3085 | |
| 3086 | |
| 3087 | |
| 3088 | |
| 3089 | // any PARAMS parms go into naming of macro |
| 3090 | |
| 3091 | module fgu_fad_dp_msff_macro__stack_32l__width_32 ( |
| 3092 | din, |
| 3093 | clk, |
| 3094 | en, |
| 3095 | se, |
| 3096 | scan_in, |
| 3097 | siclk, |
| 3098 | soclk, |
| 3099 | pce_ov, |
| 3100 | stop, |
| 3101 | dout, |
| 3102 | scan_out); |
| 3103 | wire l1clk; |
| 3104 | wire siclk_out; |
| 3105 | wire soclk_out; |
| 3106 | wire [30:0] so; |
| 3107 | |
| 3108 | input [31:0] din; |
| 3109 | |
| 3110 | |
| 3111 | input clk; |
| 3112 | input en; |
| 3113 | input se; |
| 3114 | input scan_in; |
| 3115 | input siclk; |
| 3116 | input soclk; |
| 3117 | input pce_ov; |
| 3118 | input stop; |
| 3119 | |
| 3120 | |
| 3121 | |
| 3122 | output [31:0] dout; |
| 3123 | |
| 3124 | |
| 3125 | output scan_out; |
| 3126 | |
| 3127 | |
| 3128 | |
| 3129 | |
| 3130 | cl_dp1_l1hdr_8x c0_0 ( |
| 3131 | .l2clk(clk), |
| 3132 | .pce(en), |
| 3133 | .aclk(siclk), |
| 3134 | .bclk(soclk), |
| 3135 | .l1clk(l1clk), |
| 3136 | .se(se), |
| 3137 | .pce_ov(pce_ov), |
| 3138 | .stop(stop), |
| 3139 | .siclk_out(siclk_out), |
| 3140 | .soclk_out(soclk_out) |
| 3141 | ); |
| 3142 | dff #(32) d0_0 ( |
| 3143 | .l1clk(l1clk), |
| 3144 | .siclk(siclk_out), |
| 3145 | .soclk(soclk_out), |
| 3146 | .d(din[31:0]), |
| 3147 | .si({scan_in,so[30:0]}), |
| 3148 | .so({so[30:0],scan_out}), |
| 3149 | .q(dout[31:0]) |
| 3150 | ); |
| 3151 | |
| 3152 | |
| 3153 | |
| 3154 | |
| 3155 | |
| 3156 | |
| 3157 | |
| 3158 | |
| 3159 | |
| 3160 | |
| 3161 | |
| 3162 | |
| 3163 | |
| 3164 | |
| 3165 | |
| 3166 | |
| 3167 | |
| 3168 | |
| 3169 | |
| 3170 | |
| 3171 | endmodule |
| 3172 | |
| 3173 | |
| 3174 | |
| 3175 | |
| 3176 | |
| 3177 | |
| 3178 | |
| 3179 | |
| 3180 | |
| 3181 | // |
| 3182 | // buff macro |
| 3183 | // |
| 3184 | // |
| 3185 | |
| 3186 | |
| 3187 | |
| 3188 | |
| 3189 | |
| 3190 | module fgu_fad_dp_buff_macro__rep_1__stack_32l__width_31 ( |
| 3191 | din, |
| 3192 | dout); |
| 3193 | input [30:0] din; |
| 3194 | output [30:0] dout; |
| 3195 | |
| 3196 | |
| 3197 | |
| 3198 | |
| 3199 | |
| 3200 | |
| 3201 | buff #(31) d0_0 ( |
| 3202 | .in(din[30:0]), |
| 3203 | .out(dout[30:0]) |
| 3204 | ); |
| 3205 | |
| 3206 | |
| 3207 | |
| 3208 | |
| 3209 | |
| 3210 | |
| 3211 | |
| 3212 | |
| 3213 | endmodule |
| 3214 | |
| 3215 | |
| 3216 | |
| 3217 | |
| 3218 | |
| 3219 | // |
| 3220 | // buff macro |
| 3221 | // |
| 3222 | // |
| 3223 | |
| 3224 | |
| 3225 | |
| 3226 | |
| 3227 | |
| 3228 | module fgu_fad_dp_buff_macro__rep_1__stack_32l__width_32 ( |
| 3229 | din, |
| 3230 | dout); |
| 3231 | input [31:0] din; |
| 3232 | output [31:0] dout; |
| 3233 | |
| 3234 | |
| 3235 | |
| 3236 | |
| 3237 | |
| 3238 | |
| 3239 | buff #(32) d0_0 ( |
| 3240 | .in(din[31:0]), |
| 3241 | .out(dout[31:0]) |
| 3242 | ); |
| 3243 | |
| 3244 | |
| 3245 | |
| 3246 | |
| 3247 | |
| 3248 | |
| 3249 | |
| 3250 | |
| 3251 | endmodule |
| 3252 | |
| 3253 | |
| 3254 | |
| 3255 | |
| 3256 | |
| 3257 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 3258 | // also for pass-gate with decoder |
| 3259 | |
| 3260 | |
| 3261 | |
| 3262 | |
| 3263 | |
| 3264 | // any PARAMS parms go into naming of macro |
| 3265 | |
| 3266 | module fgu_fad_dp_mux_macro__mux_aonpe__ports_5__width_64 ( |
| 3267 | din0, |
| 3268 | sel0, |
| 3269 | din1, |
| 3270 | sel1, |
| 3271 | din2, |
| 3272 | sel2, |
| 3273 | din3, |
| 3274 | sel3, |
| 3275 | din4, |
| 3276 | sel4, |
| 3277 | dout); |
| 3278 | wire buffout0; |
| 3279 | wire buffout1; |
| 3280 | wire buffout2; |
| 3281 | wire buffout3; |
| 3282 | wire buffout4; |
| 3283 | |
| 3284 | input [63:0] din0; |
| 3285 | input sel0; |
| 3286 | input [63:0] din1; |
| 3287 | input sel1; |
| 3288 | input [63:0] din2; |
| 3289 | input sel2; |
| 3290 | input [63:0] din3; |
| 3291 | input sel3; |
| 3292 | input [63:0] din4; |
| 3293 | input sel4; |
| 3294 | output [63:0] dout; |
| 3295 | |
| 3296 | |
| 3297 | |
| 3298 | |
| 3299 | |
| 3300 | cl_dp1_muxbuff5_8x c0_0 ( |
| 3301 | .in0(sel0), |
| 3302 | .in1(sel1), |
| 3303 | .in2(sel2), |
| 3304 | .in3(sel3), |
| 3305 | .in4(sel4), |
| 3306 | .out0(buffout0), |
| 3307 | .out1(buffout1), |
| 3308 | .out2(buffout2), |
| 3309 | .out3(buffout3), |
| 3310 | .out4(buffout4) |
| 3311 | ); |
| 3312 | mux5s #(64) d0_0 ( |
| 3313 | .sel0(buffout0), |
| 3314 | .sel1(buffout1), |
| 3315 | .sel2(buffout2), |
| 3316 | .sel3(buffout3), |
| 3317 | .sel4(buffout4), |
| 3318 | .in0(din0[63:0]), |
| 3319 | .in1(din1[63:0]), |
| 3320 | .in2(din2[63:0]), |
| 3321 | .in3(din3[63:0]), |
| 3322 | .in4(din4[63:0]), |
| 3323 | .dout(dout[63:0]) |
| 3324 | ); |
| 3325 | |
| 3326 | |
| 3327 | |
| 3328 | |
| 3329 | |
| 3330 | |
| 3331 | |
| 3332 | |
| 3333 | |
| 3334 | |
| 3335 | |
| 3336 | |
| 3337 | |
| 3338 | endmodule |
| 3339 | |
| 3340 | |
| 3341 | // |
| 3342 | // buff macro |
| 3343 | // |
| 3344 | // |
| 3345 | |
| 3346 | |
| 3347 | |
| 3348 | |
| 3349 | |
| 3350 | module fgu_fad_dp_buff_macro__width_64 ( |
| 3351 | din, |
| 3352 | dout); |
| 3353 | input [63:0] din; |
| 3354 | output [63:0] dout; |
| 3355 | |
| 3356 | |
| 3357 | |
| 3358 | |
| 3359 | |
| 3360 | |
| 3361 | buff #(64) d0_0 ( |
| 3362 | .in(din[63:0]), |
| 3363 | .out(dout[63:0]) |
| 3364 | ); |
| 3365 | |
| 3366 | |
| 3367 | |
| 3368 | |
| 3369 | |
| 3370 | |
| 3371 | |
| 3372 | |
| 3373 | endmodule |
| 3374 | |
| 3375 | |
| 3376 | |
| 3377 | |
| 3378 | |
| 3379 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 3380 | // also for pass-gate with decoder |
| 3381 | |
| 3382 | |
| 3383 | |
| 3384 | |
| 3385 | |
| 3386 | // any PARAMS parms go into naming of macro |
| 3387 | |
| 3388 | module fgu_fad_dp_mux_macro__mux_aonpe__ports_4__width_64 ( |
| 3389 | din0, |
| 3390 | sel0, |
| 3391 | din1, |
| 3392 | sel1, |
| 3393 | din2, |
| 3394 | sel2, |
| 3395 | din3, |
| 3396 | sel3, |
| 3397 | dout); |
| 3398 | wire buffout0; |
| 3399 | wire buffout1; |
| 3400 | wire buffout2; |
| 3401 | wire buffout3; |
| 3402 | |
| 3403 | input [63:0] din0; |
| 3404 | input sel0; |
| 3405 | input [63:0] din1; |
| 3406 | input sel1; |
| 3407 | input [63:0] din2; |
| 3408 | input sel2; |
| 3409 | input [63:0] din3; |
| 3410 | input sel3; |
| 3411 | output [63:0] dout; |
| 3412 | |
| 3413 | |
| 3414 | |
| 3415 | |
| 3416 | |
| 3417 | cl_dp1_muxbuff4_8x c0_0 ( |
| 3418 | .in0(sel0), |
| 3419 | .in1(sel1), |
| 3420 | .in2(sel2), |
| 3421 | .in3(sel3), |
| 3422 | .out0(buffout0), |
| 3423 | .out1(buffout1), |
| 3424 | .out2(buffout2), |
| 3425 | .out3(buffout3) |
| 3426 | ); |
| 3427 | mux4s #(64) d0_0 ( |
| 3428 | .sel0(buffout0), |
| 3429 | .sel1(buffout1), |
| 3430 | .sel2(buffout2), |
| 3431 | .sel3(buffout3), |
| 3432 | .in0(din0[63:0]), |
| 3433 | .in1(din1[63:0]), |
| 3434 | .in2(din2[63:0]), |
| 3435 | .in3(din3[63:0]), |
| 3436 | .dout(dout[63:0]) |
| 3437 | ); |
| 3438 | |
| 3439 | |
| 3440 | |
| 3441 | |
| 3442 | |
| 3443 | |
| 3444 | |
| 3445 | |
| 3446 | |
| 3447 | |
| 3448 | |
| 3449 | |
| 3450 | |
| 3451 | endmodule |
| 3452 | |
| 3453 | |
| 3454 | // |
| 3455 | // buff macro |
| 3456 | // |
| 3457 | // |
| 3458 | |
| 3459 | |
| 3460 | |
| 3461 | |
| 3462 | |
| 3463 | module fgu_fad_dp_buff_macro__rep_1__width_64 ( |
| 3464 | din, |
| 3465 | dout); |
| 3466 | input [63:0] din; |
| 3467 | output [63:0] dout; |
| 3468 | |
| 3469 | |
| 3470 | |
| 3471 | |
| 3472 | |
| 3473 | |
| 3474 | buff #(64) d0_0 ( |
| 3475 | .in(din[63:0]), |
| 3476 | .out(dout[63:0]) |
| 3477 | ); |
| 3478 | |
| 3479 | |
| 3480 | |
| 3481 | |
| 3482 | |
| 3483 | |
| 3484 | |
| 3485 | |
| 3486 | endmodule |
| 3487 | |
| 3488 | |
| 3489 | |
| 3490 | |
| 3491 | |
| 3492 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 3493 | // also for pass-gate with decoder |
| 3494 | |
| 3495 | |
| 3496 | |
| 3497 | |
| 3498 | |
| 3499 | // any PARAMS parms go into naming of macro |
| 3500 | |
| 3501 | module fgu_fad_dp_mux_macro__mux_aope__ports_3__width_12 ( |
| 3502 | din0, |
| 3503 | din1, |
| 3504 | din2, |
| 3505 | sel0, |
| 3506 | sel1, |
| 3507 | dout); |
| 3508 | wire psel0; |
| 3509 | wire psel1; |
| 3510 | wire psel2; |
| 3511 | |
| 3512 | input [11:0] din0; |
| 3513 | input [11:0] din1; |
| 3514 | input [11:0] din2; |
| 3515 | input sel0; |
| 3516 | input sel1; |
| 3517 | output [11:0] dout; |
| 3518 | |
| 3519 | |
| 3520 | |
| 3521 | |
| 3522 | |
| 3523 | cl_dp1_penc3_8x c0_0 ( |
| 3524 | .test(1'b1), |
| 3525 | .sel0(sel0), |
| 3526 | .sel1(sel1), |
| 3527 | .psel0(psel0), |
| 3528 | .psel1(psel1), |
| 3529 | .psel2(psel2) |
| 3530 | ); |
| 3531 | |
| 3532 | mux3s #(12) d0_0 ( |
| 3533 | .sel0(psel0), |
| 3534 | .sel1(psel1), |
| 3535 | .sel2(psel2), |
| 3536 | .in0(din0[11:0]), |
| 3537 | .in1(din1[11:0]), |
| 3538 | .in2(din2[11:0]), |
| 3539 | .dout(dout[11:0]) |
| 3540 | ); |
| 3541 | |
| 3542 | |
| 3543 | |
| 3544 | |
| 3545 | |
| 3546 | |
| 3547 | |
| 3548 | |
| 3549 | |
| 3550 | |
| 3551 | |
| 3552 | |
| 3553 | |
| 3554 | endmodule |
| 3555 | |
| 3556 | |
| 3557 | // |
| 3558 | // invert macro |
| 3559 | // |
| 3560 | // |
| 3561 | |
| 3562 | |
| 3563 | |
| 3564 | |
| 3565 | |
| 3566 | module fgu_fad_dp_inv_macro__width_5 ( |
| 3567 | din, |
| 3568 | dout); |
| 3569 | input [4:0] din; |
| 3570 | output [4:0] dout; |
| 3571 | |
| 3572 | |
| 3573 | |
| 3574 | |
| 3575 | |
| 3576 | |
| 3577 | inv #(5) d0_0 ( |
| 3578 | .in(din[4:0]), |
| 3579 | .out(dout[4:0]) |
| 3580 | ); |
| 3581 | |
| 3582 | |
| 3583 | |
| 3584 | |
| 3585 | |
| 3586 | |
| 3587 | |
| 3588 | |
| 3589 | |
| 3590 | endmodule |
| 3591 | |
| 3592 | |
| 3593 | |
| 3594 | |
| 3595 | |
| 3596 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 3597 | // also for pass-gate with decoder |
| 3598 | |
| 3599 | |
| 3600 | |
| 3601 | |
| 3602 | |
| 3603 | // any PARAMS parms go into naming of macro |
| 3604 | |
| 3605 | module fgu_fad_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 ( |
| 3606 | din0, |
| 3607 | sel0, |
| 3608 | din1, |
| 3609 | sel1, |
| 3610 | dout); |
| 3611 | input [0:0] din0; |
| 3612 | input sel0; |
| 3613 | input [0:0] din1; |
| 3614 | input sel1; |
| 3615 | output [0:0] dout; |
| 3616 | |
| 3617 | |
| 3618 | |
| 3619 | |
| 3620 | |
| 3621 | mux2s #(1) d0_0 ( |
| 3622 | .sel0(sel0), |
| 3623 | .sel1(sel1), |
| 3624 | .in0(din0[0:0]), |
| 3625 | .in1(din1[0:0]), |
| 3626 | .dout(dout[0:0]) |
| 3627 | ); |
| 3628 | |
| 3629 | |
| 3630 | |
| 3631 | |
| 3632 | |
| 3633 | |
| 3634 | |
| 3635 | |
| 3636 | |
| 3637 | |
| 3638 | |
| 3639 | |
| 3640 | |
| 3641 | endmodule |
| 3642 | |
| 3643 | |
| 3644 | // |
| 3645 | // or macro for ports = 2,3 |
| 3646 | // |
| 3647 | // |
| 3648 | |
| 3649 | |
| 3650 | |
| 3651 | |
| 3652 | |
| 3653 | module fgu_fad_dp_or_macro__ports_2__width_2 ( |
| 3654 | din0, |
| 3655 | din1, |
| 3656 | dout); |
| 3657 | input [1:0] din0; |
| 3658 | input [1:0] din1; |
| 3659 | output [1:0] dout; |
| 3660 | |
| 3661 | |
| 3662 | |
| 3663 | |
| 3664 | |
| 3665 | |
| 3666 | or2 #(2) d0_0 ( |
| 3667 | .in0(din0[1:0]), |
| 3668 | .in1(din1[1:0]), |
| 3669 | .out(dout[1:0]) |
| 3670 | ); |
| 3671 | |
| 3672 | |
| 3673 | |
| 3674 | |
| 3675 | |
| 3676 | |
| 3677 | |
| 3678 | |
| 3679 | |
| 3680 | endmodule |
| 3681 | |
| 3682 | |
| 3683 | |
| 3684 | |
| 3685 | |
| 3686 | // |
| 3687 | // and macro for ports = 2,3,4 |
| 3688 | // |
| 3689 | // |
| 3690 | |
| 3691 | |
| 3692 | |
| 3693 | |
| 3694 | |
| 3695 | module fgu_fad_dp_and_macro__ports_3__width_2 ( |
| 3696 | din0, |
| 3697 | din1, |
| 3698 | din2, |
| 3699 | dout); |
| 3700 | input [1:0] din0; |
| 3701 | input [1:0] din1; |
| 3702 | input [1:0] din2; |
| 3703 | output [1:0] dout; |
| 3704 | |
| 3705 | |
| 3706 | |
| 3707 | |
| 3708 | |
| 3709 | |
| 3710 | and3 #(2) d0_0 ( |
| 3711 | .in0(din0[1:0]), |
| 3712 | .in1(din1[1:0]), |
| 3713 | .in2(din2[1:0]), |
| 3714 | .out(dout[1:0]) |
| 3715 | ); |
| 3716 | |
| 3717 | |
| 3718 | |
| 3719 | |
| 3720 | |
| 3721 | |
| 3722 | |
| 3723 | |
| 3724 | |
| 3725 | endmodule |
| 3726 | |
| 3727 | |
| 3728 | |
| 3729 | |
| 3730 | |
| 3731 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 3732 | // also for pass-gate with decoder |
| 3733 | |
| 3734 | |
| 3735 | |
| 3736 | |
| 3737 | |
| 3738 | // any PARAMS parms go into naming of macro |
| 3739 | |
| 3740 | module fgu_fad_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_2 ( |
| 3741 | din0, |
| 3742 | sel0, |
| 3743 | din1, |
| 3744 | sel1, |
| 3745 | dout); |
| 3746 | input [1:0] din0; |
| 3747 | input sel0; |
| 3748 | input [1:0] din1; |
| 3749 | input sel1; |
| 3750 | output [1:0] dout; |
| 3751 | |
| 3752 | |
| 3753 | |
| 3754 | |
| 3755 | |
| 3756 | mux2s #(2) d0_0 ( |
| 3757 | .sel0(sel0), |
| 3758 | .sel1(sel1), |
| 3759 | .in0(din0[1:0]), |
| 3760 | .in1(din1[1:0]), |
| 3761 | .dout(dout[1:0]) |
| 3762 | ); |
| 3763 | |
| 3764 | |
| 3765 | |
| 3766 | |
| 3767 | |
| 3768 | |
| 3769 | |
| 3770 | |
| 3771 | |
| 3772 | |
| 3773 | |
| 3774 | |
| 3775 | |
| 3776 | endmodule |
| 3777 | |
| 3778 | |
| 3779 | // |
| 3780 | // and macro for ports = 2,3,4 |
| 3781 | // |
| 3782 | // |
| 3783 | |
| 3784 | |
| 3785 | |
| 3786 | |
| 3787 | |
| 3788 | module fgu_fad_dp_and_macro__ports_2__width_3 ( |
| 3789 | din0, |
| 3790 | din1, |
| 3791 | dout); |
| 3792 | input [2:0] din0; |
| 3793 | input [2:0] din1; |
| 3794 | output [2:0] dout; |
| 3795 | |
| 3796 | |
| 3797 | |
| 3798 | |
| 3799 | |
| 3800 | |
| 3801 | and2 #(3) d0_0 ( |
| 3802 | .in0(din0[2:0]), |
| 3803 | .in1(din1[2:0]), |
| 3804 | .out(dout[2:0]) |
| 3805 | ); |
| 3806 | |
| 3807 | |
| 3808 | |
| 3809 | |
| 3810 | |
| 3811 | |
| 3812 | |
| 3813 | |
| 3814 | |
| 3815 | endmodule |
| 3816 | |
| 3817 | |
| 3818 | |
| 3819 | |
| 3820 | |
| 3821 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 3822 | // also for pass-gate with decoder |
| 3823 | |
| 3824 | |
| 3825 | |
| 3826 | |
| 3827 | |
| 3828 | // any PARAMS parms go into naming of macro |
| 3829 | |
| 3830 | module fgu_fad_dp_mux_macro__mux_aonpe__ports_2__width_52 ( |
| 3831 | din0, |
| 3832 | sel0, |
| 3833 | din1, |
| 3834 | sel1, |
| 3835 | dout); |
| 3836 | wire buffout0; |
| 3837 | wire buffout1; |
| 3838 | |
| 3839 | input [51:0] din0; |
| 3840 | input sel0; |
| 3841 | input [51:0] din1; |
| 3842 | input sel1; |
| 3843 | output [51:0] dout; |
| 3844 | |
| 3845 | |
| 3846 | |
| 3847 | |
| 3848 | |
| 3849 | cl_dp1_muxbuff2_8x c0_0 ( |
| 3850 | .in0(sel0), |
| 3851 | .in1(sel1), |
| 3852 | .out0(buffout0), |
| 3853 | .out1(buffout1) |
| 3854 | ); |
| 3855 | mux2s #(52) d0_0 ( |
| 3856 | .sel0(buffout0), |
| 3857 | .sel1(buffout1), |
| 3858 | .in0(din0[51:0]), |
| 3859 | .in1(din1[51:0]), |
| 3860 | .dout(dout[51:0]) |
| 3861 | ); |
| 3862 | |
| 3863 | |
| 3864 | |
| 3865 | |
| 3866 | |
| 3867 | |
| 3868 | |
| 3869 | |
| 3870 | |
| 3871 | |
| 3872 | |
| 3873 | |
| 3874 | |
| 3875 | endmodule |
| 3876 | |
| 3877 | |
| 3878 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 3879 | // also for pass-gate with decoder |
| 3880 | |
| 3881 | |
| 3882 | |
| 3883 | |
| 3884 | |
| 3885 | // any PARAMS parms go into naming of macro |
| 3886 | |
| 3887 | module fgu_fad_dp_mux_macro__mux_aope__ports_4__width_64 ( |
| 3888 | din0, |
| 3889 | din1, |
| 3890 | din2, |
| 3891 | din3, |
| 3892 | sel0, |
| 3893 | sel1, |
| 3894 | sel2, |
| 3895 | dout); |
| 3896 | wire psel0; |
| 3897 | wire psel1; |
| 3898 | wire psel2; |
| 3899 | wire psel3; |
| 3900 | |
| 3901 | input [63:0] din0; |
| 3902 | input [63:0] din1; |
| 3903 | input [63:0] din2; |
| 3904 | input [63:0] din3; |
| 3905 | input sel0; |
| 3906 | input sel1; |
| 3907 | input sel2; |
| 3908 | output [63:0] dout; |
| 3909 | |
| 3910 | |
| 3911 | |
| 3912 | |
| 3913 | |
| 3914 | cl_dp1_penc4_8x c0_0 ( |
| 3915 | .test(1'b1), |
| 3916 | .sel0(sel0), |
| 3917 | .sel1(sel1), |
| 3918 | .sel2(sel2), |
| 3919 | .psel0(psel0), |
| 3920 | .psel1(psel1), |
| 3921 | .psel2(psel2), |
| 3922 | .psel3(psel3) |
| 3923 | ); |
| 3924 | |
| 3925 | mux4s #(64) d0_0 ( |
| 3926 | .sel0(psel0), |
| 3927 | .sel1(psel1), |
| 3928 | .sel2(psel2), |
| 3929 | .sel3(psel3), |
| 3930 | .in0(din0[63:0]), |
| 3931 | .in1(din1[63:0]), |
| 3932 | .in2(din2[63:0]), |
| 3933 | .in3(din3[63:0]), |
| 3934 | .dout(dout[63:0]) |
| 3935 | ); |
| 3936 | |
| 3937 | |
| 3938 | |
| 3939 | |
| 3940 | |
| 3941 | |
| 3942 | |
| 3943 | |
| 3944 | |
| 3945 | |
| 3946 | |
| 3947 | |
| 3948 | |
| 3949 | endmodule |
| 3950 | |
| 3951 | |
| 3952 | |
| 3953 | |
| 3954 | |
| 3955 | |
| 3956 | // any PARAMS parms go into naming of macro |
| 3957 | |
| 3958 | module fgu_fad_dp_msff_macro__width_64 ( |
| 3959 | din, |
| 3960 | clk, |
| 3961 | en, |
| 3962 | se, |
| 3963 | scan_in, |
| 3964 | siclk, |
| 3965 | soclk, |
| 3966 | pce_ov, |
| 3967 | stop, |
| 3968 | dout, |
| 3969 | scan_out); |
| 3970 | wire l1clk; |
| 3971 | wire siclk_out; |
| 3972 | wire soclk_out; |
| 3973 | wire [62:0] so; |
| 3974 | |
| 3975 | input [63:0] din; |
| 3976 | |
| 3977 | |
| 3978 | input clk; |
| 3979 | input en; |
| 3980 | input se; |
| 3981 | input scan_in; |
| 3982 | input siclk; |
| 3983 | input soclk; |
| 3984 | input pce_ov; |
| 3985 | input stop; |
| 3986 | |
| 3987 | |
| 3988 | |
| 3989 | output [63:0] dout; |
| 3990 | |
| 3991 | |
| 3992 | output scan_out; |
| 3993 | |
| 3994 | |
| 3995 | |
| 3996 | |
| 3997 | cl_dp1_l1hdr_8x c0_0 ( |
| 3998 | .l2clk(clk), |
| 3999 | .pce(en), |
| 4000 | .aclk(siclk), |
| 4001 | .bclk(soclk), |
| 4002 | .l1clk(l1clk), |
| 4003 | .se(se), |
| 4004 | .pce_ov(pce_ov), |
| 4005 | .stop(stop), |
| 4006 | .siclk_out(siclk_out), |
| 4007 | .soclk_out(soclk_out) |
| 4008 | ); |
| 4009 | dff #(64) d0_0 ( |
| 4010 | .l1clk(l1clk), |
| 4011 | .siclk(siclk_out), |
| 4012 | .soclk(soclk_out), |
| 4013 | .d(din[63:0]), |
| 4014 | .si({scan_in,so[62:0]}), |
| 4015 | .so({so[62:0],scan_out}), |
| 4016 | .q(dout[63:0]) |
| 4017 | ); |
| 4018 | |
| 4019 | |
| 4020 | |
| 4021 | |
| 4022 | |
| 4023 | |
| 4024 | |
| 4025 | |
| 4026 | |
| 4027 | |
| 4028 | |
| 4029 | |
| 4030 | |
| 4031 | |
| 4032 | |
| 4033 | |
| 4034 | |
| 4035 | |
| 4036 | |
| 4037 | |
| 4038 | endmodule |
| 4039 | |
| 4040 | |
| 4041 | |
| 4042 | |
| 4043 | |
| 4044 | |
| 4045 | |
| 4046 | |
| 4047 | |
| 4048 | |
| 4049 | |
| 4050 | |
| 4051 | |
| 4052 | // any PARAMS parms go into naming of macro |
| 4053 | |
| 4054 | module fgu_fad_dp_msff_macro__stack_32l__width_26 ( |
| 4055 | din, |
| 4056 | clk, |
| 4057 | en, |
| 4058 | se, |
| 4059 | scan_in, |
| 4060 | siclk, |
| 4061 | soclk, |
| 4062 | pce_ov, |
| 4063 | stop, |
| 4064 | dout, |
| 4065 | scan_out); |
| 4066 | wire l1clk; |
| 4067 | wire siclk_out; |
| 4068 | wire soclk_out; |
| 4069 | wire [24:0] so; |
| 4070 | |
| 4071 | input [25:0] din; |
| 4072 | |
| 4073 | |
| 4074 | input clk; |
| 4075 | input en; |
| 4076 | input se; |
| 4077 | input scan_in; |
| 4078 | input siclk; |
| 4079 | input soclk; |
| 4080 | input pce_ov; |
| 4081 | input stop; |
| 4082 | |
| 4083 | |
| 4084 | |
| 4085 | output [25:0] dout; |
| 4086 | |
| 4087 | |
| 4088 | output scan_out; |
| 4089 | |
| 4090 | |
| 4091 | |
| 4092 | |
| 4093 | cl_dp1_l1hdr_8x c0_0 ( |
| 4094 | .l2clk(clk), |
| 4095 | .pce(en), |
| 4096 | .aclk(siclk), |
| 4097 | .bclk(soclk), |
| 4098 | .l1clk(l1clk), |
| 4099 | .se(se), |
| 4100 | .pce_ov(pce_ov), |
| 4101 | .stop(stop), |
| 4102 | .siclk_out(siclk_out), |
| 4103 | .soclk_out(soclk_out) |
| 4104 | ); |
| 4105 | dff #(26) d0_0 ( |
| 4106 | .l1clk(l1clk), |
| 4107 | .siclk(siclk_out), |
| 4108 | .soclk(soclk_out), |
| 4109 | .d(din[25:0]), |
| 4110 | .si({scan_in,so[24:0]}), |
| 4111 | .so({so[24:0],scan_out}), |
| 4112 | .q(dout[25:0]) |
| 4113 | ); |
| 4114 | |
| 4115 | |
| 4116 | |
| 4117 | |
| 4118 | |
| 4119 | |
| 4120 | |
| 4121 | |
| 4122 | |
| 4123 | |
| 4124 | |
| 4125 | |
| 4126 | |
| 4127 | |
| 4128 | |
| 4129 | |
| 4130 | |
| 4131 | |
| 4132 | |
| 4133 | |
| 4134 | endmodule |
| 4135 | |
| 4136 | |
| 4137 | |
| 4138 | |
| 4139 | |
| 4140 | |
| 4141 | |
| 4142 | |
| 4143 | |
| 4144 | // |
| 4145 | // invert macro |
| 4146 | // |
| 4147 | // |
| 4148 | |
| 4149 | |
| 4150 | |
| 4151 | |
| 4152 | |
| 4153 | module fgu_fad_dp_inv_macro__width_1 ( |
| 4154 | din, |
| 4155 | dout); |
| 4156 | input [0:0] din; |
| 4157 | output [0:0] dout; |
| 4158 | |
| 4159 | |
| 4160 | |
| 4161 | |
| 4162 | |
| 4163 | |
| 4164 | inv #(1) d0_0 ( |
| 4165 | .in(din[0:0]), |
| 4166 | .out(dout[0:0]) |
| 4167 | ); |
| 4168 | |
| 4169 | |
| 4170 | |
| 4171 | |
| 4172 | |
| 4173 | |
| 4174 | |
| 4175 | |
| 4176 | |
| 4177 | endmodule |
| 4178 | |
| 4179 | |
| 4180 | |
| 4181 | |
| 4182 | |
| 4183 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 4184 | // also for pass-gate with decoder |
| 4185 | |
| 4186 | |
| 4187 | |
| 4188 | |
| 4189 | |
| 4190 | // any PARAMS parms go into naming of macro |
| 4191 | |
| 4192 | module fgu_fad_dp_mux_macro__buffsel_none__mux_aonpe__ports_3__width_2 ( |
| 4193 | din0, |
| 4194 | sel0, |
| 4195 | din1, |
| 4196 | sel1, |
| 4197 | din2, |
| 4198 | sel2, |
| 4199 | dout); |
| 4200 | input [1:0] din0; |
| 4201 | input sel0; |
| 4202 | input [1:0] din1; |
| 4203 | input sel1; |
| 4204 | input [1:0] din2; |
| 4205 | input sel2; |
| 4206 | output [1:0] dout; |
| 4207 | |
| 4208 | |
| 4209 | |
| 4210 | |
| 4211 | |
| 4212 | mux3s #(2) d0_0 ( |
| 4213 | .sel0(sel0), |
| 4214 | .sel1(sel1), |
| 4215 | .sel2(sel2), |
| 4216 | .in0(din0[1:0]), |
| 4217 | .in1(din1[1:0]), |
| 4218 | .in2(din2[1:0]), |
| 4219 | .dout(dout[1:0]) |
| 4220 | ); |
| 4221 | |
| 4222 | |
| 4223 | |
| 4224 | |
| 4225 | |
| 4226 | |
| 4227 | |
| 4228 | |
| 4229 | |
| 4230 | |
| 4231 | |
| 4232 | |
| 4233 | |
| 4234 | endmodule |
| 4235 | |
| 4236 | |
| 4237 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 4238 | // also for pass-gate with decoder |
| 4239 | |
| 4240 | |
| 4241 | |
| 4242 | |
| 4243 | |
| 4244 | // any PARAMS parms go into naming of macro |
| 4245 | |
| 4246 | module fgu_fad_dp_mux_macro__mux_pgpe__ports_2__width_64 ( |
| 4247 | din0, |
| 4248 | din1, |
| 4249 | sel0, |
| 4250 | dout); |
| 4251 | wire psel0_unused; |
| 4252 | wire psel1; |
| 4253 | |
| 4254 | input [63:0] din0; |
| 4255 | input [63:0] din1; |
| 4256 | input sel0; |
| 4257 | output [63:0] dout; |
| 4258 | |
| 4259 | |
| 4260 | |
| 4261 | |
| 4262 | |
| 4263 | cl_dp1_penc2_8x c0_0 ( |
| 4264 | .sel0(sel0), |
| 4265 | .psel0(psel0_unused), |
| 4266 | .psel1(psel1) |
| 4267 | ); |
| 4268 | |
| 4269 | mux2e #(64) d0_0 ( |
| 4270 | .sel(psel1), |
| 4271 | .in0(din0[63:0]), |
| 4272 | .in1(din1[63:0]), |
| 4273 | .dout(dout[63:0]) |
| 4274 | ); |
| 4275 | |
| 4276 | |
| 4277 | |
| 4278 | |
| 4279 | |
| 4280 | |
| 4281 | |
| 4282 | |
| 4283 | |
| 4284 | |
| 4285 | |
| 4286 | |
| 4287 | |
| 4288 | endmodule |
| 4289 | |
| 4290 | |
| 4291 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 4292 | // also for pass-gate with decoder |
| 4293 | |
| 4294 | |
| 4295 | |
| 4296 | |
| 4297 | |
| 4298 | // any PARAMS parms go into naming of macro |
| 4299 | |
| 4300 | module fgu_fad_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_8 ( |
| 4301 | din0, |
| 4302 | sel0, |
| 4303 | din1, |
| 4304 | sel1, |
| 4305 | dout); |
| 4306 | input [7:0] din0; |
| 4307 | input sel0; |
| 4308 | input [7:0] din1; |
| 4309 | input sel1; |
| 4310 | output [7:0] dout; |
| 4311 | |
| 4312 | |
| 4313 | |
| 4314 | |
| 4315 | |
| 4316 | mux2s #(8) d0_0 ( |
| 4317 | .sel0(sel0), |
| 4318 | .sel1(sel1), |
| 4319 | .in0(din0[7:0]), |
| 4320 | .in1(din1[7:0]), |
| 4321 | .dout(dout[7:0]) |
| 4322 | ); |
| 4323 | |
| 4324 | |
| 4325 | |
| 4326 | |
| 4327 | |
| 4328 | |
| 4329 | |
| 4330 | |
| 4331 | |
| 4332 | |
| 4333 | |
| 4334 | |
| 4335 | |
| 4336 | endmodule |
| 4337 | |
| 4338 | |
| 4339 | // |
| 4340 | // buff macro |
| 4341 | // |
| 4342 | // |
| 4343 | |
| 4344 | |
| 4345 | |
| 4346 | |
| 4347 | |
| 4348 | module fgu_fad_dp_buff_macro__width_8 ( |
| 4349 | din, |
| 4350 | dout); |
| 4351 | input [7:0] din; |
| 4352 | output [7:0] dout; |
| 4353 | |
| 4354 | |
| 4355 | |
| 4356 | |
| 4357 | |
| 4358 | |
| 4359 | buff #(8) d0_0 ( |
| 4360 | .in(din[7:0]), |
| 4361 | .out(dout[7:0]) |
| 4362 | ); |
| 4363 | |
| 4364 | |
| 4365 | |
| 4366 | |
| 4367 | |
| 4368 | |
| 4369 | |
| 4370 | |
| 4371 | endmodule |
| 4372 | |
| 4373 | |
| 4374 | |
| 4375 | |
| 4376 | |
| 4377 | |
| 4378 | |
| 4379 | |
| 4380 | |
| 4381 | // any PARAMS parms go into naming of macro |
| 4382 | |
| 4383 | module fgu_fad_dp_msff_macro__minbuff_1__width_64 ( |
| 4384 | din, |
| 4385 | clk, |
| 4386 | en, |
| 4387 | se, |
| 4388 | scan_in, |
| 4389 | siclk, |
| 4390 | soclk, |
| 4391 | pce_ov, |
| 4392 | stop, |
| 4393 | dout, |
| 4394 | scan_out); |
| 4395 | wire l1clk; |
| 4396 | wire siclk_out; |
| 4397 | wire soclk_out; |
| 4398 | wire [62:0] so; |
| 4399 | |
| 4400 | input [63:0] din; |
| 4401 | |
| 4402 | |
| 4403 | input clk; |
| 4404 | input en; |
| 4405 | input se; |
| 4406 | input scan_in; |
| 4407 | input siclk; |
| 4408 | input soclk; |
| 4409 | input pce_ov; |
| 4410 | input stop; |
| 4411 | |
| 4412 | |
| 4413 | |
| 4414 | output [63:0] dout; |
| 4415 | |
| 4416 | |
| 4417 | output scan_out; |
| 4418 | |
| 4419 | |
| 4420 | |
| 4421 | |
| 4422 | cl_dp1_l1hdr_8x c0_0 ( |
| 4423 | .l2clk(clk), |
| 4424 | .pce(en), |
| 4425 | .aclk(siclk), |
| 4426 | .bclk(soclk), |
| 4427 | .l1clk(l1clk), |
| 4428 | .se(se), |
| 4429 | .pce_ov(pce_ov), |
| 4430 | .stop(stop), |
| 4431 | .siclk_out(siclk_out), |
| 4432 | .soclk_out(soclk_out) |
| 4433 | ); |
| 4434 | dff #(64) d0_0 ( |
| 4435 | .l1clk(l1clk), |
| 4436 | .siclk(siclk_out), |
| 4437 | .soclk(soclk_out), |
| 4438 | .d(din[63:0]), |
| 4439 | .si({scan_in,so[62:0]}), |
| 4440 | .so({so[62:0],scan_out}), |
| 4441 | .q(dout[63:0]) |
| 4442 | ); |
| 4443 | |
| 4444 | |
| 4445 | |
| 4446 | |
| 4447 | |
| 4448 | |
| 4449 | |
| 4450 | |
| 4451 | |
| 4452 | |
| 4453 | |
| 4454 | |
| 4455 | |
| 4456 | |
| 4457 | |
| 4458 | |
| 4459 | |
| 4460 | |
| 4461 | |
| 4462 | |
| 4463 | endmodule |
| 4464 | |
| 4465 | |
| 4466 | |
| 4467 | |
| 4468 | |
| 4469 | |
| 4470 | |
| 4471 | |