| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: fgu_fpe_dp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module fgu_fpe_dp ( |
| 36 | fad_rs1_fx1, |
| 37 | fad_rs2_fx1, |
| 38 | fac_aexp_fmt_sel_e, |
| 39 | fac_bexp_fmt_sel_e, |
| 40 | fac_aux_cin_fx1, |
| 41 | main_clken, |
| 42 | fpc_exp_sel_mul_fx5, |
| 43 | fpc_eintx_sel_fx2, |
| 44 | fpc_eadjx_sel_fx2, |
| 45 | fpc_ma_fmt_sel_fx4, |
| 46 | fpc_rinc_sel_fx5, |
| 47 | fpc_q_rinc_sel_fx5, |
| 48 | fpe_aux_rs2_fmt_fx1_b0, |
| 49 | fpe_aux_eint_fx1, |
| 50 | fpe_rs1_fmt_fx1, |
| 51 | fpe_rs2_fmt_fx1, |
| 52 | fpe_einty_adj_cout_fx5, |
| 53 | fpe_einty_eq_eadj_fx5, |
| 54 | fgu_mul_result_fx5_b63, |
| 55 | fpf_rcout_fx5, |
| 56 | fpe_exp_res_fb, |
| 57 | fpe_align_sel_fx2, |
| 58 | fic_i2f_eadj_fx2, |
| 59 | fic_norm_eadj_fx5, |
| 60 | l2clk, |
| 61 | scan_in, |
| 62 | tcu_pce_ov, |
| 63 | spc_aclk, |
| 64 | spc_bclk, |
| 65 | tcu_dectest, |
| 66 | tcu_muxtest, |
| 67 | tcu_scan_en, |
| 68 | scan_out); |
| 69 | wire stop; |
| 70 | wire test; |
| 71 | wire se; |
| 72 | wire pce_ov; |
| 73 | wire siclk; |
| 74 | wire soclk; |
| 75 | wire fx1_fmtsel_scanin; |
| 76 | wire fx1_fmtsel_scanout; |
| 77 | wire [9:0] aexp_fmt_sel_fx1; |
| 78 | wire [7:0] bexp_fmt_sel_fx1; |
| 79 | wire tcu_muxtest_a_rep0; |
| 80 | wire tcu_muxtest_b_rep0; |
| 81 | wire [10:0] rs1_fmt_fx1_; |
| 82 | wire [10:0] rs2_fmt_fx1_; |
| 83 | wire amb_unused; |
| 84 | wire [10:0] ea_minus_eb_fx1; |
| 85 | wire ea_gteq_eb_fx1; |
| 86 | wire bma_unused; |
| 87 | wire [10:0] eb_minus_ea_fx1; |
| 88 | wire eb_gteq_ea_fx1; |
| 89 | wire fx2_swp_sel_scanin; |
| 90 | wire fx2_swp_sel_scanout; |
| 91 | wire [10:0] eintw_fx2; |
| 92 | wire rs1_fx1_b62_; |
| 93 | wire [10:0] rs2_fx1_b62_52_; |
| 94 | wire rs1_fx1_b30_; |
| 95 | wire [7:0] rs2_fx1_b30_23_; |
| 96 | wire tcu_muxtest_c_rep0; |
| 97 | wire [10:0] aux_rs1_fmt_fx1; |
| 98 | wire tcu_muxtest_d_rep0; |
| 99 | wire [10:1] aux_rs2_fmt_fx1; |
| 100 | wire [11:0] aux_eint_fx1; |
| 101 | wire aux_add_unused; |
| 102 | wire fx2_aux_scanin; |
| 103 | wire fx2_aux_scanout; |
| 104 | wire [10:0] aux_eint_fx2; |
| 105 | wire [10:0] eintx_fx2; |
| 106 | wire [5:0] i2f_eadj_fx2_; |
| 107 | wire [11:0] eadjx_fx2; |
| 108 | wire [1:0] einty_unused; |
| 109 | wire [10:0] einty_fx2; |
| 110 | wire fx3_einty_scanin; |
| 111 | wire fx3_einty_scanout; |
| 112 | wire [10:0] einty_fx3; |
| 113 | wire fx4_einty_scanin; |
| 114 | wire fx4_einty_scanout; |
| 115 | wire [10:0] einty_fx4; |
| 116 | wire [1:0] ma_fmt_sel_fx5; |
| 117 | wire [10:0] einty_fx5; |
| 118 | wire [1:0] einty_inc_unused; |
| 119 | wire [10:0] einty_inc_fx5; |
| 120 | wire i_exp_inc_sel_fx5; |
| 121 | wire enoinc_i1_fx5_; |
| 122 | wire enoinc_i1_fx5; |
| 123 | wire einty_adj_cin_fx5; |
| 124 | wire [5:0] eadj_fx5_; |
| 125 | wire einty_adj_unused; |
| 126 | wire [10:0] einty_adj_fx5; |
| 127 | wire [0:0] cmp_exp_eadj; |
| 128 | wire i_exp_inc_sel_fx5_; |
| 129 | wire fpc_exp_sel_mul_fx5_; |
| 130 | wire einc_i0_fx5; |
| 131 | wire einc_i1_fx5; |
| 132 | wire exp_inc_sel_fx5; |
| 133 | wire exp_noinc_sel_fx5; |
| 134 | wire [10:0] exp_res_fx5; |
| 135 | wire fb_exp_res_scanin; |
| 136 | wire fb_exp_res_scanout; |
| 137 | |
| 138 | |
| 139 | |
| 140 | // ---------------------------------------------------------------------------- |
| 141 | // Interface with FAD |
| 142 | // ---------------------------------------------------------------------------- |
| 143 | |
| 144 | input [62:23] fad_rs1_fx1; // rs1 unformatted |
| 145 | input [62:23] fad_rs2_fx1; // rs2 unformatted |
| 146 | |
| 147 | // ---------------------------------------------------------------------------- |
| 148 | // Interface with FAC |
| 149 | // ---------------------------------------------------------------------------- |
| 150 | |
| 151 | input [9:0] fac_aexp_fmt_sel_e; // aop exponent format mux select |
| 152 | input [7:0] fac_bexp_fmt_sel_e; // bop exponent format mux select |
| 153 | input fac_aux_cin_fx1; // aux exp adder cin |
| 154 | |
| 155 | input main_clken; // main clken |
| 156 | |
| 157 | // ---------------------------------------------------------------------------- |
| 158 | // Interface with FPC |
| 159 | // ---------------------------------------------------------------------------- |
| 160 | |
| 161 | input fpc_exp_sel_mul_fx5; |
| 162 | input [3:0] fpc_eintx_sel_fx2; // FxTOs=0001, FxTOd=0010, FiTO(s,d)=0100, F(s)MUL(s,d)=1000 |
| 163 | input [2:0] fpc_eadjx_sel_fx2; // F(i,x)TO(s,d)=001, FsTOd=010, FdTOs=100 |
| 164 | input [1:0] fpc_ma_fmt_sel_fx4; // FADD/FSUB: 001=00.1X, 010=1X.XX, 100=default |
| 165 | input fpc_rinc_sel_fx5; |
| 166 | input fpc_q_rinc_sel_fx5; // rinc_sel and ~logical_sub 00.1X |
| 167 | output fpe_aux_rs2_fmt_fx1_b0; |
| 168 | output [11:0] fpe_aux_eint_fx1; |
| 169 | output [10:0] fpe_rs1_fmt_fx1; |
| 170 | output [10:0] fpe_rs2_fmt_fx1; |
| 171 | output fpe_einty_adj_cout_fx5; |
| 172 | output fpe_einty_eq_eadj_fx5; |
| 173 | |
| 174 | // ---------------------------------------------------------------------------- |
| 175 | // Interface with FPY |
| 176 | // ---------------------------------------------------------------------------- |
| 177 | |
| 178 | input fgu_mul_result_fx5_b63; |
| 179 | |
| 180 | // ---------------------------------------------------------------------------- |
| 181 | // Interface with FPF |
| 182 | // ---------------------------------------------------------------------------- |
| 183 | |
| 184 | input fpf_rcout_fx5; |
| 185 | output [10:0] fpe_exp_res_fb; |
| 186 | output [10:0] fpe_align_sel_fx2; |
| 187 | |
| 188 | // ---------------------------------------------------------------------------- |
| 189 | // Interface with FIC |
| 190 | // ---------------------------------------------------------------------------- |
| 191 | |
| 192 | input [5:0] fic_i2f_eadj_fx2; |
| 193 | input [5:0] fic_norm_eadj_fx5; |
| 194 | |
| 195 | // ---------------------------------------------------------------------------- |
| 196 | // Global Signals |
| 197 | // ---------------------------------------------------------------------------- |
| 198 | |
| 199 | input l2clk; // clock input |
| 200 | input scan_in; |
| 201 | input tcu_pce_ov; // scan signals |
| 202 | input spc_aclk; |
| 203 | input spc_bclk; |
| 204 | input tcu_dectest; |
| 205 | input tcu_muxtest; |
| 206 | input tcu_scan_en; |
| 207 | output scan_out; |
| 208 | |
| 209 | // scan renames |
| 210 | assign stop = 1'b0; |
| 211 | assign test = tcu_dectest; |
| 212 | // end scan |
| 213 | |
| 214 | fgu_fpe_dp_buff_macro__dbuff_32x__rep_1__stack_32l__width_4 test_rep0 ( |
| 215 | .din ({tcu_scan_en, tcu_pce_ov, spc_aclk, spc_bclk}), |
| 216 | .dout({se, pce_ov, siclk, soclk }) |
| 217 | ); |
| 218 | |
| 219 | |
| 220 | // ---------------------------------------------------------------------------- |
| 221 | // FX1 stage |
| 222 | // ---------------------------------------------------------------------------- |
| 223 | |
| 224 | fgu_fpe_dp_msff_macro__stack_32l__width_18 fx1_fmtsel ( |
| 225 | .scan_in(fx1_fmtsel_scanin), |
| 226 | .scan_out(fx1_fmtsel_scanout), |
| 227 | .clk (l2clk), |
| 228 | .en (main_clken), |
| 229 | .din ({fac_aexp_fmt_sel_e[9:0], fac_bexp_fmt_sel_e[7:0] }), |
| 230 | .dout({ aexp_fmt_sel_fx1[9:0], bexp_fmt_sel_fx1[7:0]}), |
| 231 | .se(se), |
| 232 | .siclk(siclk), |
| 233 | .soclk(soclk), |
| 234 | .pce_ov(pce_ov), |
| 235 | .stop(stop) |
| 236 | ); |
| 237 | |
| 238 | // ------------------------------------ |
| 239 | // Add exponent input format muxes |
| 240 | // |
| 241 | // FADD: IF (Eb>=Ea) THEN (SC=(Eb-Ea)); ELSE (SC=(Ea-Eb)) |
| 242 | // IF (Eb>=Ea) THEN (Eint=Eb); ELSE (Eint=Ea) |
| 243 | // ------------------------------------ |
| 244 | |
| 245 | fgu_fpe_dp_buff_macro__dbuff_32x__stack_32l__width_1 muxtest_a_rep0 ( |
| 246 | .din (tcu_muxtest ), |
| 247 | .dout(tcu_muxtest_a_rep0) |
| 248 | ); |
| 249 | |
| 250 | fgu_fpe_dp_mux_macro__mux_pgpe__ports_8__stack_32l__width_11 add_fmt1 ( |
| 251 | .muxtst(tcu_muxtest_a_rep0), |
| 252 | .din0( 11'b00000000001 ), // FGX, F(s,d)TO(d,s), FSQRT(s,d) |
| 253 | .din1({3'b000, fad_rs1_fx1[30:23]}), // SP odd |
| 254 | .din2({3'b000, fad_rs1_fx1[62:55]}), // SP even |
| 255 | .din3( fad_rs1_fx1[62:52] ), // DP |
| 256 | .din4( 11'b00010111110 ), // FsTOx 2^(63+127) =2^190 |
| 257 | .din5( 11'b10000111110 ), // FdTOx 2^(63+1023)=2^1086 |
| 258 | .din6( 11'b00010011110 ), // FsTOi,F(i,x)TO(s,d) 2^(31+127) =2^158 |
| 259 | .din7( 11'b10000011110 ), // FdTOi 2^(31+1023)=2^1054 |
| 260 | .sel0(aexp_fmt_sel_fx1[0]), |
| 261 | .sel1(aexp_fmt_sel_fx1[1]), |
| 262 | .sel2(aexp_fmt_sel_fx1[2]), |
| 263 | .sel3(aexp_fmt_sel_fx1[3]), |
| 264 | .sel4(aexp_fmt_sel_fx1[4]), |
| 265 | .sel5(aexp_fmt_sel_fx1[5]), |
| 266 | .sel6(aexp_fmt_sel_fx1[6]), |
| 267 | .dout(fpe_rs1_fmt_fx1[10:0] ), |
| 268 | .test(test) |
| 269 | ); |
| 270 | |
| 271 | fgu_fpe_dp_buff_macro__dbuff_32x__stack_32l__width_1 muxtest_b_rep0 ( |
| 272 | .din (tcu_muxtest ), |
| 273 | .dout(tcu_muxtest_b_rep0) |
| 274 | ); |
| 275 | |
| 276 | fgu_fpe_dp_mux_macro__mux_pgpe__ports_4__stack_32l__width_11 add_fmt2 ( |
| 277 | .muxtst(tcu_muxtest_b_rep0), |
| 278 | .din0( 11'b00000000001 ), // FGX, F(i,x)TO(s,d) |
| 279 | .din1({3'b000, fad_rs2_fx1[30:23]}), // SP odd |
| 280 | .din2({3'b000, fad_rs2_fx1[62:55]}), // SP even |
| 281 | .din3( fad_rs2_fx1[62:52] ), // DP |
| 282 | .sel0(bexp_fmt_sel_fx1[0]), |
| 283 | .sel1(bexp_fmt_sel_fx1[1]), |
| 284 | .sel2(bexp_fmt_sel_fx1[2]), |
| 285 | .dout(fpe_rs2_fmt_fx1[10:0] ), |
| 286 | .test(test) |
| 287 | ); |
| 288 | |
| 289 | // ------------------------------------ |
| 290 | // Ea-Eb, Eb-Ea |
| 291 | // ------------------------------------ |
| 292 | |
| 293 | fgu_fpe_dp_inv_macro__stack_32l__width_11 inv_a ( |
| 294 | .din (fpe_rs1_fmt_fx1[10:0] ), |
| 295 | .dout( rs1_fmt_fx1_[10:0]) |
| 296 | ); |
| 297 | |
| 298 | fgu_fpe_dp_inv_macro__stack_32l__width_11 inv_b ( |
| 299 | .din (fpe_rs2_fmt_fx1[10:0] ), |
| 300 | .dout( rs2_fmt_fx1_[10:0]) |
| 301 | ); |
| 302 | |
| 303 | fgu_fpe_dp_cla_macro__width_12 amb ( |
| 304 | .din0({1'b1, rs2_fmt_fx1_[10:0]}), |
| 305 | .din1({1'b0, fpe_rs1_fmt_fx1[10:0] }), |
| 306 | .cin ( 1'b1 ), |
| 307 | .dout({amb_unused, ea_minus_eb_fx1[10:0]}), |
| 308 | .cout( ea_gteq_eb_fx1 ) |
| 309 | ); |
| 310 | |
| 311 | fgu_fpe_dp_cla_macro__width_12 bma ( |
| 312 | .din0({1'b0, fpe_rs2_fmt_fx1[10:0] }), |
| 313 | .din1({1'b1, rs1_fmt_fx1_[10:0]}), |
| 314 | .cin ( 1'b1 ), |
| 315 | .dout({bma_unused, eb_minus_ea_fx1[10:0]}), |
| 316 | .cout( eb_gteq_ea_fx1 ) |
| 317 | ); |
| 318 | |
| 319 | // ------------------------------------ |
| 320 | // {generate aligner shift selects, Eintw} |
| 321 | // ------------------------------------ |
| 322 | |
| 323 | fgu_fpe_dp_msff_macro__mux_aonpe__ports_2__stack_32l__width_22 fx2_swp_sel ( |
| 324 | .scan_in(fx2_swp_sel_scanin), |
| 325 | .scan_out(fx2_swp_sel_scanout), |
| 326 | .clk (l2clk), |
| 327 | .en (main_clken), |
| 328 | .din0({eb_minus_ea_fx1[10:0], fpe_rs2_fmt_fx1[10:0]}), |
| 329 | .din1({ea_minus_eb_fx1[10:0], fpe_rs1_fmt_fx1[10:0]}), |
| 330 | .sel0(eb_gteq_ea_fx1), |
| 331 | .sel1(ea_gteq_eb_fx1), |
| 332 | .dout({fpe_align_sel_fx2[10:0], eintw_fx2[10:0] }), |
| 333 | .se(se), |
| 334 | .siclk(siclk), |
| 335 | .soclk(soclk), |
| 336 | .pce_ov(pce_ov), |
| 337 | .stop(stop) |
| 338 | ); |
| 339 | |
| 340 | // ------------------------------------ |
| 341 | // Multiply/Divide exponent input format muxes |
| 342 | // |
| 343 | // FMUL: Eint=Ea+Eb-bias |
| 344 | // -bias is accomplished by inverting Ea MSB and setting CPA cin=1 |
| 345 | // |
| 346 | // FSQRT: Eint= 0+Eb-bias |
| 347 | // -bias is accomplished by inverting Ea MSB and setting CPA cin=1 |
| 348 | // |
| 349 | // FDIV: Eint=Ea-Eb+bias=Ea+~Eb+1+bias |
| 350 | // +bias+1 is accomplished by inverting Ea MSB, must invert Eb |
| 351 | // ------------------------------------ |
| 352 | |
| 353 | fgu_fpe_dp_inv_macro__stack_32l__width_21 inv_ab ( |
| 354 | .din ({fad_rs1_fx1[62], fad_rs2_fx1[62:52], fad_rs1_fx1[30], fad_rs2_fx1[30:23] }), |
| 355 | .dout({ rs1_fx1_b62_, rs2_fx1_b62_52_[10:0], rs1_fx1_b30_, rs2_fx1_b30_23_[7:0]}) |
| 356 | ); |
| 357 | |
| 358 | fgu_fpe_dp_buff_macro__dbuff_32x__stack_32l__width_1 muxtest_c_rep0 ( |
| 359 | .din (tcu_muxtest ), |
| 360 | .dout(tcu_muxtest_c_rep0) |
| 361 | ); |
| 362 | |
| 363 | fgu_fpe_dp_mux_macro__mux_pgpe__ports_7__stack_32l__width_11 aux_fmt1 ( |
| 364 | .muxtst(tcu_muxtest_c_rep0), |
| 365 | .din0({3'b100, bexp_fmt_sel_fx1[2] , 7'b0 }), // FSQRT (~bias), |
| 366 | // bexp_fmt_sel_fx1[2] asserts if SP |
| 367 | .din1(11'b11110000001 ), // FdTOs (-896-1=-897) |
| 368 | .din2({ {4{rs1_fx1_b30_}}, fad_rs1_fx1[29:23] }), // bias extended SP odd -> DP |
| 369 | .din3({ {4{rs1_fx1_b62_}}, fad_rs1_fx1[61:55] }), // bias extended SP even -> DP |
| 370 | .din4({3'b000, rs1_fx1_b30_, fad_rs1_fx1[29:23] }), // SP odd |
| 371 | .din5({3'b000, rs1_fx1_b62_, fad_rs1_fx1[61:55] }), // SP even |
| 372 | .din6({ rs1_fx1_b62_, fad_rs1_fx1[61:52] }), // DP |
| 373 | .sel0(aexp_fmt_sel_fx1[0]), |
| 374 | .sel1(aexp_fmt_sel_fx1[7]), |
| 375 | .sel2(aexp_fmt_sel_fx1[8]), |
| 376 | .sel3(aexp_fmt_sel_fx1[9]), |
| 377 | .sel4(aexp_fmt_sel_fx1[1]), |
| 378 | .sel5(aexp_fmt_sel_fx1[2]), |
| 379 | .dout(aux_rs1_fmt_fx1[10:0]), |
| 380 | .test(test) |
| 381 | ); |
| 382 | |
| 383 | fgu_fpe_dp_buff_macro__dbuff_32x__stack_32l__width_1 muxtest_d_rep0 ( |
| 384 | .din (tcu_muxtest ), |
| 385 | .dout(tcu_muxtest_d_rep0) |
| 386 | ); |
| 387 | |
| 388 | fgu_fpe_dp_mux_macro__mux_pgpe__ports_8__stack_32l__width_11 aux_fmt2 ( |
| 389 | .muxtst(tcu_muxtest_d_rep0), |
| 390 | .din0({3'b000, rs2_fx1_b30_23_[7:0] }), // SP odd FDIV |
| 391 | .din1({3'b000, rs2_fx1_b62_52_[10:3]}), // SP even FDIV |
| 392 | .din2({ rs2_fx1_b62_52_[10:0]}), // DP FDIV |
| 393 | .din3({fad_rs2_fx1[30], |
| 394 | {3{rs2_fx1_b30_23_[7] }}, fad_rs2_fx1[29:23]}), // bias extended SP odd -> DP |
| 395 | .din4({fad_rs2_fx1[62], |
| 396 | {3{rs2_fx1_b62_52_[10]}}, fad_rs2_fx1[61:55]}), // bias extended SP even -> DP |
| 397 | .din5({3'b000, fad_rs2_fx1[30:23] }), // SP odd |
| 398 | .din6({3'b000, fad_rs2_fx1[62:55] }), // SP even |
| 399 | .din7({ fad_rs2_fx1[62:52] }), // DP |
| 400 | .sel0(bexp_fmt_sel_fx1[3]), |
| 401 | .sel1(bexp_fmt_sel_fx1[4]), |
| 402 | .sel2(bexp_fmt_sel_fx1[5]), |
| 403 | .sel3(bexp_fmt_sel_fx1[6]), |
| 404 | .sel4(bexp_fmt_sel_fx1[7]), |
| 405 | .sel5(bexp_fmt_sel_fx1[1]), |
| 406 | .sel6(bexp_fmt_sel_fx1[2]), |
| 407 | .dout({aux_rs2_fmt_fx1[10:1], fpe_aux_rs2_fmt_fx1_b0}), |
| 408 | .test(test) |
| 409 | ); |
| 410 | |
| 411 | // ------------------------------------ |
| 412 | // Auxiliary exponent adder |
| 413 | // ------------------------------------ |
| 414 | |
| 415 | fgu_fpe_dp_cla_macro__width_12 aux_add ( |
| 416 | .din0({1'b0, aux_rs1_fmt_fx1[10:0] }), |
| 417 | .din1({1'b0, aux_rs2_fmt_fx1[10:1], fpe_aux_rs2_fmt_fx1_b0}), |
| 418 | .cin ( fac_aux_cin_fx1 ), |
| 419 | .dout( aux_eint_fx1[11:0] ), |
| 420 | .cout( aux_add_unused ) |
| 421 | ); |
| 422 | |
| 423 | fgu_fpe_dp_buff_macro__width_12 buf_aux_add ( |
| 424 | .din ( aux_eint_fx1[11:0]), |
| 425 | .dout(fpe_aux_eint_fx1[11:0]) |
| 426 | ); |
| 427 | |
| 428 | // ---------------------------------------------------------------------------- |
| 429 | // FX2 stage |
| 430 | // ---------------------------------------------------------------------------- |
| 431 | |
| 432 | fgu_fpe_dp_msff_macro__stack_32l__width_11 fx2_aux ( |
| 433 | .scan_in(fx2_aux_scanin), |
| 434 | .scan_out(fx2_aux_scanout), |
| 435 | .clk (l2clk), |
| 436 | .en (main_clken), |
| 437 | .din (fpe_aux_eint_fx1[10:0]), |
| 438 | .dout( aux_eint_fx2[10:0]), |
| 439 | .se(se), |
| 440 | .siclk(siclk), |
| 441 | .soclk(soclk), |
| 442 | .pce_ov(pce_ov), |
| 443 | .stop(stop) |
| 444 | ); |
| 445 | |
| 446 | // ------------------------------------ |
| 447 | // Eintx |
| 448 | // ------------------------------------ |
| 449 | |
| 450 | fgu_fpe_dp_mux_macro__mux_aope__ports_5__stack_32l__width_11 eintx ( |
| 451 | .din0(11'b11111111111 ), // NaN |
| 452 | .din1(11'b00010111110 ), // F(i,x)TOs 2^(63+127) =2^190 |
| 453 | .din2(11'b10000111110 ), // F(i,x)TOd 2^(63+1023)=2^1086 |
| 454 | .din3(aux_eint_fx2[10:0]), // F(s)MUL(s,d) |
| 455 | .din4(eintw_fx2[10:0] ), // other |
| 456 | .sel0(fpc_eintx_sel_fx2[0]), |
| 457 | .sel1(fpc_eintx_sel_fx2[1]), |
| 458 | .sel2(fpc_eintx_sel_fx2[2]), |
| 459 | .sel3(fpc_eintx_sel_fx2[3]), |
| 460 | .dout(eintx_fx2[10:0] ) |
| 461 | ); |
| 462 | |
| 463 | // ------------------------------------ |
| 464 | // Eadjx for F(i,x)TO(s,d), FsTOd, FdTOs |
| 465 | // ------------------------------------ |
| 466 | |
| 467 | fgu_fpe_dp_inv_macro__stack_32l__width_6 inv_i2f ( |
| 468 | .din (fic_i2f_eadj_fx2[5:0] ), |
| 469 | .dout( i2f_eadj_fx2_[5:0]) |
| 470 | ); |
| 471 | |
| 472 | fgu_fpe_dp_mux_macro__mux_aope__ports_4__stack_32l__width_12 eadjx ( |
| 473 | .din0({ 6'b111111, i2f_eadj_fx2_[5:0]}), // F(i,x)TO(s,d), ~(i2f norm amount) |
| 474 | .din1( 12'b001101111111), // FsTOd, 2^(896-1), note: cin=1 in adder below |
| 475 | .din2( 12'b110001111111), // FdTOs, ~(2^896), note: cin=1 in adder below |
| 476 | .din3( 12'b111111111111), // other, ~zero |
| 477 | .sel0(fpc_eadjx_sel_fx2[0]), |
| 478 | .sel1(fpc_eadjx_sel_fx2[1]), |
| 479 | .sel2(fpc_eadjx_sel_fx2[2]), |
| 480 | .dout(eadjx_fx2[11:0]) |
| 481 | ); |
| 482 | |
| 483 | // ------------------------------------ |
| 484 | // Einty=Eintx-Eadjx |
| 485 | // ------------------------------------ |
| 486 | |
| 487 | fgu_fpe_dp_cla_macro__width_12 einty ( |
| 488 | .din0({1'b0, eintx_fx2[10:0]}), |
| 489 | .din1( eadjx_fx2[11:0] ), |
| 490 | .cin ( 1'b1 ), |
| 491 | .dout({einty_unused[0], einty_fx2[10:0]}), |
| 492 | .cout( einty_unused[1] ) |
| 493 | ); |
| 494 | |
| 495 | // ---------------------------------------------------------------------------- |
| 496 | // FX3 stage |
| 497 | // ---------------------------------------------------------------------------- |
| 498 | |
| 499 | fgu_fpe_dp_msff_macro__stack_32l__width_11 fx3_einty ( |
| 500 | .scan_in(fx3_einty_scanin), |
| 501 | .scan_out(fx3_einty_scanout), |
| 502 | .clk (l2clk), |
| 503 | .en (main_clken), |
| 504 | .din (einty_fx2[10:0]), |
| 505 | .dout(einty_fx3[10:0]), |
| 506 | .se(se), |
| 507 | .siclk(siclk), |
| 508 | .soclk(soclk), |
| 509 | .pce_ov(pce_ov), |
| 510 | .stop(stop) |
| 511 | ); |
| 512 | |
| 513 | // ---------------------------------------------------------------------------- |
| 514 | // FX4 stage |
| 515 | // ---------------------------------------------------------------------------- |
| 516 | |
| 517 | fgu_fpe_dp_msff_macro__stack_32l__width_24 fx4_einty ( |
| 518 | .scan_in(fx4_einty_scanin), |
| 519 | .scan_out(fx4_einty_scanout), |
| 520 | .clk (l2clk), |
| 521 | .en (main_clken), |
| 522 | .din ({fpc_ma_fmt_sel_fx4[1:0], einty_fx4[10:0], einty_fx3[10:0]}), |
| 523 | .dout({ ma_fmt_sel_fx5[1:0], einty_fx5[10:0], einty_fx4[10:0]}), |
| 524 | .se(se), |
| 525 | .siclk(siclk), |
| 526 | .soclk(soclk), |
| 527 | .pce_ov(pce_ov), |
| 528 | .stop(stop) |
| 529 | ); |
| 530 | |
| 531 | // ---------------------------------------------------------------------------- |
| 532 | // FX5 stage |
| 533 | // ---------------------------------------------------------------------------- |
| 534 | |
| 535 | // ------------------------------------ |
| 536 | // Einty_inc=Einty+(1X.XX|Rcout) |
| 537 | // ------------------------------------ |
| 538 | |
| 539 | fgu_fpe_dp_increment_macro__width_12 einty_inc ( |
| 540 | .din ({1'b0, einty_fx5[10:0]}), |
| 541 | .cin ( 1'b1 ), |
| 542 | .dout({einty_inc_unused[0], einty_inc_fx5[10:0] }), |
| 543 | .cout( einty_inc_unused[1] ) |
| 544 | ); |
| 545 | |
| 546 | fgu_fpe_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_32l__width_1 i_einc ( |
| 547 | .din0(fgu_mul_result_fx5_b63), // fpy 1X.XX (fmul) |
| 548 | .din1(ma_fmt_sel_fx5[1] ), // logical_add 1X.XX, intfp 10.00 |
| 549 | .sel0(fpc_exp_sel_mul_fx5 ), // fmul instr |
| 550 | .sel1(1'b1 ), |
| 551 | .dout(i_exp_inc_sel_fx5 ) // exp inc detected |
| 552 | ); |
| 553 | |
| 554 | // ------------------------------------ |
| 555 | // Einty_adj=Einty-Eadj |
| 556 | // - cin not asserted if logical_sub and 00.1X. |
| 557 | // In this case LZD gets overridden and eadj=0, when correct eadj=1. |
| 558 | // This is accounted for by effectively subtracting 1 by not asserting cin. |
| 559 | // - If logical_sub and 00.1X, followed by Rcout, then |
| 560 | // Eint-Eadj+Rcout=Eint-1+1=Eint |
| 561 | // ------------------------------------ |
| 562 | |
| 563 | fgu_fpe_dp_inv_macro__stack_32l__width_8 inv_eadj ( |
| 564 | .din ({enoinc_i1_fx5_, ma_fmt_sel_fx5[0], fic_norm_eadj_fx5[5:0] }), |
| 565 | .dout({enoinc_i1_fx5, einty_adj_cin_fx5, eadj_fx5_[5:0]}) |
| 566 | ); |
| 567 | |
| 568 | fgu_fpe_dp_cla_macro__width_12 einty_adj ( |
| 569 | .din0({1'b0, einty_fx5[10:0]}), |
| 570 | .din1({6'b111111, eadj_fx5_[5:0] }), |
| 571 | .cin ( einty_adj_cin_fx5 ), |
| 572 | .dout({einty_adj_unused, einty_adj_fx5[10:0]}), |
| 573 | .cout( fpe_einty_adj_cout_fx5 ) |
| 574 | ); |
| 575 | |
| 576 | // ------------------------------------ |
| 577 | // Einty=Eadj |
| 578 | // ------------------------------------ |
| 579 | |
| 580 | fgu_fpe_dp_cmp_macro__width_12 cmp_exp ( |
| 581 | .din0({6'b0, fic_norm_eadj_fx5[5:1], cmp_exp_eadj[0]}), // [0] must acct for logical_sub and 00.1X case |
| 582 | .din1({1'b0, einty_fx5[10:0] }), |
| 583 | .dout(fpe_einty_eq_eadj_fx5 ) |
| 584 | ); |
| 585 | |
| 586 | // exp_noinc_sel_fx5 = |
| 587 | // (logical_sub 00.1X & |
| 588 | // Rinc output selected & |
| 589 | // Rinc output format 01.XX) | // since 00.1X first gets normalized, actually check for Rcout |
| 590 | // fmul instr |
| 591 | |
| 592 | fgu_fpe_dp_nand_macro__ports_2__stack_32l__width_2 enoinc ( |
| 593 | .din0({ma_fmt_sel_fx5[0], eadj_fx5_[0] }), |
| 594 | .din1({fpc_rinc_sel_fx5, einty_adj_cin_fx5}), |
| 595 | .dout({enoinc_i1_fx5_, cmp_exp_eadj[0] }) |
| 596 | ); |
| 597 | |
| 598 | fgu_fpe_dp_inv_macro__stack_32l__width_2 inv_einc ( |
| 599 | .din ({i_exp_inc_sel_fx5, fpc_exp_sel_mul_fx5 }), |
| 600 | .dout({i_exp_inc_sel_fx5_, fpc_exp_sel_mul_fx5_}) |
| 601 | ); |
| 602 | |
| 603 | fgu_fpe_dp_nand_macro__dnand_8x__ports_2__stack_32l__width_4 einc ( |
| 604 | .din0({fpc_q_rinc_sel_fx5, einc_i0_fx5, enoinc_i1_fx5, einc_i1_fx5 }), // fpc_q_rinc_sel_fx5 <= Rinc output selected & ~(logical_sub 00.1X) |
| 605 | .din1({fpf_rcout_fx5, i_exp_inc_sel_fx5_, fpf_rcout_fx5, fpc_exp_sel_mul_fx5_}), |
| 606 | .dout({einc_i0_fx5, exp_inc_sel_fx5, einc_i1_fx5, exp_noinc_sel_fx5 }) |
| 607 | ); |
| 608 | |
| 609 | // ------------------------------------ |
| 610 | // Eres |
| 611 | // ------------------------------------ |
| 612 | |
| 613 | fgu_fpe_dp_mux_macro__mux_aope__ports_3__stack_32l__width_11 einty_mux ( |
| 614 | .din0(einty_inc_fx5[10:0]), |
| 615 | .din1(einty_fx5[10:0] ), |
| 616 | .din2(einty_adj_fx5[10:0]), |
| 617 | .sel0(exp_inc_sel_fx5), |
| 618 | .sel1(exp_noinc_sel_fx5), |
| 619 | .dout(exp_res_fx5[10:0]) |
| 620 | ); |
| 621 | |
| 622 | // ---------------------------------------------------------------------------- |
| 623 | // FB stage |
| 624 | // ---------------------------------------------------------------------------- |
| 625 | |
| 626 | fgu_fpe_dp_msff_macro__stack_32l__width_11 fb_exp_res ( |
| 627 | .scan_in(fb_exp_res_scanin), |
| 628 | .scan_out(fb_exp_res_scanout), |
| 629 | .clk (l2clk), |
| 630 | .en (main_clken), |
| 631 | .din ( exp_res_fx5[10:0]), |
| 632 | .dout(fpe_exp_res_fb[10:0] ), |
| 633 | .se(se), |
| 634 | .siclk(siclk), |
| 635 | .soclk(soclk), |
| 636 | .pce_ov(pce_ov), |
| 637 | .stop(stop) |
| 638 | ); |
| 639 | |
| 640 | |
| 641 | |
| 642 | // fixscan start: |
| 643 | assign fx1_fmtsel_scanin = scan_in ; |
| 644 | assign fx2_swp_sel_scanin = fx1_fmtsel_scanout ; |
| 645 | assign fx2_aux_scanin = fx2_swp_sel_scanout ; |
| 646 | assign fx3_einty_scanin = fx2_aux_scanout ; |
| 647 | assign fx4_einty_scanin = fx3_einty_scanout ; |
| 648 | assign fb_exp_res_scanin = fx4_einty_scanout ; |
| 649 | assign scan_out = fb_exp_res_scanout ; |
| 650 | // fixscan end: |
| 651 | endmodule // fgu_fpe_dp |
| 652 | |
| 653 | |
| 654 | // |
| 655 | // buff macro |
| 656 | // |
| 657 | // |
| 658 | |
| 659 | |
| 660 | |
| 661 | |
| 662 | |
| 663 | module fgu_fpe_dp_buff_macro__dbuff_32x__rep_1__stack_32l__width_4 ( |
| 664 | din, |
| 665 | dout); |
| 666 | input [3:0] din; |
| 667 | output [3:0] dout; |
| 668 | |
| 669 | |
| 670 | |
| 671 | |
| 672 | |
| 673 | |
| 674 | buff #(4) d0_0 ( |
| 675 | .in(din[3:0]), |
| 676 | .out(dout[3:0]) |
| 677 | ); |
| 678 | |
| 679 | |
| 680 | |
| 681 | |
| 682 | |
| 683 | |
| 684 | |
| 685 | |
| 686 | endmodule |
| 687 | |
| 688 | |
| 689 | |
| 690 | |
| 691 | |
| 692 | |
| 693 | |
| 694 | |
| 695 | |
| 696 | // any PARAMS parms go into naming of macro |
| 697 | |
| 698 | module fgu_fpe_dp_msff_macro__stack_32l__width_18 ( |
| 699 | din, |
| 700 | clk, |
| 701 | en, |
| 702 | se, |
| 703 | scan_in, |
| 704 | siclk, |
| 705 | soclk, |
| 706 | pce_ov, |
| 707 | stop, |
| 708 | dout, |
| 709 | scan_out); |
| 710 | wire l1clk; |
| 711 | wire siclk_out; |
| 712 | wire soclk_out; |
| 713 | wire [16:0] so; |
| 714 | |
| 715 | input [17:0] din; |
| 716 | |
| 717 | |
| 718 | input clk; |
| 719 | input en; |
| 720 | input se; |
| 721 | input scan_in; |
| 722 | input siclk; |
| 723 | input soclk; |
| 724 | input pce_ov; |
| 725 | input stop; |
| 726 | |
| 727 | |
| 728 | |
| 729 | output [17:0] dout; |
| 730 | |
| 731 | |
| 732 | output scan_out; |
| 733 | |
| 734 | |
| 735 | |
| 736 | |
| 737 | cl_dp1_l1hdr_8x c0_0 ( |
| 738 | .l2clk(clk), |
| 739 | .pce(en), |
| 740 | .aclk(siclk), |
| 741 | .bclk(soclk), |
| 742 | .l1clk(l1clk), |
| 743 | .se(se), |
| 744 | .pce_ov(pce_ov), |
| 745 | .stop(stop), |
| 746 | .siclk_out(siclk_out), |
| 747 | .soclk_out(soclk_out) |
| 748 | ); |
| 749 | dff #(18) d0_0 ( |
| 750 | .l1clk(l1clk), |
| 751 | .siclk(siclk_out), |
| 752 | .soclk(soclk_out), |
| 753 | .d(din[17:0]), |
| 754 | .si({scan_in,so[16:0]}), |
| 755 | .so({so[16:0],scan_out}), |
| 756 | .q(dout[17:0]) |
| 757 | ); |
| 758 | |
| 759 | |
| 760 | |
| 761 | |
| 762 | |
| 763 | |
| 764 | |
| 765 | |
| 766 | |
| 767 | |
| 768 | |
| 769 | |
| 770 | |
| 771 | |
| 772 | |
| 773 | |
| 774 | |
| 775 | |
| 776 | |
| 777 | |
| 778 | endmodule |
| 779 | |
| 780 | |
| 781 | |
| 782 | |
| 783 | |
| 784 | |
| 785 | |
| 786 | |
| 787 | |
| 788 | // |
| 789 | // buff macro |
| 790 | // |
| 791 | // |
| 792 | |
| 793 | |
| 794 | |
| 795 | |
| 796 | |
| 797 | module fgu_fpe_dp_buff_macro__dbuff_32x__stack_32l__width_1 ( |
| 798 | din, |
| 799 | dout); |
| 800 | input [0:0] din; |
| 801 | output [0:0] dout; |
| 802 | |
| 803 | |
| 804 | |
| 805 | |
| 806 | |
| 807 | |
| 808 | buff #(1) d0_0 ( |
| 809 | .in(din[0:0]), |
| 810 | .out(dout[0:0]) |
| 811 | ); |
| 812 | |
| 813 | |
| 814 | |
| 815 | |
| 816 | |
| 817 | |
| 818 | |
| 819 | |
| 820 | endmodule |
| 821 | |
| 822 | |
| 823 | |
| 824 | |
| 825 | |
| 826 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 827 | // also for pass-gate with decoder |
| 828 | |
| 829 | |
| 830 | |
| 831 | |
| 832 | |
| 833 | // any PARAMS parms go into naming of macro |
| 834 | |
| 835 | module fgu_fpe_dp_mux_macro__mux_pgpe__ports_8__stack_32l__width_11 ( |
| 836 | din0, |
| 837 | din1, |
| 838 | din2, |
| 839 | din3, |
| 840 | din4, |
| 841 | din5, |
| 842 | din6, |
| 843 | din7, |
| 844 | sel0, |
| 845 | sel1, |
| 846 | sel2, |
| 847 | sel3, |
| 848 | sel4, |
| 849 | sel5, |
| 850 | sel6, |
| 851 | muxtst, |
| 852 | test, |
| 853 | dout); |
| 854 | wire psel0; |
| 855 | wire psel1; |
| 856 | wire psel2; |
| 857 | wire psel3; |
| 858 | wire psel4; |
| 859 | wire psel5; |
| 860 | wire psel6; |
| 861 | wire psel7; |
| 862 | |
| 863 | input [10:0] din0; |
| 864 | input [10:0] din1; |
| 865 | input [10:0] din2; |
| 866 | input [10:0] din3; |
| 867 | input [10:0] din4; |
| 868 | input [10:0] din5; |
| 869 | input [10:0] din6; |
| 870 | input [10:0] din7; |
| 871 | input sel0; |
| 872 | input sel1; |
| 873 | input sel2; |
| 874 | input sel3; |
| 875 | input sel4; |
| 876 | input sel5; |
| 877 | input sel6; |
| 878 | input muxtst; |
| 879 | input test; |
| 880 | output [10:0] dout; |
| 881 | |
| 882 | |
| 883 | |
| 884 | |
| 885 | |
| 886 | cl_dp1_penc8_8x c0_0 ( |
| 887 | .sel0(sel0), |
| 888 | .sel1(sel1), |
| 889 | .sel2(sel2), |
| 890 | .sel3(sel3), |
| 891 | .sel4(sel4), |
| 892 | .sel5(sel5), |
| 893 | .sel6(sel6), |
| 894 | .psel0(psel0), |
| 895 | .psel1(psel1), |
| 896 | .psel2(psel2), |
| 897 | .psel3(psel3), |
| 898 | .psel4(psel4), |
| 899 | .psel5(psel5), |
| 900 | .psel6(psel6), |
| 901 | .psel7(psel7), |
| 902 | .test(test) |
| 903 | ); |
| 904 | |
| 905 | mux8 #(11) d0_0 ( |
| 906 | .sel0(psel0), |
| 907 | .sel1(psel1), |
| 908 | .sel2(psel2), |
| 909 | .sel3(psel3), |
| 910 | .sel4(psel4), |
| 911 | .sel5(psel5), |
| 912 | .sel6(psel6), |
| 913 | .sel7(psel7), |
| 914 | .in0(din0[10:0]), |
| 915 | .in1(din1[10:0]), |
| 916 | .in2(din2[10:0]), |
| 917 | .in3(din3[10:0]), |
| 918 | .in4(din4[10:0]), |
| 919 | .in5(din5[10:0]), |
| 920 | .in6(din6[10:0]), |
| 921 | .in7(din7[10:0]), |
| 922 | .dout(dout[10:0]), |
| 923 | .muxtst(muxtst) |
| 924 | ); |
| 925 | |
| 926 | |
| 927 | |
| 928 | |
| 929 | |
| 930 | |
| 931 | |
| 932 | |
| 933 | |
| 934 | |
| 935 | |
| 936 | |
| 937 | |
| 938 | endmodule |
| 939 | |
| 940 | |
| 941 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 942 | // also for pass-gate with decoder |
| 943 | |
| 944 | |
| 945 | |
| 946 | |
| 947 | |
| 948 | // any PARAMS parms go into naming of macro |
| 949 | |
| 950 | module fgu_fpe_dp_mux_macro__mux_pgpe__ports_4__stack_32l__width_11 ( |
| 951 | din0, |
| 952 | din1, |
| 953 | din2, |
| 954 | din3, |
| 955 | sel0, |
| 956 | sel1, |
| 957 | sel2, |
| 958 | muxtst, |
| 959 | test, |
| 960 | dout); |
| 961 | wire psel0; |
| 962 | wire psel1; |
| 963 | wire psel2; |
| 964 | wire psel3; |
| 965 | |
| 966 | input [10:0] din0; |
| 967 | input [10:0] din1; |
| 968 | input [10:0] din2; |
| 969 | input [10:0] din3; |
| 970 | input sel0; |
| 971 | input sel1; |
| 972 | input sel2; |
| 973 | input muxtst; |
| 974 | input test; |
| 975 | output [10:0] dout; |
| 976 | |
| 977 | |
| 978 | |
| 979 | |
| 980 | |
| 981 | cl_dp1_penc4_8x c0_0 ( |
| 982 | .sel0(sel0), |
| 983 | .sel1(sel1), |
| 984 | .sel2(sel2), |
| 985 | .psel0(psel0), |
| 986 | .psel1(psel1), |
| 987 | .psel2(psel2), |
| 988 | .psel3(psel3), |
| 989 | .test(test) |
| 990 | ); |
| 991 | |
| 992 | mux4 #(11) d0_0 ( |
| 993 | .sel0(psel0), |
| 994 | .sel1(psel1), |
| 995 | .sel2(psel2), |
| 996 | .sel3(psel3), |
| 997 | .in0(din0[10:0]), |
| 998 | .in1(din1[10:0]), |
| 999 | .in2(din2[10:0]), |
| 1000 | .in3(din3[10:0]), |
| 1001 | .dout(dout[10:0]), |
| 1002 | .muxtst(muxtst) |
| 1003 | ); |
| 1004 | |
| 1005 | |
| 1006 | |
| 1007 | |
| 1008 | |
| 1009 | |
| 1010 | |
| 1011 | |
| 1012 | |
| 1013 | |
| 1014 | |
| 1015 | |
| 1016 | |
| 1017 | endmodule |
| 1018 | |
| 1019 | |
| 1020 | // |
| 1021 | // invert macro |
| 1022 | // |
| 1023 | // |
| 1024 | |
| 1025 | |
| 1026 | |
| 1027 | |
| 1028 | |
| 1029 | module fgu_fpe_dp_inv_macro__stack_32l__width_11 ( |
| 1030 | din, |
| 1031 | dout); |
| 1032 | input [10:0] din; |
| 1033 | output [10:0] dout; |
| 1034 | |
| 1035 | |
| 1036 | |
| 1037 | |
| 1038 | |
| 1039 | |
| 1040 | inv #(11) d0_0 ( |
| 1041 | .in(din[10:0]), |
| 1042 | .out(dout[10:0]) |
| 1043 | ); |
| 1044 | |
| 1045 | |
| 1046 | |
| 1047 | |
| 1048 | |
| 1049 | |
| 1050 | |
| 1051 | |
| 1052 | |
| 1053 | endmodule |
| 1054 | |
| 1055 | |
| 1056 | |
| 1057 | |
| 1058 | |
| 1059 | // |
| 1060 | // cla macro |
| 1061 | // |
| 1062 | // |
| 1063 | |
| 1064 | |
| 1065 | |
| 1066 | |
| 1067 | |
| 1068 | module fgu_fpe_dp_cla_macro__width_12 ( |
| 1069 | cin, |
| 1070 | din0, |
| 1071 | din1, |
| 1072 | dout, |
| 1073 | cout); |
| 1074 | input cin; |
| 1075 | input [11:0] din0; |
| 1076 | input [11:0] din1; |
| 1077 | output [11:0] dout; |
| 1078 | output cout; |
| 1079 | |
| 1080 | |
| 1081 | |
| 1082 | |
| 1083 | |
| 1084 | |
| 1085 | |
| 1086 | cla #(12) m0_0 ( |
| 1087 | .cin(cin), |
| 1088 | .in0(din0[11:0]), |
| 1089 | .in1(din1[11:0]), |
| 1090 | .out(dout[11:0]), |
| 1091 | .cout(cout) |
| 1092 | ); |
| 1093 | |
| 1094 | |
| 1095 | |
| 1096 | |
| 1097 | |
| 1098 | |
| 1099 | |
| 1100 | |
| 1101 | |
| 1102 | |
| 1103 | |
| 1104 | |
| 1105 | endmodule |
| 1106 | |
| 1107 | |
| 1108 | |
| 1109 | |
| 1110 | |
| 1111 | |
| 1112 | |
| 1113 | |
| 1114 | |
| 1115 | // any PARAMS parms go into naming of macro |
| 1116 | |
| 1117 | module fgu_fpe_dp_msff_macro__mux_aonpe__ports_2__stack_32l__width_22 ( |
| 1118 | din0, |
| 1119 | sel0, |
| 1120 | din1, |
| 1121 | sel1, |
| 1122 | clk, |
| 1123 | en, |
| 1124 | se, |
| 1125 | scan_in, |
| 1126 | siclk, |
| 1127 | soclk, |
| 1128 | pce_ov, |
| 1129 | stop, |
| 1130 | dout, |
| 1131 | scan_out); |
| 1132 | wire buffout0; |
| 1133 | wire buffout1; |
| 1134 | wire [21:0] muxout; |
| 1135 | wire l1clk; |
| 1136 | wire siclk_out; |
| 1137 | wire soclk_out; |
| 1138 | wire [20:0] so; |
| 1139 | |
| 1140 | input [21:0] din0; |
| 1141 | input sel0; |
| 1142 | input [21:0] din1; |
| 1143 | input sel1; |
| 1144 | |
| 1145 | |
| 1146 | input clk; |
| 1147 | input en; |
| 1148 | input se; |
| 1149 | input scan_in; |
| 1150 | input siclk; |
| 1151 | input soclk; |
| 1152 | input pce_ov; |
| 1153 | input stop; |
| 1154 | |
| 1155 | |
| 1156 | |
| 1157 | output [21:0] dout; |
| 1158 | |
| 1159 | |
| 1160 | output scan_out; |
| 1161 | |
| 1162 | |
| 1163 | |
| 1164 | |
| 1165 | cl_dp1_muxbuff2_8x c1_0 ( |
| 1166 | .in0(sel0), |
| 1167 | .in1(sel1), |
| 1168 | .out0(buffout0), |
| 1169 | .out1(buffout1) |
| 1170 | ); |
| 1171 | mux2s #(22) d1_0 ( |
| 1172 | .sel0(buffout0), |
| 1173 | .sel1(buffout1), |
| 1174 | .in0(din0[21:0]), |
| 1175 | .in1(din1[21:0]), |
| 1176 | .dout(muxout[21:0]) |
| 1177 | ); |
| 1178 | cl_dp1_l1hdr_8x c0_0 ( |
| 1179 | .l2clk(clk), |
| 1180 | .pce(en), |
| 1181 | .aclk(siclk), |
| 1182 | .bclk(soclk), |
| 1183 | .l1clk(l1clk), |
| 1184 | .se(se), |
| 1185 | .pce_ov(pce_ov), |
| 1186 | .stop(stop), |
| 1187 | .siclk_out(siclk_out), |
| 1188 | .soclk_out(soclk_out) |
| 1189 | ); |
| 1190 | dff #(22) d0_0 ( |
| 1191 | .l1clk(l1clk), |
| 1192 | .siclk(siclk_out), |
| 1193 | .soclk(soclk_out), |
| 1194 | .d(muxout[21:0]), |
| 1195 | .si({scan_in,so[20:0]}), |
| 1196 | .so({so[20:0],scan_out}), |
| 1197 | .q(dout[21:0]) |
| 1198 | ); |
| 1199 | |
| 1200 | |
| 1201 | |
| 1202 | |
| 1203 | |
| 1204 | |
| 1205 | |
| 1206 | |
| 1207 | |
| 1208 | |
| 1209 | |
| 1210 | |
| 1211 | |
| 1212 | |
| 1213 | |
| 1214 | |
| 1215 | |
| 1216 | |
| 1217 | |
| 1218 | |
| 1219 | endmodule |
| 1220 | |
| 1221 | |
| 1222 | |
| 1223 | |
| 1224 | |
| 1225 | |
| 1226 | |
| 1227 | |
| 1228 | |
| 1229 | // |
| 1230 | // invert macro |
| 1231 | // |
| 1232 | // |
| 1233 | |
| 1234 | |
| 1235 | |
| 1236 | |
| 1237 | |
| 1238 | module fgu_fpe_dp_inv_macro__stack_32l__width_21 ( |
| 1239 | din, |
| 1240 | dout); |
| 1241 | input [20:0] din; |
| 1242 | output [20:0] dout; |
| 1243 | |
| 1244 | |
| 1245 | |
| 1246 | |
| 1247 | |
| 1248 | |
| 1249 | inv #(21) d0_0 ( |
| 1250 | .in(din[20:0]), |
| 1251 | .out(dout[20:0]) |
| 1252 | ); |
| 1253 | |
| 1254 | |
| 1255 | |
| 1256 | |
| 1257 | |
| 1258 | |
| 1259 | |
| 1260 | |
| 1261 | |
| 1262 | endmodule |
| 1263 | |
| 1264 | |
| 1265 | |
| 1266 | |
| 1267 | |
| 1268 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1269 | // also for pass-gate with decoder |
| 1270 | |
| 1271 | |
| 1272 | |
| 1273 | |
| 1274 | |
| 1275 | // any PARAMS parms go into naming of macro |
| 1276 | |
| 1277 | module fgu_fpe_dp_mux_macro__mux_pgpe__ports_7__stack_32l__width_11 ( |
| 1278 | din0, |
| 1279 | din1, |
| 1280 | din2, |
| 1281 | din3, |
| 1282 | din4, |
| 1283 | din5, |
| 1284 | din6, |
| 1285 | sel0, |
| 1286 | sel1, |
| 1287 | sel2, |
| 1288 | sel3, |
| 1289 | sel4, |
| 1290 | sel5, |
| 1291 | muxtst, |
| 1292 | test, |
| 1293 | dout); |
| 1294 | wire psel0; |
| 1295 | wire psel1; |
| 1296 | wire psel2; |
| 1297 | wire psel3; |
| 1298 | wire psel4; |
| 1299 | wire psel5; |
| 1300 | wire psel6; |
| 1301 | |
| 1302 | input [10:0] din0; |
| 1303 | input [10:0] din1; |
| 1304 | input [10:0] din2; |
| 1305 | input [10:0] din3; |
| 1306 | input [10:0] din4; |
| 1307 | input [10:0] din5; |
| 1308 | input [10:0] din6; |
| 1309 | input sel0; |
| 1310 | input sel1; |
| 1311 | input sel2; |
| 1312 | input sel3; |
| 1313 | input sel4; |
| 1314 | input sel5; |
| 1315 | input muxtst; |
| 1316 | input test; |
| 1317 | output [10:0] dout; |
| 1318 | |
| 1319 | |
| 1320 | |
| 1321 | |
| 1322 | |
| 1323 | cl_dp1_penc7_8x c0_0 ( |
| 1324 | .sel0(sel0), |
| 1325 | .sel1(sel1), |
| 1326 | .sel2(sel2), |
| 1327 | .sel3(sel3), |
| 1328 | .sel4(sel4), |
| 1329 | .sel5(sel5), |
| 1330 | .psel0(psel0), |
| 1331 | .psel1(psel1), |
| 1332 | .psel2(psel2), |
| 1333 | .psel3(psel3), |
| 1334 | .psel4(psel4), |
| 1335 | .psel5(psel5), |
| 1336 | .psel6(psel6), |
| 1337 | .test(test) |
| 1338 | ); |
| 1339 | |
| 1340 | mux7 #(11) d0_0 ( |
| 1341 | .sel0(psel0), |
| 1342 | .sel1(psel1), |
| 1343 | .sel2(psel2), |
| 1344 | .sel3(psel3), |
| 1345 | .sel4(psel4), |
| 1346 | .sel5(psel5), |
| 1347 | .sel6(psel6), |
| 1348 | .in0(din0[10:0]), |
| 1349 | .in1(din1[10:0]), |
| 1350 | .in2(din2[10:0]), |
| 1351 | .in3(din3[10:0]), |
| 1352 | .in4(din4[10:0]), |
| 1353 | .in5(din5[10:0]), |
| 1354 | .in6(din6[10:0]), |
| 1355 | .dout(dout[10:0]), |
| 1356 | .muxtst(muxtst) |
| 1357 | ); |
| 1358 | |
| 1359 | |
| 1360 | |
| 1361 | |
| 1362 | |
| 1363 | |
| 1364 | |
| 1365 | |
| 1366 | |
| 1367 | |
| 1368 | |
| 1369 | |
| 1370 | |
| 1371 | endmodule |
| 1372 | |
| 1373 | |
| 1374 | // |
| 1375 | // buff macro |
| 1376 | // |
| 1377 | // |
| 1378 | |
| 1379 | |
| 1380 | |
| 1381 | |
| 1382 | |
| 1383 | module fgu_fpe_dp_buff_macro__width_12 ( |
| 1384 | din, |
| 1385 | dout); |
| 1386 | input [11:0] din; |
| 1387 | output [11:0] dout; |
| 1388 | |
| 1389 | |
| 1390 | |
| 1391 | |
| 1392 | |
| 1393 | |
| 1394 | buff #(12) d0_0 ( |
| 1395 | .in(din[11:0]), |
| 1396 | .out(dout[11:0]) |
| 1397 | ); |
| 1398 | |
| 1399 | |
| 1400 | |
| 1401 | |
| 1402 | |
| 1403 | |
| 1404 | |
| 1405 | |
| 1406 | endmodule |
| 1407 | |
| 1408 | |
| 1409 | |
| 1410 | |
| 1411 | |
| 1412 | |
| 1413 | |
| 1414 | |
| 1415 | |
| 1416 | // any PARAMS parms go into naming of macro |
| 1417 | |
| 1418 | module fgu_fpe_dp_msff_macro__stack_32l__width_11 ( |
| 1419 | din, |
| 1420 | clk, |
| 1421 | en, |
| 1422 | se, |
| 1423 | scan_in, |
| 1424 | siclk, |
| 1425 | soclk, |
| 1426 | pce_ov, |
| 1427 | stop, |
| 1428 | dout, |
| 1429 | scan_out); |
| 1430 | wire l1clk; |
| 1431 | wire siclk_out; |
| 1432 | wire soclk_out; |
| 1433 | wire [9:0] so; |
| 1434 | |
| 1435 | input [10:0] din; |
| 1436 | |
| 1437 | |
| 1438 | input clk; |
| 1439 | input en; |
| 1440 | input se; |
| 1441 | input scan_in; |
| 1442 | input siclk; |
| 1443 | input soclk; |
| 1444 | input pce_ov; |
| 1445 | input stop; |
| 1446 | |
| 1447 | |
| 1448 | |
| 1449 | output [10:0] dout; |
| 1450 | |
| 1451 | |
| 1452 | output scan_out; |
| 1453 | |
| 1454 | |
| 1455 | |
| 1456 | |
| 1457 | cl_dp1_l1hdr_8x c0_0 ( |
| 1458 | .l2clk(clk), |
| 1459 | .pce(en), |
| 1460 | .aclk(siclk), |
| 1461 | .bclk(soclk), |
| 1462 | .l1clk(l1clk), |
| 1463 | .se(se), |
| 1464 | .pce_ov(pce_ov), |
| 1465 | .stop(stop), |
| 1466 | .siclk_out(siclk_out), |
| 1467 | .soclk_out(soclk_out) |
| 1468 | ); |
| 1469 | dff #(11) d0_0 ( |
| 1470 | .l1clk(l1clk), |
| 1471 | .siclk(siclk_out), |
| 1472 | .soclk(soclk_out), |
| 1473 | .d(din[10:0]), |
| 1474 | .si({scan_in,so[9:0]}), |
| 1475 | .so({so[9:0],scan_out}), |
| 1476 | .q(dout[10:0]) |
| 1477 | ); |
| 1478 | |
| 1479 | |
| 1480 | |
| 1481 | |
| 1482 | |
| 1483 | |
| 1484 | |
| 1485 | |
| 1486 | |
| 1487 | |
| 1488 | |
| 1489 | |
| 1490 | |
| 1491 | |
| 1492 | |
| 1493 | |
| 1494 | |
| 1495 | |
| 1496 | |
| 1497 | |
| 1498 | endmodule |
| 1499 | |
| 1500 | |
| 1501 | |
| 1502 | |
| 1503 | |
| 1504 | |
| 1505 | |
| 1506 | |
| 1507 | |
| 1508 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1509 | // also for pass-gate with decoder |
| 1510 | |
| 1511 | |
| 1512 | |
| 1513 | |
| 1514 | |
| 1515 | // any PARAMS parms go into naming of macro |
| 1516 | |
| 1517 | module fgu_fpe_dp_mux_macro__mux_aope__ports_5__stack_32l__width_11 ( |
| 1518 | din0, |
| 1519 | din1, |
| 1520 | din2, |
| 1521 | din3, |
| 1522 | din4, |
| 1523 | sel0, |
| 1524 | sel1, |
| 1525 | sel2, |
| 1526 | sel3, |
| 1527 | dout); |
| 1528 | wire psel0; |
| 1529 | wire psel1; |
| 1530 | wire psel2; |
| 1531 | wire psel3; |
| 1532 | wire psel4; |
| 1533 | |
| 1534 | input [10:0] din0; |
| 1535 | input [10:0] din1; |
| 1536 | input [10:0] din2; |
| 1537 | input [10:0] din3; |
| 1538 | input [10:0] din4; |
| 1539 | input sel0; |
| 1540 | input sel1; |
| 1541 | input sel2; |
| 1542 | input sel3; |
| 1543 | output [10:0] dout; |
| 1544 | |
| 1545 | |
| 1546 | |
| 1547 | |
| 1548 | |
| 1549 | cl_dp1_penc5_8x c0_0 ( |
| 1550 | .test(1'b1), |
| 1551 | .sel0(sel0), |
| 1552 | .sel1(sel1), |
| 1553 | .sel2(sel2), |
| 1554 | .sel3(sel3), |
| 1555 | .psel0(psel0), |
| 1556 | .psel1(psel1), |
| 1557 | .psel2(psel2), |
| 1558 | .psel3(psel3), |
| 1559 | .psel4(psel4) |
| 1560 | ); |
| 1561 | |
| 1562 | mux5s #(11) d0_0 ( |
| 1563 | .sel0(psel0), |
| 1564 | .sel1(psel1), |
| 1565 | .sel2(psel2), |
| 1566 | .sel3(psel3), |
| 1567 | .sel4(psel4), |
| 1568 | .in0(din0[10:0]), |
| 1569 | .in1(din1[10:0]), |
| 1570 | .in2(din2[10:0]), |
| 1571 | .in3(din3[10:0]), |
| 1572 | .in4(din4[10:0]), |
| 1573 | .dout(dout[10:0]) |
| 1574 | ); |
| 1575 | |
| 1576 | |
| 1577 | |
| 1578 | |
| 1579 | |
| 1580 | |
| 1581 | |
| 1582 | |
| 1583 | |
| 1584 | |
| 1585 | |
| 1586 | |
| 1587 | |
| 1588 | endmodule |
| 1589 | |
| 1590 | |
| 1591 | // |
| 1592 | // invert macro |
| 1593 | // |
| 1594 | // |
| 1595 | |
| 1596 | |
| 1597 | |
| 1598 | |
| 1599 | |
| 1600 | module fgu_fpe_dp_inv_macro__stack_32l__width_6 ( |
| 1601 | din, |
| 1602 | dout); |
| 1603 | input [5:0] din; |
| 1604 | output [5:0] dout; |
| 1605 | |
| 1606 | |
| 1607 | |
| 1608 | |
| 1609 | |
| 1610 | |
| 1611 | inv #(6) d0_0 ( |
| 1612 | .in(din[5:0]), |
| 1613 | .out(dout[5:0]) |
| 1614 | ); |
| 1615 | |
| 1616 | |
| 1617 | |
| 1618 | |
| 1619 | |
| 1620 | |
| 1621 | |
| 1622 | |
| 1623 | |
| 1624 | endmodule |
| 1625 | |
| 1626 | |
| 1627 | |
| 1628 | |
| 1629 | |
| 1630 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1631 | // also for pass-gate with decoder |
| 1632 | |
| 1633 | |
| 1634 | |
| 1635 | |
| 1636 | |
| 1637 | // any PARAMS parms go into naming of macro |
| 1638 | |
| 1639 | module fgu_fpe_dp_mux_macro__mux_aope__ports_4__stack_32l__width_12 ( |
| 1640 | din0, |
| 1641 | din1, |
| 1642 | din2, |
| 1643 | din3, |
| 1644 | sel0, |
| 1645 | sel1, |
| 1646 | sel2, |
| 1647 | dout); |
| 1648 | wire psel0; |
| 1649 | wire psel1; |
| 1650 | wire psel2; |
| 1651 | wire psel3; |
| 1652 | |
| 1653 | input [11:0] din0; |
| 1654 | input [11:0] din1; |
| 1655 | input [11:0] din2; |
| 1656 | input [11:0] din3; |
| 1657 | input sel0; |
| 1658 | input sel1; |
| 1659 | input sel2; |
| 1660 | output [11:0] dout; |
| 1661 | |
| 1662 | |
| 1663 | |
| 1664 | |
| 1665 | |
| 1666 | cl_dp1_penc4_8x c0_0 ( |
| 1667 | .test(1'b1), |
| 1668 | .sel0(sel0), |
| 1669 | .sel1(sel1), |
| 1670 | .sel2(sel2), |
| 1671 | .psel0(psel0), |
| 1672 | .psel1(psel1), |
| 1673 | .psel2(psel2), |
| 1674 | .psel3(psel3) |
| 1675 | ); |
| 1676 | |
| 1677 | mux4s #(12) d0_0 ( |
| 1678 | .sel0(psel0), |
| 1679 | .sel1(psel1), |
| 1680 | .sel2(psel2), |
| 1681 | .sel3(psel3), |
| 1682 | .in0(din0[11:0]), |
| 1683 | .in1(din1[11:0]), |
| 1684 | .in2(din2[11:0]), |
| 1685 | .in3(din3[11:0]), |
| 1686 | .dout(dout[11:0]) |
| 1687 | ); |
| 1688 | |
| 1689 | |
| 1690 | |
| 1691 | |
| 1692 | |
| 1693 | |
| 1694 | |
| 1695 | |
| 1696 | |
| 1697 | |
| 1698 | |
| 1699 | |
| 1700 | |
| 1701 | endmodule |
| 1702 | |
| 1703 | |
| 1704 | |
| 1705 | |
| 1706 | |
| 1707 | |
| 1708 | // any PARAMS parms go into naming of macro |
| 1709 | |
| 1710 | module fgu_fpe_dp_msff_macro__stack_32l__width_24 ( |
| 1711 | din, |
| 1712 | clk, |
| 1713 | en, |
| 1714 | se, |
| 1715 | scan_in, |
| 1716 | siclk, |
| 1717 | soclk, |
| 1718 | pce_ov, |
| 1719 | stop, |
| 1720 | dout, |
| 1721 | scan_out); |
| 1722 | wire l1clk; |
| 1723 | wire siclk_out; |
| 1724 | wire soclk_out; |
| 1725 | wire [22:0] so; |
| 1726 | |
| 1727 | input [23:0] din; |
| 1728 | |
| 1729 | |
| 1730 | input clk; |
| 1731 | input en; |
| 1732 | input se; |
| 1733 | input scan_in; |
| 1734 | input siclk; |
| 1735 | input soclk; |
| 1736 | input pce_ov; |
| 1737 | input stop; |
| 1738 | |
| 1739 | |
| 1740 | |
| 1741 | output [23:0] dout; |
| 1742 | |
| 1743 | |
| 1744 | output scan_out; |
| 1745 | |
| 1746 | |
| 1747 | |
| 1748 | |
| 1749 | cl_dp1_l1hdr_8x c0_0 ( |
| 1750 | .l2clk(clk), |
| 1751 | .pce(en), |
| 1752 | .aclk(siclk), |
| 1753 | .bclk(soclk), |
| 1754 | .l1clk(l1clk), |
| 1755 | .se(se), |
| 1756 | .pce_ov(pce_ov), |
| 1757 | .stop(stop), |
| 1758 | .siclk_out(siclk_out), |
| 1759 | .soclk_out(soclk_out) |
| 1760 | ); |
| 1761 | dff #(24) d0_0 ( |
| 1762 | .l1clk(l1clk), |
| 1763 | .siclk(siclk_out), |
| 1764 | .soclk(soclk_out), |
| 1765 | .d(din[23:0]), |
| 1766 | .si({scan_in,so[22:0]}), |
| 1767 | .so({so[22:0],scan_out}), |
| 1768 | .q(dout[23:0]) |
| 1769 | ); |
| 1770 | |
| 1771 | |
| 1772 | |
| 1773 | |
| 1774 | |
| 1775 | |
| 1776 | |
| 1777 | |
| 1778 | |
| 1779 | |
| 1780 | |
| 1781 | |
| 1782 | |
| 1783 | |
| 1784 | |
| 1785 | |
| 1786 | |
| 1787 | |
| 1788 | |
| 1789 | |
| 1790 | endmodule |
| 1791 | |
| 1792 | |
| 1793 | |
| 1794 | |
| 1795 | |
| 1796 | |
| 1797 | |
| 1798 | |
| 1799 | |
| 1800 | // |
| 1801 | // increment macro |
| 1802 | // |
| 1803 | // |
| 1804 | |
| 1805 | |
| 1806 | |
| 1807 | |
| 1808 | |
| 1809 | module fgu_fpe_dp_increment_macro__width_12 ( |
| 1810 | din, |
| 1811 | cin, |
| 1812 | dout, |
| 1813 | cout); |
| 1814 | input [11:0] din; |
| 1815 | input cin; |
| 1816 | output [11:0] dout; |
| 1817 | output cout; |
| 1818 | |
| 1819 | |
| 1820 | |
| 1821 | |
| 1822 | |
| 1823 | |
| 1824 | incr #(12) m0_0 ( |
| 1825 | .cin(cin), |
| 1826 | .in(din[11:0]), |
| 1827 | .out(dout[11:0]), |
| 1828 | .cout(cout) |
| 1829 | ); |
| 1830 | |
| 1831 | |
| 1832 | |
| 1833 | |
| 1834 | |
| 1835 | |
| 1836 | |
| 1837 | |
| 1838 | |
| 1839 | |
| 1840 | |
| 1841 | endmodule |
| 1842 | |
| 1843 | |
| 1844 | |
| 1845 | |
| 1846 | |
| 1847 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1848 | // also for pass-gate with decoder |
| 1849 | |
| 1850 | |
| 1851 | |
| 1852 | |
| 1853 | |
| 1854 | // any PARAMS parms go into naming of macro |
| 1855 | |
| 1856 | module fgu_fpe_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_32l__width_1 ( |
| 1857 | din0, |
| 1858 | sel0, |
| 1859 | din1, |
| 1860 | sel1, |
| 1861 | dout); |
| 1862 | input [0:0] din0; |
| 1863 | input sel0; |
| 1864 | input [0:0] din1; |
| 1865 | input sel1; |
| 1866 | output [0:0] dout; |
| 1867 | |
| 1868 | |
| 1869 | |
| 1870 | |
| 1871 | |
| 1872 | mux2s #(1) d0_0 ( |
| 1873 | .sel0(sel0), |
| 1874 | .sel1(sel1), |
| 1875 | .in0(din0[0:0]), |
| 1876 | .in1(din1[0:0]), |
| 1877 | .dout(dout[0:0]) |
| 1878 | ); |
| 1879 | |
| 1880 | |
| 1881 | |
| 1882 | |
| 1883 | |
| 1884 | |
| 1885 | |
| 1886 | |
| 1887 | |
| 1888 | |
| 1889 | |
| 1890 | |
| 1891 | |
| 1892 | endmodule |
| 1893 | |
| 1894 | |
| 1895 | // |
| 1896 | // invert macro |
| 1897 | // |
| 1898 | // |
| 1899 | |
| 1900 | |
| 1901 | |
| 1902 | |
| 1903 | |
| 1904 | module fgu_fpe_dp_inv_macro__stack_32l__width_8 ( |
| 1905 | din, |
| 1906 | dout); |
| 1907 | input [7:0] din; |
| 1908 | output [7:0] dout; |
| 1909 | |
| 1910 | |
| 1911 | |
| 1912 | |
| 1913 | |
| 1914 | |
| 1915 | inv #(8) d0_0 ( |
| 1916 | .in(din[7:0]), |
| 1917 | .out(dout[7:0]) |
| 1918 | ); |
| 1919 | |
| 1920 | |
| 1921 | |
| 1922 | |
| 1923 | |
| 1924 | |
| 1925 | |
| 1926 | |
| 1927 | |
| 1928 | endmodule |
| 1929 | |
| 1930 | |
| 1931 | |
| 1932 | |
| 1933 | |
| 1934 | // |
| 1935 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) |
| 1936 | // |
| 1937 | // |
| 1938 | |
| 1939 | |
| 1940 | |
| 1941 | |
| 1942 | |
| 1943 | module fgu_fpe_dp_cmp_macro__width_12 ( |
| 1944 | din0, |
| 1945 | din1, |
| 1946 | dout); |
| 1947 | input [11:0] din0; |
| 1948 | input [11:0] din1; |
| 1949 | output dout; |
| 1950 | |
| 1951 | |
| 1952 | |
| 1953 | |
| 1954 | |
| 1955 | |
| 1956 | cmp #(12) m0_0 ( |
| 1957 | .in0(din0[11:0]), |
| 1958 | .in1(din1[11:0]), |
| 1959 | .out(dout) |
| 1960 | ); |
| 1961 | |
| 1962 | |
| 1963 | |
| 1964 | |
| 1965 | |
| 1966 | |
| 1967 | |
| 1968 | |
| 1969 | |
| 1970 | |
| 1971 | endmodule |
| 1972 | |
| 1973 | |
| 1974 | |
| 1975 | |
| 1976 | |
| 1977 | // |
| 1978 | // nand macro for ports = 2,3,4 |
| 1979 | // |
| 1980 | // |
| 1981 | |
| 1982 | |
| 1983 | |
| 1984 | |
| 1985 | |
| 1986 | module fgu_fpe_dp_nand_macro__ports_2__stack_32l__width_2 ( |
| 1987 | din0, |
| 1988 | din1, |
| 1989 | dout); |
| 1990 | input [1:0] din0; |
| 1991 | input [1:0] din1; |
| 1992 | output [1:0] dout; |
| 1993 | |
| 1994 | |
| 1995 | |
| 1996 | |
| 1997 | |
| 1998 | |
| 1999 | nand2 #(2) d0_0 ( |
| 2000 | .in0(din0[1:0]), |
| 2001 | .in1(din1[1:0]), |
| 2002 | .out(dout[1:0]) |
| 2003 | ); |
| 2004 | |
| 2005 | |
| 2006 | |
| 2007 | |
| 2008 | |
| 2009 | |
| 2010 | |
| 2011 | |
| 2012 | |
| 2013 | endmodule |
| 2014 | |
| 2015 | |
| 2016 | |
| 2017 | |
| 2018 | |
| 2019 | // |
| 2020 | // invert macro |
| 2021 | // |
| 2022 | // |
| 2023 | |
| 2024 | |
| 2025 | |
| 2026 | |
| 2027 | |
| 2028 | module fgu_fpe_dp_inv_macro__stack_32l__width_2 ( |
| 2029 | din, |
| 2030 | dout); |
| 2031 | input [1:0] din; |
| 2032 | output [1:0] dout; |
| 2033 | |
| 2034 | |
| 2035 | |
| 2036 | |
| 2037 | |
| 2038 | |
| 2039 | inv #(2) d0_0 ( |
| 2040 | .in(din[1:0]), |
| 2041 | .out(dout[1:0]) |
| 2042 | ); |
| 2043 | |
| 2044 | |
| 2045 | |
| 2046 | |
| 2047 | |
| 2048 | |
| 2049 | |
| 2050 | |
| 2051 | |
| 2052 | endmodule |
| 2053 | |
| 2054 | |
| 2055 | |
| 2056 | |
| 2057 | |
| 2058 | // |
| 2059 | // nand macro for ports = 2,3,4 |
| 2060 | // |
| 2061 | // |
| 2062 | |
| 2063 | |
| 2064 | |
| 2065 | |
| 2066 | |
| 2067 | module fgu_fpe_dp_nand_macro__dnand_8x__ports_2__stack_32l__width_4 ( |
| 2068 | din0, |
| 2069 | din1, |
| 2070 | dout); |
| 2071 | input [3:0] din0; |
| 2072 | input [3:0] din1; |
| 2073 | output [3:0] dout; |
| 2074 | |
| 2075 | |
| 2076 | |
| 2077 | |
| 2078 | |
| 2079 | |
| 2080 | nand2 #(4) d0_0 ( |
| 2081 | .in0(din0[3:0]), |
| 2082 | .in1(din1[3:0]), |
| 2083 | .out(dout[3:0]) |
| 2084 | ); |
| 2085 | |
| 2086 | |
| 2087 | |
| 2088 | |
| 2089 | |
| 2090 | |
| 2091 | |
| 2092 | |
| 2093 | |
| 2094 | endmodule |
| 2095 | |
| 2096 | |
| 2097 | |
| 2098 | |
| 2099 | |
| 2100 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2101 | // also for pass-gate with decoder |
| 2102 | |
| 2103 | |
| 2104 | |
| 2105 | |
| 2106 | |
| 2107 | // any PARAMS parms go into naming of macro |
| 2108 | |
| 2109 | module fgu_fpe_dp_mux_macro__mux_aope__ports_3__stack_32l__width_11 ( |
| 2110 | din0, |
| 2111 | din1, |
| 2112 | din2, |
| 2113 | sel0, |
| 2114 | sel1, |
| 2115 | dout); |
| 2116 | wire psel0; |
| 2117 | wire psel1; |
| 2118 | wire psel2; |
| 2119 | |
| 2120 | input [10:0] din0; |
| 2121 | input [10:0] din1; |
| 2122 | input [10:0] din2; |
| 2123 | input sel0; |
| 2124 | input sel1; |
| 2125 | output [10:0] dout; |
| 2126 | |
| 2127 | |
| 2128 | |
| 2129 | |
| 2130 | |
| 2131 | cl_dp1_penc3_8x c0_0 ( |
| 2132 | .test(1'b1), |
| 2133 | .sel0(sel0), |
| 2134 | .sel1(sel1), |
| 2135 | .psel0(psel0), |
| 2136 | .psel1(psel1), |
| 2137 | .psel2(psel2) |
| 2138 | ); |
| 2139 | |
| 2140 | mux3s #(11) d0_0 ( |
| 2141 | .sel0(psel0), |
| 2142 | .sel1(psel1), |
| 2143 | .sel2(psel2), |
| 2144 | .in0(din0[10:0]), |
| 2145 | .in1(din1[10:0]), |
| 2146 | .in2(din2[10:0]), |
| 2147 | .dout(dout[10:0]) |
| 2148 | ); |
| 2149 | |
| 2150 | |
| 2151 | |
| 2152 | |
| 2153 | |
| 2154 | |
| 2155 | |
| 2156 | |
| 2157 | |
| 2158 | |
| 2159 | |
| 2160 | |
| 2161 | |
| 2162 | endmodule |
| 2163 | |