| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: fgu_rep_dp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module fgu_rep_dp ( |
| 36 | fad_rs1_fmt_fx1, |
| 37 | fad_rs2_fmt_fx1, |
| 38 | fad_rs1_fmt_fx1_rep0, |
| 39 | fad_rs1_fmt_fx1_rep01, |
| 40 | fad_rs2_fmt_fx1_rep0, |
| 41 | fad_rs2_fmt_fx1_rep01, |
| 42 | fad_rs2_fmt_fx1_rep1, |
| 43 | fdd_result, |
| 44 | fdd_result_rep0, |
| 45 | fpf_hi_bof_fx1, |
| 46 | fpf_lo_bof_fx1, |
| 47 | fpf_hi_bof_fx1_rep0, |
| 48 | fpf_lo_bof_fx1_rep0, |
| 49 | fpe_rs2_fmt_fx1, |
| 50 | fpe_rs2_fmt_fx1_b0_rep0, |
| 51 | mul_clken, |
| 52 | div_clken, |
| 53 | mul_clken_rep0, |
| 54 | mul_clken_rep01, |
| 55 | div_clken_rep0, |
| 56 | fac_div_valid_fx1, |
| 57 | fac_divq_valid_fx1, |
| 58 | fac_div_control_fx1, |
| 59 | fac_div_valid_fx1_rep0, |
| 60 | fac_divq_valid_fx1_rep0, |
| 61 | fac_div_control_fx1_rep0, |
| 62 | fdc_finish_int_early, |
| 63 | fdc_finish_fltd_early, |
| 64 | fdc_finish_flts_early, |
| 65 | fdc_finish_int_early_rep0, |
| 66 | fdc_finish_fltd_early_rep0, |
| 67 | fdc_finish_flts_early_rep0); |
| 68 | |
| 69 | |
| 70 | // ---------------------------------------------------------------------------- |
| 71 | // |
| 72 | // ---------------------------------------------------------------------------- |
| 73 | |
| 74 | input [63:0] fad_rs1_fmt_fx1; |
| 75 | input [63:0] fad_rs2_fmt_fx1; |
| 76 | output [63:0] fad_rs1_fmt_fx1_rep0; |
| 77 | output [63:0] fad_rs1_fmt_fx1_rep01; |
| 78 | output [63:0] fad_rs2_fmt_fx1_rep0; |
| 79 | output [63:0] fad_rs2_fmt_fx1_rep01; |
| 80 | output [63:0] fad_rs2_fmt_fx1_rep1; |
| 81 | |
| 82 | input [62:11] fdd_result; |
| 83 | output [62:11] fdd_result_rep0; |
| 84 | |
| 85 | input fpf_hi_bof_fx1; |
| 86 | input fpf_lo_bof_fx1; |
| 87 | output fpf_hi_bof_fx1_rep0; |
| 88 | output fpf_lo_bof_fx1_rep0; |
| 89 | |
| 90 | input [0:0] fpe_rs2_fmt_fx1; |
| 91 | output fpe_rs2_fmt_fx1_b0_rep0; |
| 92 | |
| 93 | input mul_clken; |
| 94 | input div_clken; |
| 95 | output mul_clken_rep0; |
| 96 | output mul_clken_rep01; |
| 97 | output div_clken_rep0; |
| 98 | |
| 99 | input fac_div_valid_fx1; |
| 100 | input fac_divq_valid_fx1; |
| 101 | input [4:0] fac_div_control_fx1; |
| 102 | output fac_div_valid_fx1_rep0; |
| 103 | output fac_divq_valid_fx1_rep0; |
| 104 | output [4:0] fac_div_control_fx1_rep0; |
| 105 | |
| 106 | input fdc_finish_int_early; |
| 107 | input fdc_finish_fltd_early; |
| 108 | input fdc_finish_flts_early; |
| 109 | output fdc_finish_int_early_rep0; |
| 110 | output fdc_finish_fltd_early_rep0; |
| 111 | output fdc_finish_flts_early_rep0; |
| 112 | |
| 113 | |
| 114 | // ---------------------------------------------------------------------------- |
| 115 | // |
| 116 | // ---------------------------------------------------------------------------- |
| 117 | |
| 118 | |
| 119 | fgu_rep_dp_buff_macro__rep_1__width_64 rs1_fmt_rep0 ( |
| 120 | .din (fad_rs1_fmt_fx1[63:0] ), |
| 121 | .dout(fad_rs1_fmt_fx1_rep0[63:0]) |
| 122 | ); |
| 123 | |
| 124 | fgu_rep_dp_buff_macro__rep_1__width_64 rs1_fmt_rep01 ( |
| 125 | .din (fad_rs1_fmt_fx1[63:0] ), |
| 126 | .dout(fad_rs1_fmt_fx1_rep01[63:0]) |
| 127 | ); |
| 128 | |
| 129 | fgu_rep_dp_buff_macro__rep_1__width_64 rs2_fmt_rep0 ( |
| 130 | .din (fad_rs2_fmt_fx1[63:0] ), |
| 131 | .dout(fad_rs2_fmt_fx1_rep0[63:0]) |
| 132 | ); |
| 133 | |
| 134 | fgu_rep_dp_buff_macro__rep_1__width_64 rs2_fmt_rep01 ( |
| 135 | .din (fad_rs2_fmt_fx1[63:0] ), |
| 136 | .dout(fad_rs2_fmt_fx1_rep01[63:0]) |
| 137 | ); |
| 138 | |
| 139 | fgu_rep_dp_buff_macro__rep_1__stack_88c__width_64 rs2_fmt_rep1 ( // placed in fpy, so stack width set to match |
| 140 | .din (fad_rs2_fmt_fx1_rep0[63:0]), |
| 141 | .dout(fad_rs2_fmt_fx1_rep1[63:0]) |
| 142 | ); |
| 143 | |
| 144 | fgu_rep_dp_buff_macro__rep_1__width_52 fdd_res_rep0 ( |
| 145 | .din (fdd_result[62:11] ), |
| 146 | .dout(fdd_result_rep0[62:11]) |
| 147 | ); |
| 148 | |
| 149 | fgu_rep_dp_buff_macro__rep_1__width_2 bof_rep0 ( |
| 150 | .din ({fpf_hi_bof_fx1, fpf_lo_bof_fx1 }), |
| 151 | .dout({fpf_hi_bof_fx1_rep0, fpf_lo_bof_fx1_rep0}) |
| 152 | ); |
| 153 | |
| 154 | fgu_rep_dp_buff_macro__rep_1__width_1 fpe_fmt_rep0 ( |
| 155 | .din (fpe_rs2_fmt_fx1[0] ), |
| 156 | .dout(fpe_rs2_fmt_fx1_b0_rep0) |
| 157 | ); |
| 158 | |
| 159 | fgu_rep_dp_buff_macro__rep_1__width_2 mul_clkenable_rep0 ( |
| 160 | .din ({mul_clken, mul_clken }), |
| 161 | .dout({mul_clken_rep01, mul_clken_rep0}) |
| 162 | ); |
| 163 | |
| 164 | fgu_rep_dp_buff_macro__rep_1__width_8 div_control_rep0 ( |
| 165 | .din ({div_clken, |
| 166 | fac_div_valid_fx1, |
| 167 | fac_divq_valid_fx1, |
| 168 | fac_div_control_fx1[4:0]}), |
| 169 | .dout({div_clken_rep0, |
| 170 | fac_div_valid_fx1_rep0, |
| 171 | fac_divq_valid_fx1_rep0, |
| 172 | fac_div_control_fx1_rep0[4:0]}) |
| 173 | ); |
| 174 | |
| 175 | fgu_rep_dp_buff_macro__rep_1__width_3 finish_early_rep0 ( |
| 176 | .din ({fdc_finish_int_early, |
| 177 | fdc_finish_fltd_early, |
| 178 | fdc_finish_flts_early}), |
| 179 | .dout({fdc_finish_int_early_rep0, |
| 180 | fdc_finish_fltd_early_rep0, |
| 181 | fdc_finish_flts_early_rep0}) |
| 182 | ); |
| 183 | |
| 184 | |
| 185 | endmodule // fgu_rep_dp |
| 186 | |
| 187 | |
| 188 | |
| 189 | // |
| 190 | // buff macro |
| 191 | // |
| 192 | // |
| 193 | |
| 194 | |
| 195 | |
| 196 | |
| 197 | |
| 198 | module fgu_rep_dp_buff_macro__rep_1__width_64 ( |
| 199 | din, |
| 200 | dout); |
| 201 | input [63:0] din; |
| 202 | output [63:0] dout; |
| 203 | |
| 204 | |
| 205 | |
| 206 | |
| 207 | |
| 208 | |
| 209 | buff #(64) d0_0 ( |
| 210 | .in(din[63:0]), |
| 211 | .out(dout[63:0]) |
| 212 | ); |
| 213 | |
| 214 | |
| 215 | |
| 216 | |
| 217 | |
| 218 | |
| 219 | |
| 220 | |
| 221 | endmodule |
| 222 | |
| 223 | |
| 224 | |
| 225 | |
| 226 | |
| 227 | // |
| 228 | // buff macro |
| 229 | // |
| 230 | // |
| 231 | |
| 232 | |
| 233 | |
| 234 | |
| 235 | |
| 236 | module fgu_rep_dp_buff_macro__rep_1__stack_88c__width_64 ( |
| 237 | din, |
| 238 | dout); |
| 239 | input [63:0] din; |
| 240 | output [63:0] dout; |
| 241 | |
| 242 | |
| 243 | |
| 244 | |
| 245 | |
| 246 | |
| 247 | buff #(64) d0_0 ( |
| 248 | .in(din[63:0]), |
| 249 | .out(dout[63:0]) |
| 250 | ); |
| 251 | |
| 252 | |
| 253 | |
| 254 | |
| 255 | |
| 256 | |
| 257 | |
| 258 | |
| 259 | endmodule |
| 260 | |
| 261 | |
| 262 | |
| 263 | |
| 264 | |
| 265 | // |
| 266 | // buff macro |
| 267 | // |
| 268 | // |
| 269 | |
| 270 | |
| 271 | |
| 272 | |
| 273 | |
| 274 | module fgu_rep_dp_buff_macro__rep_1__width_52 ( |
| 275 | din, |
| 276 | dout); |
| 277 | input [51:0] din; |
| 278 | output [51:0] dout; |
| 279 | |
| 280 | |
| 281 | |
| 282 | |
| 283 | |
| 284 | |
| 285 | buff #(52) d0_0 ( |
| 286 | .in(din[51:0]), |
| 287 | .out(dout[51:0]) |
| 288 | ); |
| 289 | |
| 290 | |
| 291 | |
| 292 | |
| 293 | |
| 294 | |
| 295 | |
| 296 | |
| 297 | endmodule |
| 298 | |
| 299 | |
| 300 | |
| 301 | |
| 302 | |
| 303 | // |
| 304 | // buff macro |
| 305 | // |
| 306 | // |
| 307 | |
| 308 | |
| 309 | |
| 310 | |
| 311 | |
| 312 | module fgu_rep_dp_buff_macro__rep_1__width_2 ( |
| 313 | din, |
| 314 | dout); |
| 315 | input [1:0] din; |
| 316 | output [1:0] dout; |
| 317 | |
| 318 | |
| 319 | |
| 320 | |
| 321 | |
| 322 | |
| 323 | buff #(2) d0_0 ( |
| 324 | .in(din[1:0]), |
| 325 | .out(dout[1:0]) |
| 326 | ); |
| 327 | |
| 328 | |
| 329 | |
| 330 | |
| 331 | |
| 332 | |
| 333 | |
| 334 | |
| 335 | endmodule |
| 336 | |
| 337 | |
| 338 | |
| 339 | |
| 340 | |
| 341 | // |
| 342 | // buff macro |
| 343 | // |
| 344 | // |
| 345 | |
| 346 | |
| 347 | |
| 348 | |
| 349 | |
| 350 | module fgu_rep_dp_buff_macro__rep_1__width_1 ( |
| 351 | din, |
| 352 | dout); |
| 353 | input [0:0] din; |
| 354 | output [0:0] dout; |
| 355 | |
| 356 | |
| 357 | |
| 358 | |
| 359 | |
| 360 | |
| 361 | buff #(1) d0_0 ( |
| 362 | .in(din[0:0]), |
| 363 | .out(dout[0:0]) |
| 364 | ); |
| 365 | |
| 366 | |
| 367 | |
| 368 | |
| 369 | |
| 370 | |
| 371 | |
| 372 | |
| 373 | endmodule |
| 374 | |
| 375 | |
| 376 | |
| 377 | |
| 378 | |
| 379 | // |
| 380 | // buff macro |
| 381 | // |
| 382 | // |
| 383 | |
| 384 | |
| 385 | |
| 386 | |
| 387 | |
| 388 | module fgu_rep_dp_buff_macro__rep_1__width_8 ( |
| 389 | din, |
| 390 | dout); |
| 391 | input [7:0] din; |
| 392 | output [7:0] dout; |
| 393 | |
| 394 | |
| 395 | |
| 396 | |
| 397 | |
| 398 | |
| 399 | buff #(8) d0_0 ( |
| 400 | .in(din[7:0]), |
| 401 | .out(dout[7:0]) |
| 402 | ); |
| 403 | |
| 404 | |
| 405 | |
| 406 | |
| 407 | |
| 408 | |
| 409 | |
| 410 | |
| 411 | endmodule |
| 412 | |
| 413 | |
| 414 | |
| 415 | |
| 416 | |
| 417 | // |
| 418 | // buff macro |
| 419 | // |
| 420 | // |
| 421 | |
| 422 | |
| 423 | |
| 424 | |
| 425 | |
| 426 | module fgu_rep_dp_buff_macro__rep_1__width_3 ( |
| 427 | din, |
| 428 | dout); |
| 429 | input [2:0] din; |
| 430 | output [2:0] dout; |
| 431 | |
| 432 | |
| 433 | |
| 434 | |
| 435 | |
| 436 | |
| 437 | buff #(3) d0_0 ( |
| 438 | .in(din[2:0]), |
| 439 | .out(dout[2:0]) |
| 440 | ); |
| 441 | |
| 442 | |
| 443 | |
| 444 | |
| 445 | |
| 446 | |
| 447 | |
| 448 | |
| 449 | endmodule |
| 450 | |
| 451 | |
| 452 | |
| 453 | |