| 1 | # ========== Copyright Header Begin ========================================== |
| 2 | # |
| 3 | # OpenSPARC T2 Processor File: user_cfg.scr |
| 4 | # Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | # 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | # |
| 7 | # * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | # |
| 9 | # This program is free software; you can redistribute it and/or modify |
| 10 | # it under the terms of the GNU General Public License as published by |
| 11 | # the Free Software Foundation; version 2 of the License. |
| 12 | # |
| 13 | # This program is distributed in the hope that it will be useful, |
| 14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | # GNU General Public License for more details. |
| 17 | # |
| 18 | # You should have received a copy of the GNU General Public License |
| 19 | # along with this program; if not, write to the Free Software |
| 20 | # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | # |
| 22 | # For the avoidance of doubt, and except that if any non-GPL license |
| 23 | # choice is available it will apply instead, Sun elects to use only |
| 24 | # the General Public License version 2 (GPLv2) at this time for any |
| 25 | # software where a choice of GPL license versions is made |
| 26 | # available with the language indicating that GPLv2 or any later version |
| 27 | # may be used, or where a choice of which version of the GPL is applied is |
| 28 | # otherwise unspecified. |
| 29 | # |
| 30 | # Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | # CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | # have any questions. |
| 33 | # |
| 34 | # ========== Copyright Header End ============================================ |
| 35 | source -echo -verbose $dv_root/design/sys/synopsys/script/project_sparc_cfg.scr |
| 36 | |
| 37 | set rtl_files {\ |
| 38 | libs/cl/cl_rtl_ext.v |
| 39 | libs/cl/cl_a1/cl_a1.behV |
| 40 | libs/cl/cl_u1/cl_u1.behV |
| 41 | libs/cl/cl_dp1/cl_dp1.behV |
| 42 | libs/cl/cl_sc1/cl_sc1.behV |
| 43 | libs/cl/cl_mc1/cl_mc1.v |
| 44 | |
| 45 | libs/n2sram/mp/n2_frf_mp_256x78_cust_l/n2_frf_mp_256x78_cust/rtl/n2_frf_mp_256x78_cust.v |
| 46 | |
| 47 | design/sys/iop/spc/fgu/rtl/fgu.v |
| 48 | design/sys/iop/spc/fgu/rtl/fgu_fac_ctl.v |
| 49 | design/sys/iop/spc/fgu/rtl/fgu_fad_dp.v |
| 50 | design/sys/iop/spc/fgu/rtl/fgu_fdc_ctl.v |
| 51 | design/sys/iop/spc/fgu/rtl/fgu_fdd_dp.v |
| 52 | design/sys/iop/spc/fgu/rtl/fgu_fec_ctl.v |
| 53 | design/sys/iop/spc/fgu/rtl/fgu_fgd_dp.v |
| 54 | design/sys/iop/spc/fgu/rtl/fgu_fic_ctl.v |
| 55 | design/sys/iop/spc/fgu/rtl/fgu_fpc_ctl.v |
| 56 | design/sys/iop/spc/fgu/rtl/fgu_fpe_dp.v |
| 57 | design/sys/iop/spc/fgu/rtl/fgu_fpf_dp.v |
| 58 | design/sys/iop/spc/fgu/rtl/fgu_fpy_dp.v |
| 59 | design/sys/iop/spc/fgu/rtl/fgu_rep_dp.v |
| 60 | } |
| 61 | |
| 62 | set link_library [concat $link_library \ |
| 63 | dw_foundation.sldb \ |
| 64 | ] |
| 65 | |
| 66 | |
| 67 | set mix_files {} |
| 68 | set top_module fgu |
| 69 | |
| 70 | set include_paths {\ |
| 71 | } |
| 72 | |
| 73 | set black_box_libs {} |
| 74 | set black_box_designs {} |
| 75 | set mem_libs {} |
| 76 | |
| 77 | set dont_touch_modules {\ |
| 78 | } |
| 79 | |
| 80 | set compile_effort "medium" |
| 81 | |
| 82 | set compile_flatten_all 1 |
| 83 | |
| 84 | set compile_no_new_cells_at_top_level false |
| 85 | |
| 86 | set default_clk l2clk |
| 87 | set default_clk_freq 1400 |
| 88 | set default_setup_skew 0.0 |
| 89 | set default_hold_skew 0.0 |
| 90 | set default_clk_transition 0.05 |
| 91 | set clk_list { \ |
| 92 | { l2clk 1400.0 0.000 0.000 0.05} \ |
| 93 | } |
| 94 | |
| 95 | set ideal_net_list {} |
| 96 | set false_path_list {} |
| 97 | set enforce_input_fanout_one 0 |
| 98 | set allow_outport_drive_innodes 1 |
| 99 | set skip_scan 0 |
| 100 | set add_lockup_latch false |
| 101 | set chain_count 1 |
| 102 | set scanin_port_list {} |
| 103 | set scanout_port_list {} |
| 104 | set scanenable_port global_shift_enable |
| 105 | set has_test_stub 1 |
| 106 | set scanenable_pin test_stub_no_bist/se |
| 107 | set long_chain_so_0_net long_chain_so_0 |
| 108 | set short_chain_so_0_net short_chain_so_0 |
| 109 | set so_0_net so_0 |
| 110 | set insert_extra_lockup_latch 0 |
| 111 | set extra_lockup_latch_clk_list {} |