| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: gkt_ipd_dp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module gkt_ipd_dp ( |
| 36 | tcu_scan_en, |
| 37 | tcu_se_scancollar_out, |
| 38 | l2clk, |
| 39 | scan_in, |
| 40 | tcu_pce_ov, |
| 41 | core_isolate, |
| 42 | spc_aclk, |
| 43 | spc_bclk, |
| 44 | scan_out, |
| 45 | slow_cmp_sync_en, |
| 46 | const_cpuid, |
| 47 | ncu_spc_pm, |
| 48 | ncu_spc_ba01, |
| 49 | ncu_spc_ba23, |
| 50 | ncu_spc_ba45, |
| 51 | ncu_spc_ba67, |
| 52 | ncu_pm_ff, |
| 53 | ncu_ba01_ff, |
| 54 | ncu_ba23_ff, |
| 55 | ncu_ba45_ff, |
| 56 | ncu_ba67_ff, |
| 57 | spc_pcx_data_pa, |
| 58 | spc_pcx_req_pq, |
| 59 | spc_pcx_atm_pq, |
| 60 | l15_spc_data1, |
| 61 | cpx_spc_data_cx_rep0, |
| 62 | l15_spc_cpkt, |
| 63 | l15_mmu_valid, |
| 64 | l15_spu_valid, |
| 65 | ipd_optype, |
| 66 | pcx_spc_grant_px_buf, |
| 67 | cpx_spc_data_cx, |
| 68 | pcx_spc_grant_px, |
| 69 | ifu_l15_addr, |
| 70 | mmu_l15_addr, |
| 71 | lsu_l15_addr, |
| 72 | spu_l15_addr, |
| 73 | ifu_l15_valid, |
| 74 | mmu_l15_valid, |
| 75 | spu_l15_valid, |
| 76 | ifu_l15_cpkt, |
| 77 | mmu_l15_cpkt, |
| 78 | lsu_l15_cpkt, |
| 79 | spu_l15_cpkt, |
| 80 | lsu_l15_data, |
| 81 | spu_l15_data, |
| 82 | ipc_v0_ifu_new, |
| 83 | ipc_v0_ifu_shft, |
| 84 | ipc_v0_ifu_hold, |
| 85 | ipc_v1_ifu_new, |
| 86 | ipc_v1_ifu_hold, |
| 87 | ipc_v0_mmu_new, |
| 88 | ipc_v0_mmu_shft, |
| 89 | ipc_v0_mmu_hold, |
| 90 | ipc_v1_mmu_new, |
| 91 | ipc_v1_mmu_hold, |
| 92 | ipc_v0_lsu_new, |
| 93 | ipc_v0_lsu_shft, |
| 94 | ipc_v0_lsu_hold, |
| 95 | ipc_v1_lsu_new, |
| 96 | ipc_v1_lsu_hold, |
| 97 | ipc_v0_spu_new, |
| 98 | ipc_v0_spu_shft, |
| 99 | ipc_v0_spu_hold, |
| 100 | ipc_v1_spu_new, |
| 101 | ipc_v1_spu_hold, |
| 102 | ipc_sel_ndrop_ifu_l1, |
| 103 | ipc_sel_ndrop_mmu_l1, |
| 104 | ipc_sel_ndrop_lsu_l1, |
| 105 | ipc_sel_ndrop_spu_l1, |
| 106 | ipc_sel_drop_ifu_l1, |
| 107 | ipc_sel_drop_mmu_l1, |
| 108 | ipc_sel_drop_lsu_l1, |
| 109 | ipc_sel_drop_spu_l1, |
| 110 | ipc_pq_clken, |
| 111 | ipc_dropreg_wen, |
| 112 | ipc_op_req_li, |
| 113 | ipc_atm_req_li, |
| 114 | ncu_spc_l2_idx_hash_en); |
| 115 | wire stop; |
| 116 | wire cpuid_reg_scanin; |
| 117 | wire cpuid_reg_scanout; |
| 118 | wire [2:0] cpuid; |
| 119 | wire ncu_spc_l2_idx_hash_en_buf; |
| 120 | wire ncu_spc_pm_buf; |
| 121 | wire ncu_spc_ba01_buf; |
| 122 | wire ncu_spc_ba23_buf; |
| 123 | wire ncu_spc_ba45_buf; |
| 124 | wire ncu_spc_ba67_buf; |
| 125 | wire i_ncu_reg_scanin; |
| 126 | wire i_ncu_reg_scanout; |
| 127 | wire slow_cmp_sync_en_ff; |
| 128 | wire idx_hash_en_ff; |
| 129 | wire se; |
| 130 | wire pce_ov; |
| 131 | wire siclk; |
| 132 | wire soclk; |
| 133 | wire [39:0] mmu_l15_addr1; |
| 134 | wire [25:0] lsu_l15_cpkt1; |
| 135 | wire [25:0] spu_l15_cpkt1; |
| 136 | wire [39:0] spu_l15_addr1; |
| 137 | wire [25:0] mmu_l15_cpkt1; |
| 138 | wire [25:0] ifu_l15_cpkt1; |
| 139 | wire i_cpx_data1lo_reg_scanin; |
| 140 | wire i_cpx_data1lo_reg_scanout; |
| 141 | wire [145:0] l15_spc_data; |
| 142 | wire i_cpx_data1hi_reg_scanin; |
| 143 | wire i_cpx_data1hi_reg_scanout; |
| 144 | wire i_cpx_cpkt_reg_scanin; |
| 145 | wire i_cpx_cpkt_reg_scanout; |
| 146 | wire [18:0] cpx_cpkt; |
| 147 | wire i_req_li_reg_scanin; |
| 148 | wire i_req_li_reg_scanout; |
| 149 | wire [8:0] op_req; |
| 150 | wire [8:0] atm_req; |
| 151 | wire core_isolate_; |
| 152 | wire [8:0] pcx_req_pq_; |
| 153 | wire [8:0] pcx_atm_pq_; |
| 154 | wire i_ifu_addr_v1_muxreg_scanin; |
| 155 | wire i_ifu_addr_v1_muxreg_scanout; |
| 156 | wire [25:0] v1_ifu_cpkt; |
| 157 | wire [39:0] v1_ifu_addr; |
| 158 | wire i_ifu_addr_v0_muxreg_scanin; |
| 159 | wire i_ifu_addr_v0_muxreg_scanout; |
| 160 | wire [25:0] v0_ifu_cpkt; |
| 161 | wire [39:0] v0_ifu_addr; |
| 162 | wire i_mmu_addr_v1_muxreg_scanin; |
| 163 | wire i_mmu_addr_v1_muxreg_scanout; |
| 164 | wire [25:0] v1_mmu_cpkt; |
| 165 | wire [39:0] v1_mmu_addr; |
| 166 | wire i_mmu_addr_v0_muxreg_scanin; |
| 167 | wire i_mmu_addr_v0_muxreg_scanout; |
| 168 | wire [25:0] v0_mmu_cpkt; |
| 169 | wire [39:0] v0_mmu_addr; |
| 170 | wire i_lsu_addr_v1_muxreg_scanin; |
| 171 | wire i_lsu_addr_v1_muxreg_scanout; |
| 172 | wire [25:0] v1_lsu_cpkt; |
| 173 | wire [39:0] v1_lsu_addr; |
| 174 | wire i_lsu_addr_v0_muxreg_scanin; |
| 175 | wire i_lsu_addr_v0_muxreg_scanout; |
| 176 | wire [25:0] v0_lsu_cpkt; |
| 177 | wire [39:0] v0_lsu_addr; |
| 178 | wire i_lsu_data_v1_muxreg_scanin; |
| 179 | wire i_lsu_data_v1_muxreg_scanout; |
| 180 | wire [63:0] v1_lsu_data; |
| 181 | wire i_lsu_data_v0_muxreg_scanin; |
| 182 | wire i_lsu_data_v0_muxreg_scanout; |
| 183 | wire [63:0] v0_lsu_data; |
| 184 | wire i_spu_addr_v1_muxreg_scanin; |
| 185 | wire i_spu_addr_v1_muxreg_scanout; |
| 186 | wire [25:0] v1_spu_cpkt; |
| 187 | wire [39:0] v1_spu_addr; |
| 188 | wire i_spu_addr_v0_muxreg_scanin; |
| 189 | wire i_spu_addr_v0_muxreg_scanout; |
| 190 | wire [25:0] v0_spu_cpkt; |
| 191 | wire [39:0] v0_spu_addr; |
| 192 | wire i_spu_data_v1_muxreg_scanin; |
| 193 | wire i_spu_data_v1_muxreg_scanout; |
| 194 | wire [63:0] v1_spu_data; |
| 195 | wire i_spu_data_v0_muxreg_scanin; |
| 196 | wire i_spu_data_v0_muxreg_scanout; |
| 197 | wire [63:0] v0_spu_data; |
| 198 | wire i_ifu_addr_drop_reg_scanin; |
| 199 | wire i_ifu_addr_drop_reg_scanout; |
| 200 | wire [25:0] ipd_cpkt_l1; |
| 201 | wire [39:0] ipd_addr_l1; |
| 202 | wire [25:0] drop_ifu_cpkt; |
| 203 | wire [39:0] drop_ifu_addr; |
| 204 | wire i_mmu_addr_drop_reg_scanin; |
| 205 | wire i_mmu_addr_drop_reg_scanout; |
| 206 | wire [25:0] drop_mmu_cpkt; |
| 207 | wire [39:0] drop_mmu_addr; |
| 208 | wire i_lsu_addr_drop_reg_scanin; |
| 209 | wire i_lsu_addr_drop_reg_scanout; |
| 210 | wire [25:0] drop_lsu_cpkt; |
| 211 | wire [39:0] drop_lsu_addr; |
| 212 | wire i_spu_addr_drop_reg_scanin; |
| 213 | wire i_spu_addr_drop_reg_scanout; |
| 214 | wire [25:0] drop_spu_cpkt; |
| 215 | wire [39:0] drop_spu_addr; |
| 216 | wire i_lsu_data_drop_reg_scanin; |
| 217 | wire i_lsu_data_drop_reg_scanout; |
| 218 | wire [63:0] ipd_data_l1; |
| 219 | wire [63:0] drop_lsu_data; |
| 220 | wire i_spu_data_drop_reg_scanin; |
| 221 | wire i_spu_data_drop_reg_scanout; |
| 222 | wire [63:0] drop_spu_data; |
| 223 | wire [39:0] ipd_addr_l1_prebuf; |
| 224 | wire i_hash_en_ff2_scanin; |
| 225 | wire i_hash_en_ff2_scanout; |
| 226 | wire idx_hash_en_ff2; |
| 227 | wire idx_hash_en_; |
| 228 | wire enable_hash; |
| 229 | wire [17:11] ipd_addr_hashed_l1; |
| 230 | wire [17:11] ipd_addr_out_l1; |
| 231 | wire i_pcx_addr_pa_reg_scanin; |
| 232 | wire i_pcx_addr_pa_reg_scanout; |
| 233 | wire [25:0] pcx_cpkt_pa; |
| 234 | wire [39:0] pcx_addr_pa; |
| 235 | wire i_pcx_data_pa_reg_scanin; |
| 236 | wire i_pcx_data_pa_reg_scanout; |
| 237 | wire [63:0] pcx_data_pa; |
| 238 | |
| 239 | |
| 240 | // globals |
| 241 | input tcu_scan_en ; |
| 242 | input tcu_se_scancollar_out; |
| 243 | input l2clk; |
| 244 | input scan_in; |
| 245 | input tcu_pce_ov; // scan signals |
| 246 | input core_isolate; |
| 247 | input spc_aclk; |
| 248 | input spc_bclk; |
| 249 | output scan_out; |
| 250 | |
| 251 | input slow_cmp_sync_en; |
| 252 | |
| 253 | input [2:0] const_cpuid; |
| 254 | |
| 255 | input ncu_spc_pm; |
| 256 | input ncu_spc_ba01; |
| 257 | input ncu_spc_ba23; |
| 258 | input ncu_spc_ba45; |
| 259 | input ncu_spc_ba67; |
| 260 | |
| 261 | output ncu_pm_ff; |
| 262 | output ncu_ba01_ff; |
| 263 | output ncu_ba23_ff; |
| 264 | output ncu_ba45_ff; |
| 265 | output ncu_ba67_ff; |
| 266 | |
| 267 | output [129:0] spc_pcx_data_pa; |
| 268 | output [8:0] spc_pcx_req_pq; |
| 269 | output [8:0] spc_pcx_atm_pq; |
| 270 | |
| 271 | |
| 272 | |
| 273 | output [127:0] l15_spc_data1; |
| 274 | output [145:0] cpx_spc_data_cx_rep0; |
| 275 | |
| 276 | output [17:0] l15_spc_cpkt; |
| 277 | output l15_mmu_valid; |
| 278 | output l15_spu_valid; |
| 279 | |
| 280 | output [8:0] ipd_optype; |
| 281 | output [8:0] pcx_spc_grant_px_buf; |
| 282 | |
| 283 | |
| 284 | input [145:0] cpx_spc_data_cx; |
| 285 | input [8:0] pcx_spc_grant_px; |
| 286 | |
| 287 | |
| 288 | input [39:0] ifu_l15_addr; |
| 289 | input [39:4] mmu_l15_addr; |
| 290 | input [39:0] lsu_l15_addr; |
| 291 | input [38:3] spu_l15_addr; |
| 292 | |
| 293 | input ifu_l15_valid; |
| 294 | input mmu_l15_valid; |
| 295 | input spu_l15_valid; |
| 296 | |
| 297 | |
| 298 | input [7:0] ifu_l15_cpkt; |
| 299 | input [4:0] mmu_l15_cpkt; |
| 300 | input [25:0] lsu_l15_cpkt; |
| 301 | input [12:0] spu_l15_cpkt; |
| 302 | |
| 303 | |
| 304 | input [63:0] lsu_l15_data; |
| 305 | input [63:0] spu_l15_data; |
| 306 | |
| 307 | |
| 308 | input ipc_v0_ifu_new; |
| 309 | input ipc_v0_ifu_shft; |
| 310 | input ipc_v0_ifu_hold; |
| 311 | |
| 312 | input ipc_v1_ifu_new; |
| 313 | input ipc_v1_ifu_hold; |
| 314 | |
| 315 | input ipc_v0_mmu_new; |
| 316 | input ipc_v0_mmu_shft; |
| 317 | input ipc_v0_mmu_hold; |
| 318 | |
| 319 | input ipc_v1_mmu_new; |
| 320 | input ipc_v1_mmu_hold; |
| 321 | |
| 322 | input ipc_v0_lsu_new; |
| 323 | input ipc_v0_lsu_shft; |
| 324 | input ipc_v0_lsu_hold; |
| 325 | |
| 326 | input ipc_v1_lsu_new; |
| 327 | input ipc_v1_lsu_hold; |
| 328 | |
| 329 | |
| 330 | input ipc_v0_spu_new; |
| 331 | input ipc_v0_spu_shft; |
| 332 | input ipc_v0_spu_hold; |
| 333 | |
| 334 | input ipc_v1_spu_new; |
| 335 | input ipc_v1_spu_hold; |
| 336 | |
| 337 | |
| 338 | input ipc_sel_ndrop_ifu_l1; |
| 339 | input ipc_sel_ndrop_mmu_l1; |
| 340 | input ipc_sel_ndrop_lsu_l1; |
| 341 | input ipc_sel_ndrop_spu_l1; |
| 342 | |
| 343 | input ipc_sel_drop_ifu_l1; |
| 344 | input ipc_sel_drop_mmu_l1; |
| 345 | input ipc_sel_drop_lsu_l1; |
| 346 | input ipc_sel_drop_spu_l1; |
| 347 | |
| 348 | input ipc_pq_clken; |
| 349 | |
| 350 | |
| 351 | input [3:0] ipc_dropreg_wen; |
| 352 | |
| 353 | |
| 354 | input [8:0] ipc_op_req_li; |
| 355 | input [8:0] ipc_atm_req_li; |
| 356 | |
| 357 | |
| 358 | |
| 359 | input ncu_spc_l2_idx_hash_en; |
| 360 | |
| 361 | |
| 362 | // scan renames |
| 363 | assign stop = 1'b0; |
| 364 | // end scan |
| 365 | |
| 366 | // flop cpuid |
| 367 | |
| 368 | gkt_ipd_dp_msff_macro__stack_66c__width_3 cpuid_reg |
| 369 | ( |
| 370 | .scan_in(cpuid_reg_scanin), |
| 371 | .scan_out(cpuid_reg_scanout), |
| 372 | .clk( l2clk ), |
| 373 | .en (1'b1), |
| 374 | .din ({const_cpuid[2:0]}), |
| 375 | .dout (cpuid[2:0]), |
| 376 | .se(se), |
| 377 | .siclk(siclk), |
| 378 | .soclk(soclk), |
| 379 | .pce_ov(pce_ov), |
| 380 | .stop(stop) |
| 381 | ); |
| 382 | |
| 383 | // ISOLATION BUFFER for grant signals |
| 384 | gkt_ipd_dp_buff_macro__dbuff_16x__rep_1__stack_none__width_9 isolate_grant_buf |
| 385 | ( |
| 386 | .din({pcx_spc_grant_px[8:0]}), |
| 387 | .dout({pcx_spc_grant_px_buf[8:0]}) |
| 388 | ); |
| 389 | |
| 390 | //flop ncu signals |
| 391 | // They are launched in iol2clk domain, and captured in cmp domain using sync enable |
| 392 | // Also since these are primary inputs to sparc core, se port is connected to scancollar_out. |
| 393 | // This stops the flops from capturing state during logic bist. |
| 394 | |
| 395 | // ISOLATION BUFFER |
| 396 | gkt_ipd_dp_buff_macro__dbuff_16x__rep_1__stack_none__width_6 isolate_ncu_buf |
| 397 | ( |
| 398 | .din({ncu_spc_l2_idx_hash_en,ncu_spc_pm,ncu_spc_ba01,ncu_spc_ba23,ncu_spc_ba45,ncu_spc_ba67}), |
| 399 | .dout({ncu_spc_l2_idx_hash_en_buf,ncu_spc_pm_buf,ncu_spc_ba01_buf,ncu_spc_ba23_buf,ncu_spc_ba45_buf,ncu_spc_ba67_buf}) |
| 400 | |
| 401 | ); |
| 402 | |
| 403 | gkt_ipd_dp_msff_macro__stack_64c__width_6 i_ncu_reg |
| 404 | ( |
| 405 | .scan_in(i_ncu_reg_scanin), |
| 406 | .scan_out(i_ncu_reg_scanout), |
| 407 | .se(tcu_se_scancollar_out), |
| 408 | .clk (l2clk), |
| 409 | .en (slow_cmp_sync_en_ff), |
| 410 | .din({ncu_spc_l2_idx_hash_en_buf,ncu_spc_pm_buf,ncu_spc_ba01_buf,ncu_spc_ba23_buf,ncu_spc_ba45_buf,ncu_spc_ba67_buf}), |
| 411 | .dout({idx_hash_en_ff, ncu_pm_ff, ncu_ba01_ff, ncu_ba23_ff, ncu_ba45_ff, ncu_ba67_ff}), |
| 412 | .siclk(siclk), |
| 413 | .soclk(soclk), |
| 414 | .pce_ov(pce_ov), |
| 415 | .stop(stop) |
| 416 | ); |
| 417 | |
| 418 | gkt_ipd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0 ( |
| 419 | .din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}), |
| 420 | .dout({se,pce_ov,siclk,soclk}) |
| 421 | ); |
| 422 | |
| 423 | |
| 424 | assign mmu_l15_addr1[39:0] = {mmu_l15_addr[39:4],4'b0}; |
| 425 | |
| 426 | |
| 427 | // form the cpkts |
| 428 | assign lsu_l15_cpkt1[25:0] = lsu_l15_cpkt[25:0]; |
| 429 | |
| 430 | |
| 431 | // actual spu pkt format: |
| 432 | //assign spu_l15_cpkt[25] = spu_l15_valid; |
| 433 | //assign spu_l15_cpkt[24:21] = 4'b0010; //rqtyp |
| 434 | // assign spu_l15_cpkt[20] = req_type |
| 435 | //assign spu_l15_cpkt[19] = 1'b1; //nc |
| 436 | //assign spu_l15_cpkt[18:16] = cpuid[2:0]; //cpuid |
| 437 | //assign spu_l15_cpkt[15:13] = tid |
| 438 | //assign spu_l15_cpkt[12:11] = 2'b00; //inv,pf,bis |
| 439 | //assign spu_l15_cpkt[10] = maid |
| 440 | //assign spu_l15_cpkt[9:8] = 2'b00 |
| 441 | //assign spu_l15_cpkt[7:0] = byte valids //size |
| 442 | |
| 443 | assign spu_l15_cpkt1[25:0] = {spu_l15_valid, 4'b0010, spu_l15_cpkt[4], 1'b1, cpuid[2:0], spu_l15_cpkt[2:0], 2'b0, spu_l15_cpkt[3], 2'b0, spu_l15_cpkt[12:5]}; |
| 444 | |
| 445 | assign spu_l15_addr1[39:0] = {1'b0, spu_l15_addr[38:3], 3'b000}; |
| 446 | |
| 447 | // actual mmu pkt format: |
| 448 | //assign mmu_l15_cpkt[25] = mmu_l15_valid; |
| 449 | //assign mmu_l15_cpkt[24:20] = 5'b01000; //rqtyp |
| 450 | //assign mmu_l15_cpkt[19] = 1'b1; //nc |
| 451 | //assign mmu_l15_cpkt[18:16] = cpuid[2:0]; //cpuid |
| 452 | //assign mmu_l15_cpkt[15:13] = tid |
| 453 | //assign mmu_l15_cpkt[12:10] = 3'b000; //inv,pf,bis |
| 454 | //assign mmu_l15_cpkt[9:7] = mmuid |
| 455 | //assign mmu_l15_cpkt[7:0] = 8'b0; //size |
| 456 | |
| 457 | assign mmu_l15_cpkt1[25:0] = {mmu_l15_valid,5'b01000,1'b1,cpuid[2:0],mmu_l15_cpkt[2:0],3'b0,mmu_l15_cpkt[4:3],8'b0}; |
| 458 | |
| 459 | // Actual ifu_l15_cpkt has following fields |
| 460 | // ifu_l15_cpkt[25] = ifu_l15_valid |
| 461 | // ifu_l15_cpkt[24:20] = ifu_l15_req_type[4:0] = 5'b10000 |
| 462 | // ifu_l15_cpkt[19] = ifu_l15_nc |
| 463 | // ifu_l15_cpkt[18:16] = ifu_l15_cpuid[2:0] |
| 464 | // ifu_l15_cpkt[15:13] = ifu_l15_tid[2:0] |
| 465 | // ifu_l15_cpkt[12] = ifu_l15_inv |
| 466 | // ifu_l15_cpkt[11] = ifu_l15_pf = 0 |
| 467 | // ifu_l15_cpkt[10:8] = ifu_l15_rway[2:0] |
| 468 | // ifu_l15_cpkt[7:0] = ifu_l15_size[7:0] = 0 |
| 469 | |
| 470 | assign ifu_l15_cpkt1[25:0] = {ifu_l15_valid,5'b10000,ifu_l15_cpkt[7],cpuid[2:0], |
| 471 | ifu_l15_cpkt[2:0],ifu_l15_cpkt[6],1'b0,ifu_l15_cpkt[5:3],8'b0}; |
| 472 | |
| 473 | |
| 474 | /////////////////////////////////////////////////////////////////// |
| 475 | // PIPE the CPX data and cpkt to SPARC core |
| 476 | // Also since these are primary inputs to sparc core, se port is connected to scancollar_out. |
| 477 | // This stops the flops from capturing state during logic bist. |
| 478 | /////////////////////////////////////////////////////////////////// |
| 479 | // ISOLATION BUFFER |
| 480 | gkt_ipd_dp_buff_macro__dbuff_48x__rep_1__stack_64c__width_64 gkt_lsu_datalo_rep0 ( |
| 481 | .din (cpx_spc_data_cx[63:0]), |
| 482 | .dout(cpx_spc_data_cx_rep0[63:0]) |
| 483 | ); |
| 484 | |
| 485 | gkt_ipd_dp_msff_macro__stack_64c__width_64 i_cpx_data1lo_reg |
| 486 | ( |
| 487 | .scan_in(i_cpx_data1lo_reg_scanin), |
| 488 | .scan_out(i_cpx_data1lo_reg_scanout), |
| 489 | .se(tcu_se_scancollar_out), |
| 490 | .clk (l2clk), |
| 491 | .en (1'b1), |
| 492 | .din(cpx_spc_data_cx_rep0[63:0]), |
| 493 | .dout(l15_spc_data[63:0]), |
| 494 | .siclk(siclk), |
| 495 | .soclk(soclk), |
| 496 | .pce_ov(pce_ov), |
| 497 | .stop(stop) |
| 498 | ); |
| 499 | |
| 500 | gkt_ipd_dp_buff_macro__dbuff_48x__rep_1__stack_64c__width_64 i_buf_data1lo_spc ( |
| 501 | .din (l15_spc_data[63:0]), |
| 502 | .dout (l15_spc_data1[63:0]) |
| 503 | ); |
| 504 | |
| 505 | //ISOLATION BUFFER |
| 506 | gkt_ipd_dp_buff_macro__dbuff_48x__rep_1__stack_64c__width_64 gkt_lsu_datahi_rep0 ( |
| 507 | .din (cpx_spc_data_cx[127:64]), |
| 508 | .dout(cpx_spc_data_cx_rep0[127:64]) |
| 509 | ); |
| 510 | |
| 511 | gkt_ipd_dp_msff_macro__stack_64c__width_64 i_cpx_data1hi_reg |
| 512 | ( |
| 513 | .scan_in(i_cpx_data1hi_reg_scanin), |
| 514 | .scan_out(i_cpx_data1hi_reg_scanout), |
| 515 | .se(tcu_se_scancollar_out), |
| 516 | .clk (l2clk), |
| 517 | .en (1'b1), |
| 518 | .din(cpx_spc_data_cx_rep0[127:64]), |
| 519 | .dout(l15_spc_data[127:64]), |
| 520 | .siclk(siclk), |
| 521 | .soclk(soclk), |
| 522 | .pce_ov(pce_ov), |
| 523 | .stop(stop) |
| 524 | ); |
| 525 | |
| 526 | gkt_ipd_dp_buff_macro__dbuff_48x__rep_1__stack_64c__width_64 i_buf_data1hi_spc ( |
| 527 | .din (l15_spc_data[127:64]), |
| 528 | .dout (l15_spc_data1[127:64]) |
| 529 | ); |
| 530 | |
| 531 | //ISOLATION BUFFER |
| 532 | gkt_ipd_dp_buff_macro__dbuff_48x__rep_1__stack_none__width_18 gkt_lsu_cpkt_rep0 ( |
| 533 | .din (cpx_spc_data_cx[145:128]), |
| 534 | .dout(cpx_spc_data_cx_rep0[145:128]) |
| 535 | ); |
| 536 | |
| 537 | gkt_ipd_dp_msff_macro__stack_64c__width_18 i_cpx_cpkt_reg |
| 538 | ( |
| 539 | .scan_in(i_cpx_cpkt_reg_scanin), |
| 540 | .scan_out(i_cpx_cpkt_reg_scanout), |
| 541 | .se(tcu_se_scancollar_out), |
| 542 | .clk (l2clk), |
| 543 | .en (1'b1), |
| 544 | .din({cpx_spc_data_cx_rep0[145:128]}), |
| 545 | .dout({l15_spc_data[145:128]}), |
| 546 | .siclk(siclk), |
| 547 | .soclk(soclk), |
| 548 | .pce_ov(pce_ov), |
| 549 | .stop(stop) |
| 550 | ); |
| 551 | |
| 552 | assign cpx_cpkt[18:0] = {l15_spc_data[145:140],1'b0,l15_spc_data[139:128]}; |
| 553 | |
| 554 | gkt_ipd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_20 i_buf_cpkt_spc ( |
| 555 | .din ({cpx_cpkt[18],cpx_cpkt[18:0]}), |
| 556 | .dout ({l15_spu_valid,l15_mmu_valid,l15_spc_cpkt[17:0]}) |
| 557 | ); |
| 558 | |
| 559 | /////////////////////////////////////////////////////////////////// |
| 560 | // Generate request and atomic signals going to PCX |
| 561 | /////////////////////////////////////////////////////////////////// |
| 562 | //assign op_req[8:0] = ({9{req_dropped_lat}} & req_repeat_drop_l1[8:0]) | |
| 563 | // ({9{req_dropped_lat_}} & req_repeat_ndrop_l1[8:0]) | |
| 564 | // (req_nrepeat_drop_l1[8:0]) | |
| 565 | // (req_nrepeat_ndrop_l1[8:0]); |
| 566 | //assign spc_pcx_req_pq[8:0] = op_req[8:0] & {9{~core_isolate}}; |
| 567 | |
| 568 | // flop op_req_li and atm_req_li |
| 569 | |
| 570 | |
| 571 | gkt_ipd_dp_msff_macro__dmsff_8x__stack_64c__width_19 i_req_li_reg |
| 572 | ( |
| 573 | .scan_in(i_req_li_reg_scanin), |
| 574 | .scan_out(i_req_li_reg_scanout), |
| 575 | .clk (l2clk), |
| 576 | .en (1'b1), |
| 577 | .din({slow_cmp_sync_en,ipc_op_req_li[8:0],ipc_atm_req_li[8:0]}), |
| 578 | .dout({slow_cmp_sync_en_ff, op_req[8:0], atm_req[8:0]}), |
| 579 | .se(se), |
| 580 | .siclk(siclk), |
| 581 | .soclk(soclk), |
| 582 | .pce_ov(pce_ov), |
| 583 | .stop(stop) |
| 584 | ); |
| 585 | |
| 586 | |
| 587 | gkt_ipd_dp_inv_macro__dinv_8x__stack_64c__width_1 i_clk_stop_inv ( |
| 588 | .din (core_isolate), |
| 589 | .dout (core_isolate_) |
| 590 | ); |
| 591 | |
| 592 | gkt_ipd_dp_nand_macro__dnand_16x__ports_2__stack_64c__width_9 i_pcx_req_nand_w9 |
| 593 | ( |
| 594 | .din0(op_req[8:0]), |
| 595 | .din1({9{core_isolate_}}), |
| 596 | .dout(pcx_req_pq_[8:0]) |
| 597 | ); |
| 598 | |
| 599 | gkt_ipd_dp_inv_macro__dinv_48x__stack_64c__width_9 i_pcx_req_inv_w9 |
| 600 | ( |
| 601 | .din({pcx_req_pq_[8:0]}), |
| 602 | .dout({spc_pcx_req_pq[8:0]}) |
| 603 | ); |
| 604 | |
| 605 | |
| 606 | //assign atm_req[8:0] = {9{~ipc_dropreg_valid[2]}} & ipc_atm_l1[8:0]; |
| 607 | //assign spc_pcx_atm_pq[8:0] = atm_req[8:0] & {9{~core_isolate}}; |
| 608 | |
| 609 | gkt_ipd_dp_nand_macro__dnand_16x__ports_2__stack_64c__width_9 i_atm_nand ( |
| 610 | .din0 (atm_req[8:0]), |
| 611 | .din1 ({9{core_isolate_}}), |
| 612 | .dout (pcx_atm_pq_[8:0]) |
| 613 | ); |
| 614 | |
| 615 | gkt_ipd_dp_inv_macro__dinv_48x__stack_64c__width_9 i_pcx_atm_inv_w9 |
| 616 | ( |
| 617 | .din({pcx_atm_pq_[8:0]}), |
| 618 | .dout({spc_pcx_atm_pq[8:0]}) |
| 619 | ); |
| 620 | |
| 621 | |
| 622 | // assertion, atomic request cannot be asserted without valid request |
| 623 | /* 0in assert -var (~(|(spc_pcx_atm_pq[8:0] & ~(spc_pcx_req_pq[8:0])))) |
| 624 | -message "l15_ipc_ctl: spc_pcx_atm_pq asserted without spc_pcx_req_pq" */ |
| 625 | |
| 626 | |
| 627 | |
| 628 | /////////////////////////////////////////////////////////////////// |
| 629 | // Latch ifu pkt in 2-entry FIFO |
| 630 | /////////////////////////////////////////////////////////////////// |
| 631 | gkt_ipd_dp_msff_macro__mux_aonpe__ports_2__stack_66c__width_66 i_ifu_addr_v1_muxreg |
| 632 | ( |
| 633 | .scan_in(i_ifu_addr_v1_muxreg_scanin), |
| 634 | .scan_out(i_ifu_addr_v1_muxreg_scanout), |
| 635 | .clk (l2clk), |
| 636 | .en (1'b1), |
| 637 | .din0({ifu_l15_cpkt1[25:0],ifu_l15_addr[39:0]}), |
| 638 | .din1({v1_ifu_cpkt[25:0],v1_ifu_addr[39:0]}), |
| 639 | .sel0(ipc_v1_ifu_new), |
| 640 | .sel1(ipc_v1_ifu_hold), |
| 641 | .dout({v1_ifu_cpkt[25:0],v1_ifu_addr[39:0]}), |
| 642 | .se(se), |
| 643 | .siclk(siclk), |
| 644 | .soclk(soclk), |
| 645 | .pce_ov(pce_ov), |
| 646 | .stop(stop) |
| 647 | ); |
| 648 | |
| 649 | gkt_ipd_dp_msff_macro__mux_aonpe__ports_3__stack_66c__width_66 i_ifu_addr_v0_muxreg |
| 650 | ( |
| 651 | .scan_in(i_ifu_addr_v0_muxreg_scanin), |
| 652 | .scan_out(i_ifu_addr_v0_muxreg_scanout), |
| 653 | .clk (l2clk), |
| 654 | .en (1'b1), |
| 655 | .din0({ifu_l15_cpkt1[25:0],ifu_l15_addr[39:0]}), |
| 656 | .din1({v1_ifu_cpkt[25:0],v1_ifu_addr[39:0]}), |
| 657 | .din2({v0_ifu_cpkt[25:0],v0_ifu_addr[39:0]}), |
| 658 | .sel0(ipc_v0_ifu_new), |
| 659 | .sel1(ipc_v0_ifu_shft), |
| 660 | .sel2(ipc_v0_ifu_hold), |
| 661 | .dout({v0_ifu_cpkt[25:0],v0_ifu_addr[39:0]}), |
| 662 | .se(se), |
| 663 | .siclk(siclk), |
| 664 | .soclk(soclk), |
| 665 | .pce_ov(pce_ov), |
| 666 | .stop(stop) |
| 667 | ); |
| 668 | |
| 669 | |
| 670 | /////////////////////////////////////////////////////////////////// |
| 671 | // Latch mmu pkt in 2-entry FIFO |
| 672 | /////////////////////////////////////////////////////////////////// |
| 673 | gkt_ipd_dp_msff_macro__mux_aonpe__ports_2__stack_66c__width_66 i_mmu_addr_v1_muxreg |
| 674 | ( |
| 675 | .scan_in(i_mmu_addr_v1_muxreg_scanin), |
| 676 | .scan_out(i_mmu_addr_v1_muxreg_scanout), |
| 677 | .clk (l2clk), |
| 678 | .en (1'b1), |
| 679 | .din0({mmu_l15_cpkt1[25:0],mmu_l15_addr1[39:0]}), |
| 680 | .din1({v1_mmu_cpkt[25:0],v1_mmu_addr[39:0]}), |
| 681 | .sel0(ipc_v1_mmu_new), |
| 682 | .sel1(ipc_v1_mmu_hold), |
| 683 | .dout({v1_mmu_cpkt[25:0],v1_mmu_addr[39:0]}), |
| 684 | .se(se), |
| 685 | .siclk(siclk), |
| 686 | .soclk(soclk), |
| 687 | .pce_ov(pce_ov), |
| 688 | .stop(stop) |
| 689 | ); |
| 690 | |
| 691 | gkt_ipd_dp_msff_macro__mux_aonpe__ports_3__stack_66c__width_66 i_mmu_addr_v0_muxreg |
| 692 | ( |
| 693 | .scan_in(i_mmu_addr_v0_muxreg_scanin), |
| 694 | .scan_out(i_mmu_addr_v0_muxreg_scanout), |
| 695 | .clk (l2clk), |
| 696 | .en (1'b1), |
| 697 | .din0({mmu_l15_cpkt1[25:0],mmu_l15_addr1[39:0]}), |
| 698 | .din1({v1_mmu_cpkt[25:0],v1_mmu_addr[39:0]}), |
| 699 | .din2({v0_mmu_cpkt[25:0],v0_mmu_addr[39:0]}), |
| 700 | .sel0(ipc_v0_mmu_new), |
| 701 | .sel1(ipc_v0_mmu_shft), |
| 702 | .sel2(ipc_v0_mmu_hold), |
| 703 | .dout({v0_mmu_cpkt[25:0],v0_mmu_addr[39:0]}), |
| 704 | .se(se), |
| 705 | .siclk(siclk), |
| 706 | .soclk(soclk), |
| 707 | .pce_ov(pce_ov), |
| 708 | .stop(stop) |
| 709 | ); |
| 710 | |
| 711 | /////////////////////////////////////////////////////////////////// |
| 712 | // Latch lsu pkt in 2-entry FIFO |
| 713 | /////////////////////////////////////////////////////////////////// |
| 714 | gkt_ipd_dp_msff_macro__mux_aonpe__ports_2__stack_66c__width_66 i_lsu_addr_v1_muxreg |
| 715 | ( |
| 716 | .scan_in(i_lsu_addr_v1_muxreg_scanin), |
| 717 | .scan_out(i_lsu_addr_v1_muxreg_scanout), |
| 718 | .clk (l2clk), |
| 719 | .en (1'b1), |
| 720 | .din0({lsu_l15_cpkt1[25:0],lsu_l15_addr[39:0]}), |
| 721 | .din1({v1_lsu_cpkt[25:0],v1_lsu_addr[39:0]}), |
| 722 | .sel0(ipc_v1_lsu_new), |
| 723 | .sel1(ipc_v1_lsu_hold), |
| 724 | .dout({v1_lsu_cpkt[25:0],v1_lsu_addr[39:0]}), |
| 725 | .se(se), |
| 726 | .siclk(siclk), |
| 727 | .soclk(soclk), |
| 728 | .pce_ov(pce_ov), |
| 729 | .stop(stop) |
| 730 | ); |
| 731 | |
| 732 | gkt_ipd_dp_msff_macro__mux_aonpe__ports_3__stack_66c__width_66 i_lsu_addr_v0_muxreg |
| 733 | ( |
| 734 | .scan_in(i_lsu_addr_v0_muxreg_scanin), |
| 735 | .scan_out(i_lsu_addr_v0_muxreg_scanout), |
| 736 | .clk (l2clk), |
| 737 | .en (1'b1), |
| 738 | .din0({lsu_l15_cpkt1[25:0],lsu_l15_addr[39:0]}), |
| 739 | .din1({v1_lsu_cpkt[25:0],v1_lsu_addr[39:0]}), |
| 740 | .din2({v0_lsu_cpkt[25:0],v0_lsu_addr[39:0]}), |
| 741 | .sel0(ipc_v0_lsu_new), |
| 742 | .sel1(ipc_v0_lsu_shft), |
| 743 | .sel2(ipc_v0_lsu_hold), |
| 744 | .dout({v0_lsu_cpkt[25:0],v0_lsu_addr[39:0]}), |
| 745 | .se(se), |
| 746 | .siclk(siclk), |
| 747 | .soclk(soclk), |
| 748 | .pce_ov(pce_ov), |
| 749 | .stop(stop) |
| 750 | ); |
| 751 | |
| 752 | gkt_ipd_dp_msff_macro__mux_aonpe__ports_2__stack_64c__width_64 i_lsu_data_v1_muxreg |
| 753 | ( |
| 754 | .scan_in(i_lsu_data_v1_muxreg_scanin), |
| 755 | .scan_out(i_lsu_data_v1_muxreg_scanout), |
| 756 | .clk (l2clk), |
| 757 | .en (1'b1), |
| 758 | .din0(lsu_l15_data[63:0]), |
| 759 | .din1(v1_lsu_data[63:0]), |
| 760 | .sel0(ipc_v1_lsu_new), |
| 761 | .sel1(ipc_v1_lsu_hold), |
| 762 | .dout(v1_lsu_data[63:0]), |
| 763 | .se(se), |
| 764 | .siclk(siclk), |
| 765 | .soclk(soclk), |
| 766 | .pce_ov(pce_ov), |
| 767 | .stop(stop) |
| 768 | ); |
| 769 | |
| 770 | gkt_ipd_dp_msff_macro__mux_aonpe__ports_3__stack_64c__width_64 i_lsu_data_v0_muxreg |
| 771 | ( |
| 772 | .scan_in(i_lsu_data_v0_muxreg_scanin), |
| 773 | .scan_out(i_lsu_data_v0_muxreg_scanout), |
| 774 | .clk (l2clk), |
| 775 | .en (1'b1), |
| 776 | .din0(lsu_l15_data[63:0]), |
| 777 | .din1(v1_lsu_data[63:0]), |
| 778 | .din2(v0_lsu_data[63:0]), |
| 779 | .sel0(ipc_v0_lsu_new), |
| 780 | .sel1(ipc_v0_lsu_shft), |
| 781 | .sel2(ipc_v0_lsu_hold), |
| 782 | .dout(v0_lsu_data[63:0]), |
| 783 | .se(se), |
| 784 | .siclk(siclk), |
| 785 | .soclk(soclk), |
| 786 | .pce_ov(pce_ov), |
| 787 | .stop(stop) |
| 788 | ); |
| 789 | |
| 790 | /////////////////////////////////////////////////////////////////// |
| 791 | // Latch spu pkt in 2-entry FIFO |
| 792 | /////////////////////////////////////////////////////////////////// |
| 793 | gkt_ipd_dp_msff_macro__mux_aonpe__ports_2__stack_66c__width_66 i_spu_addr_v1_muxreg |
| 794 | ( |
| 795 | .scan_in(i_spu_addr_v1_muxreg_scanin), |
| 796 | .scan_out(i_spu_addr_v1_muxreg_scanout), |
| 797 | .clk (l2clk), |
| 798 | .en (1'b1), |
| 799 | .din0({spu_l15_cpkt1[25:0],spu_l15_addr1[39:0]}), |
| 800 | .din1({v1_spu_cpkt[25:0],v1_spu_addr[39:0]}), |
| 801 | .sel0(ipc_v1_spu_new), |
| 802 | .sel1(ipc_v1_spu_hold), |
| 803 | .dout({v1_spu_cpkt[25:0],v1_spu_addr[39:0]}), |
| 804 | .se(se), |
| 805 | .siclk(siclk), |
| 806 | .soclk(soclk), |
| 807 | .pce_ov(pce_ov), |
| 808 | .stop(stop) |
| 809 | ); |
| 810 | |
| 811 | gkt_ipd_dp_msff_macro__mux_aonpe__ports_3__stack_66c__width_66 i_spu_addr_v0_muxreg |
| 812 | ( |
| 813 | .scan_in(i_spu_addr_v0_muxreg_scanin), |
| 814 | .scan_out(i_spu_addr_v0_muxreg_scanout), |
| 815 | .clk (l2clk), |
| 816 | .en (1'b1), |
| 817 | .din0({spu_l15_cpkt1[25:0],spu_l15_addr1[39:0]}), |
| 818 | .din1({v1_spu_cpkt[25:0],v1_spu_addr[39:0]}), |
| 819 | .din2({v0_spu_cpkt[25:0],v0_spu_addr[39:0]}), |
| 820 | .sel0(ipc_v0_spu_new), |
| 821 | .sel1(ipc_v0_spu_shft), |
| 822 | .sel2(ipc_v0_spu_hold), |
| 823 | .dout({v0_spu_cpkt[25:0],v0_spu_addr[39:0]}), |
| 824 | .se(se), |
| 825 | .siclk(siclk), |
| 826 | .soclk(soclk), |
| 827 | .pce_ov(pce_ov), |
| 828 | .stop(stop) |
| 829 | ); |
| 830 | |
| 831 | gkt_ipd_dp_msff_macro__mux_aonpe__ports_2__stack_64c__width_64 i_spu_data_v1_muxreg |
| 832 | ( |
| 833 | .scan_in(i_spu_data_v1_muxreg_scanin), |
| 834 | .scan_out(i_spu_data_v1_muxreg_scanout), |
| 835 | .clk (l2clk), |
| 836 | .en (1'b1), |
| 837 | .din0(spu_l15_data[63:0]), |
| 838 | .din1(v1_spu_data[63:0]), |
| 839 | .sel0(ipc_v1_spu_new), |
| 840 | .sel1(ipc_v1_spu_hold), |
| 841 | .dout(v1_spu_data[63:0]), |
| 842 | .se(se), |
| 843 | .siclk(siclk), |
| 844 | .soclk(soclk), |
| 845 | .pce_ov(pce_ov), |
| 846 | .stop(stop) |
| 847 | ); |
| 848 | |
| 849 | gkt_ipd_dp_msff_macro__mux_aonpe__ports_3__stack_64c__width_64 i_spu_data_v0_muxreg |
| 850 | ( |
| 851 | .scan_in(i_spu_data_v0_muxreg_scanin), |
| 852 | .scan_out(i_spu_data_v0_muxreg_scanout), |
| 853 | .clk (l2clk), |
| 854 | .en (1'b1), |
| 855 | .din0(spu_l15_data[63:0]), |
| 856 | .din1(v1_spu_data[63:0]), |
| 857 | .din2(v0_spu_data[63:0]), |
| 858 | .sel0(ipc_v0_spu_new), |
| 859 | .sel1(ipc_v0_spu_shft), |
| 860 | .sel2(ipc_v0_spu_hold), |
| 861 | .dout(v0_spu_data[63:0]), |
| 862 | .se(se), |
| 863 | .siclk(siclk), |
| 864 | .soclk(soclk), |
| 865 | .pce_ov(pce_ov), |
| 866 | .stop(stop) |
| 867 | ); |
| 868 | |
| 869 | /////////////////////////////////////////////////////////////////// |
| 870 | // L1/PQ cycle. Mux the pcx packets from all sources and corresponding |
| 871 | // DROP registers |
| 872 | /////////////////////////////////////////////////////////////////// |
| 873 | |
| 874 | // save Muxed data into drop registers |
| 875 | gkt_ipd_dp_msff_macro__stack_66c__width_66 i_ifu_addr_drop_reg |
| 876 | ( |
| 877 | .scan_in(i_ifu_addr_drop_reg_scanin), |
| 878 | .scan_out(i_ifu_addr_drop_reg_scanout), |
| 879 | .clk (l2clk), |
| 880 | .en (ipc_dropreg_wen[0]), |
| 881 | .din({ipd_cpkt_l1[25:0],ipd_addr_l1[39:0]}), |
| 882 | .dout({drop_ifu_cpkt[25:0],drop_ifu_addr[39:0]}), |
| 883 | .se(se), |
| 884 | .siclk(siclk), |
| 885 | .soclk(soclk), |
| 886 | .pce_ov(pce_ov), |
| 887 | .stop(stop) |
| 888 | ); |
| 889 | |
| 890 | gkt_ipd_dp_msff_macro__stack_66c__width_66 i_mmu_addr_drop_reg |
| 891 | ( |
| 892 | .scan_in(i_mmu_addr_drop_reg_scanin), |
| 893 | .scan_out(i_mmu_addr_drop_reg_scanout), |
| 894 | .clk (l2clk), |
| 895 | .en (ipc_dropreg_wen[1]), |
| 896 | .din({ipd_cpkt_l1[25:0],ipd_addr_l1[39:0]}), |
| 897 | .dout({drop_mmu_cpkt[25:0],drop_mmu_addr[39:0]}), |
| 898 | .se(se), |
| 899 | .siclk(siclk), |
| 900 | .soclk(soclk), |
| 901 | .pce_ov(pce_ov), |
| 902 | .stop(stop) |
| 903 | ); |
| 904 | |
| 905 | gkt_ipd_dp_msff_macro__stack_66c__width_66 i_lsu_addr_drop_reg |
| 906 | ( |
| 907 | .scan_in(i_lsu_addr_drop_reg_scanin), |
| 908 | .scan_out(i_lsu_addr_drop_reg_scanout), |
| 909 | .clk (l2clk), |
| 910 | .en (ipc_dropreg_wen[2]), |
| 911 | .din({ipd_cpkt_l1[25:0],ipd_addr_l1[39:0]}), |
| 912 | .dout({drop_lsu_cpkt[25:0],drop_lsu_addr[39:0]}), |
| 913 | .se(se), |
| 914 | .siclk(siclk), |
| 915 | .soclk(soclk), |
| 916 | .pce_ov(pce_ov), |
| 917 | .stop(stop) |
| 918 | ); |
| 919 | |
| 920 | gkt_ipd_dp_msff_macro__stack_66c__width_66 i_spu_addr_drop_reg |
| 921 | ( |
| 922 | .scan_in(i_spu_addr_drop_reg_scanin), |
| 923 | .scan_out(i_spu_addr_drop_reg_scanout), |
| 924 | .clk (l2clk), |
| 925 | .en (ipc_dropreg_wen[3]), |
| 926 | .din({ipd_cpkt_l1[25:0],ipd_addr_l1[39:0]}), |
| 927 | .dout({drop_spu_cpkt[25:0],drop_spu_addr[39:0]}), |
| 928 | .se(se), |
| 929 | .siclk(siclk), |
| 930 | .soclk(soclk), |
| 931 | .pce_ov(pce_ov), |
| 932 | .stop(stop) |
| 933 | ); |
| 934 | |
| 935 | gkt_ipd_dp_msff_macro__stack_64c__width_64 i_lsu_data_drop_reg |
| 936 | ( |
| 937 | .scan_in(i_lsu_data_drop_reg_scanin), |
| 938 | .scan_out(i_lsu_data_drop_reg_scanout), |
| 939 | .clk (l2clk), |
| 940 | .en (ipc_dropreg_wen[2]), |
| 941 | .din(ipd_data_l1[63:0]), |
| 942 | .dout(drop_lsu_data[63:0]), |
| 943 | .se(se), |
| 944 | .siclk(siclk), |
| 945 | .soclk(soclk), |
| 946 | .pce_ov(pce_ov), |
| 947 | .stop(stop) |
| 948 | ); |
| 949 | |
| 950 | gkt_ipd_dp_msff_macro__stack_64c__width_64 i_spu_data_drop_reg |
| 951 | ( |
| 952 | .scan_in(i_spu_data_drop_reg_scanin), |
| 953 | .scan_out(i_spu_data_drop_reg_scanout), |
| 954 | .clk (l2clk), |
| 955 | .en (ipc_dropreg_wen[3]), |
| 956 | .din(ipd_data_l1[63:0]), |
| 957 | .dout(drop_spu_data[63:0]), |
| 958 | .se(se), |
| 959 | .siclk(siclk), |
| 960 | .soclk(soclk), |
| 961 | .pce_ov(pce_ov), |
| 962 | .stop(stop) |
| 963 | ); |
| 964 | |
| 965 | // MUX the PCX packet out |
| 966 | |
| 967 | gkt_ipd_dp_mux_macro__mux_aonpe__ports_8__stack_66c__width_66 i_l1_addr_mux |
| 968 | ( |
| 969 | .din0({v0_ifu_cpkt[25:0],v0_ifu_addr[39:0]}), |
| 970 | .din1({v0_mmu_cpkt[25:0],v0_mmu_addr[39:0]}), |
| 971 | .din2({v0_lsu_cpkt[25:0],v0_lsu_addr[39:0]}), |
| 972 | .din3({v0_spu_cpkt[25:0],v0_spu_addr[39:0]}), |
| 973 | .din4({drop_ifu_cpkt[25:0],drop_ifu_addr[39:0]}), |
| 974 | .din5({drop_mmu_cpkt[25:0],drop_mmu_addr[39:0]}), |
| 975 | .din6({drop_lsu_cpkt[25:0],drop_lsu_addr[39:0]}), |
| 976 | .din7({drop_spu_cpkt[25:0],drop_spu_addr[39:0]}), |
| 977 | .sel0(ipc_sel_ndrop_ifu_l1), |
| 978 | .sel1(ipc_sel_ndrop_mmu_l1), |
| 979 | .sel2(ipc_sel_ndrop_lsu_l1), |
| 980 | .sel3(ipc_sel_ndrop_spu_l1), |
| 981 | .sel4(ipc_sel_drop_ifu_l1), |
| 982 | .sel5(ipc_sel_drop_mmu_l1), |
| 983 | .sel6(ipc_sel_drop_lsu_l1), |
| 984 | .sel7(ipc_sel_drop_spu_l1), |
| 985 | .dout({ipd_cpkt_l1[25:0],ipd_addr_l1_prebuf[39:0]}) |
| 986 | ); |
| 987 | |
| 988 | gkt_ipd_dp_buff_macro__stack_66c__width_40 i_l1_addr_buf |
| 989 | ( |
| 990 | .din ({ipd_addr_l1_prebuf[39:0]}), |
| 991 | .dout({ipd_addr_l1[39:0]}) |
| 992 | ); |
| 993 | |
| 994 | // IF Address Hashing is enabled and Bit 39 of the address is not set (not an I/O, |
| 995 | // or L2 diagnostic access) then hash the addresses in following manner: |
| 996 | //PA[17:11] = {(PA[32:28] ^ PA[17:13]), (PA[19:18] ^ PA[12:11])} |
| 997 | // enable_hash = lsu_hash_en & ~PA[39] |
| 998 | // = ~(~lsu_hash_en | PA[39]) |
| 999 | gkt_ipd_dp_msff_macro__stack_64c__width_1 i_hash_en_ff2 |
| 1000 | ( |
| 1001 | .scan_in(i_hash_en_ff2_scanin), |
| 1002 | .scan_out(i_hash_en_ff2_scanout), |
| 1003 | .clk (l2clk), |
| 1004 | .en (1'b1), |
| 1005 | .din(idx_hash_en_ff), |
| 1006 | .dout(idx_hash_en_ff2), |
| 1007 | .se(se), |
| 1008 | .siclk(siclk), |
| 1009 | .soclk(soclk), |
| 1010 | .pce_ov(pce_ov), |
| 1011 | .stop(stop) |
| 1012 | ); |
| 1013 | |
| 1014 | gkt_ipd_dp_inv_macro__stack_64c__width_1 i_hash_en_inv |
| 1015 | ( |
| 1016 | .din(idx_hash_en_ff2), |
| 1017 | .dout(idx_hash_en_) |
| 1018 | ); |
| 1019 | |
| 1020 | gkt_ipd_dp_nor_macro__stack_66c__width_1 i_enable_hash_nor |
| 1021 | ( |
| 1022 | .din0(ipd_addr_l1[39]), |
| 1023 | .din1(idx_hash_en_), |
| 1024 | .dout(enable_hash) |
| 1025 | ); |
| 1026 | |
| 1027 | gkt_ipd_dp_xor_macro__ports_2__stack_66c__width_7 i_l1_hash_xor |
| 1028 | ( |
| 1029 | .din0({ipd_addr_l1[32:28],ipd_addr_l1[19:18]}), |
| 1030 | .din1({ipd_addr_l1[17:13],ipd_addr_l1[12:11]}), |
| 1031 | .dout(ipd_addr_hashed_l1[17:11]) |
| 1032 | ); |
| 1033 | |
| 1034 | |
| 1035 | gkt_ipd_dp_mux_macro__mux_aope__ports_2__stack_66c__width_7 i_l1_hash_mux |
| 1036 | ( |
| 1037 | .din0(ipd_addr_hashed_l1[17:11]), |
| 1038 | .din1(ipd_addr_l1[17:11]), |
| 1039 | .sel0(enable_hash), |
| 1040 | .dout(ipd_addr_out_l1[17:11]) |
| 1041 | ); |
| 1042 | |
| 1043 | |
| 1044 | // mux the store data out |
| 1045 | gkt_ipd_dp_mux_macro__mux_aonpe__ports_4__stack_64c__width_64 i_l1_data_mux |
| 1046 | ( |
| 1047 | .din0(v0_lsu_data[63:0]), |
| 1048 | .din1(v0_spu_data[63:0]), |
| 1049 | .din2(drop_lsu_data[63:0]), |
| 1050 | .din3(drop_spu_data[63:0]), |
| 1051 | .sel0(ipc_sel_ndrop_lsu_l1), |
| 1052 | .sel1(ipc_sel_ndrop_spu_l1), |
| 1053 | .sel2(ipc_sel_drop_lsu_l1), |
| 1054 | .sel3(ipc_sel_drop_spu_l1), |
| 1055 | .dout(ipd_data_l1[63:0]) |
| 1056 | ); |
| 1057 | |
| 1058 | |
| 1059 | // pipe the data out to PCX in PA |
| 1060 | gkt_ipd_dp_msff_macro__dmsff_8x__stack_66c__width_66 i_pcx_addr_pa_reg |
| 1061 | ( |
| 1062 | .scan_in(i_pcx_addr_pa_reg_scanin), |
| 1063 | .scan_out(i_pcx_addr_pa_reg_scanout), |
| 1064 | .clk (l2clk), |
| 1065 | .en (ipc_pq_clken), |
| 1066 | .din({ipd_cpkt_l1[25:0],ipd_addr_l1[39:18],ipd_addr_out_l1[17:11],ipd_addr_l1[10:0]}), |
| 1067 | .dout({pcx_cpkt_pa[25:0],pcx_addr_pa[39:0]}), |
| 1068 | .se(se), |
| 1069 | .siclk(siclk), |
| 1070 | .soclk(soclk), |
| 1071 | .pce_ov(pce_ov), |
| 1072 | .stop(stop) |
| 1073 | ); |
| 1074 | |
| 1075 | gkt_ipd_dp_buff_macro__dbuff_32x__rep_1__stack_66c__width_66 i_pcx_addr_buf |
| 1076 | ( |
| 1077 | .din({pcx_cpkt_pa[25:0],pcx_addr_pa[39:0]}), |
| 1078 | .dout({spc_pcx_data_pa[129:64]}) |
| 1079 | ); |
| 1080 | |
| 1081 | gkt_ipd_dp_buff_macro__stack_none__width_9 i_optype_buf |
| 1082 | ( |
| 1083 | .din({pcx_cpkt_pa[10],pcx_cpkt_pa[24:20],pcx_cpkt_pa[15:13]}), |
| 1084 | .dout({ipd_optype[8:0]}) |
| 1085 | ); |
| 1086 | |
| 1087 | |
| 1088 | |
| 1089 | gkt_ipd_dp_msff_macro__dmsff_8x__stack_64c__width_64 i_pcx_data_pa_reg |
| 1090 | ( |
| 1091 | .scan_in(i_pcx_data_pa_reg_scanin), |
| 1092 | .scan_out(i_pcx_data_pa_reg_scanout), |
| 1093 | .clk (l2clk), |
| 1094 | .en (ipc_pq_clken), |
| 1095 | .din(ipd_data_l1[63:0]), |
| 1096 | .dout(pcx_data_pa[63:0]), |
| 1097 | .se(se), |
| 1098 | .siclk(siclk), |
| 1099 | .soclk(soclk), |
| 1100 | .pce_ov(pce_ov), |
| 1101 | .stop(stop) |
| 1102 | ); |
| 1103 | |
| 1104 | gkt_ipd_dp_buff_macro__dbuff_32x__rep_1__stack_64c__width_64 i_pcx_data_buf |
| 1105 | ( |
| 1106 | .din(pcx_data_pa[63:0]), |
| 1107 | .dout(spc_pcx_data_pa[63:0]) |
| 1108 | ); |
| 1109 | |
| 1110 | |
| 1111 | |
| 1112 | |
| 1113 | |
| 1114 | // fixscan start: |
| 1115 | assign cpuid_reg_scanin = scan_in ; |
| 1116 | assign i_ncu_reg_scanin = cpuid_reg_scanout ; |
| 1117 | assign i_cpx_data1lo_reg_scanin = i_ncu_reg_scanout ; |
| 1118 | assign i_cpx_data1hi_reg_scanin = i_cpx_data1lo_reg_scanout; |
| 1119 | assign i_cpx_cpkt_reg_scanin = i_cpx_data1hi_reg_scanout; |
| 1120 | assign i_req_li_reg_scanin = i_cpx_cpkt_reg_scanout ; |
| 1121 | assign i_ifu_addr_v1_muxreg_scanin = i_req_li_reg_scanout ; |
| 1122 | assign i_ifu_addr_v0_muxreg_scanin = i_ifu_addr_v1_muxreg_scanout; |
| 1123 | assign i_mmu_addr_v1_muxreg_scanin = i_ifu_addr_v0_muxreg_scanout; |
| 1124 | assign i_mmu_addr_v0_muxreg_scanin = i_mmu_addr_v1_muxreg_scanout; |
| 1125 | assign i_lsu_addr_v1_muxreg_scanin = i_mmu_addr_v0_muxreg_scanout; |
| 1126 | assign i_lsu_addr_v0_muxreg_scanin = i_lsu_addr_v1_muxreg_scanout; |
| 1127 | assign i_lsu_data_v1_muxreg_scanin = i_lsu_addr_v0_muxreg_scanout; |
| 1128 | assign i_lsu_data_v0_muxreg_scanin = i_lsu_data_v1_muxreg_scanout; |
| 1129 | assign i_spu_addr_v1_muxreg_scanin = i_lsu_data_v0_muxreg_scanout; |
| 1130 | assign i_spu_addr_v0_muxreg_scanin = i_spu_addr_v1_muxreg_scanout; |
| 1131 | assign i_spu_data_v1_muxreg_scanin = i_spu_addr_v0_muxreg_scanout; |
| 1132 | assign i_spu_data_v0_muxreg_scanin = i_spu_data_v1_muxreg_scanout; |
| 1133 | assign i_ifu_addr_drop_reg_scanin = i_spu_data_v0_muxreg_scanout; |
| 1134 | assign i_mmu_addr_drop_reg_scanin = i_ifu_addr_drop_reg_scanout; |
| 1135 | assign i_lsu_addr_drop_reg_scanin = i_mmu_addr_drop_reg_scanout; |
| 1136 | assign i_spu_addr_drop_reg_scanin = i_lsu_addr_drop_reg_scanout; |
| 1137 | assign i_lsu_data_drop_reg_scanin = i_spu_addr_drop_reg_scanout; |
| 1138 | assign i_spu_data_drop_reg_scanin = i_lsu_data_drop_reg_scanout; |
| 1139 | assign i_hash_en_ff2_scanin = i_spu_data_drop_reg_scanout; |
| 1140 | assign i_pcx_addr_pa_reg_scanin = i_hash_en_ff2_scanout ; |
| 1141 | assign i_pcx_data_pa_reg_scanin = i_pcx_addr_pa_reg_scanout; |
| 1142 | assign scan_out = i_pcx_data_pa_reg_scanout; |
| 1143 | // fixscan end: |
| 1144 | endmodule |
| 1145 | |
| 1146 | |
| 1147 | |
| 1148 | |
| 1149 | |
| 1150 | |
| 1151 | |
| 1152 | // any PARAMS parms go into naming of macro |
| 1153 | |
| 1154 | module gkt_ipd_dp_msff_macro__stack_66c__width_3 ( |
| 1155 | din, |
| 1156 | clk, |
| 1157 | en, |
| 1158 | se, |
| 1159 | scan_in, |
| 1160 | siclk, |
| 1161 | soclk, |
| 1162 | pce_ov, |
| 1163 | stop, |
| 1164 | dout, |
| 1165 | scan_out); |
| 1166 | wire l1clk; |
| 1167 | wire siclk_out; |
| 1168 | wire soclk_out; |
| 1169 | wire [1:0] so; |
| 1170 | |
| 1171 | input [2:0] din; |
| 1172 | |
| 1173 | |
| 1174 | input clk; |
| 1175 | input en; |
| 1176 | input se; |
| 1177 | input scan_in; |
| 1178 | input siclk; |
| 1179 | input soclk; |
| 1180 | input pce_ov; |
| 1181 | input stop; |
| 1182 | |
| 1183 | |
| 1184 | |
| 1185 | output [2:0] dout; |
| 1186 | |
| 1187 | |
| 1188 | output scan_out; |
| 1189 | |
| 1190 | |
| 1191 | |
| 1192 | |
| 1193 | cl_dp1_l1hdr_8x c0_0 ( |
| 1194 | .l2clk(clk), |
| 1195 | .pce(en), |
| 1196 | .aclk(siclk), |
| 1197 | .bclk(soclk), |
| 1198 | .l1clk(l1clk), |
| 1199 | .se(se), |
| 1200 | .pce_ov(pce_ov), |
| 1201 | .stop(stop), |
| 1202 | .siclk_out(siclk_out), |
| 1203 | .soclk_out(soclk_out) |
| 1204 | ); |
| 1205 | dff #(3) d0_0 ( |
| 1206 | .l1clk(l1clk), |
| 1207 | .siclk(siclk_out), |
| 1208 | .soclk(soclk_out), |
| 1209 | .d(din[2:0]), |
| 1210 | .si({scan_in,so[1:0]}), |
| 1211 | .so({so[1:0],scan_out}), |
| 1212 | .q(dout[2:0]) |
| 1213 | ); |
| 1214 | |
| 1215 | |
| 1216 | |
| 1217 | |
| 1218 | |
| 1219 | |
| 1220 | |
| 1221 | |
| 1222 | |
| 1223 | |
| 1224 | |
| 1225 | |
| 1226 | |
| 1227 | |
| 1228 | |
| 1229 | |
| 1230 | |
| 1231 | |
| 1232 | |
| 1233 | |
| 1234 | endmodule |
| 1235 | |
| 1236 | |
| 1237 | |
| 1238 | |
| 1239 | |
| 1240 | |
| 1241 | |
| 1242 | |
| 1243 | |
| 1244 | // |
| 1245 | // buff macro |
| 1246 | // |
| 1247 | // |
| 1248 | |
| 1249 | |
| 1250 | |
| 1251 | |
| 1252 | |
| 1253 | module gkt_ipd_dp_buff_macro__dbuff_16x__rep_1__stack_none__width_9 ( |
| 1254 | din, |
| 1255 | dout); |
| 1256 | input [8:0] din; |
| 1257 | output [8:0] dout; |
| 1258 | |
| 1259 | |
| 1260 | |
| 1261 | |
| 1262 | |
| 1263 | |
| 1264 | buff #(9) d0_0 ( |
| 1265 | .in(din[8:0]), |
| 1266 | .out(dout[8:0]) |
| 1267 | ); |
| 1268 | |
| 1269 | |
| 1270 | |
| 1271 | |
| 1272 | |
| 1273 | |
| 1274 | |
| 1275 | |
| 1276 | endmodule |
| 1277 | |
| 1278 | |
| 1279 | |
| 1280 | |
| 1281 | |
| 1282 | // |
| 1283 | // buff macro |
| 1284 | // |
| 1285 | // |
| 1286 | |
| 1287 | |
| 1288 | |
| 1289 | |
| 1290 | |
| 1291 | module gkt_ipd_dp_buff_macro__dbuff_16x__rep_1__stack_none__width_6 ( |
| 1292 | din, |
| 1293 | dout); |
| 1294 | input [5:0] din; |
| 1295 | output [5:0] dout; |
| 1296 | |
| 1297 | |
| 1298 | |
| 1299 | |
| 1300 | |
| 1301 | |
| 1302 | buff #(6) d0_0 ( |
| 1303 | .in(din[5:0]), |
| 1304 | .out(dout[5:0]) |
| 1305 | ); |
| 1306 | |
| 1307 | |
| 1308 | |
| 1309 | |
| 1310 | |
| 1311 | |
| 1312 | |
| 1313 | |
| 1314 | endmodule |
| 1315 | |
| 1316 | |
| 1317 | |
| 1318 | |
| 1319 | |
| 1320 | |
| 1321 | |
| 1322 | |
| 1323 | |
| 1324 | // any PARAMS parms go into naming of macro |
| 1325 | |
| 1326 | module gkt_ipd_dp_msff_macro__stack_64c__width_6 ( |
| 1327 | din, |
| 1328 | clk, |
| 1329 | en, |
| 1330 | se, |
| 1331 | scan_in, |
| 1332 | siclk, |
| 1333 | soclk, |
| 1334 | pce_ov, |
| 1335 | stop, |
| 1336 | dout, |
| 1337 | scan_out); |
| 1338 | wire l1clk; |
| 1339 | wire siclk_out; |
| 1340 | wire soclk_out; |
| 1341 | wire [4:0] so; |
| 1342 | |
| 1343 | input [5:0] din; |
| 1344 | |
| 1345 | |
| 1346 | input clk; |
| 1347 | input en; |
| 1348 | input se; |
| 1349 | input scan_in; |
| 1350 | input siclk; |
| 1351 | input soclk; |
| 1352 | input pce_ov; |
| 1353 | input stop; |
| 1354 | |
| 1355 | |
| 1356 | |
| 1357 | output [5:0] dout; |
| 1358 | |
| 1359 | |
| 1360 | output scan_out; |
| 1361 | |
| 1362 | |
| 1363 | |
| 1364 | |
| 1365 | cl_dp1_l1hdr_8x c0_0 ( |
| 1366 | .l2clk(clk), |
| 1367 | .pce(en), |
| 1368 | .aclk(siclk), |
| 1369 | .bclk(soclk), |
| 1370 | .l1clk(l1clk), |
| 1371 | .se(se), |
| 1372 | .pce_ov(pce_ov), |
| 1373 | .stop(stop), |
| 1374 | .siclk_out(siclk_out), |
| 1375 | .soclk_out(soclk_out) |
| 1376 | ); |
| 1377 | dff #(6) d0_0 ( |
| 1378 | .l1clk(l1clk), |
| 1379 | .siclk(siclk_out), |
| 1380 | .soclk(soclk_out), |
| 1381 | .d(din[5:0]), |
| 1382 | .si({scan_in,so[4:0]}), |
| 1383 | .so({so[4:0],scan_out}), |
| 1384 | .q(dout[5:0]) |
| 1385 | ); |
| 1386 | |
| 1387 | |
| 1388 | |
| 1389 | |
| 1390 | |
| 1391 | |
| 1392 | |
| 1393 | |
| 1394 | |
| 1395 | |
| 1396 | |
| 1397 | |
| 1398 | |
| 1399 | |
| 1400 | |
| 1401 | |
| 1402 | |
| 1403 | |
| 1404 | |
| 1405 | |
| 1406 | endmodule |
| 1407 | |
| 1408 | |
| 1409 | |
| 1410 | |
| 1411 | |
| 1412 | |
| 1413 | |
| 1414 | |
| 1415 | |
| 1416 | // |
| 1417 | // buff macro |
| 1418 | // |
| 1419 | // |
| 1420 | |
| 1421 | |
| 1422 | |
| 1423 | |
| 1424 | |
| 1425 | module gkt_ipd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 ( |
| 1426 | din, |
| 1427 | dout); |
| 1428 | input [3:0] din; |
| 1429 | output [3:0] dout; |
| 1430 | |
| 1431 | |
| 1432 | |
| 1433 | |
| 1434 | |
| 1435 | |
| 1436 | buff #(4) d0_0 ( |
| 1437 | .in(din[3:0]), |
| 1438 | .out(dout[3:0]) |
| 1439 | ); |
| 1440 | |
| 1441 | |
| 1442 | |
| 1443 | |
| 1444 | |
| 1445 | |
| 1446 | |
| 1447 | |
| 1448 | endmodule |
| 1449 | |
| 1450 | |
| 1451 | |
| 1452 | |
| 1453 | |
| 1454 | // |
| 1455 | // buff macro |
| 1456 | // |
| 1457 | // |
| 1458 | |
| 1459 | |
| 1460 | |
| 1461 | |
| 1462 | |
| 1463 | module gkt_ipd_dp_buff_macro__dbuff_48x__rep_1__stack_64c__width_64 ( |
| 1464 | din, |
| 1465 | dout); |
| 1466 | input [63:0] din; |
| 1467 | output [63:0] dout; |
| 1468 | |
| 1469 | |
| 1470 | |
| 1471 | |
| 1472 | |
| 1473 | |
| 1474 | buff #(64) d0_0 ( |
| 1475 | .in(din[63:0]), |
| 1476 | .out(dout[63:0]) |
| 1477 | ); |
| 1478 | |
| 1479 | |
| 1480 | |
| 1481 | |
| 1482 | |
| 1483 | |
| 1484 | |
| 1485 | |
| 1486 | endmodule |
| 1487 | |
| 1488 | |
| 1489 | |
| 1490 | |
| 1491 | |
| 1492 | |
| 1493 | |
| 1494 | |
| 1495 | |
| 1496 | // any PARAMS parms go into naming of macro |
| 1497 | |
| 1498 | module gkt_ipd_dp_msff_macro__stack_64c__width_64 ( |
| 1499 | din, |
| 1500 | clk, |
| 1501 | en, |
| 1502 | se, |
| 1503 | scan_in, |
| 1504 | siclk, |
| 1505 | soclk, |
| 1506 | pce_ov, |
| 1507 | stop, |
| 1508 | dout, |
| 1509 | scan_out); |
| 1510 | wire l1clk; |
| 1511 | wire siclk_out; |
| 1512 | wire soclk_out; |
| 1513 | wire [62:0] so; |
| 1514 | |
| 1515 | input [63:0] din; |
| 1516 | |
| 1517 | |
| 1518 | input clk; |
| 1519 | input en; |
| 1520 | input se; |
| 1521 | input scan_in; |
| 1522 | input siclk; |
| 1523 | input soclk; |
| 1524 | input pce_ov; |
| 1525 | input stop; |
| 1526 | |
| 1527 | |
| 1528 | |
| 1529 | output [63:0] dout; |
| 1530 | |
| 1531 | |
| 1532 | output scan_out; |
| 1533 | |
| 1534 | |
| 1535 | |
| 1536 | |
| 1537 | cl_dp1_l1hdr_8x c0_0 ( |
| 1538 | .l2clk(clk), |
| 1539 | .pce(en), |
| 1540 | .aclk(siclk), |
| 1541 | .bclk(soclk), |
| 1542 | .l1clk(l1clk), |
| 1543 | .se(se), |
| 1544 | .pce_ov(pce_ov), |
| 1545 | .stop(stop), |
| 1546 | .siclk_out(siclk_out), |
| 1547 | .soclk_out(soclk_out) |
| 1548 | ); |
| 1549 | dff #(64) d0_0 ( |
| 1550 | .l1clk(l1clk), |
| 1551 | .siclk(siclk_out), |
| 1552 | .soclk(soclk_out), |
| 1553 | .d(din[63:0]), |
| 1554 | .si({scan_in,so[62:0]}), |
| 1555 | .so({so[62:0],scan_out}), |
| 1556 | .q(dout[63:0]) |
| 1557 | ); |
| 1558 | |
| 1559 | |
| 1560 | |
| 1561 | |
| 1562 | |
| 1563 | |
| 1564 | |
| 1565 | |
| 1566 | |
| 1567 | |
| 1568 | |
| 1569 | |
| 1570 | |
| 1571 | |
| 1572 | |
| 1573 | |
| 1574 | |
| 1575 | |
| 1576 | |
| 1577 | |
| 1578 | endmodule |
| 1579 | |
| 1580 | |
| 1581 | |
| 1582 | |
| 1583 | |
| 1584 | |
| 1585 | |
| 1586 | |
| 1587 | |
| 1588 | // |
| 1589 | // buff macro |
| 1590 | // |
| 1591 | // |
| 1592 | |
| 1593 | |
| 1594 | |
| 1595 | |
| 1596 | |
| 1597 | module gkt_ipd_dp_buff_macro__dbuff_48x__rep_1__stack_none__width_18 ( |
| 1598 | din, |
| 1599 | dout); |
| 1600 | input [17:0] din; |
| 1601 | output [17:0] dout; |
| 1602 | |
| 1603 | |
| 1604 | |
| 1605 | |
| 1606 | |
| 1607 | |
| 1608 | buff #(18) d0_0 ( |
| 1609 | .in(din[17:0]), |
| 1610 | .out(dout[17:0]) |
| 1611 | ); |
| 1612 | |
| 1613 | |
| 1614 | |
| 1615 | |
| 1616 | |
| 1617 | |
| 1618 | |
| 1619 | |
| 1620 | endmodule |
| 1621 | |
| 1622 | |
| 1623 | |
| 1624 | |
| 1625 | |
| 1626 | |
| 1627 | |
| 1628 | |
| 1629 | |
| 1630 | // any PARAMS parms go into naming of macro |
| 1631 | |
| 1632 | module gkt_ipd_dp_msff_macro__stack_64c__width_18 ( |
| 1633 | din, |
| 1634 | clk, |
| 1635 | en, |
| 1636 | se, |
| 1637 | scan_in, |
| 1638 | siclk, |
| 1639 | soclk, |
| 1640 | pce_ov, |
| 1641 | stop, |
| 1642 | dout, |
| 1643 | scan_out); |
| 1644 | wire l1clk; |
| 1645 | wire siclk_out; |
| 1646 | wire soclk_out; |
| 1647 | wire [16:0] so; |
| 1648 | |
| 1649 | input [17:0] din; |
| 1650 | |
| 1651 | |
| 1652 | input clk; |
| 1653 | input en; |
| 1654 | input se; |
| 1655 | input scan_in; |
| 1656 | input siclk; |
| 1657 | input soclk; |
| 1658 | input pce_ov; |
| 1659 | input stop; |
| 1660 | |
| 1661 | |
| 1662 | |
| 1663 | output [17:0] dout; |
| 1664 | |
| 1665 | |
| 1666 | output scan_out; |
| 1667 | |
| 1668 | |
| 1669 | |
| 1670 | |
| 1671 | cl_dp1_l1hdr_8x c0_0 ( |
| 1672 | .l2clk(clk), |
| 1673 | .pce(en), |
| 1674 | .aclk(siclk), |
| 1675 | .bclk(soclk), |
| 1676 | .l1clk(l1clk), |
| 1677 | .se(se), |
| 1678 | .pce_ov(pce_ov), |
| 1679 | .stop(stop), |
| 1680 | .siclk_out(siclk_out), |
| 1681 | .soclk_out(soclk_out) |
| 1682 | ); |
| 1683 | dff #(18) d0_0 ( |
| 1684 | .l1clk(l1clk), |
| 1685 | .siclk(siclk_out), |
| 1686 | .soclk(soclk_out), |
| 1687 | .d(din[17:0]), |
| 1688 | .si({scan_in,so[16:0]}), |
| 1689 | .so({so[16:0],scan_out}), |
| 1690 | .q(dout[17:0]) |
| 1691 | ); |
| 1692 | |
| 1693 | |
| 1694 | |
| 1695 | |
| 1696 | |
| 1697 | |
| 1698 | |
| 1699 | |
| 1700 | |
| 1701 | |
| 1702 | |
| 1703 | |
| 1704 | |
| 1705 | |
| 1706 | |
| 1707 | |
| 1708 | |
| 1709 | |
| 1710 | |
| 1711 | |
| 1712 | endmodule |
| 1713 | |
| 1714 | |
| 1715 | |
| 1716 | |
| 1717 | |
| 1718 | |
| 1719 | |
| 1720 | |
| 1721 | |
| 1722 | // |
| 1723 | // buff macro |
| 1724 | // |
| 1725 | // |
| 1726 | |
| 1727 | |
| 1728 | |
| 1729 | |
| 1730 | |
| 1731 | module gkt_ipd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_20 ( |
| 1732 | din, |
| 1733 | dout); |
| 1734 | input [19:0] din; |
| 1735 | output [19:0] dout; |
| 1736 | |
| 1737 | |
| 1738 | |
| 1739 | |
| 1740 | |
| 1741 | |
| 1742 | buff #(20) d0_0 ( |
| 1743 | .in(din[19:0]), |
| 1744 | .out(dout[19:0]) |
| 1745 | ); |
| 1746 | |
| 1747 | |
| 1748 | |
| 1749 | |
| 1750 | |
| 1751 | |
| 1752 | |
| 1753 | |
| 1754 | endmodule |
| 1755 | |
| 1756 | |
| 1757 | |
| 1758 | |
| 1759 | |
| 1760 | |
| 1761 | |
| 1762 | |
| 1763 | |
| 1764 | // any PARAMS parms go into naming of macro |
| 1765 | |
| 1766 | module gkt_ipd_dp_msff_macro__dmsff_8x__stack_64c__width_19 ( |
| 1767 | din, |
| 1768 | clk, |
| 1769 | en, |
| 1770 | se, |
| 1771 | scan_in, |
| 1772 | siclk, |
| 1773 | soclk, |
| 1774 | pce_ov, |
| 1775 | stop, |
| 1776 | dout, |
| 1777 | scan_out); |
| 1778 | wire l1clk; |
| 1779 | wire siclk_out; |
| 1780 | wire soclk_out; |
| 1781 | wire [17:0] so; |
| 1782 | |
| 1783 | input [18:0] din; |
| 1784 | |
| 1785 | |
| 1786 | input clk; |
| 1787 | input en; |
| 1788 | input se; |
| 1789 | input scan_in; |
| 1790 | input siclk; |
| 1791 | input soclk; |
| 1792 | input pce_ov; |
| 1793 | input stop; |
| 1794 | |
| 1795 | |
| 1796 | |
| 1797 | output [18:0] dout; |
| 1798 | |
| 1799 | |
| 1800 | output scan_out; |
| 1801 | |
| 1802 | |
| 1803 | |
| 1804 | |
| 1805 | cl_dp1_l1hdr_8x c0_0 ( |
| 1806 | .l2clk(clk), |
| 1807 | .pce(en), |
| 1808 | .aclk(siclk), |
| 1809 | .bclk(soclk), |
| 1810 | .l1clk(l1clk), |
| 1811 | .se(se), |
| 1812 | .pce_ov(pce_ov), |
| 1813 | .stop(stop), |
| 1814 | .siclk_out(siclk_out), |
| 1815 | .soclk_out(soclk_out) |
| 1816 | ); |
| 1817 | dff #(19) d0_0 ( |
| 1818 | .l1clk(l1clk), |
| 1819 | .siclk(siclk_out), |
| 1820 | .soclk(soclk_out), |
| 1821 | .d(din[18:0]), |
| 1822 | .si({scan_in,so[17:0]}), |
| 1823 | .so({so[17:0],scan_out}), |
| 1824 | .q(dout[18:0]) |
| 1825 | ); |
| 1826 | |
| 1827 | |
| 1828 | |
| 1829 | |
| 1830 | |
| 1831 | |
| 1832 | |
| 1833 | |
| 1834 | |
| 1835 | |
| 1836 | |
| 1837 | |
| 1838 | |
| 1839 | |
| 1840 | |
| 1841 | |
| 1842 | |
| 1843 | |
| 1844 | |
| 1845 | |
| 1846 | endmodule |
| 1847 | |
| 1848 | |
| 1849 | |
| 1850 | |
| 1851 | |
| 1852 | |
| 1853 | |
| 1854 | |
| 1855 | |
| 1856 | // |
| 1857 | // invert macro |
| 1858 | // |
| 1859 | // |
| 1860 | |
| 1861 | |
| 1862 | |
| 1863 | |
| 1864 | |
| 1865 | module gkt_ipd_dp_inv_macro__dinv_8x__stack_64c__width_1 ( |
| 1866 | din, |
| 1867 | dout); |
| 1868 | input [0:0] din; |
| 1869 | output [0:0] dout; |
| 1870 | |
| 1871 | |
| 1872 | |
| 1873 | |
| 1874 | |
| 1875 | |
| 1876 | inv #(1) d0_0 ( |
| 1877 | .in(din[0:0]), |
| 1878 | .out(dout[0:0]) |
| 1879 | ); |
| 1880 | |
| 1881 | |
| 1882 | |
| 1883 | |
| 1884 | |
| 1885 | |
| 1886 | |
| 1887 | |
| 1888 | |
| 1889 | endmodule |
| 1890 | |
| 1891 | |
| 1892 | |
| 1893 | |
| 1894 | |
| 1895 | // |
| 1896 | // nand macro for ports = 2,3,4 |
| 1897 | // |
| 1898 | // |
| 1899 | |
| 1900 | |
| 1901 | |
| 1902 | |
| 1903 | |
| 1904 | module gkt_ipd_dp_nand_macro__dnand_16x__ports_2__stack_64c__width_9 ( |
| 1905 | din0, |
| 1906 | din1, |
| 1907 | dout); |
| 1908 | input [8:0] din0; |
| 1909 | input [8:0] din1; |
| 1910 | output [8:0] dout; |
| 1911 | |
| 1912 | |
| 1913 | |
| 1914 | |
| 1915 | |
| 1916 | |
| 1917 | nand2 #(9) d0_0 ( |
| 1918 | .in0(din0[8:0]), |
| 1919 | .in1(din1[8:0]), |
| 1920 | .out(dout[8:0]) |
| 1921 | ); |
| 1922 | |
| 1923 | |
| 1924 | |
| 1925 | |
| 1926 | |
| 1927 | |
| 1928 | |
| 1929 | |
| 1930 | |
| 1931 | endmodule |
| 1932 | |
| 1933 | |
| 1934 | |
| 1935 | |
| 1936 | |
| 1937 | // |
| 1938 | // invert macro |
| 1939 | // |
| 1940 | // |
| 1941 | |
| 1942 | |
| 1943 | |
| 1944 | |
| 1945 | |
| 1946 | module gkt_ipd_dp_inv_macro__dinv_48x__stack_64c__width_9 ( |
| 1947 | din, |
| 1948 | dout); |
| 1949 | input [8:0] din; |
| 1950 | output [8:0] dout; |
| 1951 | |
| 1952 | |
| 1953 | |
| 1954 | |
| 1955 | |
| 1956 | |
| 1957 | inv #(9) d0_0 ( |
| 1958 | .in(din[8:0]), |
| 1959 | .out(dout[8:0]) |
| 1960 | ); |
| 1961 | |
| 1962 | |
| 1963 | |
| 1964 | |
| 1965 | |
| 1966 | |
| 1967 | |
| 1968 | |
| 1969 | |
| 1970 | endmodule |
| 1971 | |
| 1972 | |
| 1973 | |
| 1974 | |
| 1975 | |
| 1976 | |
| 1977 | |
| 1978 | |
| 1979 | |
| 1980 | // any PARAMS parms go into naming of macro |
| 1981 | |
| 1982 | module gkt_ipd_dp_msff_macro__mux_aonpe__ports_2__stack_66c__width_66 ( |
| 1983 | din0, |
| 1984 | sel0, |
| 1985 | din1, |
| 1986 | sel1, |
| 1987 | clk, |
| 1988 | en, |
| 1989 | se, |
| 1990 | scan_in, |
| 1991 | siclk, |
| 1992 | soclk, |
| 1993 | pce_ov, |
| 1994 | stop, |
| 1995 | dout, |
| 1996 | scan_out); |
| 1997 | wire buffout0; |
| 1998 | wire buffout1; |
| 1999 | wire [65:0] muxout; |
| 2000 | wire l1clk; |
| 2001 | wire siclk_out; |
| 2002 | wire soclk_out; |
| 2003 | wire [64:0] so; |
| 2004 | |
| 2005 | input [65:0] din0; |
| 2006 | input sel0; |
| 2007 | input [65:0] din1; |
| 2008 | input sel1; |
| 2009 | |
| 2010 | |
| 2011 | input clk; |
| 2012 | input en; |
| 2013 | input se; |
| 2014 | input scan_in; |
| 2015 | input siclk; |
| 2016 | input soclk; |
| 2017 | input pce_ov; |
| 2018 | input stop; |
| 2019 | |
| 2020 | |
| 2021 | |
| 2022 | output [65:0] dout; |
| 2023 | |
| 2024 | |
| 2025 | output scan_out; |
| 2026 | |
| 2027 | |
| 2028 | |
| 2029 | |
| 2030 | cl_dp1_muxbuff2_8x c1_0 ( |
| 2031 | .in0(sel0), |
| 2032 | .in1(sel1), |
| 2033 | .out0(buffout0), |
| 2034 | .out1(buffout1) |
| 2035 | ); |
| 2036 | mux2s #(66) d1_0 ( |
| 2037 | .sel0(buffout0), |
| 2038 | .sel1(buffout1), |
| 2039 | .in0(din0[65:0]), |
| 2040 | .in1(din1[65:0]), |
| 2041 | .dout(muxout[65:0]) |
| 2042 | ); |
| 2043 | cl_dp1_l1hdr_8x c0_0 ( |
| 2044 | .l2clk(clk), |
| 2045 | .pce(en), |
| 2046 | .aclk(siclk), |
| 2047 | .bclk(soclk), |
| 2048 | .l1clk(l1clk), |
| 2049 | .se(se), |
| 2050 | .pce_ov(pce_ov), |
| 2051 | .stop(stop), |
| 2052 | .siclk_out(siclk_out), |
| 2053 | .soclk_out(soclk_out) |
| 2054 | ); |
| 2055 | dff #(66) d0_0 ( |
| 2056 | .l1clk(l1clk), |
| 2057 | .siclk(siclk_out), |
| 2058 | .soclk(soclk_out), |
| 2059 | .d(muxout[65:0]), |
| 2060 | .si({scan_in,so[64:0]}), |
| 2061 | .so({so[64:0],scan_out}), |
| 2062 | .q(dout[65:0]) |
| 2063 | ); |
| 2064 | |
| 2065 | |
| 2066 | |
| 2067 | |
| 2068 | |
| 2069 | |
| 2070 | |
| 2071 | |
| 2072 | |
| 2073 | |
| 2074 | |
| 2075 | |
| 2076 | |
| 2077 | |
| 2078 | |
| 2079 | |
| 2080 | |
| 2081 | |
| 2082 | |
| 2083 | |
| 2084 | endmodule |
| 2085 | |
| 2086 | |
| 2087 | |
| 2088 | |
| 2089 | |
| 2090 | |
| 2091 | |
| 2092 | |
| 2093 | |
| 2094 | |
| 2095 | |
| 2096 | |
| 2097 | |
| 2098 | // any PARAMS parms go into naming of macro |
| 2099 | |
| 2100 | module gkt_ipd_dp_msff_macro__mux_aonpe__ports_3__stack_66c__width_66 ( |
| 2101 | din0, |
| 2102 | sel0, |
| 2103 | din1, |
| 2104 | sel1, |
| 2105 | din2, |
| 2106 | sel2, |
| 2107 | clk, |
| 2108 | en, |
| 2109 | se, |
| 2110 | scan_in, |
| 2111 | siclk, |
| 2112 | soclk, |
| 2113 | pce_ov, |
| 2114 | stop, |
| 2115 | dout, |
| 2116 | scan_out); |
| 2117 | wire buffout0; |
| 2118 | wire buffout1; |
| 2119 | wire buffout2; |
| 2120 | wire [65:0] muxout; |
| 2121 | wire l1clk; |
| 2122 | wire siclk_out; |
| 2123 | wire soclk_out; |
| 2124 | wire [64:0] so; |
| 2125 | |
| 2126 | input [65:0] din0; |
| 2127 | input sel0; |
| 2128 | input [65:0] din1; |
| 2129 | input sel1; |
| 2130 | input [65:0] din2; |
| 2131 | input sel2; |
| 2132 | |
| 2133 | |
| 2134 | input clk; |
| 2135 | input en; |
| 2136 | input se; |
| 2137 | input scan_in; |
| 2138 | input siclk; |
| 2139 | input soclk; |
| 2140 | input pce_ov; |
| 2141 | input stop; |
| 2142 | |
| 2143 | |
| 2144 | |
| 2145 | output [65:0] dout; |
| 2146 | |
| 2147 | |
| 2148 | output scan_out; |
| 2149 | |
| 2150 | |
| 2151 | |
| 2152 | |
| 2153 | cl_dp1_muxbuff3_8x c1_0 ( |
| 2154 | .in0(sel0), |
| 2155 | .in1(sel1), |
| 2156 | .in2(sel2), |
| 2157 | .out0(buffout0), |
| 2158 | .out1(buffout1), |
| 2159 | .out2(buffout2) |
| 2160 | ); |
| 2161 | mux3s #(66) d1_0 ( |
| 2162 | .sel0(buffout0), |
| 2163 | .sel1(buffout1), |
| 2164 | .sel2(buffout2), |
| 2165 | .in0(din0[65:0]), |
| 2166 | .in1(din1[65:0]), |
| 2167 | .in2(din2[65:0]), |
| 2168 | .dout(muxout[65:0]) |
| 2169 | ); |
| 2170 | cl_dp1_l1hdr_8x c0_0 ( |
| 2171 | .l2clk(clk), |
| 2172 | .pce(en), |
| 2173 | .aclk(siclk), |
| 2174 | .bclk(soclk), |
| 2175 | .l1clk(l1clk), |
| 2176 | .se(se), |
| 2177 | .pce_ov(pce_ov), |
| 2178 | .stop(stop), |
| 2179 | .siclk_out(siclk_out), |
| 2180 | .soclk_out(soclk_out) |
| 2181 | ); |
| 2182 | dff #(66) d0_0 ( |
| 2183 | .l1clk(l1clk), |
| 2184 | .siclk(siclk_out), |
| 2185 | .soclk(soclk_out), |
| 2186 | .d(muxout[65:0]), |
| 2187 | .si({scan_in,so[64:0]}), |
| 2188 | .so({so[64:0],scan_out}), |
| 2189 | .q(dout[65:0]) |
| 2190 | ); |
| 2191 | |
| 2192 | |
| 2193 | |
| 2194 | |
| 2195 | |
| 2196 | |
| 2197 | |
| 2198 | |
| 2199 | |
| 2200 | |
| 2201 | |
| 2202 | |
| 2203 | |
| 2204 | |
| 2205 | |
| 2206 | |
| 2207 | |
| 2208 | |
| 2209 | |
| 2210 | |
| 2211 | endmodule |
| 2212 | |
| 2213 | |
| 2214 | |
| 2215 | |
| 2216 | |
| 2217 | |
| 2218 | |
| 2219 | |
| 2220 | |
| 2221 | |
| 2222 | |
| 2223 | |
| 2224 | |
| 2225 | // any PARAMS parms go into naming of macro |
| 2226 | |
| 2227 | module gkt_ipd_dp_msff_macro__mux_aonpe__ports_2__stack_64c__width_64 ( |
| 2228 | din0, |
| 2229 | sel0, |
| 2230 | din1, |
| 2231 | sel1, |
| 2232 | clk, |
| 2233 | en, |
| 2234 | se, |
| 2235 | scan_in, |
| 2236 | siclk, |
| 2237 | soclk, |
| 2238 | pce_ov, |
| 2239 | stop, |
| 2240 | dout, |
| 2241 | scan_out); |
| 2242 | wire buffout0; |
| 2243 | wire buffout1; |
| 2244 | wire [63:0] muxout; |
| 2245 | wire l1clk; |
| 2246 | wire siclk_out; |
| 2247 | wire soclk_out; |
| 2248 | wire [62:0] so; |
| 2249 | |
| 2250 | input [63:0] din0; |
| 2251 | input sel0; |
| 2252 | input [63:0] din1; |
| 2253 | input sel1; |
| 2254 | |
| 2255 | |
| 2256 | input clk; |
| 2257 | input en; |
| 2258 | input se; |
| 2259 | input scan_in; |
| 2260 | input siclk; |
| 2261 | input soclk; |
| 2262 | input pce_ov; |
| 2263 | input stop; |
| 2264 | |
| 2265 | |
| 2266 | |
| 2267 | output [63:0] dout; |
| 2268 | |
| 2269 | |
| 2270 | output scan_out; |
| 2271 | |
| 2272 | |
| 2273 | |
| 2274 | |
| 2275 | cl_dp1_muxbuff2_8x c1_0 ( |
| 2276 | .in0(sel0), |
| 2277 | .in1(sel1), |
| 2278 | .out0(buffout0), |
| 2279 | .out1(buffout1) |
| 2280 | ); |
| 2281 | mux2s #(64) d1_0 ( |
| 2282 | .sel0(buffout0), |
| 2283 | .sel1(buffout1), |
| 2284 | .in0(din0[63:0]), |
| 2285 | .in1(din1[63:0]), |
| 2286 | .dout(muxout[63:0]) |
| 2287 | ); |
| 2288 | cl_dp1_l1hdr_8x c0_0 ( |
| 2289 | .l2clk(clk), |
| 2290 | .pce(en), |
| 2291 | .aclk(siclk), |
| 2292 | .bclk(soclk), |
| 2293 | .l1clk(l1clk), |
| 2294 | .se(se), |
| 2295 | .pce_ov(pce_ov), |
| 2296 | .stop(stop), |
| 2297 | .siclk_out(siclk_out), |
| 2298 | .soclk_out(soclk_out) |
| 2299 | ); |
| 2300 | dff #(64) d0_0 ( |
| 2301 | .l1clk(l1clk), |
| 2302 | .siclk(siclk_out), |
| 2303 | .soclk(soclk_out), |
| 2304 | .d(muxout[63:0]), |
| 2305 | .si({scan_in,so[62:0]}), |
| 2306 | .so({so[62:0],scan_out}), |
| 2307 | .q(dout[63:0]) |
| 2308 | ); |
| 2309 | |
| 2310 | |
| 2311 | |
| 2312 | |
| 2313 | |
| 2314 | |
| 2315 | |
| 2316 | |
| 2317 | |
| 2318 | |
| 2319 | |
| 2320 | |
| 2321 | |
| 2322 | |
| 2323 | |
| 2324 | |
| 2325 | |
| 2326 | |
| 2327 | |
| 2328 | |
| 2329 | endmodule |
| 2330 | |
| 2331 | |
| 2332 | |
| 2333 | |
| 2334 | |
| 2335 | |
| 2336 | |
| 2337 | |
| 2338 | |
| 2339 | |
| 2340 | |
| 2341 | |
| 2342 | |
| 2343 | // any PARAMS parms go into naming of macro |
| 2344 | |
| 2345 | module gkt_ipd_dp_msff_macro__mux_aonpe__ports_3__stack_64c__width_64 ( |
| 2346 | din0, |
| 2347 | sel0, |
| 2348 | din1, |
| 2349 | sel1, |
| 2350 | din2, |
| 2351 | sel2, |
| 2352 | clk, |
| 2353 | en, |
| 2354 | se, |
| 2355 | scan_in, |
| 2356 | siclk, |
| 2357 | soclk, |
| 2358 | pce_ov, |
| 2359 | stop, |
| 2360 | dout, |
| 2361 | scan_out); |
| 2362 | wire buffout0; |
| 2363 | wire buffout1; |
| 2364 | wire buffout2; |
| 2365 | wire [63:0] muxout; |
| 2366 | wire l1clk; |
| 2367 | wire siclk_out; |
| 2368 | wire soclk_out; |
| 2369 | wire [62:0] so; |
| 2370 | |
| 2371 | input [63:0] din0; |
| 2372 | input sel0; |
| 2373 | input [63:0] din1; |
| 2374 | input sel1; |
| 2375 | input [63:0] din2; |
| 2376 | input sel2; |
| 2377 | |
| 2378 | |
| 2379 | input clk; |
| 2380 | input en; |
| 2381 | input se; |
| 2382 | input scan_in; |
| 2383 | input siclk; |
| 2384 | input soclk; |
| 2385 | input pce_ov; |
| 2386 | input stop; |
| 2387 | |
| 2388 | |
| 2389 | |
| 2390 | output [63:0] dout; |
| 2391 | |
| 2392 | |
| 2393 | output scan_out; |
| 2394 | |
| 2395 | |
| 2396 | |
| 2397 | |
| 2398 | cl_dp1_muxbuff3_8x c1_0 ( |
| 2399 | .in0(sel0), |
| 2400 | .in1(sel1), |
| 2401 | .in2(sel2), |
| 2402 | .out0(buffout0), |
| 2403 | .out1(buffout1), |
| 2404 | .out2(buffout2) |
| 2405 | ); |
| 2406 | mux3s #(64) d1_0 ( |
| 2407 | .sel0(buffout0), |
| 2408 | .sel1(buffout1), |
| 2409 | .sel2(buffout2), |
| 2410 | .in0(din0[63:0]), |
| 2411 | .in1(din1[63:0]), |
| 2412 | .in2(din2[63:0]), |
| 2413 | .dout(muxout[63:0]) |
| 2414 | ); |
| 2415 | cl_dp1_l1hdr_8x c0_0 ( |
| 2416 | .l2clk(clk), |
| 2417 | .pce(en), |
| 2418 | .aclk(siclk), |
| 2419 | .bclk(soclk), |
| 2420 | .l1clk(l1clk), |
| 2421 | .se(se), |
| 2422 | .pce_ov(pce_ov), |
| 2423 | .stop(stop), |
| 2424 | .siclk_out(siclk_out), |
| 2425 | .soclk_out(soclk_out) |
| 2426 | ); |
| 2427 | dff #(64) d0_0 ( |
| 2428 | .l1clk(l1clk), |
| 2429 | .siclk(siclk_out), |
| 2430 | .soclk(soclk_out), |
| 2431 | .d(muxout[63:0]), |
| 2432 | .si({scan_in,so[62:0]}), |
| 2433 | .so({so[62:0],scan_out}), |
| 2434 | .q(dout[63:0]) |
| 2435 | ); |
| 2436 | |
| 2437 | |
| 2438 | |
| 2439 | |
| 2440 | |
| 2441 | |
| 2442 | |
| 2443 | |
| 2444 | |
| 2445 | |
| 2446 | |
| 2447 | |
| 2448 | |
| 2449 | |
| 2450 | |
| 2451 | |
| 2452 | |
| 2453 | |
| 2454 | |
| 2455 | |
| 2456 | endmodule |
| 2457 | |
| 2458 | |
| 2459 | |
| 2460 | |
| 2461 | |
| 2462 | |
| 2463 | |
| 2464 | |
| 2465 | |
| 2466 | |
| 2467 | |
| 2468 | |
| 2469 | |
| 2470 | // any PARAMS parms go into naming of macro |
| 2471 | |
| 2472 | module gkt_ipd_dp_msff_macro__stack_66c__width_66 ( |
| 2473 | din, |
| 2474 | clk, |
| 2475 | en, |
| 2476 | se, |
| 2477 | scan_in, |
| 2478 | siclk, |
| 2479 | soclk, |
| 2480 | pce_ov, |
| 2481 | stop, |
| 2482 | dout, |
| 2483 | scan_out); |
| 2484 | wire l1clk; |
| 2485 | wire siclk_out; |
| 2486 | wire soclk_out; |
| 2487 | wire [64:0] so; |
| 2488 | |
| 2489 | input [65:0] din; |
| 2490 | |
| 2491 | |
| 2492 | input clk; |
| 2493 | input en; |
| 2494 | input se; |
| 2495 | input scan_in; |
| 2496 | input siclk; |
| 2497 | input soclk; |
| 2498 | input pce_ov; |
| 2499 | input stop; |
| 2500 | |
| 2501 | |
| 2502 | |
| 2503 | output [65:0] dout; |
| 2504 | |
| 2505 | |
| 2506 | output scan_out; |
| 2507 | |
| 2508 | |
| 2509 | |
| 2510 | |
| 2511 | cl_dp1_l1hdr_8x c0_0 ( |
| 2512 | .l2clk(clk), |
| 2513 | .pce(en), |
| 2514 | .aclk(siclk), |
| 2515 | .bclk(soclk), |
| 2516 | .l1clk(l1clk), |
| 2517 | .se(se), |
| 2518 | .pce_ov(pce_ov), |
| 2519 | .stop(stop), |
| 2520 | .siclk_out(siclk_out), |
| 2521 | .soclk_out(soclk_out) |
| 2522 | ); |
| 2523 | dff #(66) d0_0 ( |
| 2524 | .l1clk(l1clk), |
| 2525 | .siclk(siclk_out), |
| 2526 | .soclk(soclk_out), |
| 2527 | .d(din[65:0]), |
| 2528 | .si({scan_in,so[64:0]}), |
| 2529 | .so({so[64:0],scan_out}), |
| 2530 | .q(dout[65:0]) |
| 2531 | ); |
| 2532 | |
| 2533 | |
| 2534 | |
| 2535 | |
| 2536 | |
| 2537 | |
| 2538 | |
| 2539 | |
| 2540 | |
| 2541 | |
| 2542 | |
| 2543 | |
| 2544 | |
| 2545 | |
| 2546 | |
| 2547 | |
| 2548 | |
| 2549 | |
| 2550 | |
| 2551 | |
| 2552 | endmodule |
| 2553 | |
| 2554 | |
| 2555 | |
| 2556 | |
| 2557 | |
| 2558 | |
| 2559 | |
| 2560 | |
| 2561 | |
| 2562 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2563 | // also for pass-gate with decoder |
| 2564 | |
| 2565 | |
| 2566 | |
| 2567 | |
| 2568 | |
| 2569 | // any PARAMS parms go into naming of macro |
| 2570 | |
| 2571 | module gkt_ipd_dp_mux_macro__mux_aonpe__ports_8__stack_66c__width_66 ( |
| 2572 | din0, |
| 2573 | sel0, |
| 2574 | din1, |
| 2575 | sel1, |
| 2576 | din2, |
| 2577 | sel2, |
| 2578 | din3, |
| 2579 | sel3, |
| 2580 | din4, |
| 2581 | sel4, |
| 2582 | din5, |
| 2583 | sel5, |
| 2584 | din6, |
| 2585 | sel6, |
| 2586 | din7, |
| 2587 | sel7, |
| 2588 | dout); |
| 2589 | wire buffout0; |
| 2590 | wire buffout1; |
| 2591 | wire buffout2; |
| 2592 | wire buffout3; |
| 2593 | wire buffout4; |
| 2594 | wire buffout5; |
| 2595 | wire buffout6; |
| 2596 | wire buffout7; |
| 2597 | |
| 2598 | input [65:0] din0; |
| 2599 | input sel0; |
| 2600 | input [65:0] din1; |
| 2601 | input sel1; |
| 2602 | input [65:0] din2; |
| 2603 | input sel2; |
| 2604 | input [65:0] din3; |
| 2605 | input sel3; |
| 2606 | input [65:0] din4; |
| 2607 | input sel4; |
| 2608 | input [65:0] din5; |
| 2609 | input sel5; |
| 2610 | input [65:0] din6; |
| 2611 | input sel6; |
| 2612 | input [65:0] din7; |
| 2613 | input sel7; |
| 2614 | output [65:0] dout; |
| 2615 | |
| 2616 | |
| 2617 | |
| 2618 | |
| 2619 | |
| 2620 | cl_dp1_muxbuff8_8x c0_0 ( |
| 2621 | .in0(sel0), |
| 2622 | .in1(sel1), |
| 2623 | .in2(sel2), |
| 2624 | .in3(sel3), |
| 2625 | .in4(sel4), |
| 2626 | .in5(sel5), |
| 2627 | .in6(sel6), |
| 2628 | .in7(sel7), |
| 2629 | .out0(buffout0), |
| 2630 | .out1(buffout1), |
| 2631 | .out2(buffout2), |
| 2632 | .out3(buffout3), |
| 2633 | .out4(buffout4), |
| 2634 | .out5(buffout5), |
| 2635 | .out6(buffout6), |
| 2636 | .out7(buffout7) |
| 2637 | ); |
| 2638 | mux8s #(66) d0_0 ( |
| 2639 | .sel0(buffout0), |
| 2640 | .sel1(buffout1), |
| 2641 | .sel2(buffout2), |
| 2642 | .sel3(buffout3), |
| 2643 | .sel4(buffout4), |
| 2644 | .sel5(buffout5), |
| 2645 | .sel6(buffout6), |
| 2646 | .sel7(buffout7), |
| 2647 | .in0(din0[65:0]), |
| 2648 | .in1(din1[65:0]), |
| 2649 | .in2(din2[65:0]), |
| 2650 | .in3(din3[65:0]), |
| 2651 | .in4(din4[65:0]), |
| 2652 | .in5(din5[65:0]), |
| 2653 | .in6(din6[65:0]), |
| 2654 | .in7(din7[65:0]), |
| 2655 | .dout(dout[65:0]) |
| 2656 | ); |
| 2657 | |
| 2658 | |
| 2659 | |
| 2660 | |
| 2661 | |
| 2662 | |
| 2663 | |
| 2664 | |
| 2665 | |
| 2666 | |
| 2667 | |
| 2668 | |
| 2669 | |
| 2670 | endmodule |
| 2671 | |
| 2672 | |
| 2673 | // |
| 2674 | // buff macro |
| 2675 | // |
| 2676 | // |
| 2677 | |
| 2678 | |
| 2679 | |
| 2680 | |
| 2681 | |
| 2682 | module gkt_ipd_dp_buff_macro__stack_66c__width_40 ( |
| 2683 | din, |
| 2684 | dout); |
| 2685 | input [39:0] din; |
| 2686 | output [39:0] dout; |
| 2687 | |
| 2688 | |
| 2689 | |
| 2690 | |
| 2691 | |
| 2692 | |
| 2693 | buff #(40) d0_0 ( |
| 2694 | .in(din[39:0]), |
| 2695 | .out(dout[39:0]) |
| 2696 | ); |
| 2697 | |
| 2698 | |
| 2699 | |
| 2700 | |
| 2701 | |
| 2702 | |
| 2703 | |
| 2704 | |
| 2705 | endmodule |
| 2706 | |
| 2707 | |
| 2708 | |
| 2709 | |
| 2710 | |
| 2711 | |
| 2712 | |
| 2713 | |
| 2714 | |
| 2715 | // any PARAMS parms go into naming of macro |
| 2716 | |
| 2717 | module gkt_ipd_dp_msff_macro__stack_64c__width_1 ( |
| 2718 | din, |
| 2719 | clk, |
| 2720 | en, |
| 2721 | se, |
| 2722 | scan_in, |
| 2723 | siclk, |
| 2724 | soclk, |
| 2725 | pce_ov, |
| 2726 | stop, |
| 2727 | dout, |
| 2728 | scan_out); |
| 2729 | wire l1clk; |
| 2730 | wire siclk_out; |
| 2731 | wire soclk_out; |
| 2732 | |
| 2733 | input [0:0] din; |
| 2734 | |
| 2735 | |
| 2736 | input clk; |
| 2737 | input en; |
| 2738 | input se; |
| 2739 | input scan_in; |
| 2740 | input siclk; |
| 2741 | input soclk; |
| 2742 | input pce_ov; |
| 2743 | input stop; |
| 2744 | |
| 2745 | |
| 2746 | |
| 2747 | output [0:0] dout; |
| 2748 | |
| 2749 | |
| 2750 | output scan_out; |
| 2751 | |
| 2752 | |
| 2753 | |
| 2754 | |
| 2755 | cl_dp1_l1hdr_8x c0_0 ( |
| 2756 | .l2clk(clk), |
| 2757 | .pce(en), |
| 2758 | .aclk(siclk), |
| 2759 | .bclk(soclk), |
| 2760 | .l1clk(l1clk), |
| 2761 | .se(se), |
| 2762 | .pce_ov(pce_ov), |
| 2763 | .stop(stop), |
| 2764 | .siclk_out(siclk_out), |
| 2765 | .soclk_out(soclk_out) |
| 2766 | ); |
| 2767 | dff #(1) d0_0 ( |
| 2768 | .l1clk(l1clk), |
| 2769 | .siclk(siclk_out), |
| 2770 | .soclk(soclk_out), |
| 2771 | .d(din[0:0]), |
| 2772 | .si(scan_in), |
| 2773 | .so(scan_out), |
| 2774 | .q(dout[0:0]) |
| 2775 | ); |
| 2776 | |
| 2777 | |
| 2778 | |
| 2779 | |
| 2780 | |
| 2781 | |
| 2782 | |
| 2783 | |
| 2784 | |
| 2785 | |
| 2786 | |
| 2787 | |
| 2788 | |
| 2789 | |
| 2790 | |
| 2791 | |
| 2792 | |
| 2793 | |
| 2794 | |
| 2795 | |
| 2796 | endmodule |
| 2797 | |
| 2798 | |
| 2799 | |
| 2800 | |
| 2801 | |
| 2802 | |
| 2803 | |
| 2804 | |
| 2805 | |
| 2806 | // |
| 2807 | // invert macro |
| 2808 | // |
| 2809 | // |
| 2810 | |
| 2811 | |
| 2812 | |
| 2813 | |
| 2814 | |
| 2815 | module gkt_ipd_dp_inv_macro__stack_64c__width_1 ( |
| 2816 | din, |
| 2817 | dout); |
| 2818 | input [0:0] din; |
| 2819 | output [0:0] dout; |
| 2820 | |
| 2821 | |
| 2822 | |
| 2823 | |
| 2824 | |
| 2825 | |
| 2826 | inv #(1) d0_0 ( |
| 2827 | .in(din[0:0]), |
| 2828 | .out(dout[0:0]) |
| 2829 | ); |
| 2830 | |
| 2831 | |
| 2832 | |
| 2833 | |
| 2834 | |
| 2835 | |
| 2836 | |
| 2837 | |
| 2838 | |
| 2839 | endmodule |
| 2840 | |
| 2841 | |
| 2842 | |
| 2843 | |
| 2844 | |
| 2845 | // |
| 2846 | // nor macro for ports = 2,3 |
| 2847 | // |
| 2848 | // |
| 2849 | |
| 2850 | |
| 2851 | |
| 2852 | |
| 2853 | |
| 2854 | module gkt_ipd_dp_nor_macro__stack_66c__width_1 ( |
| 2855 | din0, |
| 2856 | din1, |
| 2857 | dout); |
| 2858 | input [0:0] din0; |
| 2859 | input [0:0] din1; |
| 2860 | output [0:0] dout; |
| 2861 | |
| 2862 | |
| 2863 | |
| 2864 | |
| 2865 | |
| 2866 | |
| 2867 | nor2 #(1) d0_0 ( |
| 2868 | .in0(din0[0:0]), |
| 2869 | .in1(din1[0:0]), |
| 2870 | .out(dout[0:0]) |
| 2871 | ); |
| 2872 | |
| 2873 | |
| 2874 | |
| 2875 | |
| 2876 | |
| 2877 | |
| 2878 | |
| 2879 | endmodule |
| 2880 | |
| 2881 | |
| 2882 | |
| 2883 | |
| 2884 | |
| 2885 | // |
| 2886 | // xor macro for ports = 2,3 |
| 2887 | // |
| 2888 | // |
| 2889 | |
| 2890 | |
| 2891 | |
| 2892 | |
| 2893 | |
| 2894 | module gkt_ipd_dp_xor_macro__ports_2__stack_66c__width_7 ( |
| 2895 | din0, |
| 2896 | din1, |
| 2897 | dout); |
| 2898 | input [6:0] din0; |
| 2899 | input [6:0] din1; |
| 2900 | output [6:0] dout; |
| 2901 | |
| 2902 | |
| 2903 | |
| 2904 | |
| 2905 | |
| 2906 | xor2 #(7) d0_0 ( |
| 2907 | .in0(din0[6:0]), |
| 2908 | .in1(din1[6:0]), |
| 2909 | .out(dout[6:0]) |
| 2910 | ); |
| 2911 | |
| 2912 | |
| 2913 | |
| 2914 | |
| 2915 | |
| 2916 | |
| 2917 | |
| 2918 | |
| 2919 | endmodule |
| 2920 | |
| 2921 | |
| 2922 | |
| 2923 | |
| 2924 | |
| 2925 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2926 | // also for pass-gate with decoder |
| 2927 | |
| 2928 | |
| 2929 | |
| 2930 | |
| 2931 | |
| 2932 | // any PARAMS parms go into naming of macro |
| 2933 | |
| 2934 | module gkt_ipd_dp_mux_macro__mux_aope__ports_2__stack_66c__width_7 ( |
| 2935 | din0, |
| 2936 | din1, |
| 2937 | sel0, |
| 2938 | dout); |
| 2939 | wire psel0; |
| 2940 | wire psel1; |
| 2941 | |
| 2942 | input [6:0] din0; |
| 2943 | input [6:0] din1; |
| 2944 | input sel0; |
| 2945 | output [6:0] dout; |
| 2946 | |
| 2947 | |
| 2948 | |
| 2949 | |
| 2950 | |
| 2951 | cl_dp1_penc2_8x c0_0 ( |
| 2952 | .sel0(sel0), |
| 2953 | .psel0(psel0), |
| 2954 | .psel1(psel1) |
| 2955 | ); |
| 2956 | |
| 2957 | mux2s #(7) d0_0 ( |
| 2958 | .sel0(psel0), |
| 2959 | .sel1(psel1), |
| 2960 | .in0(din0[6:0]), |
| 2961 | .in1(din1[6:0]), |
| 2962 | .dout(dout[6:0]) |
| 2963 | ); |
| 2964 | |
| 2965 | |
| 2966 | |
| 2967 | |
| 2968 | |
| 2969 | |
| 2970 | |
| 2971 | |
| 2972 | |
| 2973 | |
| 2974 | |
| 2975 | |
| 2976 | |
| 2977 | endmodule |
| 2978 | |
| 2979 | |
| 2980 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2981 | // also for pass-gate with decoder |
| 2982 | |
| 2983 | |
| 2984 | |
| 2985 | |
| 2986 | |
| 2987 | // any PARAMS parms go into naming of macro |
| 2988 | |
| 2989 | module gkt_ipd_dp_mux_macro__mux_aonpe__ports_4__stack_64c__width_64 ( |
| 2990 | din0, |
| 2991 | sel0, |
| 2992 | din1, |
| 2993 | sel1, |
| 2994 | din2, |
| 2995 | sel2, |
| 2996 | din3, |
| 2997 | sel3, |
| 2998 | dout); |
| 2999 | wire buffout0; |
| 3000 | wire buffout1; |
| 3001 | wire buffout2; |
| 3002 | wire buffout3; |
| 3003 | |
| 3004 | input [63:0] din0; |
| 3005 | input sel0; |
| 3006 | input [63:0] din1; |
| 3007 | input sel1; |
| 3008 | input [63:0] din2; |
| 3009 | input sel2; |
| 3010 | input [63:0] din3; |
| 3011 | input sel3; |
| 3012 | output [63:0] dout; |
| 3013 | |
| 3014 | |
| 3015 | |
| 3016 | |
| 3017 | |
| 3018 | cl_dp1_muxbuff4_8x c0_0 ( |
| 3019 | .in0(sel0), |
| 3020 | .in1(sel1), |
| 3021 | .in2(sel2), |
| 3022 | .in3(sel3), |
| 3023 | .out0(buffout0), |
| 3024 | .out1(buffout1), |
| 3025 | .out2(buffout2), |
| 3026 | .out3(buffout3) |
| 3027 | ); |
| 3028 | mux4s #(64) d0_0 ( |
| 3029 | .sel0(buffout0), |
| 3030 | .sel1(buffout1), |
| 3031 | .sel2(buffout2), |
| 3032 | .sel3(buffout3), |
| 3033 | .in0(din0[63:0]), |
| 3034 | .in1(din1[63:0]), |
| 3035 | .in2(din2[63:0]), |
| 3036 | .in3(din3[63:0]), |
| 3037 | .dout(dout[63:0]) |
| 3038 | ); |
| 3039 | |
| 3040 | |
| 3041 | |
| 3042 | |
| 3043 | |
| 3044 | |
| 3045 | |
| 3046 | |
| 3047 | |
| 3048 | |
| 3049 | |
| 3050 | |
| 3051 | |
| 3052 | endmodule |
| 3053 | |
| 3054 | |
| 3055 | |
| 3056 | |
| 3057 | |
| 3058 | |
| 3059 | // any PARAMS parms go into naming of macro |
| 3060 | |
| 3061 | module gkt_ipd_dp_msff_macro__dmsff_8x__stack_66c__width_66 ( |
| 3062 | din, |
| 3063 | clk, |
| 3064 | en, |
| 3065 | se, |
| 3066 | scan_in, |
| 3067 | siclk, |
| 3068 | soclk, |
| 3069 | pce_ov, |
| 3070 | stop, |
| 3071 | dout, |
| 3072 | scan_out); |
| 3073 | wire l1clk; |
| 3074 | wire siclk_out; |
| 3075 | wire soclk_out; |
| 3076 | wire [64:0] so; |
| 3077 | |
| 3078 | input [65:0] din; |
| 3079 | |
| 3080 | |
| 3081 | input clk; |
| 3082 | input en; |
| 3083 | input se; |
| 3084 | input scan_in; |
| 3085 | input siclk; |
| 3086 | input soclk; |
| 3087 | input pce_ov; |
| 3088 | input stop; |
| 3089 | |
| 3090 | |
| 3091 | |
| 3092 | output [65:0] dout; |
| 3093 | |
| 3094 | |
| 3095 | output scan_out; |
| 3096 | |
| 3097 | |
| 3098 | |
| 3099 | |
| 3100 | cl_dp1_l1hdr_8x c0_0 ( |
| 3101 | .l2clk(clk), |
| 3102 | .pce(en), |
| 3103 | .aclk(siclk), |
| 3104 | .bclk(soclk), |
| 3105 | .l1clk(l1clk), |
| 3106 | .se(se), |
| 3107 | .pce_ov(pce_ov), |
| 3108 | .stop(stop), |
| 3109 | .siclk_out(siclk_out), |
| 3110 | .soclk_out(soclk_out) |
| 3111 | ); |
| 3112 | dff #(66) d0_0 ( |
| 3113 | .l1clk(l1clk), |
| 3114 | .siclk(siclk_out), |
| 3115 | .soclk(soclk_out), |
| 3116 | .d(din[65:0]), |
| 3117 | .si({scan_in,so[64:0]}), |
| 3118 | .so({so[64:0],scan_out}), |
| 3119 | .q(dout[65:0]) |
| 3120 | ); |
| 3121 | |
| 3122 | |
| 3123 | |
| 3124 | |
| 3125 | |
| 3126 | |
| 3127 | |
| 3128 | |
| 3129 | |
| 3130 | |
| 3131 | |
| 3132 | |
| 3133 | |
| 3134 | |
| 3135 | |
| 3136 | |
| 3137 | |
| 3138 | |
| 3139 | |
| 3140 | |
| 3141 | endmodule |
| 3142 | |
| 3143 | |
| 3144 | |
| 3145 | |
| 3146 | |
| 3147 | |
| 3148 | |
| 3149 | |
| 3150 | |
| 3151 | // |
| 3152 | // buff macro |
| 3153 | // |
| 3154 | // |
| 3155 | |
| 3156 | |
| 3157 | |
| 3158 | |
| 3159 | |
| 3160 | module gkt_ipd_dp_buff_macro__dbuff_32x__rep_1__stack_66c__width_66 ( |
| 3161 | din, |
| 3162 | dout); |
| 3163 | input [65:0] din; |
| 3164 | output [65:0] dout; |
| 3165 | |
| 3166 | |
| 3167 | |
| 3168 | |
| 3169 | |
| 3170 | |
| 3171 | buff #(66) d0_0 ( |
| 3172 | .in(din[65:0]), |
| 3173 | .out(dout[65:0]) |
| 3174 | ); |
| 3175 | |
| 3176 | |
| 3177 | |
| 3178 | |
| 3179 | |
| 3180 | |
| 3181 | |
| 3182 | |
| 3183 | endmodule |
| 3184 | |
| 3185 | |
| 3186 | |
| 3187 | |
| 3188 | |
| 3189 | // |
| 3190 | // buff macro |
| 3191 | // |
| 3192 | // |
| 3193 | |
| 3194 | |
| 3195 | |
| 3196 | |
| 3197 | |
| 3198 | module gkt_ipd_dp_buff_macro__stack_none__width_9 ( |
| 3199 | din, |
| 3200 | dout); |
| 3201 | input [8:0] din; |
| 3202 | output [8:0] dout; |
| 3203 | |
| 3204 | |
| 3205 | |
| 3206 | |
| 3207 | |
| 3208 | |
| 3209 | buff #(9) d0_0 ( |
| 3210 | .in(din[8:0]), |
| 3211 | .out(dout[8:0]) |
| 3212 | ); |
| 3213 | |
| 3214 | |
| 3215 | |
| 3216 | |
| 3217 | |
| 3218 | |
| 3219 | |
| 3220 | |
| 3221 | endmodule |
| 3222 | |
| 3223 | |
| 3224 | |
| 3225 | |
| 3226 | |
| 3227 | |
| 3228 | |
| 3229 | |
| 3230 | |
| 3231 | // any PARAMS parms go into naming of macro |
| 3232 | |
| 3233 | module gkt_ipd_dp_msff_macro__dmsff_8x__stack_64c__width_64 ( |
| 3234 | din, |
| 3235 | clk, |
| 3236 | en, |
| 3237 | se, |
| 3238 | scan_in, |
| 3239 | siclk, |
| 3240 | soclk, |
| 3241 | pce_ov, |
| 3242 | stop, |
| 3243 | dout, |
| 3244 | scan_out); |
| 3245 | wire l1clk; |
| 3246 | wire siclk_out; |
| 3247 | wire soclk_out; |
| 3248 | wire [62:0] so; |
| 3249 | |
| 3250 | input [63:0] din; |
| 3251 | |
| 3252 | |
| 3253 | input clk; |
| 3254 | input en; |
| 3255 | input se; |
| 3256 | input scan_in; |
| 3257 | input siclk; |
| 3258 | input soclk; |
| 3259 | input pce_ov; |
| 3260 | input stop; |
| 3261 | |
| 3262 | |
| 3263 | |
| 3264 | output [63:0] dout; |
| 3265 | |
| 3266 | |
| 3267 | output scan_out; |
| 3268 | |
| 3269 | |
| 3270 | |
| 3271 | |
| 3272 | cl_dp1_l1hdr_8x c0_0 ( |
| 3273 | .l2clk(clk), |
| 3274 | .pce(en), |
| 3275 | .aclk(siclk), |
| 3276 | .bclk(soclk), |
| 3277 | .l1clk(l1clk), |
| 3278 | .se(se), |
| 3279 | .pce_ov(pce_ov), |
| 3280 | .stop(stop), |
| 3281 | .siclk_out(siclk_out), |
| 3282 | .soclk_out(soclk_out) |
| 3283 | ); |
| 3284 | dff #(64) d0_0 ( |
| 3285 | .l1clk(l1clk), |
| 3286 | .siclk(siclk_out), |
| 3287 | .soclk(soclk_out), |
| 3288 | .d(din[63:0]), |
| 3289 | .si({scan_in,so[62:0]}), |
| 3290 | .so({so[62:0],scan_out}), |
| 3291 | .q(dout[63:0]) |
| 3292 | ); |
| 3293 | |
| 3294 | |
| 3295 | |
| 3296 | |
| 3297 | |
| 3298 | |
| 3299 | |
| 3300 | |
| 3301 | |
| 3302 | |
| 3303 | |
| 3304 | |
| 3305 | |
| 3306 | |
| 3307 | |
| 3308 | |
| 3309 | |
| 3310 | |
| 3311 | |
| 3312 | |
| 3313 | endmodule |
| 3314 | |
| 3315 | |
| 3316 | |
| 3317 | |
| 3318 | |
| 3319 | |
| 3320 | |
| 3321 | |
| 3322 | |
| 3323 | // |
| 3324 | // buff macro |
| 3325 | // |
| 3326 | // |
| 3327 | |
| 3328 | |
| 3329 | |
| 3330 | |
| 3331 | |
| 3332 | module gkt_ipd_dp_buff_macro__dbuff_32x__rep_1__stack_64c__width_64 ( |
| 3333 | din, |
| 3334 | dout); |
| 3335 | input [63:0] din; |
| 3336 | output [63:0] dout; |
| 3337 | |
| 3338 | |
| 3339 | |
| 3340 | |
| 3341 | |
| 3342 | |
| 3343 | buff #(64) d0_0 ( |
| 3344 | .in(din[63:0]), |
| 3345 | .out(dout[63:0]) |
| 3346 | ); |
| 3347 | |
| 3348 | |
| 3349 | |
| 3350 | |
| 3351 | |
| 3352 | |
| 3353 | |
| 3354 | |
| 3355 | endmodule |
| 3356 | |
| 3357 | |
| 3358 | |
| 3359 | |