| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: ifu_ftu_agd_dp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module ifu_ftu_agd_dp ( |
| 36 | tcu_scan_en, |
| 37 | l2clk, |
| 38 | scan_in, |
| 39 | tcu_pce_ov, |
| 40 | spc_aclk, |
| 41 | spc_bclk, |
| 42 | tcu_muxtest, |
| 43 | mbi_addr, |
| 44 | mbi_cmpsel, |
| 45 | mbi_wdata, |
| 46 | mbi_icv_read_en, |
| 47 | ftp_thr0_trprdpc_sel_bf, |
| 48 | ftp_thr1_trprdpc_sel_bf, |
| 49 | ftp_thr2_trprdpc_sel_bf, |
| 50 | ftp_thr3_trprdpc_sel_bf, |
| 51 | ftp_thr4_trprdpc_sel_bf, |
| 52 | ftp_thr5_trprdpc_sel_bf, |
| 53 | ftp_thr6_trprdpc_sel_bf, |
| 54 | ftp_thr7_trprdpc_sel_bf, |
| 55 | agc_thr0_pcf_sel_bf, |
| 56 | agc_thr1_pcf_sel_bf, |
| 57 | agc_thr2_pcf_sel_bf, |
| 58 | agc_thr3_pcf_sel_bf, |
| 59 | agc_thr4_pcf_sel_bf, |
| 60 | agc_thr5_pcf_sel_bf, |
| 61 | agc_thr6_pcf_sel_bf, |
| 62 | agc_thr7_pcf_sel_bf, |
| 63 | agc_thr0_pcf_sel_last_bf, |
| 64 | agc_thr1_pcf_sel_last_bf, |
| 65 | agc_thr2_pcf_sel_last_bf, |
| 66 | agc_thr3_pcf_sel_last_bf, |
| 67 | agc_thr4_pcf_sel_last_bf, |
| 68 | agc_thr5_pcf_sel_last_bf, |
| 69 | agc_thr6_pcf_sel_last_bf, |
| 70 | agc_thr7_pcf_sel_last_bf, |
| 71 | ftp_thr0_sel_br_bf, |
| 72 | ftp_thr1_sel_br_bf, |
| 73 | ftp_thr2_sel_br_bf, |
| 74 | ftp_thr3_sel_br_bf, |
| 75 | ftp_thr4_sel_br_bf, |
| 76 | ftp_thr5_sel_br_bf, |
| 77 | ftp_thr6_sel_br_bf, |
| 78 | ftp_thr7_sel_br_bf, |
| 79 | agc_sel_inv_index, |
| 80 | agc_pc_sel_for_c, |
| 81 | icv_valid_f, |
| 82 | asi_addr_bf, |
| 83 | agc_thr0_byp_incr_bit5, |
| 84 | agc_thr1_byp_incr_bit5, |
| 85 | agc_thr2_byp_incr_bit5, |
| 86 | agc_thr3_byp_incr_bit5, |
| 87 | agc_thr4_byp_incr_bit5, |
| 88 | agc_thr5_byp_incr_bit5, |
| 89 | agc_thr6_byp_incr_bit5, |
| 90 | agc_thr7_byp_incr_bit5, |
| 91 | agc_thr0_byp_pc_update_bf, |
| 92 | agc_thr1_byp_pc_update_bf, |
| 93 | agc_thr2_byp_pc_update_bf, |
| 94 | agc_thr3_byp_pc_update_bf, |
| 95 | agc_thr4_byp_pc_update_bf, |
| 96 | agc_thr5_byp_pc_update_bf, |
| 97 | agc_thr6_byp_pc_update_bf, |
| 98 | agc_thr7_byp_pc_update_bf, |
| 99 | ftp_new_thr_sel_bf, |
| 100 | ftp_ict_data_sel_bf, |
| 101 | ftp_pc_sel_am, |
| 102 | ftp_pc_sel_tag_part1, |
| 103 | ftp_pc_sel_tag_part2, |
| 104 | ftp_pc_sel_tag_pc_bot, |
| 105 | ftp_pc_sel_tag_pc_top, |
| 106 | ftp_any_thr_clken, |
| 107 | ftp_sel_icv_mbist_addr, |
| 108 | ftp_icaddr_sel_first_mux, |
| 109 | tlu_trap_pc_0, |
| 110 | tlu_trap_pc_1, |
| 111 | itc_va, |
| 112 | exu_address0_e, |
| 113 | exu_address1_e, |
| 114 | tlu_npc_w, |
| 115 | cmu_fill_paddr, |
| 116 | asi_wr_data, |
| 117 | cmu_icache_invalidate_index, |
| 118 | cmu_thr0_data_ready, |
| 119 | cmu_thr1_data_ready, |
| 120 | cmu_thr2_data_ready, |
| 121 | cmu_thr3_data_ready, |
| 122 | cmu_thr4_data_ready, |
| 123 | cmu_thr5_data_ready, |
| 124 | cmu_thr6_data_ready, |
| 125 | cmu_thr7_data_ready, |
| 126 | agd_direct_map_rep_way, |
| 127 | agd_itlb_valid_f, |
| 128 | agd_itlb_valid_fast_f, |
| 129 | agd_itlb_valid_dupl_f, |
| 130 | ifu_agd_pc_bf, |
| 131 | agd_ict_index_bf, |
| 132 | agd_ic_index_bf, |
| 133 | agd_icv_windex_bf, |
| 134 | ifu_agd_pc_f, |
| 135 | agd_thr0_pc_4_2_f, |
| 136 | agd_thr1_pc_4_2_f, |
| 137 | agd_thr2_pc_4_2_f, |
| 138 | agd_thr3_pc_4_2_f, |
| 139 | agd_thr4_pc_4_2_f, |
| 140 | agd_thr5_pc_4_2_f, |
| 141 | agd_thr6_pc_4_2_f, |
| 142 | agd_thr7_pc_4_2_f, |
| 143 | agd_ict_wrtag_bf, |
| 144 | agd_asi_bist_wrdata, |
| 145 | agd_mbist_wdata_bf, |
| 146 | ftu_paddr, |
| 147 | ftu_mbi_icv_fail, |
| 148 | agd_va_hole_excp_f, |
| 149 | agd_address0_m, |
| 150 | agd_address1_m, |
| 151 | scan_out); |
| 152 | wire stop; |
| 153 | wire se; |
| 154 | wire pce_ov; |
| 155 | wire siclk; |
| 156 | wire soclk; |
| 157 | wire br_address0_m_reg0_scanin; |
| 158 | wire br_address0_m_reg0_scanout; |
| 159 | wire [47:0] address0_m; |
| 160 | wire br_address0_m_reg1_scanin; |
| 161 | wire br_address0_m_reg1_scanout; |
| 162 | wire [47:0] address0_m_rep0; |
| 163 | wire br_address1_m_reg0_scanin; |
| 164 | wire br_address1_m_reg0_scanout; |
| 165 | wire [47:0] address1_m; |
| 166 | wire br_address1_m_reg1_scanin; |
| 167 | wire br_address1_m_reg1_scanout; |
| 168 | wire [47:0] address1_m_rep0; |
| 169 | wire [48:0] pc_c; |
| 170 | wire [48:0] thr0_trap_rd_pc_bf; |
| 171 | wire [48:0] thr1_trap_rd_pc_bf; |
| 172 | wire [48:0] thr2_trap_rd_pc_bf; |
| 173 | wire [48:0] thr3_trap_rd_pc_bf; |
| 174 | wire [48:0] thr4_trap_rd_pc_bf; |
| 175 | wire [48:0] thr5_trap_rd_pc_bf; |
| 176 | wire [48:0] thr6_trap_rd_pc_bf; |
| 177 | wire [48:0] thr7_trap_rd_pc_bf; |
| 178 | wire [48:0] curr_thr_pc_bf; |
| 179 | wire [48:0] by_pass_pc_update_bf; |
| 180 | wire [48:0] thr0_pc_f; |
| 181 | wire [48:0] thr0_pc_before_last_bf; |
| 182 | wire [48:0] next_thr0_pc_bf; |
| 183 | wire [48:0] thr1_pc_f; |
| 184 | wire [48:0] thr1_pc_before_last_bf; |
| 185 | wire [48:0] next_thr1_pc_bf; |
| 186 | wire [48:0] thr2_pc_f; |
| 187 | wire [48:0] thr2_pc_before_last_bf; |
| 188 | wire [48:0] next_thr2_pc_bf; |
| 189 | wire [48:0] thr3_pc_f; |
| 190 | wire [48:0] thr3_pc_before_last_bf; |
| 191 | wire [48:0] next_thr3_pc_bf; |
| 192 | wire [48:0] thr4_pc_f; |
| 193 | wire [48:0] thr4_pc_before_last_bf; |
| 194 | wire [48:0] next_thr4_pc_bf; |
| 195 | wire [48:0] thr5_pc_f; |
| 196 | wire [48:0] thr5_pc_before_last_bf; |
| 197 | wire [48:0] next_thr5_pc_bf; |
| 198 | wire [48:0] thr6_pc_f; |
| 199 | wire [48:0] thr6_pc_before_last_bf; |
| 200 | wire [48:0] next_thr6_pc_bf; |
| 201 | wire [48:0] thr7_pc_f; |
| 202 | wire [48:0] thr7_pc_before_last_bf; |
| 203 | wire [48:0] next_thr7_pc_bf; |
| 204 | wire thr0_pc_f_reg_scanin; |
| 205 | wire thr0_pc_f_reg_scanout; |
| 206 | wire thr1_pc_f_reg_scanin; |
| 207 | wire thr1_pc_f_reg_scanout; |
| 208 | wire thr2_pc_f_reg_scanin; |
| 209 | wire thr2_pc_f_reg_scanout; |
| 210 | wire thr3_pc_f_reg_scanin; |
| 211 | wire thr3_pc_f_reg_scanout; |
| 212 | wire thr4_pc_f_reg_scanin; |
| 213 | wire thr4_pc_f_reg_scanout; |
| 214 | wire thr5_pc_f_reg_scanin; |
| 215 | wire thr5_pc_f_reg_scanout; |
| 216 | wire thr6_pc_f_reg_scanin; |
| 217 | wire thr6_pc_f_reg_scanout; |
| 218 | wire thr7_pc_f_reg_scanin; |
| 219 | wire thr7_pc_f_reg_scanout; |
| 220 | wire [48:2] inc_pc_bf; |
| 221 | wire [10:5] curr_thr_pc_crit_bf; |
| 222 | wire [10:5] inc_pc_crit_bf; |
| 223 | wire [48:0] thr0_pc_muxed_f; |
| 224 | wire [48:0] thr1_pc_muxed_f; |
| 225 | wire [48:0] thr2_pc_muxed_f; |
| 226 | wire [48:0] thr3_pc_muxed_f; |
| 227 | wire [48:0] thr4_pc_muxed_f; |
| 228 | wire [48:0] thr5_pc_muxed_f; |
| 229 | wire [48:0] thr6_pc_muxed_f; |
| 230 | wire [48:0] thr7_pc_muxed_f; |
| 231 | wire [48:0] new_thr_pc_bf; |
| 232 | wire tcu_muxtest_rep1; |
| 233 | wire [48:0] next_pc_bf; |
| 234 | wire [47:13] pc_tag_1; |
| 235 | wire [47:13] pc_tag; |
| 236 | wire [47:13] pc_tag_buf; |
| 237 | wire pc_f_reg_scanin; |
| 238 | wire pc_f_reg_scanout; |
| 239 | wire [48:0] pc_f; |
| 240 | wire [1:0] pc_f_unused; |
| 241 | wire pc_f_incr; |
| 242 | wire inc_pc_f_top_data; |
| 243 | wire [1:0] nc_crit_unused; |
| 244 | wire inc_crit_cout_unused; |
| 245 | wire [52:48] pc_f_1_unused; |
| 246 | wire [48:37] inc_pc_bf_top_inc; |
| 247 | wire pc_f_2_unused; |
| 248 | wire [47:47] pc_f_; |
| 249 | wire [52:49] pc_f_3_unused; |
| 250 | wire [48:2] by_pass_pc_addr_to_buf; |
| 251 | wire by_pass_pc_addr_bf_incr_to_buf; |
| 252 | wire [48:2] by_pass_inc_pc_bf; |
| 253 | wire inc_by_pass_pc_addr_bf_top_data; |
| 254 | wire [52:48] by_pass_pc_addr_bf_1_unused; |
| 255 | wire [48:37] by_pass_inc_pc_bf_top_inc; |
| 256 | wire by_pass_pc_addr_bf_2_unused; |
| 257 | wire [48:2] by_pass_pc_addr_bf; |
| 258 | wire [47:47] by_pass_pc_addr_bf_; |
| 259 | wire [52:49] by_pass_pc_addr_bf_3_unused; |
| 260 | wire [5:0] agd_mbist_addr_bf; |
| 261 | wire [2:0] agd_mbist_cmpsel_bf; |
| 262 | wire [10:0] mbist_addr_muxed; |
| 263 | wire tcu_muxtest_rep2; |
| 264 | wire [10:2] curr_thr_pc_bf_del; |
| 265 | wire [39:5] phys_addr_bf; |
| 266 | wire [1:0] agd_ic_index_bf_unused; |
| 267 | wire tcu_muxtest_rep4; |
| 268 | wire mbist_in_reg_scanin; |
| 269 | wire mbist_in_reg_scanout; |
| 270 | wire [7:0] agd_mbist_wdata_f; |
| 271 | wire mbi_icv_read_en_bf; |
| 272 | wire mbi_icv_read_en_f; |
| 273 | wire [7:0] agd_mbist_wdata_c; |
| 274 | wire mbi_icv_read_en_c; |
| 275 | wire [10:6] inv_addr_bf; |
| 276 | wire [48:0] pc_wo_by_pass_c; |
| 277 | wire [48:2] by_pass_pc_addr_f; |
| 278 | wire [48:2] by_pass_pc_addr_c; |
| 279 | wire [48:2] pc_c_to_buf; |
| 280 | wire pc_wo_by_pass_c_reg_scanin; |
| 281 | wire pc_wo_by_pass_c_reg_scanout; |
| 282 | wire by_pass_sel_reg_scanin; |
| 283 | wire by_pass_sel_reg_scanout; |
| 284 | wire [7:0] by_pass_sel_bf; |
| 285 | wire [4:2] by_pass_inc_pc_to_buf; |
| 286 | wire by_pass_pc_f_reg_scanin; |
| 287 | wire by_pass_pc_f_reg_scanout; |
| 288 | wire by_pass_pc_c_reg_scanin; |
| 289 | wire by_pass_pc_c_reg_scanout; |
| 290 | wire phys_addr_bf_reg_scanin; |
| 291 | wire phys_addr_bf_reg_scanout; |
| 292 | wire [3:0] tag_parity; |
| 293 | wire ic_tag_parity; |
| 294 | wire inv_addr_bf_reg_scanin; |
| 295 | wire inv_addr_bf_reg_scanout; |
| 296 | wire [5:5] agd_ic_index_f; |
| 297 | wire [7:0] itlb_valid_dupl_f; |
| 298 | wire tcu_muxtest_rep3; |
| 299 | wire tag_data_29_nand_0; |
| 300 | wire tag_data_29_nand_1; |
| 301 | wire tag_data_29_nand_2; |
| 302 | wire tag_data_29; |
| 303 | wire valid_c_reg_a_scanin; |
| 304 | wire valid_c_reg_a_scanout; |
| 305 | wire [31:0] icv_valid_c; |
| 306 | wire valid_c_reg_b_scanin; |
| 307 | wire valid_c_reg_b_scanout; |
| 308 | wire agd_icv_fail_l; |
| 309 | wire agd_icv_fail; |
| 310 | |
| 311 | |
| 312 | input tcu_scan_en; |
| 313 | input l2clk; |
| 314 | input scan_in; |
| 315 | input tcu_pce_ov; // scan signals |
| 316 | input spc_aclk; |
| 317 | input spc_bclk; |
| 318 | input tcu_muxtest; |
| 319 | input [5:0] mbi_addr; |
| 320 | input [2:0] mbi_cmpsel; |
| 321 | input [7:0] mbi_wdata; |
| 322 | input mbi_icv_read_en; |
| 323 | |
| 324 | input [2:0] ftp_thr0_trprdpc_sel_bf; // 0in bits_on -max 1 |
| 325 | input [2:0] ftp_thr1_trprdpc_sel_bf; // 0in bits_on -max 1 |
| 326 | input [2:0] ftp_thr2_trprdpc_sel_bf; // 0in bits_on -max 1 |
| 327 | input [2:0] ftp_thr3_trprdpc_sel_bf; // 0in bits_on -max 1 |
| 328 | input [2:0] ftp_thr4_trprdpc_sel_bf; // 0in bits_on -max 1 |
| 329 | input [2:0] ftp_thr5_trprdpc_sel_bf; // 0in bits_on -max 1 |
| 330 | input [2:0] ftp_thr6_trprdpc_sel_bf; // 0in bits_on -max 1 |
| 331 | input [2:0] ftp_thr7_trprdpc_sel_bf; // 0in bits_on -max 1 |
| 332 | |
| 333 | input [3:0] agc_thr0_pcf_sel_bf; // 0in one_hot |
| 334 | input [3:0] agc_thr1_pcf_sel_bf; // 0in one_hot |
| 335 | input [3:0] agc_thr2_pcf_sel_bf; // 0in one_hot |
| 336 | input [3:0] agc_thr3_pcf_sel_bf; // 0in one_hot |
| 337 | input [3:0] agc_thr4_pcf_sel_bf; // 0in one_hot |
| 338 | input [3:0] agc_thr5_pcf_sel_bf; // 0in one_hot |
| 339 | input [3:0] agc_thr6_pcf_sel_bf; // 0in one_hot |
| 340 | input [3:0] agc_thr7_pcf_sel_bf; // 0in one_hot |
| 341 | |
| 342 | input [1:0] agc_thr0_pcf_sel_last_bf; // 0in one_hot |
| 343 | input [1:0] agc_thr1_pcf_sel_last_bf; // 0in one_hot |
| 344 | input [1:0] agc_thr2_pcf_sel_last_bf; // 0in one_hot |
| 345 | input [1:0] agc_thr3_pcf_sel_last_bf; // 0in one_hot |
| 346 | input [1:0] agc_thr4_pcf_sel_last_bf; // 0in one_hot |
| 347 | input [1:0] agc_thr5_pcf_sel_last_bf; // 0in one_hot |
| 348 | input [1:0] agc_thr6_pcf_sel_last_bf; // 0in one_hot |
| 349 | input [1:0] agc_thr7_pcf_sel_last_bf; // 0in one_hot |
| 350 | |
| 351 | input ftp_thr0_sel_br_bf ; |
| 352 | input ftp_thr1_sel_br_bf ; |
| 353 | input ftp_thr2_sel_br_bf ; |
| 354 | input ftp_thr3_sel_br_bf ; |
| 355 | input ftp_thr4_sel_br_bf ; |
| 356 | input ftp_thr5_sel_br_bf ; |
| 357 | input ftp_thr6_sel_br_bf ; |
| 358 | input ftp_thr7_sel_br_bf ; |
| 359 | |
| 360 | input [3:0] agc_sel_inv_index; // 0in bits_on -max 1 |
| 361 | |
| 362 | input [3:0] agc_pc_sel_for_c; // 0in bits_on -max 1 |
| 363 | |
| 364 | input [31:0] icv_valid_f; |
| 365 | input [39:3] asi_addr_bf; |
| 366 | |
| 367 | input agc_thr0_byp_incr_bit5 ; |
| 368 | input agc_thr1_byp_incr_bit5 ; |
| 369 | input agc_thr2_byp_incr_bit5 ; |
| 370 | input agc_thr3_byp_incr_bit5 ; |
| 371 | input agc_thr4_byp_incr_bit5 ; |
| 372 | input agc_thr5_byp_incr_bit5 ; |
| 373 | input agc_thr6_byp_incr_bit5 ; |
| 374 | input agc_thr7_byp_incr_bit5 ; |
| 375 | |
| 376 | input [4:2] agc_thr0_byp_pc_update_bf ; |
| 377 | input [4:2] agc_thr1_byp_pc_update_bf ; |
| 378 | input [4:2] agc_thr2_byp_pc_update_bf ; |
| 379 | input [4:2] agc_thr3_byp_pc_update_bf ; |
| 380 | input [4:2] agc_thr4_byp_pc_update_bf ; |
| 381 | input [4:2] agc_thr5_byp_pc_update_bf ; |
| 382 | input [4:2] agc_thr6_byp_pc_update_bf ; |
| 383 | input [4:2] agc_thr7_byp_pc_update_bf ; |
| 384 | |
| 385 | input [7:0] ftp_new_thr_sel_bf; |
| 386 | input [2:0] ftp_ict_data_sel_bf; |
| 387 | input [5:0] ftp_pc_sel_am; |
| 388 | input [2:0] ftp_pc_sel_tag_part1; |
| 389 | input [3:0] ftp_pc_sel_tag_part2; |
| 390 | input [1:0] ftp_pc_sel_tag_pc_bot; |
| 391 | input [1:0] ftp_pc_sel_tag_pc_top; |
| 392 | // input [4:0] agc_pc_sel_am_final; |
| 393 | input ftp_any_thr_clken; |
| 394 | |
| 395 | |
| 396 | |
| 397 | input ftp_sel_icv_mbist_addr; |
| 398 | input [4:0] ftp_icaddr_sel_first_mux; |
| 399 | // input [3:0] ftp_icaddr_sel_final_mux; |
| 400 | // input [4:0] ftp_icaddr_sel_nb0_nb1; |
| 401 | // input [4:0] ftp_icaddr_sel_b0_nb1; |
| 402 | // input [4:0] ftp_icaddr_sel_nb0_b1; |
| 403 | // input [4:0] ftp_icaddr_sel_b0_b1; |
| 404 | |
| 405 | // input dec_nb0_nb1_bf; |
| 406 | // input dec_b0_nb1_bf; |
| 407 | // input dec_nb0_b1_bf; |
| 408 | // input dec_b0_b1_bf; |
| 409 | |
| 410 | |
| 411 | input [47:2] tlu_trap_pc_0; |
| 412 | input [47:2] tlu_trap_pc_1; |
| 413 | |
| 414 | input [47:13] itc_va ; |
| 415 | |
| 416 | input [47:0] exu_address0_e; |
| 417 | input [47:0] exu_address1_e; |
| 418 | |
| 419 | input [47:2] tlu_npc_w; |
| 420 | |
| 421 | input [39:5] cmu_fill_paddr ; |
| 422 | input [32:0] asi_wr_data ; |
| 423 | input [10:6] cmu_icache_invalidate_index ; |
| 424 | input cmu_thr0_data_ready; |
| 425 | input cmu_thr1_data_ready; |
| 426 | input cmu_thr2_data_ready; |
| 427 | input cmu_thr3_data_ready; |
| 428 | input cmu_thr4_data_ready; |
| 429 | input cmu_thr5_data_ready; |
| 430 | input cmu_thr6_data_ready; |
| 431 | input cmu_thr7_data_ready; |
| 432 | |
| 433 | |
| 434 | |
| 435 | output [2:0] agd_direct_map_rep_way; |
| 436 | output [7:0] agd_itlb_valid_f; |
| 437 | output [7:0] agd_itlb_valid_fast_f; |
| 438 | output [7:0] agd_itlb_valid_dupl_f; |
| 439 | output [47:0] ifu_agd_pc_bf ; |
| 440 | |
| 441 | output [10:5] agd_ict_index_bf ; |
| 442 | output [10:2] agd_ic_index_bf ; |
| 443 | output [10:6] agd_icv_windex_bf ; |
| 444 | |
| 445 | output [47:2] ifu_agd_pc_f ; |
| 446 | output [4:2] agd_thr0_pc_4_2_f ; |
| 447 | output [4:2] agd_thr1_pc_4_2_f ; |
| 448 | output [4:2] agd_thr2_pc_4_2_f ; |
| 449 | output [4:2] agd_thr3_pc_4_2_f ; |
| 450 | output [4:2] agd_thr4_pc_4_2_f ; |
| 451 | output [4:2] agd_thr5_pc_4_2_f ; |
| 452 | output [4:2] agd_thr6_pc_4_2_f ; |
| 453 | output [4:2] agd_thr7_pc_4_2_f ; |
| 454 | |
| 455 | output [29:0] agd_ict_wrtag_bf; |
| 456 | output [32:0] agd_asi_bist_wrdata; |
| 457 | output [7:0] agd_mbist_wdata_bf; |
| 458 | output [12:0] ftu_paddr; |
| 459 | |
| 460 | output ftu_mbi_icv_fail; |
| 461 | output agd_va_hole_excp_f; |
| 462 | |
| 463 | output [4:2] agd_address0_m ; |
| 464 | output [4:2] agd_address1_m ; |
| 465 | |
| 466 | output scan_out; |
| 467 | |
| 468 | // assign pce_ov = tcu_pce_ov; |
| 469 | // assign stop = tcu_clk_stop; |
| 470 | assign stop = 1'b0 ; |
| 471 | // assign siclk = spc_aclk; |
| 472 | // assign soclk = spc_bclk; |
| 473 | |
| 474 | ifu_ftu_agd_dp_buff_macro__dbuff_32x__stack_none__width_4 test_rep0 ( |
| 475 | .din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}), |
| 476 | .dout({se,pce_ov,siclk,soclk}) |
| 477 | ); |
| 478 | /////////////////////////////////////////////////////////////////////// |
| 479 | // Flop exu_addresses // |
| 480 | /////////////////////////////////////////////////////////////////////// |
| 481 | ifu_ftu_agd_dp_msff_macro__stack_24l__width_24 br_address0_m_reg0 ( |
| 482 | .scan_in(br_address0_m_reg0_scanin), |
| 483 | .scan_out(br_address0_m_reg0_scanout), |
| 484 | .clk ( l2clk ), |
| 485 | .en ( 1'b1 ), |
| 486 | .din ( exu_address0_e[47:24]), |
| 487 | .dout( address0_m[47:24] ), |
| 488 | .se(se), |
| 489 | .siclk(siclk), |
| 490 | .soclk(soclk), |
| 491 | .pce_ov(pce_ov), |
| 492 | .stop(stop)); |
| 493 | ifu_ftu_agd_dp_msff_macro__stack_24l__width_24 br_address0_m_reg1 ( |
| 494 | .scan_in(br_address0_m_reg1_scanin), |
| 495 | .scan_out(br_address0_m_reg1_scanout), |
| 496 | .clk ( l2clk ), |
| 497 | .en ( 1'b1 ), |
| 498 | .din ( exu_address0_e[23:0]), |
| 499 | .dout( address0_m[23:0] ), |
| 500 | .se(se), |
| 501 | .siclk(siclk), |
| 502 | .soclk(soclk), |
| 503 | .pce_ov(pce_ov), |
| 504 | .stop(stop)); |
| 505 | |
| 506 | ifu_ftu_agd_dp_buff_macro__dbuff_48x__rep_1__stack_50c__width_48 br_address0_m_rep0 ( |
| 507 | .din ( address0_m[47:0] ), |
| 508 | .dout( address0_m_rep0[47:0] )); |
| 509 | |
| 510 | // buff_macro br_address0_m_rep01 (width=48,stack=50c,dbuff=32x) ( |
| 511 | // .din ( address0_m_rep0[47:0] ), |
| 512 | // .dout( address0_m_rep01[47:0] )); |
| 513 | |
| 514 | ifu_ftu_agd_dp_msff_macro__stack_24l__width_24 br_address1_m_reg0 ( |
| 515 | .scan_in(br_address1_m_reg0_scanin), |
| 516 | .scan_out(br_address1_m_reg0_scanout), |
| 517 | .clk ( l2clk ), |
| 518 | .en ( 1'b1 ), |
| 519 | .din ( exu_address1_e[47:24]), |
| 520 | .dout( address1_m[47:24] ), |
| 521 | .se(se), |
| 522 | .siclk(siclk), |
| 523 | .soclk(soclk), |
| 524 | .pce_ov(pce_ov), |
| 525 | .stop(stop)); |
| 526 | ifu_ftu_agd_dp_msff_macro__stack_24l__width_24 br_address1_m_reg1 ( |
| 527 | .scan_in(br_address1_m_reg1_scanin), |
| 528 | .scan_out(br_address1_m_reg1_scanout), |
| 529 | .clk ( l2clk ), |
| 530 | .en ( 1'b1 ), |
| 531 | .din ( exu_address1_e[23:0]), |
| 532 | .dout( address1_m[23:0] ), |
| 533 | .se(se), |
| 534 | .siclk(siclk), |
| 535 | .soclk(soclk), |
| 536 | .pce_ov(pce_ov), |
| 537 | .stop(stop)); |
| 538 | |
| 539 | ifu_ftu_agd_dp_buff_macro__dbuff_48x__rep_1__stack_50c__width_48 br_address1_m_rep0 ( |
| 540 | .din ( address1_m[47:0] ), |
| 541 | .dout( address1_m_rep0[47:0] )); |
| 542 | |
| 543 | // buff_macro br_address1_m_rep01 (width=48,stack=50c,dbuff=32x) ( |
| 544 | // .din ( address1_m_rep0[47:0] ), |
| 545 | // .dout( address1_m_rep01[47:0] )); |
| 546 | |
| 547 | assign agd_address0_m[4:2] = address0_m_rep0[4:2] ; |
| 548 | assign agd_address1_m[4:2] = address1_m_rep0[4:2] ; |
| 549 | /////////////////////////////////////////////////////////////////////// |
| 550 | // First level of redirection muxing for thread_0 to thread_7 // |
| 551 | /////////////////////////////////////////////////////////////////////// |
| 552 | |
| 553 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_50c__width_49 thr0_trp_rd_pc_mux ( |
| 554 | .din0( {1'b0,tlu_trap_pc_0[47:2],2'b00}), // trap pc from thread_g_0 |
| 555 | .din1( {1'b0,tlu_npc_w[47:2],2'b00}), // npc at w stage,thread_g_0 |
| 556 | .din2( pc_c[48:0]), // pc at c stage |
| 557 | .sel0( ftp_thr0_trprdpc_sel_bf[0]), |
| 558 | .sel1( ftp_thr0_trprdpc_sel_bf[1]), |
| 559 | .sel2( ftp_thr0_trprdpc_sel_bf[2]), |
| 560 | .dout( thr0_trap_rd_pc_bf[48:0] )); |
| 561 | |
| 562 | |
| 563 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_50c__width_49 thr1_trp_rd_pc_mux ( |
| 564 | .din0( {1'b0,tlu_trap_pc_0[47:2],2'b00}), // trap pc from thread_g_0 |
| 565 | .din1( {1'b0,tlu_npc_w[47:2],2'b00}), // npc at w stage,thread_g_0 |
| 566 | .din2( pc_c[48:0]), // pc at c stage |
| 567 | .sel0( ftp_thr1_trprdpc_sel_bf[0]), |
| 568 | .sel1( ftp_thr1_trprdpc_sel_bf[1]), |
| 569 | .sel2( ftp_thr1_trprdpc_sel_bf[2]), |
| 570 | .dout( thr1_trap_rd_pc_bf[48:0] )); |
| 571 | |
| 572 | |
| 573 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_50c__width_49 thr2_trp_rd_pc_mux ( |
| 574 | .din0( {1'b0,tlu_trap_pc_0[47:2],2'b00}), // trap pc from thread_g_0 |
| 575 | .din1( {1'b0,tlu_npc_w[47:2],2'b00}), // npc at w stage,thread_g_0 |
| 576 | .din2( pc_c[48:0]), // pc at c stage |
| 577 | .sel0( ftp_thr2_trprdpc_sel_bf[0]), |
| 578 | .sel1( ftp_thr2_trprdpc_sel_bf[1]), |
| 579 | .sel2( ftp_thr2_trprdpc_sel_bf[2]), |
| 580 | .dout( thr2_trap_rd_pc_bf[48:0] )); |
| 581 | |
| 582 | |
| 583 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_50c__width_49 thr3_trp_rd_pc_mux ( |
| 584 | .din0( {1'b0,tlu_trap_pc_0[47:2],2'b00}), // trap pc from thread_g_0 |
| 585 | .din1( {1'b0,tlu_npc_w[47:2],2'b00}), // npc at w stage,thread_g_0 |
| 586 | .din2( pc_c[48:0]), // pc at c stage |
| 587 | .sel0( ftp_thr3_trprdpc_sel_bf[0]), |
| 588 | .sel1( ftp_thr3_trprdpc_sel_bf[1]), |
| 589 | .sel2( ftp_thr3_trprdpc_sel_bf[2]), |
| 590 | .dout( thr3_trap_rd_pc_bf[48:0] )); |
| 591 | |
| 592 | |
| 593 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_50c__width_49 thr4_trp_rd_pc_mux ( |
| 594 | .din0( {1'b0,tlu_trap_pc_1[47:2],2'b00}), // trap pc from thread_g_1 |
| 595 | .din1( {1'b0,tlu_npc_w[47:2],2'b00}), // npc at w stage,thread_g_1 |
| 596 | .din2( pc_c[48:0]), // pc at c stage |
| 597 | .sel0( ftp_thr4_trprdpc_sel_bf[0]), |
| 598 | .sel1( ftp_thr4_trprdpc_sel_bf[1]), |
| 599 | .sel2( ftp_thr4_trprdpc_sel_bf[2]), |
| 600 | .dout( thr4_trap_rd_pc_bf[48:0] )); |
| 601 | |
| 602 | |
| 603 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_50c__width_49 thr5_trp_rd_pc_mux ( |
| 604 | .din0( {1'b0,tlu_trap_pc_1[47:2],2'b00}), // trap pc from thread_g_1 |
| 605 | .din1( {1'b0,tlu_npc_w[47:2],2'b00}), // npc at w stage,thread_g_1 |
| 606 | .din2( pc_c[48:0]), // pc at c stage |
| 607 | .sel0( ftp_thr5_trprdpc_sel_bf[0]), |
| 608 | .sel1( ftp_thr5_trprdpc_sel_bf[1]), |
| 609 | .sel2( ftp_thr5_trprdpc_sel_bf[2]), |
| 610 | .dout( thr5_trap_rd_pc_bf[48:0] )); |
| 611 | |
| 612 | |
| 613 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_50c__width_49 thr6_trp_rd_pc_mux ( |
| 614 | .din0( {1'b0,tlu_trap_pc_1[47:2],2'b00}), // trap pc from thread_g_1 |
| 615 | .din1( {1'b0,tlu_npc_w[47:2],2'b00}), // npc at w stage,thread_g_1 |
| 616 | .din2( pc_c[48:0]), // pc at c stage |
| 617 | .sel0( ftp_thr6_trprdpc_sel_bf[0]), |
| 618 | .sel1( ftp_thr6_trprdpc_sel_bf[1]), |
| 619 | .sel2( ftp_thr6_trprdpc_sel_bf[2]), |
| 620 | .dout( thr6_trap_rd_pc_bf[48:0] )); |
| 621 | |
| 622 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_50c__width_49 thr7_trp_rd_pc_mux ( |
| 623 | .din0( {1'b0,tlu_trap_pc_1[47:2],2'b00}), // trap pc from thread_g_1 |
| 624 | .din1( {1'b0,tlu_npc_w[47:2],2'b00}), // npc at w stage,thread_g_1 |
| 625 | .din2( pc_c[48:0]), // pc at c stage |
| 626 | .sel0( ftp_thr7_trprdpc_sel_bf[0]), |
| 627 | .sel1( ftp_thr7_trprdpc_sel_bf[1]), |
| 628 | .sel2( ftp_thr7_trprdpc_sel_bf[2]), |
| 629 | .dout( thr7_trap_rd_pc_bf[48:0] )); |
| 630 | |
| 631 | /////////////////////////////////////////////////////////////////////// |
| 632 | // Second level of redirection muxing // |
| 633 | /////////////////////////////////////////////////////////////////////// |
| 634 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_49 thr0_pc_bf_mux ( |
| 635 | .din0( thr0_trap_rd_pc_bf[48:0]), // redirection pc from 1st level of muxing |
| 636 | .din1( curr_thr_pc_bf[48:0]), // Current thread incr pc. |
| 637 | .din2( by_pass_pc_update_bf[48:0]), // select bypass incremented addr. |
| 638 | .din3( thr0_pc_f[48:0]), // Hold the pc_f for the this thread |
| 639 | .sel0( agc_thr0_pcf_sel_bf[0]), |
| 640 | .sel1( agc_thr0_pcf_sel_bf[1]), |
| 641 | .sel2( agc_thr0_pcf_sel_bf[2]), |
| 642 | .sel3( agc_thr0_pcf_sel_bf[3]), |
| 643 | .dout( thr0_pc_before_last_bf[48:0] )); |
| 644 | |
| 645 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_50c__width_49 thr0_pc_bf_last_mux ( |
| 646 | .din0( {1'b0,address0_m_rep0[47:0]}), // br misprediction pc from thread_g_0 |
| 647 | .din1( thr0_pc_before_last_bf[48:0]), // redirection pc from 1st level of muxing |
| 648 | .sel0( agc_thr0_pcf_sel_last_bf[0]), |
| 649 | .sel1( agc_thr0_pcf_sel_last_bf[1]), |
| 650 | .dout( next_thr0_pc_bf[48:0] )); |
| 651 | |
| 652 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_49 thr1_pc_bf_mux ( |
| 653 | .din0( thr1_trap_rd_pc_bf[48:0]), // redirection pc from 1st level of muxing |
| 654 | .din1( curr_thr_pc_bf[48:0]), // Current thread incr pc. |
| 655 | .din2( by_pass_pc_update_bf[48:0]), // select bypass incremented addr. |
| 656 | .din3( thr1_pc_f[48:0]), // Hold the pc_f for the this thread |
| 657 | .sel0( agc_thr1_pcf_sel_bf[0]), |
| 658 | .sel1( agc_thr1_pcf_sel_bf[1]), |
| 659 | .sel2( agc_thr1_pcf_sel_bf[2]), |
| 660 | .sel3( agc_thr1_pcf_sel_bf[3]), |
| 661 | .dout( thr1_pc_before_last_bf[48:0] )); |
| 662 | |
| 663 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_50c__width_49 thr1_pc_bf_last_mux ( |
| 664 | .din0( {1'b0,address0_m_rep0[47:0]}), // br misprediction pc from thread_g_0 |
| 665 | .din1( thr1_pc_before_last_bf[48:0]), // redirection pc from 1st level of muxing |
| 666 | .sel0( agc_thr1_pcf_sel_last_bf[0]), |
| 667 | .sel1( agc_thr1_pcf_sel_last_bf[1]), |
| 668 | .dout( next_thr1_pc_bf[48:0] )); |
| 669 | |
| 670 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_49 thr2_pc_bf_mux ( |
| 671 | .din0( thr2_trap_rd_pc_bf[48:0]), // redirection pc from 1st level of muxing |
| 672 | .din1( curr_thr_pc_bf[48:0]), // Current thread incr pc. |
| 673 | .din2( by_pass_pc_update_bf[48:0]), // select bypass incremented addr. |
| 674 | .din3( thr2_pc_f[48:0]), // Hold the pc_f for the this thread |
| 675 | .sel0( agc_thr2_pcf_sel_bf[0]), |
| 676 | .sel1( agc_thr2_pcf_sel_bf[1]), |
| 677 | .sel2( agc_thr2_pcf_sel_bf[2]), |
| 678 | .sel3( agc_thr2_pcf_sel_bf[3]), |
| 679 | .dout( thr2_pc_before_last_bf[48:0] )); |
| 680 | |
| 681 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_50c__width_49 thr2_pc_bf_last_mux ( |
| 682 | .din0( {1'b0,address0_m_rep0[47:0]}), // br misprediction pc from thread_g_0 |
| 683 | .din1( thr2_pc_before_last_bf[48:0]), // redirection pc from 1st level of muxing |
| 684 | .sel0( agc_thr2_pcf_sel_last_bf[0]), |
| 685 | .sel1( agc_thr2_pcf_sel_last_bf[1]), |
| 686 | .dout( next_thr2_pc_bf[48:0] )); |
| 687 | |
| 688 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_49 thr3_pc_bf_mux ( |
| 689 | .din0( thr3_trap_rd_pc_bf[48:0]), // redirection pc from 1st level of muxing |
| 690 | .din1( curr_thr_pc_bf[48:0]), // Current thread incr pc. |
| 691 | .din2( by_pass_pc_update_bf[48:0]), // select bypass incremented addr. |
| 692 | .din3( thr3_pc_f[48:0]), // Hold the pc_f for the this thread |
| 693 | .sel0( agc_thr3_pcf_sel_bf[0]), |
| 694 | .sel1( agc_thr3_pcf_sel_bf[1]), |
| 695 | .sel2( agc_thr3_pcf_sel_bf[2]), |
| 696 | .sel3( agc_thr3_pcf_sel_bf[3]), |
| 697 | .dout( thr3_pc_before_last_bf[48:0] )); |
| 698 | |
| 699 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_50c__width_49 thr3_pc_bf_last_mux ( |
| 700 | .din0( {1'b0,address0_m_rep0[47:0]}), // br misprediction pc from thread_g_0 |
| 701 | .din1( thr3_pc_before_last_bf[48:0]), // redirection pc from 1st level of muxing |
| 702 | .sel0( agc_thr3_pcf_sel_last_bf[0]), |
| 703 | .sel1( agc_thr3_pcf_sel_last_bf[1]), |
| 704 | .dout( next_thr3_pc_bf[48:0] )); |
| 705 | |
| 706 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_49 thr4_pc_bf_mux ( |
| 707 | .din0( thr4_trap_rd_pc_bf[48:0]), // redirection pc from 1st level of muxing |
| 708 | .din1( curr_thr_pc_bf[48:0]), // Current thread incr pc. |
| 709 | .din2( by_pass_pc_update_bf[48:0]), // select bypass incremented addr. |
| 710 | .din3( thr4_pc_f[48:0]), // Hold the pc_f for the this thread |
| 711 | .sel0( agc_thr4_pcf_sel_bf[0]), |
| 712 | .sel1( agc_thr4_pcf_sel_bf[1]), |
| 713 | .sel2( agc_thr4_pcf_sel_bf[2]), |
| 714 | .sel3( agc_thr4_pcf_sel_bf[3]), |
| 715 | .dout( thr4_pc_before_last_bf[48:0] )); |
| 716 | |
| 717 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_50c__width_49 thr4_pc_bf_last_mux ( |
| 718 | .din0( {1'b0,address1_m_rep0[47:0]}), // br misprediction pc from thread_g_1 |
| 719 | .din1( thr4_pc_before_last_bf[48:0]), // redirection pc from 1st level of muxing |
| 720 | .sel0( agc_thr4_pcf_sel_last_bf[0]), |
| 721 | .sel1( agc_thr4_pcf_sel_last_bf[1]), |
| 722 | .dout( next_thr4_pc_bf[48:0] )); |
| 723 | |
| 724 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_49 thr5_pc_bf_mux ( |
| 725 | .din0( thr5_trap_rd_pc_bf[48:0]), // redirection pc from 1st level of muxing |
| 726 | .din1( curr_thr_pc_bf[48:0]), // Current thread incr pc. |
| 727 | .din2( by_pass_pc_update_bf[48:0]), // select bypass incremented addr. |
| 728 | .din3( thr5_pc_f[48:0]), // Hold the pc_f for the this thread |
| 729 | .sel0( agc_thr5_pcf_sel_bf[0]), |
| 730 | .sel1( agc_thr5_pcf_sel_bf[1]), |
| 731 | .sel2( agc_thr5_pcf_sel_bf[2]), |
| 732 | .sel3( agc_thr5_pcf_sel_bf[3]), |
| 733 | .dout( thr5_pc_before_last_bf[48:0] )); |
| 734 | |
| 735 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_50c__width_49 thr5_pc_bf_last_mux ( |
| 736 | .din0( {1'b0,address1_m_rep0[47:0]}), // br misprediction pc from thread_g_1 |
| 737 | .din1( thr5_pc_before_last_bf[48:0]), // redirection pc from 1st level of muxing |
| 738 | .sel0( agc_thr5_pcf_sel_last_bf[0]), |
| 739 | .sel1( agc_thr5_pcf_sel_last_bf[1]), |
| 740 | .dout( next_thr5_pc_bf[48:0] )); |
| 741 | |
| 742 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_49 thr6_pc_bf_mux ( |
| 743 | .din0( thr6_trap_rd_pc_bf[48:0]), // redirection pc from 1st level of muxing |
| 744 | .din1( curr_thr_pc_bf[48:0]), // Current thread incr pc. |
| 745 | .din2( by_pass_pc_update_bf[48:0]), // select bypass incremented addr. |
| 746 | .din3( thr6_pc_f[48:0]), // Hold the pc_f for the this thread |
| 747 | .sel0( agc_thr6_pcf_sel_bf[0]), |
| 748 | .sel1( agc_thr6_pcf_sel_bf[1]), |
| 749 | .sel2( agc_thr6_pcf_sel_bf[2]), |
| 750 | .sel3( agc_thr6_pcf_sel_bf[3]), |
| 751 | .dout( thr6_pc_before_last_bf[48:0] )); |
| 752 | |
| 753 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_50c__width_49 thr6_pc_bf_last_mux ( |
| 754 | .din0( {1'b0,address1_m_rep0[47:0]}), // br misprediction pc from thread_g_1 |
| 755 | .din1( thr6_pc_before_last_bf[48:0]), // redirection pc from 1st level of muxing |
| 756 | .sel0( agc_thr6_pcf_sel_last_bf[0]), |
| 757 | .sel1( agc_thr6_pcf_sel_last_bf[1]), |
| 758 | .dout( next_thr6_pc_bf[48:0] )); |
| 759 | |
| 760 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_49 thr7_pc_bf_mux ( |
| 761 | .din0( thr7_trap_rd_pc_bf[48:0]), // redirection pc from 1st level of muxing |
| 762 | .din1( curr_thr_pc_bf[48:0]), // Current thread incr pc. |
| 763 | .din2( by_pass_pc_update_bf[48:0]), // select bypass incremented addr. |
| 764 | .din3( thr7_pc_f[48:0]), // Hold the pc_f for the this thread |
| 765 | .sel0( agc_thr7_pcf_sel_bf[0]), |
| 766 | .sel1( agc_thr7_pcf_sel_bf[1]), |
| 767 | .sel2( agc_thr7_pcf_sel_bf[2]), |
| 768 | .sel3( agc_thr7_pcf_sel_bf[3]), |
| 769 | .dout( thr7_pc_before_last_bf[48:0] )); |
| 770 | |
| 771 | |
| 772 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_50c__width_49 thr7_pc_bf_last_mux ( |
| 773 | .din0( {1'b0,address1_m_rep0[47:0]}), // br misprediction pc from thread_g_1 |
| 774 | .din1( thr7_pc_before_last_bf[48:0]), // redirection pc from 1st level of muxing |
| 775 | .sel0( agc_thr7_pcf_sel_last_bf[0]), |
| 776 | .sel1( agc_thr7_pcf_sel_last_bf[1]), |
| 777 | .dout( next_thr7_pc_bf[48:0] )); |
| 778 | |
| 779 | /////////////////////////////////////////////////////////////////////// |
| 780 | // Thread 0 to thread 7 pc_f registers // |
| 781 | /////////////////////////////////////////////////////////////////////// |
| 782 | ifu_ftu_agd_dp_msff_macro__stack_50c__width_49 thr0_pc_f_reg ( |
| 783 | .scan_in(thr0_pc_f_reg_scanin), |
| 784 | .scan_out(thr0_pc_f_reg_scanout), |
| 785 | .clk ( l2clk ), |
| 786 | .en ( ftp_any_thr_clken ), |
| 787 | .din ( next_thr0_pc_bf[48:0]), |
| 788 | .dout( thr0_pc_f[48:0] ), |
| 789 | .se(se), |
| 790 | .siclk(siclk), |
| 791 | .soclk(soclk), |
| 792 | .pce_ov(pce_ov), |
| 793 | .stop(stop)); |
| 794 | |
| 795 | // buff_macro thr0_pc_f_reg_buf (width=49,stack=50c,dbuff=32x) ( |
| 796 | // .din ( thr0_pc_f_to_buf[48:0] ), |
| 797 | // .dout( thr0_pc_f[48:0] )); |
| 798 | |
| 799 | assign agd_thr0_pc_4_2_f[4:2] = thr0_pc_f[4:2] ; |
| 800 | |
| 801 | ifu_ftu_agd_dp_msff_macro__stack_50c__width_49 thr1_pc_f_reg ( |
| 802 | .scan_in(thr1_pc_f_reg_scanin), |
| 803 | .scan_out(thr1_pc_f_reg_scanout), |
| 804 | .clk ( l2clk ), |
| 805 | .en ( ftp_any_thr_clken ), |
| 806 | .din ( next_thr1_pc_bf[48:0]), |
| 807 | .dout( thr1_pc_f[48:0] ), |
| 808 | .se(se), |
| 809 | .siclk(siclk), |
| 810 | .soclk(soclk), |
| 811 | .pce_ov(pce_ov), |
| 812 | .stop(stop)); |
| 813 | |
| 814 | assign agd_thr1_pc_4_2_f[4:2] = thr1_pc_f[4:2] ; |
| 815 | |
| 816 | |
| 817 | ifu_ftu_agd_dp_msff_macro__stack_50c__width_49 thr2_pc_f_reg ( |
| 818 | .scan_in(thr2_pc_f_reg_scanin), |
| 819 | .scan_out(thr2_pc_f_reg_scanout), |
| 820 | .clk ( l2clk ), |
| 821 | .en ( ftp_any_thr_clken ), |
| 822 | .din ( next_thr2_pc_bf[48:0]), |
| 823 | .dout( thr2_pc_f[48:0] ), |
| 824 | .se(se), |
| 825 | .siclk(siclk), |
| 826 | .soclk(soclk), |
| 827 | .pce_ov(pce_ov), |
| 828 | .stop(stop)); |
| 829 | |
| 830 | assign agd_thr2_pc_4_2_f[4:2] = thr2_pc_f[4:2] ; |
| 831 | |
| 832 | |
| 833 | ifu_ftu_agd_dp_msff_macro__stack_50c__width_49 thr3_pc_f_reg ( |
| 834 | .scan_in(thr3_pc_f_reg_scanin), |
| 835 | .scan_out(thr3_pc_f_reg_scanout), |
| 836 | .clk ( l2clk ), |
| 837 | .en ( ftp_any_thr_clken ), |
| 838 | .din ( next_thr3_pc_bf[48:0]), |
| 839 | .dout( thr3_pc_f[48:0] ), |
| 840 | .se(se), |
| 841 | .siclk(siclk), |
| 842 | .soclk(soclk), |
| 843 | .pce_ov(pce_ov), |
| 844 | .stop(stop)); |
| 845 | |
| 846 | assign agd_thr3_pc_4_2_f[4:2] = thr3_pc_f[4:2] ; |
| 847 | |
| 848 | |
| 849 | ifu_ftu_agd_dp_msff_macro__stack_50c__width_49 thr4_pc_f_reg ( |
| 850 | .scan_in(thr4_pc_f_reg_scanin), |
| 851 | .scan_out(thr4_pc_f_reg_scanout), |
| 852 | .clk ( l2clk ), |
| 853 | .en ( ftp_any_thr_clken ), |
| 854 | .din ( next_thr4_pc_bf[48:0]), |
| 855 | .dout( thr4_pc_f[48:0] ), |
| 856 | .se(se), |
| 857 | .siclk(siclk), |
| 858 | .soclk(soclk), |
| 859 | .pce_ov(pce_ov), |
| 860 | .stop(stop)); |
| 861 | |
| 862 | assign agd_thr4_pc_4_2_f[4:2] = thr4_pc_f[4:2] ; |
| 863 | |
| 864 | |
| 865 | ifu_ftu_agd_dp_msff_macro__stack_50c__width_49 thr5_pc_f_reg ( |
| 866 | .scan_in(thr5_pc_f_reg_scanin), |
| 867 | .scan_out(thr5_pc_f_reg_scanout), |
| 868 | .clk ( l2clk ), |
| 869 | .en ( ftp_any_thr_clken ), |
| 870 | .din ( next_thr5_pc_bf[48:0]), |
| 871 | .dout( thr5_pc_f[48:0] ), |
| 872 | .se(se), |
| 873 | .siclk(siclk), |
| 874 | .soclk(soclk), |
| 875 | .pce_ov(pce_ov), |
| 876 | .stop(stop)); |
| 877 | |
| 878 | assign agd_thr5_pc_4_2_f[4:2] = thr5_pc_f[4:2] ; |
| 879 | |
| 880 | |
| 881 | ifu_ftu_agd_dp_msff_macro__stack_50c__width_49 thr6_pc_f_reg ( |
| 882 | .scan_in(thr6_pc_f_reg_scanin), |
| 883 | .scan_out(thr6_pc_f_reg_scanout), |
| 884 | .clk ( l2clk ), |
| 885 | .en ( ftp_any_thr_clken ), |
| 886 | .din ( next_thr6_pc_bf[48:0]), |
| 887 | .dout( thr6_pc_f[48:0] ), |
| 888 | .se(se), |
| 889 | .siclk(siclk), |
| 890 | .soclk(soclk), |
| 891 | .pce_ov(pce_ov), |
| 892 | .stop(stop)); |
| 893 | |
| 894 | assign agd_thr6_pc_4_2_f[4:2] = thr6_pc_f[4:2] ; |
| 895 | |
| 896 | ifu_ftu_agd_dp_msff_macro__stack_50c__width_49 thr7_pc_f_reg ( |
| 897 | .scan_in(thr7_pc_f_reg_scanin), |
| 898 | .scan_out(thr7_pc_f_reg_scanout), |
| 899 | .clk ( l2clk ), |
| 900 | .en ( ftp_any_thr_clken ), |
| 901 | .din ( next_thr7_pc_bf[48:0]), |
| 902 | .dout( thr7_pc_f[48:0] ), |
| 903 | .se(se), |
| 904 | .siclk(siclk), |
| 905 | .soclk(soclk), |
| 906 | .pce_ov(pce_ov), |
| 907 | .stop(stop)); |
| 908 | |
| 909 | assign agd_thr7_pc_4_2_f[4:2] = thr7_pc_f[4:2] ; |
| 910 | |
| 911 | assign curr_thr_pc_bf[48:0] = {inc_pc_bf[48:2], 2'b00} ; |
| 912 | assign curr_thr_pc_crit_bf[10:5] = inc_pc_crit_bf[10:5] ; |
| 913 | /////////////////////////////////////////////////////////////////////// |
| 914 | // Mux between the branch address flopped and the thread pc register // |
| 915 | /////////////////////////////////////////////////////////////////////// |
| 916 | ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_50c__width_49 thr0_pc_reg_mux ( |
| 917 | .din0( {1'b0,address0_m_rep0[47:0]}), // branch address 0 flopped |
| 918 | .din1( thr0_pc_f[48:0]), // thread 0 pc_f |
| 919 | .sel0( ftp_thr0_sel_br_bf), |
| 920 | .dout( thr0_pc_muxed_f[48:0] )); |
| 921 | |
| 922 | ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_50c__width_49 thr1_pc_reg_mux ( |
| 923 | .din0( {1'b0,address0_m_rep0[47:0]}), // branch address 0 flopped |
| 924 | .din1( thr1_pc_f[48:0]), // thread 1 pc_f |
| 925 | .sel0( ftp_thr1_sel_br_bf), |
| 926 | .dout( thr1_pc_muxed_f[48:0] )); |
| 927 | |
| 928 | ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_50c__width_49 thr2_pc_reg_mux ( |
| 929 | .din0( {1'b0,address0_m_rep0[47:0]}), // branch address 0 flopped |
| 930 | .din1( thr2_pc_f[48:0]), // thread 2 pc_f |
| 931 | .sel0( ftp_thr2_sel_br_bf), |
| 932 | .dout( thr2_pc_muxed_f[48:0] )); |
| 933 | |
| 934 | ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_50c__width_49 thr3_pc_reg_mux ( |
| 935 | .din0( {1'b0,address0_m_rep0[47:0]}), // branch address 0 flopped |
| 936 | .din1( thr3_pc_f[48:0]), // thread 3 pc_f |
| 937 | .sel0( ftp_thr3_sel_br_bf), |
| 938 | .dout( thr3_pc_muxed_f[48:0] )); |
| 939 | |
| 940 | ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_50c__width_49 thr4_pc_reg_mux ( |
| 941 | .din0( {1'b0,address1_m_rep0[47:0]}), // branch address 1 flopped |
| 942 | .din1( thr4_pc_f[48:0]), // thread 4 pc_f |
| 943 | .sel0( ftp_thr4_sel_br_bf), |
| 944 | .dout( thr4_pc_muxed_f[48:0] )); |
| 945 | |
| 946 | ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_50c__width_49 thr5_pc_reg_mux ( |
| 947 | .din0( {1'b0,address1_m_rep0[47:0]}), // branch address 1 flopped |
| 948 | .din1( thr5_pc_f[48:0]), // thread 5 pc_f |
| 949 | .sel0( ftp_thr5_sel_br_bf), |
| 950 | .dout( thr5_pc_muxed_f[48:0] )); |
| 951 | |
| 952 | ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_50c__width_49 thr6_pc_reg_mux ( |
| 953 | .din0( {1'b0,address1_m_rep0[47:0]}), // branch address 1 flopped |
| 954 | .din1( thr6_pc_f[48:0]), // thread 6 pc_f |
| 955 | .sel0( ftp_thr6_sel_br_bf), |
| 956 | .dout( thr6_pc_muxed_f[48:0] )); |
| 957 | |
| 958 | ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_50c__width_49 thr7_pc_reg_mux ( |
| 959 | .din0( {1'b0,address1_m_rep0[47:0]}), // branch address 1 flopped |
| 960 | .din1( thr7_pc_f[48:0]), // thread 7 pc_f |
| 961 | .sel0( ftp_thr7_sel_br_bf), |
| 962 | .dout( thr7_pc_muxed_f[48:0] )); |
| 963 | |
| 964 | |
| 965 | /////////////////////////////////////////////////////////////////////// |
| 966 | // One mux for all eight PCs from the different threads. // |
| 967 | /////////////////////////////////////////////////////////////////////// |
| 968 | |
| 969 | // buff_macro tst_mux_rep0 (width=1,dbuff=48x) ( |
| 970 | // .din ( tcu_muxtest ), |
| 971 | // .dout( tcu_muxtest_rep0 )); |
| 972 | |
| 973 | ifu_ftu_agd_dp_mux_macro__dmux_8x__mux_aonpe__ports_8__stack_50c__width_49 new_thr_pc_mux ( |
| 974 | .din0( thr0_pc_muxed_f[48:0]), // thread 0 pc_f |
| 975 | .din1( thr1_pc_muxed_f[48:0]), // thread 1 pc_f |
| 976 | .din2( thr2_pc_muxed_f[48:0]), // thread 2 pc_f |
| 977 | .din3( thr3_pc_muxed_f[48:0]), // thread 3 pc_f |
| 978 | .din4( thr4_pc_muxed_f[48:0]), // thread 4 pc_f |
| 979 | .din5( thr5_pc_muxed_f[48:0]), // thread 5 pc_f |
| 980 | .din6( thr6_pc_muxed_f[48:0]), // thread 6 pc_f |
| 981 | .din7( thr7_pc_muxed_f[48:0]), // thread 7 pc_f |
| 982 | // .muxtst (tcu_muxtest_rep0), |
| 983 | .sel0( ftp_new_thr_sel_bf[0]), |
| 984 | .sel1( ftp_new_thr_sel_bf[1]), |
| 985 | .sel2( ftp_new_thr_sel_bf[2]), |
| 986 | .sel3( ftp_new_thr_sel_bf[3]), |
| 987 | .sel4( ftp_new_thr_sel_bf[4]), |
| 988 | .sel5( ftp_new_thr_sel_bf[5]), |
| 989 | .sel6( ftp_new_thr_sel_bf[6]), |
| 990 | .sel7( ftp_new_thr_sel_bf[7]), |
| 991 | .dout( new_thr_pc_bf[48:0] )); |
| 992 | |
| 993 | // mux_macro new_thr_pc_crit_mux (width=6,ports=8,mux=aonpe,stack=6l,dmux=8x,buffsel=none) ( |
| 994 | // .din0( thr0_pc_muxed_f[10:5]), // thread 0 pc_f |
| 995 | // .din1( thr1_pc_muxed_f[10:5]), // thread 1 pc_f |
| 996 | // .din2( thr2_pc_muxed_f[10:5]), // thread 2 pc_f |
| 997 | // .din3( thr3_pc_muxed_f[10:5]), // thread 3 pc_f |
| 998 | // .din4( thr4_pc_muxed_f[10:5]), // thread 4 pc_f |
| 999 | // .din5( thr5_pc_muxed_f[10:5]), // thread 5 pc_f |
| 1000 | // .din6( thr6_pc_muxed_f[10:5]), // thread 6 pc_f |
| 1001 | // .din7( thr7_pc_muxed_f[10:5]), // thread 7 pc_f |
| 1002 | // .sel0( ftp_new_thr_sel_bf[0]), |
| 1003 | // .sel1( ftp_new_thr_sel_bf[1]), |
| 1004 | // .sel2( ftp_new_thr_sel_bf[2]), |
| 1005 | // .sel3( ftp_new_thr_sel_bf[3]), |
| 1006 | // .sel4( ftp_new_thr_sel_bf[4]), |
| 1007 | // .sel5( ftp_new_thr_sel_bf[5]), |
| 1008 | // .sel6( ftp_new_thr_sel_bf[6]), |
| 1009 | // .sel7( ftp_new_thr_sel_bf[7]), |
| 1010 | // .dout( new_thr_pc_crit_bf[10:5] )); |
| 1011 | |
| 1012 | // buff_macro new_thr_pc_buf (width=49,stack=50c) ( |
| 1013 | // .din( new_thr_pc_to_buf[48:0] ) , |
| 1014 | // .dout( new_thr_pc_bf[48:0] )); |
| 1015 | |
| 1016 | /////////////////////////////////////////////////////////////////////// |
| 1017 | // Final mux for the PC_F // |
| 1018 | /////////////////////////////////////////////////////////////////////// |
| 1019 | /////////////////////////////////////////////////////////////////////// |
| 1020 | |
| 1021 | ifu_ftu_agd_dp_buff_macro__dbuff_48x__width_1 tst_mux_rep1 ( |
| 1022 | .din ( tcu_muxtest ), |
| 1023 | .dout( tcu_muxtest_rep1 )); |
| 1024 | |
| 1025 | ifu_ftu_agd_dp_mux_macro__mux_pgnpe__ports_6__stack_50c__width_49 pc_f_am_mux ( |
| 1026 | .din0( new_thr_pc_bf[48:0]), // new fetch thread pc |
| 1027 | .din1( curr_thr_pc_bf[48:0]), // current thread incr pc. |
| 1028 | .din2( {17'b0, new_thr_pc_bf[31:0]}), // new fetch thread pc am=1 |
| 1029 | .din3( {17'b0, curr_thr_pc_bf[31:0]}), // current thread next pc. am=1 |
| 1030 | .din4( {1'b0, itc_va[47:13],13'b0}), // itlb va address |
| 1031 | .din5( {1'b0, asi_addr_bf[39:5],13'b0}), // itlb asi=53 translation request |
| 1032 | .muxtst (tcu_muxtest_rep1), |
| 1033 | .sel0( ftp_pc_sel_am[0]), |
| 1034 | .sel1( ftp_pc_sel_am[1]), |
| 1035 | .sel2( ftp_pc_sel_am[2]), |
| 1036 | .sel3( ftp_pc_sel_am[3]), |
| 1037 | .sel4( ftp_pc_sel_am[4]), |
| 1038 | .sel5( ftp_pc_sel_am[5]), |
| 1039 | .dout( next_pc_bf[48:0] )); |
| 1040 | |
| 1041 | |
| 1042 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_20r__width_19 pc_bf_to_itb_part1 ( |
| 1043 | .din0( curr_thr_pc_bf[31:13]), // current thread incr pc. |
| 1044 | .din1( itc_va[31:13]), // itlb va address |
| 1045 | .din2( asi_addr_bf[23:5]), // itlb asi=53 translation request |
| 1046 | .sel0( ftp_pc_sel_tag_part1[0]), |
| 1047 | .sel1( ftp_pc_sel_tag_part1[1]), |
| 1048 | .sel2( ftp_pc_sel_tag_part1[2]), |
| 1049 | .dout( pc_tag_1[31:13] )); |
| 1050 | |
| 1051 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_20c__width_16 pc_bf_to_itb_part2 ( |
| 1052 | .din0( curr_thr_pc_bf[47:32]), // current thread incr pc. |
| 1053 | .din1( itc_va[47:32]), // itlb va address |
| 1054 | .din2( asi_addr_bf[39:24]), // itlb asi=53 translation request |
| 1055 | .din3( 16'h0000), // itlb asi=53 translation request |
| 1056 | .sel0( ftp_pc_sel_tag_part2[0]), |
| 1057 | .sel1( ftp_pc_sel_tag_part2[1]), |
| 1058 | .sel2( ftp_pc_sel_tag_part2[2]), |
| 1059 | .sel3( ftp_pc_sel_tag_part2[3]), |
| 1060 | .dout( pc_tag_1[47:32] )); |
| 1061 | |
| 1062 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_20c__width_19 pc_bf_to_itb_bot ( |
| 1063 | .din0( new_thr_pc_bf[31:13]), // current thread incr pc. |
| 1064 | .din1( pc_tag_1[31:13]), // itlb va address |
| 1065 | .sel0( ftp_pc_sel_tag_pc_bot[0]), |
| 1066 | .sel1( ftp_pc_sel_tag_pc_bot[1]), |
| 1067 | .dout( pc_tag[31:13] )); |
| 1068 | |
| 1069 | |
| 1070 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_16c__width_16 pc_bf_to_itb_top ( |
| 1071 | .din0( new_thr_pc_bf[47:32]), // current thread incr pc. |
| 1072 | .din1( pc_tag_1[47:32]), // itlb va address |
| 1073 | .sel0( ftp_pc_sel_tag_pc_top[0]), |
| 1074 | .sel1( ftp_pc_sel_tag_pc_top[1]), |
| 1075 | .dout( pc_tag[47:32] )); |
| 1076 | |
| 1077 | ifu_ftu_agd_dp_buff_macro__dbuff_40x__rep_1__width_35 pc_tag_buffer ( |
| 1078 | .din ( pc_tag[47:13] ), |
| 1079 | .dout( pc_tag_buf[47:13] )); |
| 1080 | |
| 1081 | // mux_macro pc_f_mux (width=49,ports=5,mux=aonpe,stack=50c,dmux=8x) ( |
| 1082 | // .din0( next_am_pc_bf[48:0]), // Normal path |
| 1083 | // .din1( {1'b0, exu_address0_e[47:0]}), // br0 misprediction pc am=0 |
| 1084 | // .din2( {17'b0, exu_address0_e[31:0]}), // br0 target address am=1 |
| 1085 | // .din3( {1'b0, exu_address1_e[47:0]}), // br1 misprediction pc am=0 |
| 1086 | // .din4( {17'b0, exu_address1_e[31:0]}), // br1 target address am=1 |
| 1087 | // .sel0( agc_pc_sel_am_final[0]), |
| 1088 | // .sel1( agc_pc_sel_am_final[1]), |
| 1089 | // .sel2( agc_pc_sel_am_final[2]), |
| 1090 | // .sel3( agc_pc_sel_am_final[3]), |
| 1091 | // .sel4( agc_pc_sel_am_final[4]), |
| 1092 | // .dout( next_pc_bf[48:0] )); |
| 1093 | |
| 1094 | // buff_macro pc_f_mux_buf (width=49,stack=50c) ( |
| 1095 | // .din ( next_pc_bf_to_buf[48:0] ), |
| 1096 | // .dout( next_pc_bf[48:0] )); |
| 1097 | |
| 1098 | assign ifu_agd_pc_bf[47:0] = {pc_tag_buf[47:13],next_pc_bf[12:0]} ; |
| 1099 | |
| 1100 | /////////////////////////////////////////////////////////////////////// |
| 1101 | // PC_F (fetch address at F stage) // |
| 1102 | /////////////////////////////////////////////////////////////////////// |
| 1103 | ifu_ftu_agd_dp_msff_macro__stack_50c__width_49 pc_f_reg ( |
| 1104 | .scan_in(pc_f_reg_scanin), |
| 1105 | .scan_out(pc_f_reg_scanout), |
| 1106 | .clk ( l2clk ), |
| 1107 | .en ( ftp_any_thr_clken ), |
| 1108 | .din ( next_pc_bf[48:0]), |
| 1109 | .dout( pc_f[48:0] ), |
| 1110 | .se(se), |
| 1111 | .siclk(siclk), |
| 1112 | .soclk(soclk), |
| 1113 | .pce_ov(pce_ov), |
| 1114 | .stop(stop)); |
| 1115 | |
| 1116 | assign ifu_agd_pc_f[47:2] = pc_f[47:2] ; |
| 1117 | assign pc_f_unused[1:0] = pc_f[1:0] ; |
| 1118 | assign agd_direct_map_rep_way[2:0] = pc_f[13:11] ; |
| 1119 | /////////////////////////////////////////////////////////////////////// |
| 1120 | // Custom incrementor. // |
| 1121 | /////////////////////////////////////////////////////////////////////// |
| 1122 | |
| 1123 | |
| 1124 | //////////////////////////////////////////// |
| 1125 | // pc_f[47:4] is incremented depending // |
| 1126 | // on the bits [3:0] // |
| 1127 | //////////////////////////////////////////// |
| 1128 | |
| 1129 | // assign inc_pc_bf[4] = (!pc_f[4]); |
| 1130 | // assign inc_pc_bf[3] = (!pc_f[4]&pc_f[3]); |
| 1131 | // assign inc_pc_bf[2] = (!pc_f[4]&pc_f[2]); |
| 1132 | // assign pc_f_incr = (pc_f[4]); |
| 1133 | |
| 1134 | ifu_ftu_agd_dp_inv_macro__stack_2c__width_1 pc_f_incr_b4 ( |
| 1135 | .din(pc_f[4]), |
| 1136 | .dout(inc_pc_bf[4]) |
| 1137 | ); |
| 1138 | |
| 1139 | ifu_ftu_agd_dp_and_macro__ports_2__stack_2c__width_1 pc_f_incr_b3 ( |
| 1140 | .din0(inc_pc_bf[4]), |
| 1141 | .din1(pc_f[3]), |
| 1142 | .dout(inc_pc_bf[3]) |
| 1143 | ); |
| 1144 | |
| 1145 | ifu_ftu_agd_dp_and_macro__ports_2__stack_2c__width_1 pc_f_incr_b2 ( |
| 1146 | .din0(inc_pc_bf[4]), |
| 1147 | .din1(pc_f[2]), |
| 1148 | .dout(inc_pc_bf[2]) |
| 1149 | ); |
| 1150 | assign pc_f_incr = pc_f[4] ; |
| 1151 | |
| 1152 | |
| 1153 | ifu_ftu_agd_dp_increment_macro__dincr_8x__width_32 pc_f_data_32b_inc ( |
| 1154 | .din( pc_f[36:5] ) , |
| 1155 | .cin(pc_f_incr ) , |
| 1156 | .dout(inc_pc_bf[36:5] ) , |
| 1157 | .cout(inc_pc_f_top_data )) ; |
| 1158 | |
| 1159 | ifu_ftu_agd_dp_increment_macro__dincr_8x__width_8 pc_f_data_8b_crit_inc ( |
| 1160 | .din( {2'b00,pc_f[10:5]} ) , |
| 1161 | .cin(pc_f_incr) , |
| 1162 | .dout({nc_crit_unused[1:0],inc_pc_crit_bf[10:5]} ) , |
| 1163 | .cout(inc_crit_cout_unused )) ; |
| 1164 | |
| 1165 | ifu_ftu_agd_dp_increment_macro__dincr_8x__width_16 pc_f_plus_4_16b_at_f ( |
| 1166 | .din( {5'b00000,pc_f[47:37]} ) , |
| 1167 | .cin(1'b1 ) , |
| 1168 | .dout({pc_f_1_unused[52:48], inc_pc_bf_top_inc[47:37] }) , |
| 1169 | .cout(pc_f_2_unused )) ; |
| 1170 | |
| 1171 | // assign inc_pc_bf_top_inc[48] = inc_pc_bf_top_inc[47] & ~pc_f[47] ; |
| 1172 | ifu_ftu_agd_dp_inv_macro__stack_2c__width_1 pc_f_b47_l ( |
| 1173 | .din(pc_f[47]), |
| 1174 | .dout(pc_f_[47]) |
| 1175 | ); |
| 1176 | |
| 1177 | ifu_ftu_agd_dp_and_macro__ports_2__stack_2c__width_1 pc_f_incr_b48 ( |
| 1178 | .din0(pc_f_[47]), |
| 1179 | .din1(inc_pc_bf_top_inc[47]), |
| 1180 | .dout(inc_pc_bf_top_inc[48]) |
| 1181 | ); |
| 1182 | |
| 1183 | |
| 1184 | |
| 1185 | |
| 1186 | ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_16c__width_16 pc_f_p_plus4_mux ( |
| 1187 | .din0( {4'b0000,inc_pc_bf_top_inc[48:37]}), |
| 1188 | .din1( {4'b0000,pc_f[48:37]}), |
| 1189 | .sel0( inc_pc_f_top_data), |
| 1190 | .dout( {pc_f_3_unused[52:49],inc_pc_bf[48:37]} )); |
| 1191 | |
| 1192 | |
| 1193 | ifu_ftu_agd_dp_increment_macro__dincr_8x__width_32 by_p_data_32b_inc ( |
| 1194 | .din( by_pass_pc_addr_to_buf[36:5] ) , |
| 1195 | .cin(by_pass_pc_addr_bf_incr_to_buf ) , |
| 1196 | .dout(by_pass_inc_pc_bf[36:5] ) , |
| 1197 | .cout(inc_by_pass_pc_addr_bf_top_data )) ; |
| 1198 | |
| 1199 | ifu_ftu_agd_dp_increment_macro__dincr_8x__width_16 by_p_pc_plus_4_16b_at_bf ( |
| 1200 | .din( {5'b00000,by_pass_pc_addr_to_buf[47:37]} ) , |
| 1201 | .cin(1'b1 ) , |
| 1202 | .dout({by_pass_pc_addr_bf_1_unused[52:48], by_pass_inc_pc_bf_top_inc[47:37] }) , |
| 1203 | .cout(by_pass_pc_addr_bf_2_unused )) ; |
| 1204 | |
| 1205 | ifu_ftu_agd_dp_inv_macro__stack_2c__width_1 by_pass_pc_f_b47_l ( |
| 1206 | .din(by_pass_pc_addr_bf[47]), |
| 1207 | .dout(by_pass_pc_addr_bf_[47]) |
| 1208 | ); |
| 1209 | |
| 1210 | ifu_ftu_agd_dp_and_macro__ports_2__stack_2c__width_1 by_pass_pc_f_incr_b48 ( |
| 1211 | .din0(by_pass_pc_addr_bf_[47]), |
| 1212 | .din1(by_pass_inc_pc_bf_top_inc[47]), |
| 1213 | .dout(by_pass_inc_pc_bf_top_inc[48]) |
| 1214 | ); |
| 1215 | |
| 1216 | |
| 1217 | |
| 1218 | |
| 1219 | |
| 1220 | ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_16c__width_16 by_p_pc_p_plus4_mux ( |
| 1221 | .din0( {4'b0000,by_pass_inc_pc_bf_top_inc[48:37]}), |
| 1222 | .din1( {5'b00000,by_pass_pc_addr_bf[47:37]}), |
| 1223 | .sel0( inc_by_pass_pc_addr_bf_top_data), |
| 1224 | .dout( {by_pass_pc_addr_bf_3_unused[52:49],by_pass_inc_pc_bf[48:37]} )); |
| 1225 | |
| 1226 | |
| 1227 | |
| 1228 | |
| 1229 | |
| 1230 | ifu_ftu_agd_dp_buff_macro__dbuff_32x__rep_1__stack_50c__width_49 by_pass_inc_pc_reg_buf ( |
| 1231 | .din ( {by_pass_inc_pc_bf[48:2],2'b00} ), |
| 1232 | .dout( by_pass_pc_update_bf[48:0] )); |
| 1233 | |
| 1234 | // assign by_pass_pc_update_bf[48:0] = {by_pass_inc_pc_bf[48:2],2'b00} ; |
| 1235 | |
| 1236 | |
| 1237 | /////////////////////////////////////////////////////////////////////// |
| 1238 | // Final mux for the ICADDR // |
| 1239 | /////////////////////////////////////////////////////////////////////// |
| 1240 | |
| 1241 | ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_12c__width_11 mbist_addr_mux ( |
| 1242 | .din0( {agd_mbist_addr_bf[4:0],6'b0}), // |
| 1243 | .din1( {agd_mbist_addr_bf[5:0],agd_mbist_cmpsel_bf[2:0],2'b0}), // |
| 1244 | .sel0( ftp_sel_icv_mbist_addr), |
| 1245 | .dout( mbist_addr_muxed[10:0] )); |
| 1246 | |
| 1247 | ifu_ftu_agd_dp_buff_macro__dbuff_24x__width_1 tst_mux_rep2 ( |
| 1248 | .din ( tcu_muxtest ), |
| 1249 | .dout( tcu_muxtest_rep2 )); |
| 1250 | |
| 1251 | ifu_ftu_agd_dp_buff_macro__minbuff_1__width_9 curr_thr_pc_bf_minbuf ( |
| 1252 | .din ( curr_thr_pc_bf[10:2]), |
| 1253 | .dout( curr_thr_pc_bf_del[10:2]) |
| 1254 | ); |
| 1255 | |
| 1256 | ifu_ftu_agd_dp_mux_macro__mux_pgnpe__ports_5__stack_12c__width_11 icaddr_first_mux ( |
| 1257 | .din0( new_thr_pc_bf[10:0]), // new fetch thread pc |
| 1258 | .din1( {curr_thr_pc_bf_del[10:2],2'b00}),// current thread incr pc. |
| 1259 | .din2( {phys_addr_bf[10:5],5'b00000}), // Icache fill write index. |
| 1260 | .din3( {asi_addr_bf[11:3],2'b00}), // Icache asi write index. |
| 1261 | .din4( mbist_addr_muxed[10:0]), // |
| 1262 | .muxtst (tcu_muxtest_rep2), |
| 1263 | .sel0( ftp_icaddr_sel_first_mux[0]), |
| 1264 | .sel1( ftp_icaddr_sel_first_mux[1]), |
| 1265 | .sel2( ftp_icaddr_sel_first_mux[2]), |
| 1266 | .sel3( ftp_icaddr_sel_first_mux[3]), |
| 1267 | .sel4( ftp_icaddr_sel_first_mux[4]), |
| 1268 | .dout( {agd_ic_index_bf[10:2],agd_ic_index_bf_unused[1:0]} )); |
| 1269 | |
| 1270 | ifu_ftu_agd_dp_buff_macro__dbuff_24x__width_1 tst_mux_rep4 ( |
| 1271 | .din ( tcu_muxtest ), |
| 1272 | .dout( tcu_muxtest_rep4 )); |
| 1273 | |
| 1274 | ifu_ftu_agd_dp_mux_macro__mux_pgnpe__ports_5__stack_6l__width_6 ict_addr_first_mux ( |
| 1275 | .din0( new_thr_pc_bf[10:5]), // new fetch thread pc |
| 1276 | .din1( curr_thr_pc_crit_bf[10:5]), // current thread incr pc. |
| 1277 | .din2( phys_addr_bf[10:5]), // Icache fill write index. |
| 1278 | .din3( asi_addr_bf[11:6]), // Icache asi write index. |
| 1279 | .din4( agd_mbist_addr_bf[5:0]), // bist address |
| 1280 | .muxtst (tcu_muxtest_rep4), |
| 1281 | .sel0( ftp_icaddr_sel_first_mux[0]), |
| 1282 | .sel1( ftp_icaddr_sel_first_mux[1]), |
| 1283 | .sel2( ftp_icaddr_sel_first_mux[2]), |
| 1284 | .sel3( ftp_icaddr_sel_first_mux[3]), |
| 1285 | .sel4( ftp_icaddr_sel_first_mux[4]), |
| 1286 | .dout( agd_ict_index_bf[10:5] )); |
| 1287 | |
| 1288 | ifu_ftu_agd_dp_msff_macro__stack_50c__width_36 mbist_in_reg ( |
| 1289 | .scan_in(mbist_in_reg_scanin), |
| 1290 | .scan_out(mbist_in_reg_scanout), |
| 1291 | .clk ( l2clk ), |
| 1292 | .en ( 1'b1 ), |
| 1293 | .din ( {mbi_addr[5:0],mbi_cmpsel[2:0],mbi_wdata[7:0],agd_mbist_wdata_bf[7:0],agd_mbist_wdata_f[7:0],mbi_icv_read_en, |
| 1294 | mbi_icv_read_en_bf, mbi_icv_read_en_f}), |
| 1295 | .dout( {agd_mbist_addr_bf[5:0],agd_mbist_cmpsel_bf[2:0],agd_mbist_wdata_bf[7:0],agd_mbist_wdata_f[7:0], |
| 1296 | agd_mbist_wdata_c[7:0],mbi_icv_read_en_bf,mbi_icv_read_en_f, mbi_icv_read_en_c} ), |
| 1297 | .se(se), |
| 1298 | .siclk(siclk), |
| 1299 | .soclk(soclk), |
| 1300 | .pce_ov(pce_ov), |
| 1301 | .stop(stop)); |
| 1302 | |
| 1303 | // mux_macro icaddr_mux (width=11,ports=4,mux=aonpe,stack=12c,dmux=8x) ( |
| 1304 | // .din0( agd_ic_index_first_bf[10:0]), // |
| 1305 | // .din1( exu_address0_e[10:0]), // |
| 1306 | // .din2( exu_address1_e[10:0]), // |
| 1307 | // .din3( {agd_mbist_addr_bf[8:0],2'b0}), // |
| 1308 | // .sel0( ftp_icaddr_sel_final_mux[0]), |
| 1309 | // .sel1( ftp_icaddr_sel_final_mux[1]), |
| 1310 | // .sel2( ftp_icaddr_sel_final_mux[2]), |
| 1311 | // .sel3( ftp_icaddr_sel_final_mux[3]), |
| 1312 | // .dout( {agd_ic_index_bf[10:2],agd_ic_index_bf_unused[1:0]} )); |
| 1313 | |
| 1314 | /////////////////////////////////////////////////////////////////////// |
| 1315 | // ICache ADDR Index // |
| 1316 | /////////////////////////////////////////////////////////////////////// |
| 1317 | |
| 1318 | |
| 1319 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_12c__width_5 icv_indx_mux ( |
| 1320 | .din0( phys_addr_bf[10:6]), // |
| 1321 | .din1( inv_addr_bf[10:6] ), // |
| 1322 | .din2( asi_addr_bf[11:7] ), // |
| 1323 | .din3( agd_mbist_addr_bf[4:0]), // |
| 1324 | .sel0( agc_sel_inv_index[0]), |
| 1325 | .sel1( agc_sel_inv_index[1]), |
| 1326 | .sel2( agc_sel_inv_index[2]), |
| 1327 | .sel3( agc_sel_inv_index[3]), |
| 1328 | .dout( agd_icv_windex_bf[10:6] )); |
| 1329 | |
| 1330 | |
| 1331 | ////////////////////////////////////////////// |
| 1332 | ////////////////////////////////////////////// |
| 1333 | ////////////////////////////////////////////// |
| 1334 | ////////////////////////////////////////////// |
| 1335 | ////////////////////////////////////////////// |
| 1336 | // PC at C stage. // |
| 1337 | ////////////////////////////////////////////// |
| 1338 | |
| 1339 | ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_47 pc_c_mux ( |
| 1340 | .din0( pc_wo_by_pass_c[48:2]), |
| 1341 | .din1( by_pass_pc_addr_bf[48:2]), |
| 1342 | .din2( by_pass_pc_addr_f[48:2]), |
| 1343 | .din3( by_pass_pc_addr_c[48:2]), |
| 1344 | .sel0( agc_pc_sel_for_c[0]), |
| 1345 | .sel1( agc_pc_sel_for_c[1]), |
| 1346 | .sel2( agc_pc_sel_for_c[2]), |
| 1347 | .sel3( agc_pc_sel_for_c[3]), |
| 1348 | .dout( pc_c_to_buf[48:2] )); |
| 1349 | |
| 1350 | ifu_ftu_agd_dp_buff_macro__stack_50c__width_47 pc_c_mux_buf ( |
| 1351 | .din ( pc_c_to_buf[48:2] ), |
| 1352 | .dout( pc_c[48:2] )); |
| 1353 | |
| 1354 | assign pc_c[1:0] = 2'b00 ; |
| 1355 | ifu_ftu_agd_dp_msff_macro__minbuff_1__stack_50c__width_49 pc_wo_by_pass_c_reg ( |
| 1356 | .scan_in(pc_wo_by_pass_c_reg_scanin), |
| 1357 | .scan_out(pc_wo_by_pass_c_reg_scanout), |
| 1358 | .clk ( l2clk ), |
| 1359 | .en ( ftp_any_thr_clken ), |
| 1360 | .din ({pc_f[48:2],2'b00}), |
| 1361 | .dout(pc_wo_by_pass_c[48:0] ), |
| 1362 | .se(se), |
| 1363 | .siclk(siclk), |
| 1364 | .soclk(soclk), |
| 1365 | .pce_ov(pce_ov), |
| 1366 | .stop(stop)); |
| 1367 | |
| 1368 | assign ftu_paddr[12:0] = pc_wo_by_pass_c[12:0]; |
| 1369 | assign agd_va_hole_excp_f = pc_f[48] ; |
| 1370 | |
| 1371 | |
| 1372 | ////////////////////////////////////////////// |
| 1373 | ////////////////////////////////////////////// |
| 1374 | ////////////////////////////////////////////// |
| 1375 | |
| 1376 | ifu_ftu_agd_dp_msff_macro__stack_8c__width_8 by_pass_sel_reg ( |
| 1377 | .scan_in(by_pass_sel_reg_scanin), |
| 1378 | .scan_out(by_pass_sel_reg_scanout), |
| 1379 | .clk ( l2clk ), |
| 1380 | .en ( ftp_any_thr_clken ), |
| 1381 | .din ({cmu_thr7_data_ready,cmu_thr6_data_ready,cmu_thr5_data_ready,cmu_thr4_data_ready, |
| 1382 | cmu_thr3_data_ready,cmu_thr2_data_ready,cmu_thr1_data_ready,cmu_thr0_data_ready}), |
| 1383 | .dout(by_pass_sel_bf[7:0] ), |
| 1384 | .se(se), |
| 1385 | .siclk(siclk), |
| 1386 | .soclk(soclk), |
| 1387 | .pce_ov(pce_ov), |
| 1388 | .stop(stop)); |
| 1389 | |
| 1390 | |
| 1391 | ifu_ftu_agd_dp_mux_macro__dmux_8x__mux_aonpe__ports_8__stack_52c__width_51 by_pass_pc_mux ( |
| 1392 | .din0( {thr0_pc_f[48:2],agc_thr0_byp_pc_update_bf[4:2],agc_thr0_byp_incr_bit5}), |
| 1393 | .din1( {thr1_pc_f[48:2],agc_thr1_byp_pc_update_bf[4:2],agc_thr1_byp_incr_bit5}), |
| 1394 | .din2( {thr2_pc_f[48:2],agc_thr2_byp_pc_update_bf[4:2],agc_thr2_byp_incr_bit5}), |
| 1395 | .din3( {thr3_pc_f[48:2],agc_thr3_byp_pc_update_bf[4:2],agc_thr3_byp_incr_bit5}), |
| 1396 | .din4( {thr4_pc_f[48:2],agc_thr4_byp_pc_update_bf[4:2],agc_thr4_byp_incr_bit5}), |
| 1397 | .din5( {thr5_pc_f[48:2],agc_thr5_byp_pc_update_bf[4:2],agc_thr5_byp_incr_bit5}), |
| 1398 | .din6( {thr6_pc_f[48:2],agc_thr6_byp_pc_update_bf[4:2],agc_thr6_byp_incr_bit5}), |
| 1399 | .din7( {thr7_pc_f[48:2],agc_thr7_byp_pc_update_bf[4:2],agc_thr7_byp_incr_bit5}), |
| 1400 | .sel0( by_pass_sel_bf[0]), |
| 1401 | .sel1( by_pass_sel_bf[1]), |
| 1402 | .sel2( by_pass_sel_bf[2]), |
| 1403 | .sel3( by_pass_sel_bf[3]), |
| 1404 | .sel4( by_pass_sel_bf[4]), |
| 1405 | .sel5( by_pass_sel_bf[5]), |
| 1406 | .sel6( by_pass_sel_bf[6]), |
| 1407 | .sel7( by_pass_sel_bf[7]), |
| 1408 | .dout( {by_pass_pc_addr_to_buf[48:2],by_pass_inc_pc_to_buf[4:2], by_pass_pc_addr_bf_incr_to_buf})); |
| 1409 | |
| 1410 | // buff_macro by_pass_pc_mux_buf (width=51,stack=52c) ( |
| 1411 | // .din ( {by_pass_pc_addr_to_buf[48:2],by_pass_inc_pc_to_buf[4:2], by_pass_pc_addr_bf_incr_to_buf}), |
| 1412 | // .dout( {by_pass_pc_addr_bf[48:2],by_pass_inc_pc_bf[4:2], by_pass_pc_addr_bf_incr})); |
| 1413 | |
| 1414 | ifu_ftu_agd_dp_buff_macro__stack_52c__width_50 by_pass_pc_mux_buf ( |
| 1415 | .din ( {by_pass_pc_addr_to_buf[48:2],by_pass_inc_pc_to_buf[4:2]}), |
| 1416 | .dout( {by_pass_pc_addr_bf[48:2],by_pass_inc_pc_bf[4:2]})); |
| 1417 | |
| 1418 | ifu_ftu_agd_dp_msff_macro__stack_50c__width_47 by_pass_pc_f_reg ( |
| 1419 | .scan_in(by_pass_pc_f_reg_scanin), |
| 1420 | .scan_out(by_pass_pc_f_reg_scanout), |
| 1421 | .clk ( l2clk ), |
| 1422 | .en ( ftp_any_thr_clken ), |
| 1423 | .din (by_pass_pc_addr_bf[48:2]), |
| 1424 | .dout(by_pass_pc_addr_f[48:2] ), |
| 1425 | .se(se), |
| 1426 | .siclk(siclk), |
| 1427 | .soclk(soclk), |
| 1428 | .pce_ov(pce_ov), |
| 1429 | .stop(stop)); |
| 1430 | |
| 1431 | |
| 1432 | ifu_ftu_agd_dp_msff_macro__stack_50c__width_47 by_pass_pc_c_reg ( |
| 1433 | .scan_in(by_pass_pc_c_reg_scanin), |
| 1434 | .scan_out(by_pass_pc_c_reg_scanout), |
| 1435 | .clk ( l2clk ), |
| 1436 | .en ( ftp_any_thr_clken ), |
| 1437 | .din (by_pass_pc_addr_f[48:2]), |
| 1438 | .dout(by_pass_pc_addr_c[48:2] ), |
| 1439 | .se(se), |
| 1440 | .siclk(siclk), |
| 1441 | .soclk(soclk), |
| 1442 | .pce_ov(pce_ov), |
| 1443 | .stop(stop)); |
| 1444 | |
| 1445 | |
| 1446 | /////////////////////////////////////////////////////////////////// |
| 1447 | // Stage the physical address to be written to the IC tags. // |
| 1448 | /////////////////////////////////////////////////////////////////// |
| 1449 | ifu_ftu_agd_dp_msff_macro__stack_50c__width_35 phys_addr_bf_reg ( |
| 1450 | .scan_in(phys_addr_bf_reg_scanin), |
| 1451 | .scan_out(phys_addr_bf_reg_scanout), |
| 1452 | .clk ( l2clk ), |
| 1453 | .en ( 1'b1 ), |
| 1454 | .din (cmu_fill_paddr[39:5]), |
| 1455 | .dout(phys_addr_bf[39:5] ), |
| 1456 | .se(se), |
| 1457 | .siclk(siclk), |
| 1458 | .soclk(soclk), |
| 1459 | .pce_ov(pce_ov), |
| 1460 | .stop(stop)); |
| 1461 | |
| 1462 | ifu_ftu_agd_dp_prty_macro__width_8 tag_parity_0_gen ( |
| 1463 | .din (phys_addr_bf[18:11]), |
| 1464 | .dout (tag_parity[0]) |
| 1465 | ); |
| 1466 | |
| 1467 | ifu_ftu_agd_dp_prty_macro__width_8 tag_parity_1_gen ( |
| 1468 | .din (phys_addr_bf[26:19]), |
| 1469 | .dout (tag_parity[1]) |
| 1470 | ); |
| 1471 | |
| 1472 | ifu_ftu_agd_dp_prty_macro__width_8 tag_parity_2_gen ( |
| 1473 | .din (phys_addr_bf[34:27]), |
| 1474 | .dout (tag_parity[2]) |
| 1475 | ); |
| 1476 | |
| 1477 | ifu_ftu_agd_dp_prty_macro__width_8 tag_parity_3_gen ( |
| 1478 | .din ({3'b000,phys_addr_bf[39:35]}), |
| 1479 | .dout (tag_parity[3]) |
| 1480 | ); |
| 1481 | |
| 1482 | ifu_ftu_agd_dp_prty_macro__width_4 tag_parity_gen ( |
| 1483 | .din (tag_parity[3:0]), |
| 1484 | .dout (ic_tag_parity) |
| 1485 | ); |
| 1486 | |
| 1487 | ifu_ftu_agd_dp_msff_macro__stack_12c__width_6 inv_addr_bf_reg ( |
| 1488 | .scan_in(inv_addr_bf_reg_scanin), |
| 1489 | .scan_out(inv_addr_bf_reg_scanout), |
| 1490 | .clk ( l2clk ), |
| 1491 | .en ( 1'b1 ), |
| 1492 | .din ({cmu_icache_invalidate_index[10:6],agd_ic_index_bf[5]}), |
| 1493 | .dout({inv_addr_bf[10:6],agd_ic_index_f[5]} ), |
| 1494 | .se(se), |
| 1495 | .siclk(siclk), |
| 1496 | .soclk(soclk), |
| 1497 | .pce_ov(pce_ov), |
| 1498 | .stop(stop)); |
| 1499 | |
| 1500 | |
| 1501 | |
| 1502 | ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_8r__width_8 icv_valid_f_mux ( |
| 1503 | .din0( icv_valid_f[15:8]), // |
| 1504 | .din1( icv_valid_f[7:0]), // |
| 1505 | .sel0( agd_ic_index_f[5]), |
| 1506 | .dout( agd_itlb_valid_f[7:0] )); |
| 1507 | assign agd_itlb_valid_dupl_f[7:0] = itlb_valid_dupl_f[7:0] ; |
| 1508 | |
| 1509 | ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_8r__width_8 icv_valid_f_below_icv_mux ( |
| 1510 | .din0( icv_valid_f[15:8]), // |
| 1511 | .din1( icv_valid_f[7:0]), // |
| 1512 | .sel0( agd_ic_index_f[5]), |
| 1513 | .dout( agd_itlb_valid_fast_f[7:0] )); |
| 1514 | |
| 1515 | ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_8r__width_8 icv_valid_f_2_mux ( |
| 1516 | .din0( icv_valid_f[31:24]), // |
| 1517 | .din1( icv_valid_f[23:16]), // |
| 1518 | .sel0( agd_ic_index_f[5]), |
| 1519 | .dout( itlb_valid_dupl_f[7:0] )); |
| 1520 | |
| 1521 | // cmp_macro valid_err_detect (dcmp=8x,width=8) ( |
| 1522 | // .dout( agd_ic_valid_err_l_to_buf), |
| 1523 | // .din0( itlb_valid_dupl_f[7:0]), |
| 1524 | // .din1( agd_itlb_valid_f[7:0]) |
| 1525 | // ); |
| 1526 | |
| 1527 | // buff_macro valid_err_detect_buf (width=1,stack=2r) ( |
| 1528 | // .din ( agd_ic_valid_err_l_to_buf ), |
| 1529 | // .dout( agd_ic_valid_err_l )); |
| 1530 | |
| 1531 | ifu_ftu_agd_dp_buff_macro__dbuff_32x__width_1 tst_mux_rep3 ( |
| 1532 | .din ( tcu_muxtest ), |
| 1533 | .dout( tcu_muxtest_rep3 )); |
| 1534 | |
| 1535 | |
| 1536 | ifu_ftu_agd_dp_nand_macro__width_1 tag_data_mux_29_nand0 ( |
| 1537 | .dout( tag_data_29_nand_0), |
| 1538 | .din0( ic_tag_parity), |
| 1539 | .din1( ftp_ict_data_sel_bf[0])); |
| 1540 | |
| 1541 | ifu_ftu_agd_dp_nand_macro__width_1 tag_data_mux_29_nand1 ( |
| 1542 | .dout( tag_data_29_nand_1), |
| 1543 | .din0( asi_wr_data[29]), |
| 1544 | .din1( ftp_ict_data_sel_bf[1])); |
| 1545 | |
| 1546 | ifu_ftu_agd_dp_nand_macro__width_1 tag_data_mux_29_nand2 ( |
| 1547 | .dout( tag_data_29_nand_2), |
| 1548 | .din0( agd_mbist_wdata_bf[5]), |
| 1549 | .din1( ftp_ict_data_sel_bf[2])); |
| 1550 | |
| 1551 | ifu_ftu_agd_dp_nand_macro__ports_3__width_1 tag_data_mux_29_nand3 ( |
| 1552 | .dout( tag_data_29), |
| 1553 | .din0( tag_data_29_nand_0), |
| 1554 | .din1( tag_data_29_nand_1), |
| 1555 | .din2( tag_data_29_nand_2)); |
| 1556 | |
| 1557 | |
| 1558 | ifu_ftu_agd_dp_mux_macro__mux_pgnpe__ports_3__stack_50c__width_33 tag_data_mux ( |
| 1559 | // .din0( {3'b000,ic_tag_parity,phys_addr_bf[39:11]}), // |
| 1560 | .din0( {4'b000,phys_addr_bf[39:11]}), // |
| 1561 | .din1( asi_wr_data[32:0]), // |
| 1562 | .din2( {agd_mbist_wdata_bf[0],agd_mbist_wdata_bf[7:0],agd_mbist_wdata_bf[7:0], agd_mbist_wdata_bf[7:0], agd_mbist_wdata_bf[7:0]}), // |
| 1563 | .muxtst (tcu_muxtest_rep3), |
| 1564 | .sel0( ftp_ict_data_sel_bf[0]), |
| 1565 | .sel1( ftp_ict_data_sel_bf[1]), |
| 1566 | .sel2( ftp_ict_data_sel_bf[2]), |
| 1567 | .dout( agd_asi_bist_wrdata[32:0] )); |
| 1568 | |
| 1569 | assign agd_ict_wrtag_bf[29:0] ={tag_data_29,agd_asi_bist_wrdata[28:0]} ; |
| 1570 | |
| 1571 | |
| 1572 | ifu_ftu_agd_dp_msff_macro__minbuff_1__stack_16c__width_16 valid_c_reg_a ( |
| 1573 | .scan_in(valid_c_reg_a_scanin), |
| 1574 | .scan_out(valid_c_reg_a_scanout), |
| 1575 | .clk ( l2clk ), |
| 1576 | .en ( ftp_any_thr_clken ), |
| 1577 | .din (icv_valid_f[31:16]), |
| 1578 | .dout(icv_valid_c[31:16]), |
| 1579 | .se(se), |
| 1580 | .siclk(siclk), |
| 1581 | .soclk(soclk), |
| 1582 | .pce_ov(pce_ov), |
| 1583 | .stop(stop)); |
| 1584 | |
| 1585 | ifu_ftu_agd_dp_msff_macro__minbuff_1__stack_16c__width_16 valid_c_reg_b ( |
| 1586 | .scan_in(valid_c_reg_b_scanin), |
| 1587 | .scan_out(valid_c_reg_b_scanout), |
| 1588 | .clk ( l2clk ), |
| 1589 | .en ( ftp_any_thr_clken ), |
| 1590 | .din (icv_valid_f[15:0]), |
| 1591 | .dout(icv_valid_c[15:0]), |
| 1592 | .se(se), |
| 1593 | .siclk(siclk), |
| 1594 | .soclk(soclk), |
| 1595 | .pce_ov(pce_ov), |
| 1596 | .stop(stop)); |
| 1597 | |
| 1598 | ifu_ftu_agd_dp_cmp_macro__dcmp_8x__width_32 mbi_icv_fail_cmp ( |
| 1599 | .dout( agd_icv_fail_l), |
| 1600 | .din0( icv_valid_c[31:0]), |
| 1601 | .din1( {agd_mbist_wdata_c[7:0],agd_mbist_wdata_c[7:0],agd_mbist_wdata_c[7:0],agd_mbist_wdata_c[7:0]}) |
| 1602 | ); |
| 1603 | |
| 1604 | ifu_ftu_agd_dp_inv_macro__width_1 icv_fail_inv_macro ( |
| 1605 | .dout( agd_icv_fail), |
| 1606 | .din( agd_icv_fail_l) |
| 1607 | ); |
| 1608 | |
| 1609 | ifu_ftu_agd_dp_and_macro__width_1 icv_fail_and_qual ( |
| 1610 | .dout( ftu_mbi_icv_fail), |
| 1611 | .din0( agd_icv_fail), |
| 1612 | .din1( mbi_icv_read_en_c)); |
| 1613 | |
| 1614 | |
| 1615 | |
| 1616 | // assign agd_ict_wrtag_bf[29:0] = {ic_tag_parity,phys_addr_bf[39:11]} ; |
| 1617 | |
| 1618 | // assign se = tcu_scan_en ; |
| 1619 | // fixscan start: |
| 1620 | assign br_address0_m_reg0_scanin = scan_in ; |
| 1621 | assign br_address0_m_reg1_scanin = br_address0_m_reg0_scanout; |
| 1622 | assign br_address1_m_reg0_scanin = br_address0_m_reg1_scanout; |
| 1623 | assign br_address1_m_reg1_scanin = br_address1_m_reg0_scanout; |
| 1624 | assign thr0_pc_f_reg_scanin = br_address1_m_reg1_scanout; |
| 1625 | assign thr1_pc_f_reg_scanin = thr0_pc_f_reg_scanout ; |
| 1626 | assign thr2_pc_f_reg_scanin = thr1_pc_f_reg_scanout ; |
| 1627 | assign thr3_pc_f_reg_scanin = thr2_pc_f_reg_scanout ; |
| 1628 | assign thr4_pc_f_reg_scanin = thr3_pc_f_reg_scanout ; |
| 1629 | assign thr5_pc_f_reg_scanin = thr4_pc_f_reg_scanout ; |
| 1630 | assign thr6_pc_f_reg_scanin = thr5_pc_f_reg_scanout ; |
| 1631 | assign thr7_pc_f_reg_scanin = thr6_pc_f_reg_scanout ; |
| 1632 | assign pc_f_reg_scanin = thr7_pc_f_reg_scanout ; |
| 1633 | assign mbist_in_reg_scanin = pc_f_reg_scanout ; |
| 1634 | assign pc_wo_by_pass_c_reg_scanin = mbist_in_reg_scanout ; |
| 1635 | assign by_pass_sel_reg_scanin = pc_wo_by_pass_c_reg_scanout; |
| 1636 | assign by_pass_pc_f_reg_scanin = by_pass_sel_reg_scanout ; |
| 1637 | assign by_pass_pc_c_reg_scanin = by_pass_pc_f_reg_scanout ; |
| 1638 | assign phys_addr_bf_reg_scanin = by_pass_pc_c_reg_scanout ; |
| 1639 | assign inv_addr_bf_reg_scanin = phys_addr_bf_reg_scanout ; |
| 1640 | assign valid_c_reg_a_scanin = inv_addr_bf_reg_scanout ; |
| 1641 | assign valid_c_reg_b_scanin = valid_c_reg_a_scanout ; |
| 1642 | assign scan_out = valid_c_reg_b_scanout ; |
| 1643 | // fixscan end: |
| 1644 | endmodule |
| 1645 | |
| 1646 | |
| 1647 | |
| 1648 | |
| 1649 | // |
| 1650 | // buff macro |
| 1651 | // |
| 1652 | // |
| 1653 | |
| 1654 | |
| 1655 | |
| 1656 | |
| 1657 | |
| 1658 | module ifu_ftu_agd_dp_buff_macro__dbuff_32x__stack_none__width_4 ( |
| 1659 | din, |
| 1660 | dout); |
| 1661 | input [3:0] din; |
| 1662 | output [3:0] dout; |
| 1663 | |
| 1664 | |
| 1665 | |
| 1666 | |
| 1667 | |
| 1668 | |
| 1669 | buff #(4) d0_0 ( |
| 1670 | .in(din[3:0]), |
| 1671 | .out(dout[3:0]) |
| 1672 | ); |
| 1673 | |
| 1674 | |
| 1675 | |
| 1676 | |
| 1677 | |
| 1678 | |
| 1679 | |
| 1680 | |
| 1681 | endmodule |
| 1682 | |
| 1683 | |
| 1684 | |
| 1685 | |
| 1686 | |
| 1687 | |
| 1688 | |
| 1689 | |
| 1690 | |
| 1691 | // any PARAMS parms go into naming of macro |
| 1692 | |
| 1693 | module ifu_ftu_agd_dp_msff_macro__stack_24l__width_24 ( |
| 1694 | din, |
| 1695 | clk, |
| 1696 | en, |
| 1697 | se, |
| 1698 | scan_in, |
| 1699 | siclk, |
| 1700 | soclk, |
| 1701 | pce_ov, |
| 1702 | stop, |
| 1703 | dout, |
| 1704 | scan_out); |
| 1705 | wire l1clk; |
| 1706 | wire siclk_out; |
| 1707 | wire soclk_out; |
| 1708 | wire [22:0] so; |
| 1709 | |
| 1710 | input [23:0] din; |
| 1711 | |
| 1712 | |
| 1713 | input clk; |
| 1714 | input en; |
| 1715 | input se; |
| 1716 | input scan_in; |
| 1717 | input siclk; |
| 1718 | input soclk; |
| 1719 | input pce_ov; |
| 1720 | input stop; |
| 1721 | |
| 1722 | |
| 1723 | |
| 1724 | output [23:0] dout; |
| 1725 | |
| 1726 | |
| 1727 | output scan_out; |
| 1728 | |
| 1729 | |
| 1730 | |
| 1731 | |
| 1732 | cl_dp1_l1hdr_8x c0_0 ( |
| 1733 | .l2clk(clk), |
| 1734 | .pce(en), |
| 1735 | .aclk(siclk), |
| 1736 | .bclk(soclk), |
| 1737 | .l1clk(l1clk), |
| 1738 | .se(se), |
| 1739 | .pce_ov(pce_ov), |
| 1740 | .stop(stop), |
| 1741 | .siclk_out(siclk_out), |
| 1742 | .soclk_out(soclk_out) |
| 1743 | ); |
| 1744 | dff #(24) d0_0 ( |
| 1745 | .l1clk(l1clk), |
| 1746 | .siclk(siclk_out), |
| 1747 | .soclk(soclk_out), |
| 1748 | .d(din[23:0]), |
| 1749 | .si({scan_in,so[22:0]}), |
| 1750 | .so({so[22:0],scan_out}), |
| 1751 | .q(dout[23:0]) |
| 1752 | ); |
| 1753 | |
| 1754 | |
| 1755 | |
| 1756 | |
| 1757 | |
| 1758 | |
| 1759 | |
| 1760 | |
| 1761 | |
| 1762 | |
| 1763 | |
| 1764 | |
| 1765 | |
| 1766 | |
| 1767 | |
| 1768 | |
| 1769 | |
| 1770 | |
| 1771 | |
| 1772 | |
| 1773 | endmodule |
| 1774 | |
| 1775 | |
| 1776 | |
| 1777 | |
| 1778 | |
| 1779 | |
| 1780 | |
| 1781 | |
| 1782 | |
| 1783 | // |
| 1784 | // buff macro |
| 1785 | // |
| 1786 | // |
| 1787 | |
| 1788 | |
| 1789 | |
| 1790 | |
| 1791 | |
| 1792 | module ifu_ftu_agd_dp_buff_macro__dbuff_48x__rep_1__stack_50c__width_48 ( |
| 1793 | din, |
| 1794 | dout); |
| 1795 | input [47:0] din; |
| 1796 | output [47:0] dout; |
| 1797 | |
| 1798 | |
| 1799 | |
| 1800 | |
| 1801 | |
| 1802 | |
| 1803 | buff #(48) d0_0 ( |
| 1804 | .in(din[47:0]), |
| 1805 | .out(dout[47:0]) |
| 1806 | ); |
| 1807 | |
| 1808 | |
| 1809 | |
| 1810 | |
| 1811 | |
| 1812 | |
| 1813 | |
| 1814 | |
| 1815 | endmodule |
| 1816 | |
| 1817 | |
| 1818 | |
| 1819 | |
| 1820 | |
| 1821 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1822 | // also for pass-gate with decoder |
| 1823 | |
| 1824 | |
| 1825 | |
| 1826 | |
| 1827 | |
| 1828 | // any PARAMS parms go into naming of macro |
| 1829 | |
| 1830 | module ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_50c__width_49 ( |
| 1831 | din0, |
| 1832 | sel0, |
| 1833 | din1, |
| 1834 | sel1, |
| 1835 | din2, |
| 1836 | sel2, |
| 1837 | dout); |
| 1838 | wire buffout0; |
| 1839 | wire buffout1; |
| 1840 | wire buffout2; |
| 1841 | |
| 1842 | input [48:0] din0; |
| 1843 | input sel0; |
| 1844 | input [48:0] din1; |
| 1845 | input sel1; |
| 1846 | input [48:0] din2; |
| 1847 | input sel2; |
| 1848 | output [48:0] dout; |
| 1849 | |
| 1850 | |
| 1851 | |
| 1852 | |
| 1853 | |
| 1854 | cl_dp1_muxbuff3_8x c0_0 ( |
| 1855 | .in0(sel0), |
| 1856 | .in1(sel1), |
| 1857 | .in2(sel2), |
| 1858 | .out0(buffout0), |
| 1859 | .out1(buffout1), |
| 1860 | .out2(buffout2) |
| 1861 | ); |
| 1862 | mux3s #(49) d0_0 ( |
| 1863 | .sel0(buffout0), |
| 1864 | .sel1(buffout1), |
| 1865 | .sel2(buffout2), |
| 1866 | .in0(din0[48:0]), |
| 1867 | .in1(din1[48:0]), |
| 1868 | .in2(din2[48:0]), |
| 1869 | .dout(dout[48:0]) |
| 1870 | ); |
| 1871 | |
| 1872 | |
| 1873 | |
| 1874 | |
| 1875 | |
| 1876 | |
| 1877 | |
| 1878 | |
| 1879 | |
| 1880 | |
| 1881 | |
| 1882 | |
| 1883 | |
| 1884 | endmodule |
| 1885 | |
| 1886 | |
| 1887 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1888 | // also for pass-gate with decoder |
| 1889 | |
| 1890 | |
| 1891 | |
| 1892 | |
| 1893 | |
| 1894 | // any PARAMS parms go into naming of macro |
| 1895 | |
| 1896 | module ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_49 ( |
| 1897 | din0, |
| 1898 | sel0, |
| 1899 | din1, |
| 1900 | sel1, |
| 1901 | din2, |
| 1902 | sel2, |
| 1903 | din3, |
| 1904 | sel3, |
| 1905 | dout); |
| 1906 | wire buffout0; |
| 1907 | wire buffout1; |
| 1908 | wire buffout2; |
| 1909 | wire buffout3; |
| 1910 | |
| 1911 | input [48:0] din0; |
| 1912 | input sel0; |
| 1913 | input [48:0] din1; |
| 1914 | input sel1; |
| 1915 | input [48:0] din2; |
| 1916 | input sel2; |
| 1917 | input [48:0] din3; |
| 1918 | input sel3; |
| 1919 | output [48:0] dout; |
| 1920 | |
| 1921 | |
| 1922 | |
| 1923 | |
| 1924 | |
| 1925 | cl_dp1_muxbuff4_8x c0_0 ( |
| 1926 | .in0(sel0), |
| 1927 | .in1(sel1), |
| 1928 | .in2(sel2), |
| 1929 | .in3(sel3), |
| 1930 | .out0(buffout0), |
| 1931 | .out1(buffout1), |
| 1932 | .out2(buffout2), |
| 1933 | .out3(buffout3) |
| 1934 | ); |
| 1935 | mux4s #(49) d0_0 ( |
| 1936 | .sel0(buffout0), |
| 1937 | .sel1(buffout1), |
| 1938 | .sel2(buffout2), |
| 1939 | .sel3(buffout3), |
| 1940 | .in0(din0[48:0]), |
| 1941 | .in1(din1[48:0]), |
| 1942 | .in2(din2[48:0]), |
| 1943 | .in3(din3[48:0]), |
| 1944 | .dout(dout[48:0]) |
| 1945 | ); |
| 1946 | |
| 1947 | |
| 1948 | |
| 1949 | |
| 1950 | |
| 1951 | |
| 1952 | |
| 1953 | |
| 1954 | |
| 1955 | |
| 1956 | |
| 1957 | |
| 1958 | |
| 1959 | endmodule |
| 1960 | |
| 1961 | |
| 1962 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1963 | // also for pass-gate with decoder |
| 1964 | |
| 1965 | |
| 1966 | |
| 1967 | |
| 1968 | |
| 1969 | // any PARAMS parms go into naming of macro |
| 1970 | |
| 1971 | module ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_50c__width_49 ( |
| 1972 | din0, |
| 1973 | sel0, |
| 1974 | din1, |
| 1975 | sel1, |
| 1976 | dout); |
| 1977 | wire buffout0; |
| 1978 | wire buffout1; |
| 1979 | |
| 1980 | input [48:0] din0; |
| 1981 | input sel0; |
| 1982 | input [48:0] din1; |
| 1983 | input sel1; |
| 1984 | output [48:0] dout; |
| 1985 | |
| 1986 | |
| 1987 | |
| 1988 | |
| 1989 | |
| 1990 | cl_dp1_muxbuff2_8x c0_0 ( |
| 1991 | .in0(sel0), |
| 1992 | .in1(sel1), |
| 1993 | .out0(buffout0), |
| 1994 | .out1(buffout1) |
| 1995 | ); |
| 1996 | mux2s #(49) d0_0 ( |
| 1997 | .sel0(buffout0), |
| 1998 | .sel1(buffout1), |
| 1999 | .in0(din0[48:0]), |
| 2000 | .in1(din1[48:0]), |
| 2001 | .dout(dout[48:0]) |
| 2002 | ); |
| 2003 | |
| 2004 | |
| 2005 | |
| 2006 | |
| 2007 | |
| 2008 | |
| 2009 | |
| 2010 | |
| 2011 | |
| 2012 | |
| 2013 | |
| 2014 | |
| 2015 | |
| 2016 | endmodule |
| 2017 | |
| 2018 | |
| 2019 | |
| 2020 | |
| 2021 | |
| 2022 | |
| 2023 | // any PARAMS parms go into naming of macro |
| 2024 | |
| 2025 | module ifu_ftu_agd_dp_msff_macro__stack_50c__width_49 ( |
| 2026 | din, |
| 2027 | clk, |
| 2028 | en, |
| 2029 | se, |
| 2030 | scan_in, |
| 2031 | siclk, |
| 2032 | soclk, |
| 2033 | pce_ov, |
| 2034 | stop, |
| 2035 | dout, |
| 2036 | scan_out); |
| 2037 | wire l1clk; |
| 2038 | wire siclk_out; |
| 2039 | wire soclk_out; |
| 2040 | wire [47:0] so; |
| 2041 | |
| 2042 | input [48:0] din; |
| 2043 | |
| 2044 | |
| 2045 | input clk; |
| 2046 | input en; |
| 2047 | input se; |
| 2048 | input scan_in; |
| 2049 | input siclk; |
| 2050 | input soclk; |
| 2051 | input pce_ov; |
| 2052 | input stop; |
| 2053 | |
| 2054 | |
| 2055 | |
| 2056 | output [48:0] dout; |
| 2057 | |
| 2058 | |
| 2059 | output scan_out; |
| 2060 | |
| 2061 | |
| 2062 | |
| 2063 | |
| 2064 | cl_dp1_l1hdr_8x c0_0 ( |
| 2065 | .l2clk(clk), |
| 2066 | .pce(en), |
| 2067 | .aclk(siclk), |
| 2068 | .bclk(soclk), |
| 2069 | .l1clk(l1clk), |
| 2070 | .se(se), |
| 2071 | .pce_ov(pce_ov), |
| 2072 | .stop(stop), |
| 2073 | .siclk_out(siclk_out), |
| 2074 | .soclk_out(soclk_out) |
| 2075 | ); |
| 2076 | dff #(49) d0_0 ( |
| 2077 | .l1clk(l1clk), |
| 2078 | .siclk(siclk_out), |
| 2079 | .soclk(soclk_out), |
| 2080 | .d(din[48:0]), |
| 2081 | .si({scan_in,so[47:0]}), |
| 2082 | .so({so[47:0],scan_out}), |
| 2083 | .q(dout[48:0]) |
| 2084 | ); |
| 2085 | |
| 2086 | |
| 2087 | |
| 2088 | |
| 2089 | |
| 2090 | |
| 2091 | |
| 2092 | |
| 2093 | |
| 2094 | |
| 2095 | |
| 2096 | |
| 2097 | |
| 2098 | |
| 2099 | |
| 2100 | |
| 2101 | |
| 2102 | |
| 2103 | |
| 2104 | |
| 2105 | endmodule |
| 2106 | |
| 2107 | |
| 2108 | |
| 2109 | |
| 2110 | |
| 2111 | |
| 2112 | |
| 2113 | |
| 2114 | |
| 2115 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2116 | // also for pass-gate with decoder |
| 2117 | |
| 2118 | |
| 2119 | |
| 2120 | |
| 2121 | |
| 2122 | // any PARAMS parms go into naming of macro |
| 2123 | |
| 2124 | module ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_50c__width_49 ( |
| 2125 | din0, |
| 2126 | din1, |
| 2127 | sel0, |
| 2128 | dout); |
| 2129 | wire psel0_unused; |
| 2130 | wire psel1; |
| 2131 | |
| 2132 | input [48:0] din0; |
| 2133 | input [48:0] din1; |
| 2134 | input sel0; |
| 2135 | output [48:0] dout; |
| 2136 | |
| 2137 | |
| 2138 | |
| 2139 | |
| 2140 | |
| 2141 | cl_dp1_penc2_8x c0_0 ( |
| 2142 | .sel0(sel0), |
| 2143 | .psel0(psel0_unused), |
| 2144 | .psel1(psel1) |
| 2145 | ); |
| 2146 | |
| 2147 | mux2e #(49) d0_0 ( |
| 2148 | .sel(psel1), |
| 2149 | .in0(din0[48:0]), |
| 2150 | .in1(din1[48:0]), |
| 2151 | .dout(dout[48:0]) |
| 2152 | ); |
| 2153 | |
| 2154 | |
| 2155 | |
| 2156 | |
| 2157 | |
| 2158 | |
| 2159 | |
| 2160 | |
| 2161 | |
| 2162 | |
| 2163 | |
| 2164 | |
| 2165 | |
| 2166 | endmodule |
| 2167 | |
| 2168 | |
| 2169 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2170 | // also for pass-gate with decoder |
| 2171 | |
| 2172 | |
| 2173 | |
| 2174 | |
| 2175 | |
| 2176 | // any PARAMS parms go into naming of macro |
| 2177 | |
| 2178 | module ifu_ftu_agd_dp_mux_macro__dmux_8x__mux_aonpe__ports_8__stack_50c__width_49 ( |
| 2179 | din0, |
| 2180 | sel0, |
| 2181 | din1, |
| 2182 | sel1, |
| 2183 | din2, |
| 2184 | sel2, |
| 2185 | din3, |
| 2186 | sel3, |
| 2187 | din4, |
| 2188 | sel4, |
| 2189 | din5, |
| 2190 | sel5, |
| 2191 | din6, |
| 2192 | sel6, |
| 2193 | din7, |
| 2194 | sel7, |
| 2195 | dout); |
| 2196 | wire buffout0; |
| 2197 | wire buffout1; |
| 2198 | wire buffout2; |
| 2199 | wire buffout3; |
| 2200 | wire buffout4; |
| 2201 | wire buffout5; |
| 2202 | wire buffout6; |
| 2203 | wire buffout7; |
| 2204 | |
| 2205 | input [48:0] din0; |
| 2206 | input sel0; |
| 2207 | input [48:0] din1; |
| 2208 | input sel1; |
| 2209 | input [48:0] din2; |
| 2210 | input sel2; |
| 2211 | input [48:0] din3; |
| 2212 | input sel3; |
| 2213 | input [48:0] din4; |
| 2214 | input sel4; |
| 2215 | input [48:0] din5; |
| 2216 | input sel5; |
| 2217 | input [48:0] din6; |
| 2218 | input sel6; |
| 2219 | input [48:0] din7; |
| 2220 | input sel7; |
| 2221 | output [48:0] dout; |
| 2222 | |
| 2223 | |
| 2224 | |
| 2225 | |
| 2226 | |
| 2227 | cl_dp1_muxbuff8_8x c0_0 ( |
| 2228 | .in0(sel0), |
| 2229 | .in1(sel1), |
| 2230 | .in2(sel2), |
| 2231 | .in3(sel3), |
| 2232 | .in4(sel4), |
| 2233 | .in5(sel5), |
| 2234 | .in6(sel6), |
| 2235 | .in7(sel7), |
| 2236 | .out0(buffout0), |
| 2237 | .out1(buffout1), |
| 2238 | .out2(buffout2), |
| 2239 | .out3(buffout3), |
| 2240 | .out4(buffout4), |
| 2241 | .out5(buffout5), |
| 2242 | .out6(buffout6), |
| 2243 | .out7(buffout7) |
| 2244 | ); |
| 2245 | mux8s #(49) d0_0 ( |
| 2246 | .sel0(buffout0), |
| 2247 | .sel1(buffout1), |
| 2248 | .sel2(buffout2), |
| 2249 | .sel3(buffout3), |
| 2250 | .sel4(buffout4), |
| 2251 | .sel5(buffout5), |
| 2252 | .sel6(buffout6), |
| 2253 | .sel7(buffout7), |
| 2254 | .in0(din0[48:0]), |
| 2255 | .in1(din1[48:0]), |
| 2256 | .in2(din2[48:0]), |
| 2257 | .in3(din3[48:0]), |
| 2258 | .in4(din4[48:0]), |
| 2259 | .in5(din5[48:0]), |
| 2260 | .in6(din6[48:0]), |
| 2261 | .in7(din7[48:0]), |
| 2262 | .dout(dout[48:0]) |
| 2263 | ); |
| 2264 | |
| 2265 | |
| 2266 | |
| 2267 | |
| 2268 | |
| 2269 | |
| 2270 | |
| 2271 | |
| 2272 | |
| 2273 | |
| 2274 | |
| 2275 | |
| 2276 | |
| 2277 | endmodule |
| 2278 | |
| 2279 | |
| 2280 | // |
| 2281 | // buff macro |
| 2282 | // |
| 2283 | // |
| 2284 | |
| 2285 | |
| 2286 | |
| 2287 | |
| 2288 | |
| 2289 | module ifu_ftu_agd_dp_buff_macro__dbuff_48x__width_1 ( |
| 2290 | din, |
| 2291 | dout); |
| 2292 | input [0:0] din; |
| 2293 | output [0:0] dout; |
| 2294 | |
| 2295 | |
| 2296 | |
| 2297 | |
| 2298 | |
| 2299 | |
| 2300 | buff #(1) d0_0 ( |
| 2301 | .in(din[0:0]), |
| 2302 | .out(dout[0:0]) |
| 2303 | ); |
| 2304 | |
| 2305 | |
| 2306 | |
| 2307 | |
| 2308 | |
| 2309 | |
| 2310 | |
| 2311 | |
| 2312 | endmodule |
| 2313 | |
| 2314 | |
| 2315 | |
| 2316 | |
| 2317 | |
| 2318 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2319 | // also for pass-gate with decoder |
| 2320 | |
| 2321 | |
| 2322 | |
| 2323 | |
| 2324 | |
| 2325 | // any PARAMS parms go into naming of macro |
| 2326 | |
| 2327 | module ifu_ftu_agd_dp_mux_macro__mux_pgnpe__ports_6__stack_50c__width_49 ( |
| 2328 | din0, |
| 2329 | sel0, |
| 2330 | din1, |
| 2331 | sel1, |
| 2332 | din2, |
| 2333 | sel2, |
| 2334 | din3, |
| 2335 | sel3, |
| 2336 | din4, |
| 2337 | sel4, |
| 2338 | din5, |
| 2339 | sel5, |
| 2340 | muxtst, |
| 2341 | dout); |
| 2342 | wire buffout0; |
| 2343 | wire buffout1; |
| 2344 | wire buffout2; |
| 2345 | wire buffout3; |
| 2346 | wire buffout4; |
| 2347 | wire buffout5; |
| 2348 | |
| 2349 | input [48:0] din0; |
| 2350 | input sel0; |
| 2351 | input [48:0] din1; |
| 2352 | input sel1; |
| 2353 | input [48:0] din2; |
| 2354 | input sel2; |
| 2355 | input [48:0] din3; |
| 2356 | input sel3; |
| 2357 | input [48:0] din4; |
| 2358 | input sel4; |
| 2359 | input [48:0] din5; |
| 2360 | input sel5; |
| 2361 | input muxtst; |
| 2362 | output [48:0] dout; |
| 2363 | |
| 2364 | |
| 2365 | |
| 2366 | |
| 2367 | |
| 2368 | cl_dp1_muxbuff6_8x c0_0 ( |
| 2369 | .in0(sel0), |
| 2370 | .in1(sel1), |
| 2371 | .in2(sel2), |
| 2372 | .in3(sel3), |
| 2373 | .in4(sel4), |
| 2374 | .in5(sel5), |
| 2375 | .out0(buffout0), |
| 2376 | .out1(buffout1), |
| 2377 | .out2(buffout2), |
| 2378 | .out3(buffout3), |
| 2379 | .out4(buffout4), |
| 2380 | .out5(buffout5) |
| 2381 | ); |
| 2382 | mux6 #(49) d0_0 ( |
| 2383 | .sel0(buffout0), |
| 2384 | .sel1(buffout1), |
| 2385 | .sel2(buffout2), |
| 2386 | .sel3(buffout3), |
| 2387 | .sel4(buffout4), |
| 2388 | .sel5(buffout5), |
| 2389 | .in0(din0[48:0]), |
| 2390 | .in1(din1[48:0]), |
| 2391 | .in2(din2[48:0]), |
| 2392 | .in3(din3[48:0]), |
| 2393 | .in4(din4[48:0]), |
| 2394 | .in5(din5[48:0]), |
| 2395 | .dout(dout[48:0]), |
| 2396 | .muxtst(muxtst) |
| 2397 | ); |
| 2398 | |
| 2399 | |
| 2400 | |
| 2401 | |
| 2402 | |
| 2403 | |
| 2404 | |
| 2405 | |
| 2406 | |
| 2407 | |
| 2408 | |
| 2409 | |
| 2410 | |
| 2411 | endmodule |
| 2412 | |
| 2413 | |
| 2414 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2415 | // also for pass-gate with decoder |
| 2416 | |
| 2417 | |
| 2418 | |
| 2419 | |
| 2420 | |
| 2421 | // any PARAMS parms go into naming of macro |
| 2422 | |
| 2423 | module ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_20r__width_19 ( |
| 2424 | din0, |
| 2425 | sel0, |
| 2426 | din1, |
| 2427 | sel1, |
| 2428 | din2, |
| 2429 | sel2, |
| 2430 | dout); |
| 2431 | wire buffout0; |
| 2432 | wire buffout1; |
| 2433 | wire buffout2; |
| 2434 | |
| 2435 | input [18:0] din0; |
| 2436 | input sel0; |
| 2437 | input [18:0] din1; |
| 2438 | input sel1; |
| 2439 | input [18:0] din2; |
| 2440 | input sel2; |
| 2441 | output [18:0] dout; |
| 2442 | |
| 2443 | |
| 2444 | |
| 2445 | |
| 2446 | |
| 2447 | cl_dp1_muxbuff3_8x c0_0 ( |
| 2448 | .in0(sel0), |
| 2449 | .in1(sel1), |
| 2450 | .in2(sel2), |
| 2451 | .out0(buffout0), |
| 2452 | .out1(buffout1), |
| 2453 | .out2(buffout2) |
| 2454 | ); |
| 2455 | mux3s #(19) d0_0 ( |
| 2456 | .sel0(buffout0), |
| 2457 | .sel1(buffout1), |
| 2458 | .sel2(buffout2), |
| 2459 | .in0(din0[18:0]), |
| 2460 | .in1(din1[18:0]), |
| 2461 | .in2(din2[18:0]), |
| 2462 | .dout(dout[18:0]) |
| 2463 | ); |
| 2464 | |
| 2465 | |
| 2466 | |
| 2467 | |
| 2468 | |
| 2469 | |
| 2470 | |
| 2471 | |
| 2472 | |
| 2473 | |
| 2474 | |
| 2475 | |
| 2476 | |
| 2477 | endmodule |
| 2478 | |
| 2479 | |
| 2480 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2481 | // also for pass-gate with decoder |
| 2482 | |
| 2483 | |
| 2484 | |
| 2485 | |
| 2486 | |
| 2487 | // any PARAMS parms go into naming of macro |
| 2488 | |
| 2489 | module ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_20c__width_16 ( |
| 2490 | din0, |
| 2491 | sel0, |
| 2492 | din1, |
| 2493 | sel1, |
| 2494 | din2, |
| 2495 | sel2, |
| 2496 | din3, |
| 2497 | sel3, |
| 2498 | dout); |
| 2499 | wire buffout0; |
| 2500 | wire buffout1; |
| 2501 | wire buffout2; |
| 2502 | wire buffout3; |
| 2503 | |
| 2504 | input [15:0] din0; |
| 2505 | input sel0; |
| 2506 | input [15:0] din1; |
| 2507 | input sel1; |
| 2508 | input [15:0] din2; |
| 2509 | input sel2; |
| 2510 | input [15:0] din3; |
| 2511 | input sel3; |
| 2512 | output [15:0] dout; |
| 2513 | |
| 2514 | |
| 2515 | |
| 2516 | |
| 2517 | |
| 2518 | cl_dp1_muxbuff4_8x c0_0 ( |
| 2519 | .in0(sel0), |
| 2520 | .in1(sel1), |
| 2521 | .in2(sel2), |
| 2522 | .in3(sel3), |
| 2523 | .out0(buffout0), |
| 2524 | .out1(buffout1), |
| 2525 | .out2(buffout2), |
| 2526 | .out3(buffout3) |
| 2527 | ); |
| 2528 | mux4s #(16) d0_0 ( |
| 2529 | .sel0(buffout0), |
| 2530 | .sel1(buffout1), |
| 2531 | .sel2(buffout2), |
| 2532 | .sel3(buffout3), |
| 2533 | .in0(din0[15:0]), |
| 2534 | .in1(din1[15:0]), |
| 2535 | .in2(din2[15:0]), |
| 2536 | .in3(din3[15:0]), |
| 2537 | .dout(dout[15:0]) |
| 2538 | ); |
| 2539 | |
| 2540 | |
| 2541 | |
| 2542 | |
| 2543 | |
| 2544 | |
| 2545 | |
| 2546 | |
| 2547 | |
| 2548 | |
| 2549 | |
| 2550 | |
| 2551 | |
| 2552 | endmodule |
| 2553 | |
| 2554 | |
| 2555 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2556 | // also for pass-gate with decoder |
| 2557 | |
| 2558 | |
| 2559 | |
| 2560 | |
| 2561 | |
| 2562 | // any PARAMS parms go into naming of macro |
| 2563 | |
| 2564 | module ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_20c__width_19 ( |
| 2565 | din0, |
| 2566 | sel0, |
| 2567 | din1, |
| 2568 | sel1, |
| 2569 | dout); |
| 2570 | wire buffout0; |
| 2571 | wire buffout1; |
| 2572 | |
| 2573 | input [18:0] din0; |
| 2574 | input sel0; |
| 2575 | input [18:0] din1; |
| 2576 | input sel1; |
| 2577 | output [18:0] dout; |
| 2578 | |
| 2579 | |
| 2580 | |
| 2581 | |
| 2582 | |
| 2583 | cl_dp1_muxbuff2_8x c0_0 ( |
| 2584 | .in0(sel0), |
| 2585 | .in1(sel1), |
| 2586 | .out0(buffout0), |
| 2587 | .out1(buffout1) |
| 2588 | ); |
| 2589 | mux2s #(19) d0_0 ( |
| 2590 | .sel0(buffout0), |
| 2591 | .sel1(buffout1), |
| 2592 | .in0(din0[18:0]), |
| 2593 | .in1(din1[18:0]), |
| 2594 | .dout(dout[18:0]) |
| 2595 | ); |
| 2596 | |
| 2597 | |
| 2598 | |
| 2599 | |
| 2600 | |
| 2601 | |
| 2602 | |
| 2603 | |
| 2604 | |
| 2605 | |
| 2606 | |
| 2607 | |
| 2608 | |
| 2609 | endmodule |
| 2610 | |
| 2611 | |
| 2612 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2613 | // also for pass-gate with decoder |
| 2614 | |
| 2615 | |
| 2616 | |
| 2617 | |
| 2618 | |
| 2619 | // any PARAMS parms go into naming of macro |
| 2620 | |
| 2621 | module ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_16c__width_16 ( |
| 2622 | din0, |
| 2623 | sel0, |
| 2624 | din1, |
| 2625 | sel1, |
| 2626 | dout); |
| 2627 | wire buffout0; |
| 2628 | wire buffout1; |
| 2629 | |
| 2630 | input [15:0] din0; |
| 2631 | input sel0; |
| 2632 | input [15:0] din1; |
| 2633 | input sel1; |
| 2634 | output [15:0] dout; |
| 2635 | |
| 2636 | |
| 2637 | |
| 2638 | |
| 2639 | |
| 2640 | cl_dp1_muxbuff2_8x c0_0 ( |
| 2641 | .in0(sel0), |
| 2642 | .in1(sel1), |
| 2643 | .out0(buffout0), |
| 2644 | .out1(buffout1) |
| 2645 | ); |
| 2646 | mux2s #(16) d0_0 ( |
| 2647 | .sel0(buffout0), |
| 2648 | .sel1(buffout1), |
| 2649 | .in0(din0[15:0]), |
| 2650 | .in1(din1[15:0]), |
| 2651 | .dout(dout[15:0]) |
| 2652 | ); |
| 2653 | |
| 2654 | |
| 2655 | |
| 2656 | |
| 2657 | |
| 2658 | |
| 2659 | |
| 2660 | |
| 2661 | |
| 2662 | |
| 2663 | |
| 2664 | |
| 2665 | |
| 2666 | endmodule |
| 2667 | |
| 2668 | |
| 2669 | // |
| 2670 | // buff macro |
| 2671 | // |
| 2672 | // |
| 2673 | |
| 2674 | |
| 2675 | |
| 2676 | |
| 2677 | |
| 2678 | module ifu_ftu_agd_dp_buff_macro__dbuff_40x__rep_1__width_35 ( |
| 2679 | din, |
| 2680 | dout); |
| 2681 | input [34:0] din; |
| 2682 | output [34:0] dout; |
| 2683 | |
| 2684 | |
| 2685 | |
| 2686 | |
| 2687 | |
| 2688 | |
| 2689 | buff #(35) d0_0 ( |
| 2690 | .in(din[34:0]), |
| 2691 | .out(dout[34:0]) |
| 2692 | ); |
| 2693 | |
| 2694 | |
| 2695 | |
| 2696 | |
| 2697 | |
| 2698 | |
| 2699 | |
| 2700 | |
| 2701 | endmodule |
| 2702 | |
| 2703 | |
| 2704 | |
| 2705 | |
| 2706 | |
| 2707 | // |
| 2708 | // invert macro |
| 2709 | // |
| 2710 | // |
| 2711 | |
| 2712 | |
| 2713 | |
| 2714 | |
| 2715 | |
| 2716 | module ifu_ftu_agd_dp_inv_macro__stack_2c__width_1 ( |
| 2717 | din, |
| 2718 | dout); |
| 2719 | input [0:0] din; |
| 2720 | output [0:0] dout; |
| 2721 | |
| 2722 | |
| 2723 | |
| 2724 | |
| 2725 | |
| 2726 | |
| 2727 | inv #(1) d0_0 ( |
| 2728 | .in(din[0:0]), |
| 2729 | .out(dout[0:0]) |
| 2730 | ); |
| 2731 | |
| 2732 | |
| 2733 | |
| 2734 | |
| 2735 | |
| 2736 | |
| 2737 | |
| 2738 | |
| 2739 | |
| 2740 | endmodule |
| 2741 | |
| 2742 | |
| 2743 | |
| 2744 | |
| 2745 | |
| 2746 | // |
| 2747 | // and macro for ports = 2,3,4 |
| 2748 | // |
| 2749 | // |
| 2750 | |
| 2751 | |
| 2752 | |
| 2753 | |
| 2754 | |
| 2755 | module ifu_ftu_agd_dp_and_macro__ports_2__stack_2c__width_1 ( |
| 2756 | din0, |
| 2757 | din1, |
| 2758 | dout); |
| 2759 | input [0:0] din0; |
| 2760 | input [0:0] din1; |
| 2761 | output [0:0] dout; |
| 2762 | |
| 2763 | |
| 2764 | |
| 2765 | |
| 2766 | |
| 2767 | |
| 2768 | and2 #(1) d0_0 ( |
| 2769 | .in0(din0[0:0]), |
| 2770 | .in1(din1[0:0]), |
| 2771 | .out(dout[0:0]) |
| 2772 | ); |
| 2773 | |
| 2774 | |
| 2775 | |
| 2776 | |
| 2777 | |
| 2778 | |
| 2779 | |
| 2780 | |
| 2781 | |
| 2782 | endmodule |
| 2783 | |
| 2784 | |
| 2785 | |
| 2786 | |
| 2787 | |
| 2788 | // |
| 2789 | // increment macro |
| 2790 | // |
| 2791 | // |
| 2792 | |
| 2793 | |
| 2794 | |
| 2795 | |
| 2796 | |
| 2797 | module ifu_ftu_agd_dp_increment_macro__dincr_8x__width_32 ( |
| 2798 | din, |
| 2799 | cin, |
| 2800 | dout, |
| 2801 | cout); |
| 2802 | input [31:0] din; |
| 2803 | input cin; |
| 2804 | output [31:0] dout; |
| 2805 | output cout; |
| 2806 | |
| 2807 | |
| 2808 | |
| 2809 | |
| 2810 | |
| 2811 | |
| 2812 | incr #(32) m0_0 ( |
| 2813 | .cin(cin), |
| 2814 | .in(din[31:0]), |
| 2815 | .out(dout[31:0]), |
| 2816 | .cout(cout) |
| 2817 | ); |
| 2818 | |
| 2819 | |
| 2820 | |
| 2821 | |
| 2822 | |
| 2823 | |
| 2824 | |
| 2825 | |
| 2826 | |
| 2827 | |
| 2828 | |
| 2829 | endmodule |
| 2830 | |
| 2831 | |
| 2832 | |
| 2833 | |
| 2834 | |
| 2835 | // |
| 2836 | // increment macro |
| 2837 | // |
| 2838 | // |
| 2839 | |
| 2840 | |
| 2841 | |
| 2842 | |
| 2843 | |
| 2844 | module ifu_ftu_agd_dp_increment_macro__dincr_8x__width_8 ( |
| 2845 | din, |
| 2846 | cin, |
| 2847 | dout, |
| 2848 | cout); |
| 2849 | input [7:0] din; |
| 2850 | input cin; |
| 2851 | output [7:0] dout; |
| 2852 | output cout; |
| 2853 | |
| 2854 | |
| 2855 | |
| 2856 | |
| 2857 | |
| 2858 | |
| 2859 | incr #(8) m0_0 ( |
| 2860 | .cin(cin), |
| 2861 | .in(din[7:0]), |
| 2862 | .out(dout[7:0]), |
| 2863 | .cout(cout) |
| 2864 | ); |
| 2865 | |
| 2866 | |
| 2867 | |
| 2868 | |
| 2869 | |
| 2870 | |
| 2871 | |
| 2872 | |
| 2873 | |
| 2874 | |
| 2875 | |
| 2876 | endmodule |
| 2877 | |
| 2878 | |
| 2879 | |
| 2880 | |
| 2881 | |
| 2882 | // |
| 2883 | // increment macro |
| 2884 | // |
| 2885 | // |
| 2886 | |
| 2887 | |
| 2888 | |
| 2889 | |
| 2890 | |
| 2891 | module ifu_ftu_agd_dp_increment_macro__dincr_8x__width_16 ( |
| 2892 | din, |
| 2893 | cin, |
| 2894 | dout, |
| 2895 | cout); |
| 2896 | input [15:0] din; |
| 2897 | input cin; |
| 2898 | output [15:0] dout; |
| 2899 | output cout; |
| 2900 | |
| 2901 | |
| 2902 | |
| 2903 | |
| 2904 | |
| 2905 | |
| 2906 | incr #(16) m0_0 ( |
| 2907 | .cin(cin), |
| 2908 | .in(din[15:0]), |
| 2909 | .out(dout[15:0]), |
| 2910 | .cout(cout) |
| 2911 | ); |
| 2912 | |
| 2913 | |
| 2914 | |
| 2915 | |
| 2916 | |
| 2917 | |
| 2918 | |
| 2919 | |
| 2920 | |
| 2921 | |
| 2922 | |
| 2923 | endmodule |
| 2924 | |
| 2925 | |
| 2926 | |
| 2927 | |
| 2928 | |
| 2929 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2930 | // also for pass-gate with decoder |
| 2931 | |
| 2932 | |
| 2933 | |
| 2934 | |
| 2935 | |
| 2936 | // any PARAMS parms go into naming of macro |
| 2937 | |
| 2938 | module ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_16c__width_16 ( |
| 2939 | din0, |
| 2940 | din1, |
| 2941 | sel0, |
| 2942 | dout); |
| 2943 | wire psel0_unused; |
| 2944 | wire psel1; |
| 2945 | |
| 2946 | input [15:0] din0; |
| 2947 | input [15:0] din1; |
| 2948 | input sel0; |
| 2949 | output [15:0] dout; |
| 2950 | |
| 2951 | |
| 2952 | |
| 2953 | |
| 2954 | |
| 2955 | cl_dp1_penc2_8x c0_0 ( |
| 2956 | .sel0(sel0), |
| 2957 | .psel0(psel0_unused), |
| 2958 | .psel1(psel1) |
| 2959 | ); |
| 2960 | |
| 2961 | mux2e #(16) d0_0 ( |
| 2962 | .sel(psel1), |
| 2963 | .in0(din0[15:0]), |
| 2964 | .in1(din1[15:0]), |
| 2965 | .dout(dout[15:0]) |
| 2966 | ); |
| 2967 | |
| 2968 | |
| 2969 | |
| 2970 | |
| 2971 | |
| 2972 | |
| 2973 | |
| 2974 | |
| 2975 | |
| 2976 | |
| 2977 | |
| 2978 | |
| 2979 | |
| 2980 | endmodule |
| 2981 | |
| 2982 | |
| 2983 | // |
| 2984 | // buff macro |
| 2985 | // |
| 2986 | // |
| 2987 | |
| 2988 | |
| 2989 | |
| 2990 | |
| 2991 | |
| 2992 | module ifu_ftu_agd_dp_buff_macro__dbuff_32x__rep_1__stack_50c__width_49 ( |
| 2993 | din, |
| 2994 | dout); |
| 2995 | input [48:0] din; |
| 2996 | output [48:0] dout; |
| 2997 | |
| 2998 | |
| 2999 | |
| 3000 | |
| 3001 | |
| 3002 | |
| 3003 | buff #(49) d0_0 ( |
| 3004 | .in(din[48:0]), |
| 3005 | .out(dout[48:0]) |
| 3006 | ); |
| 3007 | |
| 3008 | |
| 3009 | |
| 3010 | |
| 3011 | |
| 3012 | |
| 3013 | |
| 3014 | |
| 3015 | endmodule |
| 3016 | |
| 3017 | |
| 3018 | |
| 3019 | |
| 3020 | |
| 3021 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 3022 | // also for pass-gate with decoder |
| 3023 | |
| 3024 | |
| 3025 | |
| 3026 | |
| 3027 | |
| 3028 | // any PARAMS parms go into naming of macro |
| 3029 | |
| 3030 | module ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_12c__width_11 ( |
| 3031 | din0, |
| 3032 | din1, |
| 3033 | sel0, |
| 3034 | dout); |
| 3035 | wire psel0_unused; |
| 3036 | wire psel1; |
| 3037 | |
| 3038 | input [10:0] din0; |
| 3039 | input [10:0] din1; |
| 3040 | input sel0; |
| 3041 | output [10:0] dout; |
| 3042 | |
| 3043 | |
| 3044 | |
| 3045 | |
| 3046 | |
| 3047 | cl_dp1_penc2_8x c0_0 ( |
| 3048 | .sel0(sel0), |
| 3049 | .psel0(psel0_unused), |
| 3050 | .psel1(psel1) |
| 3051 | ); |
| 3052 | |
| 3053 | mux2e #(11) d0_0 ( |
| 3054 | .sel(psel1), |
| 3055 | .in0(din0[10:0]), |
| 3056 | .in1(din1[10:0]), |
| 3057 | .dout(dout[10:0]) |
| 3058 | ); |
| 3059 | |
| 3060 | |
| 3061 | |
| 3062 | |
| 3063 | |
| 3064 | |
| 3065 | |
| 3066 | |
| 3067 | |
| 3068 | |
| 3069 | |
| 3070 | |
| 3071 | |
| 3072 | endmodule |
| 3073 | |
| 3074 | |
| 3075 | // |
| 3076 | // buff macro |
| 3077 | // |
| 3078 | // |
| 3079 | |
| 3080 | |
| 3081 | |
| 3082 | |
| 3083 | |
| 3084 | module ifu_ftu_agd_dp_buff_macro__dbuff_24x__width_1 ( |
| 3085 | din, |
| 3086 | dout); |
| 3087 | input [0:0] din; |
| 3088 | output [0:0] dout; |
| 3089 | |
| 3090 | |
| 3091 | |
| 3092 | |
| 3093 | |
| 3094 | |
| 3095 | buff #(1) d0_0 ( |
| 3096 | .in(din[0:0]), |
| 3097 | .out(dout[0:0]) |
| 3098 | ); |
| 3099 | |
| 3100 | |
| 3101 | |
| 3102 | |
| 3103 | |
| 3104 | |
| 3105 | |
| 3106 | |
| 3107 | endmodule |
| 3108 | |
| 3109 | |
| 3110 | |
| 3111 | |
| 3112 | |
| 3113 | // |
| 3114 | // buff macro |
| 3115 | // |
| 3116 | // |
| 3117 | |
| 3118 | |
| 3119 | |
| 3120 | |
| 3121 | |
| 3122 | module ifu_ftu_agd_dp_buff_macro__minbuff_1__width_9 ( |
| 3123 | din, |
| 3124 | dout); |
| 3125 | input [8:0] din; |
| 3126 | output [8:0] dout; |
| 3127 | |
| 3128 | |
| 3129 | |
| 3130 | |
| 3131 | |
| 3132 | |
| 3133 | buff #(9) d0_0 ( |
| 3134 | .in(din[8:0]), |
| 3135 | .out(dout[8:0]) |
| 3136 | ); |
| 3137 | |
| 3138 | |
| 3139 | |
| 3140 | |
| 3141 | |
| 3142 | |
| 3143 | |
| 3144 | |
| 3145 | endmodule |
| 3146 | |
| 3147 | |
| 3148 | |
| 3149 | |
| 3150 | |
| 3151 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 3152 | // also for pass-gate with decoder |
| 3153 | |
| 3154 | |
| 3155 | |
| 3156 | |
| 3157 | |
| 3158 | // any PARAMS parms go into naming of macro |
| 3159 | |
| 3160 | module ifu_ftu_agd_dp_mux_macro__mux_pgnpe__ports_5__stack_12c__width_11 ( |
| 3161 | din0, |
| 3162 | sel0, |
| 3163 | din1, |
| 3164 | sel1, |
| 3165 | din2, |
| 3166 | sel2, |
| 3167 | din3, |
| 3168 | sel3, |
| 3169 | din4, |
| 3170 | sel4, |
| 3171 | muxtst, |
| 3172 | dout); |
| 3173 | wire buffout0; |
| 3174 | wire buffout1; |
| 3175 | wire buffout2; |
| 3176 | wire buffout3; |
| 3177 | wire buffout4; |
| 3178 | |
| 3179 | input [10:0] din0; |
| 3180 | input sel0; |
| 3181 | input [10:0] din1; |
| 3182 | input sel1; |
| 3183 | input [10:0] din2; |
| 3184 | input sel2; |
| 3185 | input [10:0] din3; |
| 3186 | input sel3; |
| 3187 | input [10:0] din4; |
| 3188 | input sel4; |
| 3189 | input muxtst; |
| 3190 | output [10:0] dout; |
| 3191 | |
| 3192 | |
| 3193 | |
| 3194 | |
| 3195 | |
| 3196 | cl_dp1_muxbuff5_8x c0_0 ( |
| 3197 | .in0(sel0), |
| 3198 | .in1(sel1), |
| 3199 | .in2(sel2), |
| 3200 | .in3(sel3), |
| 3201 | .in4(sel4), |
| 3202 | .out0(buffout0), |
| 3203 | .out1(buffout1), |
| 3204 | .out2(buffout2), |
| 3205 | .out3(buffout3), |
| 3206 | .out4(buffout4) |
| 3207 | ); |
| 3208 | mux5 #(11) d0_0 ( |
| 3209 | .sel0(buffout0), |
| 3210 | .sel1(buffout1), |
| 3211 | .sel2(buffout2), |
| 3212 | .sel3(buffout3), |
| 3213 | .sel4(buffout4), |
| 3214 | .in0(din0[10:0]), |
| 3215 | .in1(din1[10:0]), |
| 3216 | .in2(din2[10:0]), |
| 3217 | .in3(din3[10:0]), |
| 3218 | .in4(din4[10:0]), |
| 3219 | .dout(dout[10:0]), |
| 3220 | .muxtst(muxtst) |
| 3221 | ); |
| 3222 | |
| 3223 | |
| 3224 | |
| 3225 | |
| 3226 | |
| 3227 | |
| 3228 | |
| 3229 | |
| 3230 | |
| 3231 | |
| 3232 | |
| 3233 | |
| 3234 | |
| 3235 | endmodule |
| 3236 | |
| 3237 | |
| 3238 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 3239 | // also for pass-gate with decoder |
| 3240 | |
| 3241 | |
| 3242 | |
| 3243 | |
| 3244 | |
| 3245 | // any PARAMS parms go into naming of macro |
| 3246 | |
| 3247 | module ifu_ftu_agd_dp_mux_macro__mux_pgnpe__ports_5__stack_6l__width_6 ( |
| 3248 | din0, |
| 3249 | sel0, |
| 3250 | din1, |
| 3251 | sel1, |
| 3252 | din2, |
| 3253 | sel2, |
| 3254 | din3, |
| 3255 | sel3, |
| 3256 | din4, |
| 3257 | sel4, |
| 3258 | muxtst, |
| 3259 | dout); |
| 3260 | wire buffout0; |
| 3261 | wire buffout1; |
| 3262 | wire buffout2; |
| 3263 | wire buffout3; |
| 3264 | wire buffout4; |
| 3265 | |
| 3266 | input [5:0] din0; |
| 3267 | input sel0; |
| 3268 | input [5:0] din1; |
| 3269 | input sel1; |
| 3270 | input [5:0] din2; |
| 3271 | input sel2; |
| 3272 | input [5:0] din3; |
| 3273 | input sel3; |
| 3274 | input [5:0] din4; |
| 3275 | input sel4; |
| 3276 | input muxtst; |
| 3277 | output [5:0] dout; |
| 3278 | |
| 3279 | |
| 3280 | |
| 3281 | |
| 3282 | |
| 3283 | cl_dp1_muxbuff5_8x c0_0 ( |
| 3284 | .in0(sel0), |
| 3285 | .in1(sel1), |
| 3286 | .in2(sel2), |
| 3287 | .in3(sel3), |
| 3288 | .in4(sel4), |
| 3289 | .out0(buffout0), |
| 3290 | .out1(buffout1), |
| 3291 | .out2(buffout2), |
| 3292 | .out3(buffout3), |
| 3293 | .out4(buffout4) |
| 3294 | ); |
| 3295 | mux5 #(6) d0_0 ( |
| 3296 | .sel0(buffout0), |
| 3297 | .sel1(buffout1), |
| 3298 | .sel2(buffout2), |
| 3299 | .sel3(buffout3), |
| 3300 | .sel4(buffout4), |
| 3301 | .in0(din0[5:0]), |
| 3302 | .in1(din1[5:0]), |
| 3303 | .in2(din2[5:0]), |
| 3304 | .in3(din3[5:0]), |
| 3305 | .in4(din4[5:0]), |
| 3306 | .dout(dout[5:0]), |
| 3307 | .muxtst(muxtst) |
| 3308 | ); |
| 3309 | |
| 3310 | |
| 3311 | |
| 3312 | |
| 3313 | |
| 3314 | |
| 3315 | |
| 3316 | |
| 3317 | |
| 3318 | |
| 3319 | |
| 3320 | |
| 3321 | |
| 3322 | endmodule |
| 3323 | |
| 3324 | |
| 3325 | |
| 3326 | |
| 3327 | |
| 3328 | |
| 3329 | // any PARAMS parms go into naming of macro |
| 3330 | |
| 3331 | module ifu_ftu_agd_dp_msff_macro__stack_50c__width_36 ( |
| 3332 | din, |
| 3333 | clk, |
| 3334 | en, |
| 3335 | se, |
| 3336 | scan_in, |
| 3337 | siclk, |
| 3338 | soclk, |
| 3339 | pce_ov, |
| 3340 | stop, |
| 3341 | dout, |
| 3342 | scan_out); |
| 3343 | wire l1clk; |
| 3344 | wire siclk_out; |
| 3345 | wire soclk_out; |
| 3346 | wire [34:0] so; |
| 3347 | |
| 3348 | input [35:0] din; |
| 3349 | |
| 3350 | |
| 3351 | input clk; |
| 3352 | input en; |
| 3353 | input se; |
| 3354 | input scan_in; |
| 3355 | input siclk; |
| 3356 | input soclk; |
| 3357 | input pce_ov; |
| 3358 | input stop; |
| 3359 | |
| 3360 | |
| 3361 | |
| 3362 | output [35:0] dout; |
| 3363 | |
| 3364 | |
| 3365 | output scan_out; |
| 3366 | |
| 3367 | |
| 3368 | |
| 3369 | |
| 3370 | cl_dp1_l1hdr_8x c0_0 ( |
| 3371 | .l2clk(clk), |
| 3372 | .pce(en), |
| 3373 | .aclk(siclk), |
| 3374 | .bclk(soclk), |
| 3375 | .l1clk(l1clk), |
| 3376 | .se(se), |
| 3377 | .pce_ov(pce_ov), |
| 3378 | .stop(stop), |
| 3379 | .siclk_out(siclk_out), |
| 3380 | .soclk_out(soclk_out) |
| 3381 | ); |
| 3382 | dff #(36) d0_0 ( |
| 3383 | .l1clk(l1clk), |
| 3384 | .siclk(siclk_out), |
| 3385 | .soclk(soclk_out), |
| 3386 | .d(din[35:0]), |
| 3387 | .si({scan_in,so[34:0]}), |
| 3388 | .so({so[34:0],scan_out}), |
| 3389 | .q(dout[35:0]) |
| 3390 | ); |
| 3391 | |
| 3392 | |
| 3393 | |
| 3394 | |
| 3395 | |
| 3396 | |
| 3397 | |
| 3398 | |
| 3399 | |
| 3400 | |
| 3401 | |
| 3402 | |
| 3403 | |
| 3404 | |
| 3405 | |
| 3406 | |
| 3407 | |
| 3408 | |
| 3409 | |
| 3410 | |
| 3411 | endmodule |
| 3412 | |
| 3413 | |
| 3414 | |
| 3415 | |
| 3416 | |
| 3417 | |
| 3418 | |
| 3419 | |
| 3420 | |
| 3421 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 3422 | // also for pass-gate with decoder |
| 3423 | |
| 3424 | |
| 3425 | |
| 3426 | |
| 3427 | |
| 3428 | // any PARAMS parms go into naming of macro |
| 3429 | |
| 3430 | module ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_12c__width_5 ( |
| 3431 | din0, |
| 3432 | sel0, |
| 3433 | din1, |
| 3434 | sel1, |
| 3435 | din2, |
| 3436 | sel2, |
| 3437 | din3, |
| 3438 | sel3, |
| 3439 | dout); |
| 3440 | wire buffout0; |
| 3441 | wire buffout1; |
| 3442 | wire buffout2; |
| 3443 | wire buffout3; |
| 3444 | |
| 3445 | input [4:0] din0; |
| 3446 | input sel0; |
| 3447 | input [4:0] din1; |
| 3448 | input sel1; |
| 3449 | input [4:0] din2; |
| 3450 | input sel2; |
| 3451 | input [4:0] din3; |
| 3452 | input sel3; |
| 3453 | output [4:0] dout; |
| 3454 | |
| 3455 | |
| 3456 | |
| 3457 | |
| 3458 | |
| 3459 | cl_dp1_muxbuff4_8x c0_0 ( |
| 3460 | .in0(sel0), |
| 3461 | .in1(sel1), |
| 3462 | .in2(sel2), |
| 3463 | .in3(sel3), |
| 3464 | .out0(buffout0), |
| 3465 | .out1(buffout1), |
| 3466 | .out2(buffout2), |
| 3467 | .out3(buffout3) |
| 3468 | ); |
| 3469 | mux4s #(5) d0_0 ( |
| 3470 | .sel0(buffout0), |
| 3471 | .sel1(buffout1), |
| 3472 | .sel2(buffout2), |
| 3473 | .sel3(buffout3), |
| 3474 | .in0(din0[4:0]), |
| 3475 | .in1(din1[4:0]), |
| 3476 | .in2(din2[4:0]), |
| 3477 | .in3(din3[4:0]), |
| 3478 | .dout(dout[4:0]) |
| 3479 | ); |
| 3480 | |
| 3481 | |
| 3482 | |
| 3483 | |
| 3484 | |
| 3485 | |
| 3486 | |
| 3487 | |
| 3488 | |
| 3489 | |
| 3490 | |
| 3491 | |
| 3492 | |
| 3493 | endmodule |
| 3494 | |
| 3495 | |
| 3496 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 3497 | // also for pass-gate with decoder |
| 3498 | |
| 3499 | |
| 3500 | |
| 3501 | |
| 3502 | |
| 3503 | // any PARAMS parms go into naming of macro |
| 3504 | |
| 3505 | module ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_47 ( |
| 3506 | din0, |
| 3507 | sel0, |
| 3508 | din1, |
| 3509 | sel1, |
| 3510 | din2, |
| 3511 | sel2, |
| 3512 | din3, |
| 3513 | sel3, |
| 3514 | dout); |
| 3515 | wire buffout0; |
| 3516 | wire buffout1; |
| 3517 | wire buffout2; |
| 3518 | wire buffout3; |
| 3519 | |
| 3520 | input [46:0] din0; |
| 3521 | input sel0; |
| 3522 | input [46:0] din1; |
| 3523 | input sel1; |
| 3524 | input [46:0] din2; |
| 3525 | input sel2; |
| 3526 | input [46:0] din3; |
| 3527 | input sel3; |
| 3528 | output [46:0] dout; |
| 3529 | |
| 3530 | |
| 3531 | |
| 3532 | |
| 3533 | |
| 3534 | cl_dp1_muxbuff4_8x c0_0 ( |
| 3535 | .in0(sel0), |
| 3536 | .in1(sel1), |
| 3537 | .in2(sel2), |
| 3538 | .in3(sel3), |
| 3539 | .out0(buffout0), |
| 3540 | .out1(buffout1), |
| 3541 | .out2(buffout2), |
| 3542 | .out3(buffout3) |
| 3543 | ); |
| 3544 | mux4s #(47) d0_0 ( |
| 3545 | .sel0(buffout0), |
| 3546 | .sel1(buffout1), |
| 3547 | .sel2(buffout2), |
| 3548 | .sel3(buffout3), |
| 3549 | .in0(din0[46:0]), |
| 3550 | .in1(din1[46:0]), |
| 3551 | .in2(din2[46:0]), |
| 3552 | .in3(din3[46:0]), |
| 3553 | .dout(dout[46:0]) |
| 3554 | ); |
| 3555 | |
| 3556 | |
| 3557 | |
| 3558 | |
| 3559 | |
| 3560 | |
| 3561 | |
| 3562 | |
| 3563 | |
| 3564 | |
| 3565 | |
| 3566 | |
| 3567 | |
| 3568 | endmodule |
| 3569 | |
| 3570 | |
| 3571 | // |
| 3572 | // buff macro |
| 3573 | // |
| 3574 | // |
| 3575 | |
| 3576 | |
| 3577 | |
| 3578 | |
| 3579 | |
| 3580 | module ifu_ftu_agd_dp_buff_macro__stack_50c__width_47 ( |
| 3581 | din, |
| 3582 | dout); |
| 3583 | input [46:0] din; |
| 3584 | output [46:0] dout; |
| 3585 | |
| 3586 | |
| 3587 | |
| 3588 | |
| 3589 | |
| 3590 | |
| 3591 | buff #(47) d0_0 ( |
| 3592 | .in(din[46:0]), |
| 3593 | .out(dout[46:0]) |
| 3594 | ); |
| 3595 | |
| 3596 | |
| 3597 | |
| 3598 | |
| 3599 | |
| 3600 | |
| 3601 | |
| 3602 | |
| 3603 | endmodule |
| 3604 | |
| 3605 | |
| 3606 | |
| 3607 | |
| 3608 | |
| 3609 | |
| 3610 | |
| 3611 | |
| 3612 | |
| 3613 | // any PARAMS parms go into naming of macro |
| 3614 | |
| 3615 | module ifu_ftu_agd_dp_msff_macro__minbuff_1__stack_50c__width_49 ( |
| 3616 | din, |
| 3617 | clk, |
| 3618 | en, |
| 3619 | se, |
| 3620 | scan_in, |
| 3621 | siclk, |
| 3622 | soclk, |
| 3623 | pce_ov, |
| 3624 | stop, |
| 3625 | dout, |
| 3626 | scan_out); |
| 3627 | wire l1clk; |
| 3628 | wire siclk_out; |
| 3629 | wire soclk_out; |
| 3630 | wire [47:0] so; |
| 3631 | |
| 3632 | input [48:0] din; |
| 3633 | |
| 3634 | |
| 3635 | input clk; |
| 3636 | input en; |
| 3637 | input se; |
| 3638 | input scan_in; |
| 3639 | input siclk; |
| 3640 | input soclk; |
| 3641 | input pce_ov; |
| 3642 | input stop; |
| 3643 | |
| 3644 | |
| 3645 | |
| 3646 | output [48:0] dout; |
| 3647 | |
| 3648 | |
| 3649 | output scan_out; |
| 3650 | |
| 3651 | |
| 3652 | |
| 3653 | |
| 3654 | cl_dp1_l1hdr_8x c0_0 ( |
| 3655 | .l2clk(clk), |
| 3656 | .pce(en), |
| 3657 | .aclk(siclk), |
| 3658 | .bclk(soclk), |
| 3659 | .l1clk(l1clk), |
| 3660 | .se(se), |
| 3661 | .pce_ov(pce_ov), |
| 3662 | .stop(stop), |
| 3663 | .siclk_out(siclk_out), |
| 3664 | .soclk_out(soclk_out) |
| 3665 | ); |
| 3666 | dff #(49) d0_0 ( |
| 3667 | .l1clk(l1clk), |
| 3668 | .siclk(siclk_out), |
| 3669 | .soclk(soclk_out), |
| 3670 | .d(din[48:0]), |
| 3671 | .si({scan_in,so[47:0]}), |
| 3672 | .so({so[47:0],scan_out}), |
| 3673 | .q(dout[48:0]) |
| 3674 | ); |
| 3675 | |
| 3676 | |
| 3677 | |
| 3678 | |
| 3679 | |
| 3680 | |
| 3681 | |
| 3682 | |
| 3683 | |
| 3684 | |
| 3685 | |
| 3686 | |
| 3687 | |
| 3688 | |
| 3689 | |
| 3690 | |
| 3691 | |
| 3692 | |
| 3693 | |
| 3694 | |
| 3695 | endmodule |
| 3696 | |
| 3697 | |
| 3698 | |
| 3699 | |
| 3700 | |
| 3701 | |
| 3702 | |
| 3703 | |
| 3704 | |
| 3705 | |
| 3706 | |
| 3707 | |
| 3708 | |
| 3709 | // any PARAMS parms go into naming of macro |
| 3710 | |
| 3711 | module ifu_ftu_agd_dp_msff_macro__stack_8c__width_8 ( |
| 3712 | din, |
| 3713 | clk, |
| 3714 | en, |
| 3715 | se, |
| 3716 | scan_in, |
| 3717 | siclk, |
| 3718 | soclk, |
| 3719 | pce_ov, |
| 3720 | stop, |
| 3721 | dout, |
| 3722 | scan_out); |
| 3723 | wire l1clk; |
| 3724 | wire siclk_out; |
| 3725 | wire soclk_out; |
| 3726 | wire [6:0] so; |
| 3727 | |
| 3728 | input [7:0] din; |
| 3729 | |
| 3730 | |
| 3731 | input clk; |
| 3732 | input en; |
| 3733 | input se; |
| 3734 | input scan_in; |
| 3735 | input siclk; |
| 3736 | input soclk; |
| 3737 | input pce_ov; |
| 3738 | input stop; |
| 3739 | |
| 3740 | |
| 3741 | |
| 3742 | output [7:0] dout; |
| 3743 | |
| 3744 | |
| 3745 | output scan_out; |
| 3746 | |
| 3747 | |
| 3748 | |
| 3749 | |
| 3750 | cl_dp1_l1hdr_8x c0_0 ( |
| 3751 | .l2clk(clk), |
| 3752 | .pce(en), |
| 3753 | .aclk(siclk), |
| 3754 | .bclk(soclk), |
| 3755 | .l1clk(l1clk), |
| 3756 | .se(se), |
| 3757 | .pce_ov(pce_ov), |
| 3758 | .stop(stop), |
| 3759 | .siclk_out(siclk_out), |
| 3760 | .soclk_out(soclk_out) |
| 3761 | ); |
| 3762 | dff #(8) d0_0 ( |
| 3763 | .l1clk(l1clk), |
| 3764 | .siclk(siclk_out), |
| 3765 | .soclk(soclk_out), |
| 3766 | .d(din[7:0]), |
| 3767 | .si({scan_in,so[6:0]}), |
| 3768 | .so({so[6:0],scan_out}), |
| 3769 | .q(dout[7:0]) |
| 3770 | ); |
| 3771 | |
| 3772 | |
| 3773 | |
| 3774 | |
| 3775 | |
| 3776 | |
| 3777 | |
| 3778 | |
| 3779 | |
| 3780 | |
| 3781 | |
| 3782 | |
| 3783 | |
| 3784 | |
| 3785 | |
| 3786 | |
| 3787 | |
| 3788 | |
| 3789 | |
| 3790 | |
| 3791 | endmodule |
| 3792 | |
| 3793 | |
| 3794 | |
| 3795 | |
| 3796 | |
| 3797 | |
| 3798 | |
| 3799 | |
| 3800 | |
| 3801 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 3802 | // also for pass-gate with decoder |
| 3803 | |
| 3804 | |
| 3805 | |
| 3806 | |
| 3807 | |
| 3808 | // any PARAMS parms go into naming of macro |
| 3809 | |
| 3810 | module ifu_ftu_agd_dp_mux_macro__dmux_8x__mux_aonpe__ports_8__stack_52c__width_51 ( |
| 3811 | din0, |
| 3812 | sel0, |
| 3813 | din1, |
| 3814 | sel1, |
| 3815 | din2, |
| 3816 | sel2, |
| 3817 | din3, |
| 3818 | sel3, |
| 3819 | din4, |
| 3820 | sel4, |
| 3821 | din5, |
| 3822 | sel5, |
| 3823 | din6, |
| 3824 | sel6, |
| 3825 | din7, |
| 3826 | sel7, |
| 3827 | dout); |
| 3828 | wire buffout0; |
| 3829 | wire buffout1; |
| 3830 | wire buffout2; |
| 3831 | wire buffout3; |
| 3832 | wire buffout4; |
| 3833 | wire buffout5; |
| 3834 | wire buffout6; |
| 3835 | wire buffout7; |
| 3836 | |
| 3837 | input [50:0] din0; |
| 3838 | input sel0; |
| 3839 | input [50:0] din1; |
| 3840 | input sel1; |
| 3841 | input [50:0] din2; |
| 3842 | input sel2; |
| 3843 | input [50:0] din3; |
| 3844 | input sel3; |
| 3845 | input [50:0] din4; |
| 3846 | input sel4; |
| 3847 | input [50:0] din5; |
| 3848 | input sel5; |
| 3849 | input [50:0] din6; |
| 3850 | input sel6; |
| 3851 | input [50:0] din7; |
| 3852 | input sel7; |
| 3853 | output [50:0] dout; |
| 3854 | |
| 3855 | |
| 3856 | |
| 3857 | |
| 3858 | |
| 3859 | cl_dp1_muxbuff8_8x c0_0 ( |
| 3860 | .in0(sel0), |
| 3861 | .in1(sel1), |
| 3862 | .in2(sel2), |
| 3863 | .in3(sel3), |
| 3864 | .in4(sel4), |
| 3865 | .in5(sel5), |
| 3866 | .in6(sel6), |
| 3867 | .in7(sel7), |
| 3868 | .out0(buffout0), |
| 3869 | .out1(buffout1), |
| 3870 | .out2(buffout2), |
| 3871 | .out3(buffout3), |
| 3872 | .out4(buffout4), |
| 3873 | .out5(buffout5), |
| 3874 | .out6(buffout6), |
| 3875 | .out7(buffout7) |
| 3876 | ); |
| 3877 | mux8s #(51) d0_0 ( |
| 3878 | .sel0(buffout0), |
| 3879 | .sel1(buffout1), |
| 3880 | .sel2(buffout2), |
| 3881 | .sel3(buffout3), |
| 3882 | .sel4(buffout4), |
| 3883 | .sel5(buffout5), |
| 3884 | .sel6(buffout6), |
| 3885 | .sel7(buffout7), |
| 3886 | .in0(din0[50:0]), |
| 3887 | .in1(din1[50:0]), |
| 3888 | .in2(din2[50:0]), |
| 3889 | .in3(din3[50:0]), |
| 3890 | .in4(din4[50:0]), |
| 3891 | .in5(din5[50:0]), |
| 3892 | .in6(din6[50:0]), |
| 3893 | .in7(din7[50:0]), |
| 3894 | .dout(dout[50:0]) |
| 3895 | ); |
| 3896 | |
| 3897 | |
| 3898 | |
| 3899 | |
| 3900 | |
| 3901 | |
| 3902 | |
| 3903 | |
| 3904 | |
| 3905 | |
| 3906 | |
| 3907 | |
| 3908 | |
| 3909 | endmodule |
| 3910 | |
| 3911 | |
| 3912 | // |
| 3913 | // buff macro |
| 3914 | // |
| 3915 | // |
| 3916 | |
| 3917 | |
| 3918 | |
| 3919 | |
| 3920 | |
| 3921 | module ifu_ftu_agd_dp_buff_macro__stack_52c__width_50 ( |
| 3922 | din, |
| 3923 | dout); |
| 3924 | input [49:0] din; |
| 3925 | output [49:0] dout; |
| 3926 | |
| 3927 | |
| 3928 | |
| 3929 | |
| 3930 | |
| 3931 | |
| 3932 | buff #(50) d0_0 ( |
| 3933 | .in(din[49:0]), |
| 3934 | .out(dout[49:0]) |
| 3935 | ); |
| 3936 | |
| 3937 | |
| 3938 | |
| 3939 | |
| 3940 | |
| 3941 | |
| 3942 | |
| 3943 | |
| 3944 | endmodule |
| 3945 | |
| 3946 | |
| 3947 | |
| 3948 | |
| 3949 | |
| 3950 | |
| 3951 | |
| 3952 | |
| 3953 | |
| 3954 | // any PARAMS parms go into naming of macro |
| 3955 | |
| 3956 | module ifu_ftu_agd_dp_msff_macro__stack_50c__width_47 ( |
| 3957 | din, |
| 3958 | clk, |
| 3959 | en, |
| 3960 | se, |
| 3961 | scan_in, |
| 3962 | siclk, |
| 3963 | soclk, |
| 3964 | pce_ov, |
| 3965 | stop, |
| 3966 | dout, |
| 3967 | scan_out); |
| 3968 | wire l1clk; |
| 3969 | wire siclk_out; |
| 3970 | wire soclk_out; |
| 3971 | wire [45:0] so; |
| 3972 | |
| 3973 | input [46:0] din; |
| 3974 | |
| 3975 | |
| 3976 | input clk; |
| 3977 | input en; |
| 3978 | input se; |
| 3979 | input scan_in; |
| 3980 | input siclk; |
| 3981 | input soclk; |
| 3982 | input pce_ov; |
| 3983 | input stop; |
| 3984 | |
| 3985 | |
| 3986 | |
| 3987 | output [46:0] dout; |
| 3988 | |
| 3989 | |
| 3990 | output scan_out; |
| 3991 | |
| 3992 | |
| 3993 | |
| 3994 | |
| 3995 | cl_dp1_l1hdr_8x c0_0 ( |
| 3996 | .l2clk(clk), |
| 3997 | .pce(en), |
| 3998 | .aclk(siclk), |
| 3999 | .bclk(soclk), |
| 4000 | .l1clk(l1clk), |
| 4001 | .se(se), |
| 4002 | .pce_ov(pce_ov), |
| 4003 | .stop(stop), |
| 4004 | .siclk_out(siclk_out), |
| 4005 | .soclk_out(soclk_out) |
| 4006 | ); |
| 4007 | dff #(47) d0_0 ( |
| 4008 | .l1clk(l1clk), |
| 4009 | .siclk(siclk_out), |
| 4010 | .soclk(soclk_out), |
| 4011 | .d(din[46:0]), |
| 4012 | .si({scan_in,so[45:0]}), |
| 4013 | .so({so[45:0],scan_out}), |
| 4014 | .q(dout[46:0]) |
| 4015 | ); |
| 4016 | |
| 4017 | |
| 4018 | |
| 4019 | |
| 4020 | |
| 4021 | |
| 4022 | |
| 4023 | |
| 4024 | |
| 4025 | |
| 4026 | |
| 4027 | |
| 4028 | |
| 4029 | |
| 4030 | |
| 4031 | |
| 4032 | |
| 4033 | |
| 4034 | |
| 4035 | |
| 4036 | endmodule |
| 4037 | |
| 4038 | |
| 4039 | |
| 4040 | |
| 4041 | |
| 4042 | |
| 4043 | |
| 4044 | |
| 4045 | |
| 4046 | |
| 4047 | |
| 4048 | |
| 4049 | |
| 4050 | // any PARAMS parms go into naming of macro |
| 4051 | |
| 4052 | module ifu_ftu_agd_dp_msff_macro__stack_50c__width_35 ( |
| 4053 | din, |
| 4054 | clk, |
| 4055 | en, |
| 4056 | se, |
| 4057 | scan_in, |
| 4058 | siclk, |
| 4059 | soclk, |
| 4060 | pce_ov, |
| 4061 | stop, |
| 4062 | dout, |
| 4063 | scan_out); |
| 4064 | wire l1clk; |
| 4065 | wire siclk_out; |
| 4066 | wire soclk_out; |
| 4067 | wire [33:0] so; |
| 4068 | |
| 4069 | input [34:0] din; |
| 4070 | |
| 4071 | |
| 4072 | input clk; |
| 4073 | input en; |
| 4074 | input se; |
| 4075 | input scan_in; |
| 4076 | input siclk; |
| 4077 | input soclk; |
| 4078 | input pce_ov; |
| 4079 | input stop; |
| 4080 | |
| 4081 | |
| 4082 | |
| 4083 | output [34:0] dout; |
| 4084 | |
| 4085 | |
| 4086 | output scan_out; |
| 4087 | |
| 4088 | |
| 4089 | |
| 4090 | |
| 4091 | cl_dp1_l1hdr_8x c0_0 ( |
| 4092 | .l2clk(clk), |
| 4093 | .pce(en), |
| 4094 | .aclk(siclk), |
| 4095 | .bclk(soclk), |
| 4096 | .l1clk(l1clk), |
| 4097 | .se(se), |
| 4098 | .pce_ov(pce_ov), |
| 4099 | .stop(stop), |
| 4100 | .siclk_out(siclk_out), |
| 4101 | .soclk_out(soclk_out) |
| 4102 | ); |
| 4103 | dff #(35) d0_0 ( |
| 4104 | .l1clk(l1clk), |
| 4105 | .siclk(siclk_out), |
| 4106 | .soclk(soclk_out), |
| 4107 | .d(din[34:0]), |
| 4108 | .si({scan_in,so[33:0]}), |
| 4109 | .so({so[33:0],scan_out}), |
| 4110 | .q(dout[34:0]) |
| 4111 | ); |
| 4112 | |
| 4113 | |
| 4114 | |
| 4115 | |
| 4116 | |
| 4117 | |
| 4118 | |
| 4119 | |
| 4120 | |
| 4121 | |
| 4122 | |
| 4123 | |
| 4124 | |
| 4125 | |
| 4126 | |
| 4127 | |
| 4128 | |
| 4129 | |
| 4130 | |
| 4131 | |
| 4132 | endmodule |
| 4133 | |
| 4134 | |
| 4135 | |
| 4136 | |
| 4137 | |
| 4138 | |
| 4139 | |
| 4140 | |
| 4141 | |
| 4142 | // |
| 4143 | // parity macro (even parity) |
| 4144 | // |
| 4145 | // |
| 4146 | |
| 4147 | |
| 4148 | |
| 4149 | |
| 4150 | |
| 4151 | module ifu_ftu_agd_dp_prty_macro__width_8 ( |
| 4152 | din, |
| 4153 | dout); |
| 4154 | input [7:0] din; |
| 4155 | output dout; |
| 4156 | |
| 4157 | |
| 4158 | |
| 4159 | |
| 4160 | |
| 4161 | |
| 4162 | |
| 4163 | prty #(8) m0_0 ( |
| 4164 | .in(din[7:0]), |
| 4165 | .out(dout) |
| 4166 | ); |
| 4167 | |
| 4168 | |
| 4169 | |
| 4170 | |
| 4171 | |
| 4172 | |
| 4173 | |
| 4174 | |
| 4175 | |
| 4176 | |
| 4177 | endmodule |
| 4178 | |
| 4179 | |
| 4180 | |
| 4181 | |
| 4182 | |
| 4183 | // |
| 4184 | // parity macro (even parity) |
| 4185 | // |
| 4186 | // |
| 4187 | |
| 4188 | |
| 4189 | |
| 4190 | |
| 4191 | |
| 4192 | module ifu_ftu_agd_dp_prty_macro__width_4 ( |
| 4193 | din, |
| 4194 | dout); |
| 4195 | input [3:0] din; |
| 4196 | output dout; |
| 4197 | |
| 4198 | |
| 4199 | |
| 4200 | |
| 4201 | |
| 4202 | |
| 4203 | |
| 4204 | prty #(4) m0_0 ( |
| 4205 | .in(din[3:0]), |
| 4206 | .out(dout) |
| 4207 | ); |
| 4208 | |
| 4209 | |
| 4210 | |
| 4211 | |
| 4212 | |
| 4213 | |
| 4214 | |
| 4215 | |
| 4216 | |
| 4217 | |
| 4218 | endmodule |
| 4219 | |
| 4220 | |
| 4221 | |
| 4222 | |
| 4223 | |
| 4224 | |
| 4225 | |
| 4226 | |
| 4227 | |
| 4228 | // any PARAMS parms go into naming of macro |
| 4229 | |
| 4230 | module ifu_ftu_agd_dp_msff_macro__stack_12c__width_6 ( |
| 4231 | din, |
| 4232 | clk, |
| 4233 | en, |
| 4234 | se, |
| 4235 | scan_in, |
| 4236 | siclk, |
| 4237 | soclk, |
| 4238 | pce_ov, |
| 4239 | stop, |
| 4240 | dout, |
| 4241 | scan_out); |
| 4242 | wire l1clk; |
| 4243 | wire siclk_out; |
| 4244 | wire soclk_out; |
| 4245 | wire [4:0] so; |
| 4246 | |
| 4247 | input [5:0] din; |
| 4248 | |
| 4249 | |
| 4250 | input clk; |
| 4251 | input en; |
| 4252 | input se; |
| 4253 | input scan_in; |
| 4254 | input siclk; |
| 4255 | input soclk; |
| 4256 | input pce_ov; |
| 4257 | input stop; |
| 4258 | |
| 4259 | |
| 4260 | |
| 4261 | output [5:0] dout; |
| 4262 | |
| 4263 | |
| 4264 | output scan_out; |
| 4265 | |
| 4266 | |
| 4267 | |
| 4268 | |
| 4269 | cl_dp1_l1hdr_8x c0_0 ( |
| 4270 | .l2clk(clk), |
| 4271 | .pce(en), |
| 4272 | .aclk(siclk), |
| 4273 | .bclk(soclk), |
| 4274 | .l1clk(l1clk), |
| 4275 | .se(se), |
| 4276 | .pce_ov(pce_ov), |
| 4277 | .stop(stop), |
| 4278 | .siclk_out(siclk_out), |
| 4279 | .soclk_out(soclk_out) |
| 4280 | ); |
| 4281 | dff #(6) d0_0 ( |
| 4282 | .l1clk(l1clk), |
| 4283 | .siclk(siclk_out), |
| 4284 | .soclk(soclk_out), |
| 4285 | .d(din[5:0]), |
| 4286 | .si({scan_in,so[4:0]}), |
| 4287 | .so({so[4:0],scan_out}), |
| 4288 | .q(dout[5:0]) |
| 4289 | ); |
| 4290 | |
| 4291 | |
| 4292 | |
| 4293 | |
| 4294 | |
| 4295 | |
| 4296 | |
| 4297 | |
| 4298 | |
| 4299 | |
| 4300 | |
| 4301 | |
| 4302 | |
| 4303 | |
| 4304 | |
| 4305 | |
| 4306 | |
| 4307 | |
| 4308 | |
| 4309 | |
| 4310 | endmodule |
| 4311 | |
| 4312 | |
| 4313 | |
| 4314 | |
| 4315 | |
| 4316 | |
| 4317 | |
| 4318 | |
| 4319 | |
| 4320 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 4321 | // also for pass-gate with decoder |
| 4322 | |
| 4323 | |
| 4324 | |
| 4325 | |
| 4326 | |
| 4327 | // any PARAMS parms go into naming of macro |
| 4328 | |
| 4329 | module ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_8r__width_8 ( |
| 4330 | din0, |
| 4331 | din1, |
| 4332 | sel0, |
| 4333 | dout); |
| 4334 | wire psel0_unused; |
| 4335 | wire psel1; |
| 4336 | |
| 4337 | input [7:0] din0; |
| 4338 | input [7:0] din1; |
| 4339 | input sel0; |
| 4340 | output [7:0] dout; |
| 4341 | |
| 4342 | |
| 4343 | |
| 4344 | |
| 4345 | |
| 4346 | cl_dp1_penc2_8x c0_0 ( |
| 4347 | .sel0(sel0), |
| 4348 | .psel0(psel0_unused), |
| 4349 | .psel1(psel1) |
| 4350 | ); |
| 4351 | |
| 4352 | mux2e #(8) d0_0 ( |
| 4353 | .sel(psel1), |
| 4354 | .in0(din0[7:0]), |
| 4355 | .in1(din1[7:0]), |
| 4356 | .dout(dout[7:0]) |
| 4357 | ); |
| 4358 | |
| 4359 | |
| 4360 | |
| 4361 | |
| 4362 | |
| 4363 | |
| 4364 | |
| 4365 | |
| 4366 | |
| 4367 | |
| 4368 | |
| 4369 | |
| 4370 | |
| 4371 | endmodule |
| 4372 | |
| 4373 | |
| 4374 | // |
| 4375 | // buff macro |
| 4376 | // |
| 4377 | // |
| 4378 | |
| 4379 | |
| 4380 | |
| 4381 | |
| 4382 | |
| 4383 | module ifu_ftu_agd_dp_buff_macro__dbuff_32x__width_1 ( |
| 4384 | din, |
| 4385 | dout); |
| 4386 | input [0:0] din; |
| 4387 | output [0:0] dout; |
| 4388 | |
| 4389 | |
| 4390 | |
| 4391 | |
| 4392 | |
| 4393 | |
| 4394 | buff #(1) d0_0 ( |
| 4395 | .in(din[0:0]), |
| 4396 | .out(dout[0:0]) |
| 4397 | ); |
| 4398 | |
| 4399 | |
| 4400 | |
| 4401 | |
| 4402 | |
| 4403 | |
| 4404 | |
| 4405 | |
| 4406 | endmodule |
| 4407 | |
| 4408 | |
| 4409 | |
| 4410 | |
| 4411 | |
| 4412 | // |
| 4413 | // nand macro for ports = 2,3,4 |
| 4414 | // |
| 4415 | // |
| 4416 | |
| 4417 | |
| 4418 | |
| 4419 | |
| 4420 | |
| 4421 | module ifu_ftu_agd_dp_nand_macro__width_1 ( |
| 4422 | din0, |
| 4423 | din1, |
| 4424 | dout); |
| 4425 | input [0:0] din0; |
| 4426 | input [0:0] din1; |
| 4427 | output [0:0] dout; |
| 4428 | |
| 4429 | |
| 4430 | |
| 4431 | |
| 4432 | |
| 4433 | |
| 4434 | nand2 #(1) d0_0 ( |
| 4435 | .in0(din0[0:0]), |
| 4436 | .in1(din1[0:0]), |
| 4437 | .out(dout[0:0]) |
| 4438 | ); |
| 4439 | |
| 4440 | |
| 4441 | |
| 4442 | |
| 4443 | |
| 4444 | |
| 4445 | |
| 4446 | |
| 4447 | |
| 4448 | endmodule |
| 4449 | |
| 4450 | |
| 4451 | |
| 4452 | |
| 4453 | |
| 4454 | // |
| 4455 | // nand macro for ports = 2,3,4 |
| 4456 | // |
| 4457 | // |
| 4458 | |
| 4459 | |
| 4460 | |
| 4461 | |
| 4462 | |
| 4463 | module ifu_ftu_agd_dp_nand_macro__ports_3__width_1 ( |
| 4464 | din0, |
| 4465 | din1, |
| 4466 | din2, |
| 4467 | dout); |
| 4468 | input [0:0] din0; |
| 4469 | input [0:0] din1; |
| 4470 | input [0:0] din2; |
| 4471 | output [0:0] dout; |
| 4472 | |
| 4473 | |
| 4474 | |
| 4475 | |
| 4476 | |
| 4477 | |
| 4478 | nand3 #(1) d0_0 ( |
| 4479 | .in0(din0[0:0]), |
| 4480 | .in1(din1[0:0]), |
| 4481 | .in2(din2[0:0]), |
| 4482 | .out(dout[0:0]) |
| 4483 | ); |
| 4484 | |
| 4485 | |
| 4486 | |
| 4487 | |
| 4488 | |
| 4489 | |
| 4490 | |
| 4491 | |
| 4492 | |
| 4493 | endmodule |
| 4494 | |
| 4495 | |
| 4496 | |
| 4497 | |
| 4498 | |
| 4499 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 4500 | // also for pass-gate with decoder |
| 4501 | |
| 4502 | |
| 4503 | |
| 4504 | |
| 4505 | |
| 4506 | // any PARAMS parms go into naming of macro |
| 4507 | |
| 4508 | module ifu_ftu_agd_dp_mux_macro__mux_pgnpe__ports_3__stack_50c__width_33 ( |
| 4509 | din0, |
| 4510 | sel0, |
| 4511 | din1, |
| 4512 | sel1, |
| 4513 | din2, |
| 4514 | sel2, |
| 4515 | muxtst, |
| 4516 | dout); |
| 4517 | wire buffout0; |
| 4518 | wire buffout1; |
| 4519 | wire buffout2; |
| 4520 | |
| 4521 | input [32:0] din0; |
| 4522 | input sel0; |
| 4523 | input [32:0] din1; |
| 4524 | input sel1; |
| 4525 | input [32:0] din2; |
| 4526 | input sel2; |
| 4527 | input muxtst; |
| 4528 | output [32:0] dout; |
| 4529 | |
| 4530 | |
| 4531 | |
| 4532 | |
| 4533 | |
| 4534 | cl_dp1_muxbuff3_8x c0_0 ( |
| 4535 | .in0(sel0), |
| 4536 | .in1(sel1), |
| 4537 | .in2(sel2), |
| 4538 | .out0(buffout0), |
| 4539 | .out1(buffout1), |
| 4540 | .out2(buffout2) |
| 4541 | ); |
| 4542 | mux3 #(33) d0_0 ( |
| 4543 | .sel0(buffout0), |
| 4544 | .sel1(buffout1), |
| 4545 | .sel2(buffout2), |
| 4546 | .in0(din0[32:0]), |
| 4547 | .in1(din1[32:0]), |
| 4548 | .in2(din2[32:0]), |
| 4549 | .dout(dout[32:0]), |
| 4550 | .muxtst(muxtst) |
| 4551 | ); |
| 4552 | |
| 4553 | |
| 4554 | |
| 4555 | |
| 4556 | |
| 4557 | |
| 4558 | |
| 4559 | |
| 4560 | |
| 4561 | |
| 4562 | |
| 4563 | |
| 4564 | |
| 4565 | endmodule |
| 4566 | |
| 4567 | |
| 4568 | |
| 4569 | |
| 4570 | |
| 4571 | |
| 4572 | // any PARAMS parms go into naming of macro |
| 4573 | |
| 4574 | module ifu_ftu_agd_dp_msff_macro__minbuff_1__stack_16c__width_16 ( |
| 4575 | din, |
| 4576 | clk, |
| 4577 | en, |
| 4578 | se, |
| 4579 | scan_in, |
| 4580 | siclk, |
| 4581 | soclk, |
| 4582 | pce_ov, |
| 4583 | stop, |
| 4584 | dout, |
| 4585 | scan_out); |
| 4586 | wire l1clk; |
| 4587 | wire siclk_out; |
| 4588 | wire soclk_out; |
| 4589 | wire [14:0] so; |
| 4590 | |
| 4591 | input [15:0] din; |
| 4592 | |
| 4593 | |
| 4594 | input clk; |
| 4595 | input en; |
| 4596 | input se; |
| 4597 | input scan_in; |
| 4598 | input siclk; |
| 4599 | input soclk; |
| 4600 | input pce_ov; |
| 4601 | input stop; |
| 4602 | |
| 4603 | |
| 4604 | |
| 4605 | output [15:0] dout; |
| 4606 | |
| 4607 | |
| 4608 | output scan_out; |
| 4609 | |
| 4610 | |
| 4611 | |
| 4612 | |
| 4613 | cl_dp1_l1hdr_8x c0_0 ( |
| 4614 | .l2clk(clk), |
| 4615 | .pce(en), |
| 4616 | .aclk(siclk), |
| 4617 | .bclk(soclk), |
| 4618 | .l1clk(l1clk), |
| 4619 | .se(se), |
| 4620 | .pce_ov(pce_ov), |
| 4621 | .stop(stop), |
| 4622 | .siclk_out(siclk_out), |
| 4623 | .soclk_out(soclk_out) |
| 4624 | ); |
| 4625 | dff #(16) d0_0 ( |
| 4626 | .l1clk(l1clk), |
| 4627 | .siclk(siclk_out), |
| 4628 | .soclk(soclk_out), |
| 4629 | .d(din[15:0]), |
| 4630 | .si({scan_in,so[14:0]}), |
| 4631 | .so({so[14:0],scan_out}), |
| 4632 | .q(dout[15:0]) |
| 4633 | ); |
| 4634 | |
| 4635 | |
| 4636 | |
| 4637 | |
| 4638 | |
| 4639 | |
| 4640 | |
| 4641 | |
| 4642 | |
| 4643 | |
| 4644 | |
| 4645 | |
| 4646 | |
| 4647 | |
| 4648 | |
| 4649 | |
| 4650 | |
| 4651 | |
| 4652 | |
| 4653 | |
| 4654 | endmodule |
| 4655 | |
| 4656 | |
| 4657 | |
| 4658 | |
| 4659 | |
| 4660 | |
| 4661 | |
| 4662 | |
| 4663 | |
| 4664 | // |
| 4665 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) |
| 4666 | // |
| 4667 | // |
| 4668 | |
| 4669 | |
| 4670 | |
| 4671 | |
| 4672 | |
| 4673 | module ifu_ftu_agd_dp_cmp_macro__dcmp_8x__width_32 ( |
| 4674 | din0, |
| 4675 | din1, |
| 4676 | dout); |
| 4677 | input [31:0] din0; |
| 4678 | input [31:0] din1; |
| 4679 | output dout; |
| 4680 | |
| 4681 | |
| 4682 | |
| 4683 | |
| 4684 | |
| 4685 | |
| 4686 | cmp #(32) m0_0 ( |
| 4687 | .in0(din0[31:0]), |
| 4688 | .in1(din1[31:0]), |
| 4689 | .out(dout) |
| 4690 | ); |
| 4691 | |
| 4692 | |
| 4693 | |
| 4694 | |
| 4695 | |
| 4696 | |
| 4697 | |
| 4698 | |
| 4699 | |
| 4700 | |
| 4701 | endmodule |
| 4702 | |
| 4703 | |
| 4704 | |
| 4705 | |
| 4706 | |
| 4707 | // |
| 4708 | // invert macro |
| 4709 | // |
| 4710 | // |
| 4711 | |
| 4712 | |
| 4713 | |
| 4714 | |
| 4715 | |
| 4716 | module ifu_ftu_agd_dp_inv_macro__width_1 ( |
| 4717 | din, |
| 4718 | dout); |
| 4719 | input [0:0] din; |
| 4720 | output [0:0] dout; |
| 4721 | |
| 4722 | |
| 4723 | |
| 4724 | |
| 4725 | |
| 4726 | |
| 4727 | inv #(1) d0_0 ( |
| 4728 | .in(din[0:0]), |
| 4729 | .out(dout[0:0]) |
| 4730 | ); |
| 4731 | |
| 4732 | |
| 4733 | |
| 4734 | |
| 4735 | |
| 4736 | |
| 4737 | |
| 4738 | |
| 4739 | |
| 4740 | endmodule |
| 4741 | |
| 4742 | |
| 4743 | |
| 4744 | |
| 4745 | |
| 4746 | // |
| 4747 | // and macro for ports = 2,3,4 |
| 4748 | // |
| 4749 | // |
| 4750 | |
| 4751 | |
| 4752 | |
| 4753 | |
| 4754 | |
| 4755 | module ifu_ftu_agd_dp_and_macro__width_1 ( |
| 4756 | din0, |
| 4757 | din1, |
| 4758 | dout); |
| 4759 | input [0:0] din0; |
| 4760 | input [0:0] din1; |
| 4761 | output [0:0] dout; |
| 4762 | |
| 4763 | |
| 4764 | |
| 4765 | |
| 4766 | |
| 4767 | |
| 4768 | and2 #(1) d0_0 ( |
| 4769 | .in0(din0[0:0]), |
| 4770 | .in1(din1[0:0]), |
| 4771 | .out(dout[0:0]) |
| 4772 | ); |
| 4773 | |
| 4774 | |
| 4775 | |
| 4776 | |
| 4777 | |
| 4778 | |
| 4779 | |
| 4780 | |
| 4781 | |
| 4782 | endmodule |
| 4783 | |
| 4784 | |
| 4785 | |
| 4786 | |