| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: ifu_ftu_ctx_dp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module ifu_ftu_ctx_dp ( |
| 36 | tcu_scan_en, |
| 37 | l2clk, |
| 38 | scan_in, |
| 39 | tcu_pce_ov, |
| 40 | spc_aclk, |
| 41 | spc_bclk, |
| 42 | spc_aclk_wmr, |
| 43 | wmr_scan_in, |
| 44 | wmr_scan_out, |
| 45 | lsu_ifu_ctxt_data, |
| 46 | agc_thr0_cntx_0_sel_ff, |
| 47 | agc_thr0_cntx_1_sel_ff, |
| 48 | agc_thr1_cntx_0_sel_ff, |
| 49 | agc_thr1_cntx_1_sel_ff, |
| 50 | agc_thr2_cntx_0_sel_ff, |
| 51 | agc_thr2_cntx_1_sel_ff, |
| 52 | agc_thr3_cntx_0_sel_ff, |
| 53 | agc_thr3_cntx_1_sel_ff, |
| 54 | agc_thr4_cntx_0_sel_ff, |
| 55 | agc_thr4_cntx_1_sel_ff, |
| 56 | agc_thr5_cntx_0_sel_ff, |
| 57 | agc_thr5_cntx_1_sel_ff, |
| 58 | agc_thr6_cntx_0_sel_ff, |
| 59 | agc_thr6_cntx_1_sel_ff, |
| 60 | agc_thr7_cntx_0_sel_ff, |
| 61 | agc_thr7_cntx_1_sel_ff, |
| 62 | agc_thr0_cntx_0_sel, |
| 63 | agc_thr0_cntx_1_sel, |
| 64 | agc_thr1_cntx_0_sel, |
| 65 | agc_thr1_cntx_1_sel, |
| 66 | agc_thr2_cntx_0_sel, |
| 67 | agc_thr2_cntx_1_sel, |
| 68 | agc_thr3_cntx_0_sel, |
| 69 | agc_thr3_cntx_1_sel, |
| 70 | agc_thr4_cntx_0_sel, |
| 71 | agc_thr4_cntx_1_sel, |
| 72 | agc_thr5_cntx_0_sel, |
| 73 | agc_thr5_cntx_1_sel, |
| 74 | agc_thr6_cntx_0_sel, |
| 75 | agc_thr6_cntx_1_sel, |
| 76 | agc_thr7_cntx_0_sel, |
| 77 | agc_thr7_cntx_1_sel, |
| 78 | ftp_itb_fetch_thr_bf, |
| 79 | itc_thr_to_write, |
| 80 | tlu_tl_gt_0, |
| 81 | ftp_itlb_probe_req_l, |
| 82 | ctx_curr_cntx_0_bf, |
| 83 | ctx_curr_cntx_1_bf, |
| 84 | ctx_cntx_0_to_write_bf, |
| 85 | ctx_cntx_1_to_write_bf, |
| 86 | scan_out) ; |
| 87 | wire stop; |
| 88 | wire se; |
| 89 | wire pce_ov; |
| 90 | wire siclk; |
| 91 | wire soclk; |
| 92 | wire tlu_tl_gt_0_reg_scanin; |
| 93 | wire tlu_tl_gt_0_reg_scanout; |
| 94 | wire [7:0] gt_t_zero_to_buf; |
| 95 | wire [7:0] gt_t_zero; |
| 96 | wire lsu_ifu_data_reg_scanin; |
| 97 | wire lsu_ifu_data_reg_scanout; |
| 98 | wire [12:0] ifu_ctx_data_ff; |
| 99 | wire prty_ctxt; |
| 100 | wire [13:0] thr0_cntx_0; |
| 101 | wire thr0_prty_ctx_0; |
| 102 | wire [13:0] thr0_cntx_1; |
| 103 | wire thr0_prty_ctx_1; |
| 104 | wire [13:0] thr1_cntx_0; |
| 105 | wire thr1_prty_ctx_0; |
| 106 | wire [13:0] thr1_cntx_1; |
| 107 | wire thr1_prty_ctx_1; |
| 108 | wire [13:0] thr2_cntx_0; |
| 109 | wire thr2_prty_ctx_0; |
| 110 | wire [13:0] thr2_cntx_1; |
| 111 | wire thr2_prty_ctx_1; |
| 112 | wire [13:0] thr3_cntx_0; |
| 113 | wire thr3_prty_ctx_0; |
| 114 | wire [13:0] thr3_cntx_1; |
| 115 | wire thr3_prty_ctx_1; |
| 116 | wire [13:0] thr4_cntx_0; |
| 117 | wire thr4_prty_ctx_0; |
| 118 | wire [13:0] thr4_cntx_1; |
| 119 | wire thr4_prty_ctx_1; |
| 120 | wire [13:0] thr5_cntx_0; |
| 121 | wire thr5_prty_ctx_0; |
| 122 | wire [13:0] thr5_cntx_1; |
| 123 | wire thr5_prty_ctx_1; |
| 124 | wire [13:0] thr6_cntx_0; |
| 125 | wire thr6_prty_ctx_0; |
| 126 | wire [13:0] thr6_cntx_1; |
| 127 | wire thr6_prty_ctx_1; |
| 128 | wire [13:0] thr7_cntx_0; |
| 129 | wire thr7_prty_ctx_0; |
| 130 | wire [13:0] thr7_cntx_1; |
| 131 | wire thr7_prty_ctx_1; |
| 132 | wire [13:0] next_thr0_cnxt_0_data; |
| 133 | wire [13:0] next_thr0_cnxt_1_data; |
| 134 | wire [13:0] next_thr1_cnxt_0_data; |
| 135 | wire [13:0] next_thr1_cnxt_1_data; |
| 136 | wire [13:0] next_thr2_cnxt_0_data; |
| 137 | wire [13:0] next_thr2_cnxt_1_data; |
| 138 | wire [13:0] next_thr3_cnxt_0_data; |
| 139 | wire [13:0] next_thr3_cnxt_1_data; |
| 140 | wire [13:0] next_thr4_cnxt_0_data; |
| 141 | wire [13:0] next_thr4_cnxt_1_data; |
| 142 | wire [13:0] next_thr5_cnxt_0_data; |
| 143 | wire [13:0] next_thr5_cnxt_1_data; |
| 144 | wire [13:0] next_thr6_cnxt_0_data; |
| 145 | wire [13:0] next_thr6_cnxt_1_data; |
| 146 | wire [13:0] next_thr7_cnxt_0_data; |
| 147 | wire [13:0] next_thr7_cnxt_1_data; |
| 148 | wire thr0_cntx_0_reg_wmr_scanin; |
| 149 | wire thr0_cntx_0_reg_wmr_scanout; |
| 150 | wire [7:0] ctx_gt_zero_0_; |
| 151 | wire [12:0] thr0_cntx_0_q; |
| 152 | wire thr0_cntx_1_reg_wmr_scanin; |
| 153 | wire thr0_cntx_1_reg_wmr_scanout; |
| 154 | wire [12:0] thr0_cntx_1_q; |
| 155 | wire thr1_cntx_0_reg_wmr_scanin; |
| 156 | wire thr1_cntx_0_reg_wmr_scanout; |
| 157 | wire [12:0] thr1_cntx_0_q; |
| 158 | wire thr1_cntx_1_reg_wmr_scanin; |
| 159 | wire thr1_cntx_1_reg_wmr_scanout; |
| 160 | wire [12:0] thr1_cntx_1_q; |
| 161 | wire thr2_cntx_0_reg_wmr_scanin; |
| 162 | wire thr2_cntx_0_reg_wmr_scanout; |
| 163 | wire [12:0] thr2_cntx_0_q; |
| 164 | wire thr2_cntx_1_reg_wmr_scanin; |
| 165 | wire thr2_cntx_1_reg_wmr_scanout; |
| 166 | wire [12:0] thr2_cntx_1_q; |
| 167 | wire thr3_cntx_0_reg_wmr_scanin; |
| 168 | wire thr3_cntx_0_reg_wmr_scanout; |
| 169 | wire [12:0] thr3_cntx_0_q; |
| 170 | wire thr3_cntx_1_reg_wmr_scanin; |
| 171 | wire thr3_cntx_1_reg_wmr_scanout; |
| 172 | wire [12:0] thr3_cntx_1_q; |
| 173 | wire thr4_cntx_0_reg_wmr_scanin; |
| 174 | wire thr4_cntx_0_reg_wmr_scanout; |
| 175 | wire [12:0] thr4_cntx_0_q; |
| 176 | wire thr4_cntx_1_reg_wmr_scanin; |
| 177 | wire thr4_cntx_1_reg_wmr_scanout; |
| 178 | wire [12:0] thr4_cntx_1_q; |
| 179 | wire thr5_cntx_0_reg_wmr_scanin; |
| 180 | wire thr5_cntx_0_reg_wmr_scanout; |
| 181 | wire [12:0] thr5_cntx_0_q; |
| 182 | wire thr5_cntx_1_reg_wmr_scanin; |
| 183 | wire thr5_cntx_1_reg_wmr_scanout; |
| 184 | wire [12:0] thr5_cntx_1_q; |
| 185 | wire thr6_cntx_0_reg_wmr_scanin; |
| 186 | wire thr6_cntx_0_reg_wmr_scanout; |
| 187 | wire [12:0] thr6_cntx_0_q; |
| 188 | wire thr6_cntx_1_reg_wmr_scanin; |
| 189 | wire thr6_cntx_1_reg_wmr_scanout; |
| 190 | wire [12:0] thr6_cntx_1_q; |
| 191 | wire thr7_cntx_0_reg_wmr_scanin; |
| 192 | wire thr7_cntx_0_reg_wmr_scanout; |
| 193 | wire [12:0] thr7_cntx_0_q; |
| 194 | wire thr7_cntx_1_reg_wmr_scanin; |
| 195 | wire thr7_cntx_1_reg_wmr_scanout; |
| 196 | wire [12:0] thr7_cntx_1_q; |
| 197 | wire [12:0] ctx_curr_cntx_0_to_buf; |
| 198 | wire [12:0] ctx_curr_cntx_1_to_buf; |
| 199 | wire [13:0] ctx_cntx_0_to_write_to_buf; |
| 200 | wire [13:0] ctx_cntx_1_to_write_to_buf; |
| 201 | |
| 202 | |
| 203 | |
| 204 | input tcu_scan_en ; |
| 205 | input l2clk; |
| 206 | input scan_in; |
| 207 | input tcu_pce_ov; // scan signals |
| 208 | input spc_aclk; |
| 209 | input spc_bclk; |
| 210 | // input tcu_muxtest; |
| 211 | input spc_aclk_wmr; |
| 212 | input wmr_scan_in; |
| 213 | output wmr_scan_out; |
| 214 | |
| 215 | |
| 216 | |
| 217 | input [12:0] lsu_ifu_ctxt_data; |
| 218 | input agc_thr0_cntx_0_sel_ff; |
| 219 | input agc_thr0_cntx_1_sel_ff; |
| 220 | input agc_thr1_cntx_0_sel_ff; |
| 221 | input agc_thr1_cntx_1_sel_ff; |
| 222 | input agc_thr2_cntx_0_sel_ff; |
| 223 | input agc_thr2_cntx_1_sel_ff; |
| 224 | input agc_thr3_cntx_0_sel_ff; |
| 225 | input agc_thr3_cntx_1_sel_ff; |
| 226 | input agc_thr4_cntx_0_sel_ff; |
| 227 | input agc_thr4_cntx_1_sel_ff; |
| 228 | input agc_thr5_cntx_0_sel_ff; |
| 229 | input agc_thr5_cntx_1_sel_ff; |
| 230 | input agc_thr6_cntx_0_sel_ff; |
| 231 | input agc_thr6_cntx_1_sel_ff; |
| 232 | input agc_thr7_cntx_0_sel_ff; |
| 233 | input agc_thr7_cntx_1_sel_ff; |
| 234 | |
| 235 | input [1:0] agc_thr0_cntx_0_sel; |
| 236 | input [1:0] agc_thr0_cntx_1_sel; |
| 237 | input [1:0] agc_thr1_cntx_0_sel; |
| 238 | input [1:0] agc_thr1_cntx_1_sel; |
| 239 | input [1:0] agc_thr2_cntx_0_sel; |
| 240 | input [1:0] agc_thr2_cntx_1_sel; |
| 241 | input [1:0] agc_thr3_cntx_0_sel; |
| 242 | input [1:0] agc_thr3_cntx_1_sel; |
| 243 | input [1:0] agc_thr4_cntx_0_sel; |
| 244 | input [1:0] agc_thr4_cntx_1_sel; |
| 245 | input [1:0] agc_thr5_cntx_0_sel; |
| 246 | input [1:0] agc_thr5_cntx_1_sel; |
| 247 | input [1:0] agc_thr6_cntx_0_sel; |
| 248 | input [1:0] agc_thr6_cntx_1_sel; |
| 249 | input [1:0] agc_thr7_cntx_0_sel; |
| 250 | input [1:0] agc_thr7_cntx_1_sel; |
| 251 | input [7:0] ftp_itb_fetch_thr_bf; |
| 252 | input [7:0] itc_thr_to_write; |
| 253 | input [7:0] tlu_tl_gt_0; |
| 254 | |
| 255 | input ftp_itlb_probe_req_l; |
| 256 | |
| 257 | output [12:0] ctx_curr_cntx_0_bf; |
| 258 | output [12:0] ctx_curr_cntx_1_bf; |
| 259 | |
| 260 | output [13:0] ctx_cntx_0_to_write_bf; |
| 261 | output [13:0] ctx_cntx_1_to_write_bf; |
| 262 | output scan_out; |
| 263 | |
| 264 | // scan renames |
| 265 | // assign pce_ov = tcu_pce_ov; |
| 266 | assign stop = 1'b0; |
| 267 | // assign siclk = spc_aclk; |
| 268 | // assign soclk = spc_bclk; |
| 269 | // assign muxtst = tcu_muxtest; |
| 270 | // end scan |
| 271 | |
| 272 | ifu_ftu_ctx_dp_buff_macro__dbuff_32x__stack_none__width_4 test_rep0 ( |
| 273 | .din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}), |
| 274 | .dout({se,pce_ov,siclk,soclk}) |
| 275 | ); |
| 276 | |
| 277 | |
| 278 | |
| 279 | |
| 280 | |
| 281 | ifu_ftu_ctx_dp_msff_macro__stack_14c__width_8 tlu_tl_gt_0_reg ( |
| 282 | .scan_in(tlu_tl_gt_0_reg_scanin), |
| 283 | .scan_out(tlu_tl_gt_0_reg_scanout), |
| 284 | .clk ( l2clk ), |
| 285 | .en ( 1'b1 ), |
| 286 | .din ( tlu_tl_gt_0[7:0]), |
| 287 | .dout( gt_t_zero_to_buf[7:0] ), |
| 288 | .se(se), |
| 289 | .siclk(siclk), |
| 290 | .soclk(soclk), |
| 291 | .pce_ov(pce_ov), |
| 292 | .stop(stop)); |
| 293 | |
| 294 | |
| 295 | ifu_ftu_ctx_dp_buff_macro__stack_14c__width_8 tlu_tl_gt_0_buf ( |
| 296 | .din(gt_t_zero_to_buf[7:0]), |
| 297 | .dout(gt_t_zero[7:0])); |
| 298 | |
| 299 | |
| 300 | |
| 301 | ifu_ftu_ctx_dp_msff_macro__stack_14c__width_13 lsu_ifu_data_reg ( |
| 302 | .scan_in(lsu_ifu_data_reg_scanin), |
| 303 | .scan_out(lsu_ifu_data_reg_scanout), |
| 304 | .clk ( l2clk ), |
| 305 | .en ( 1'b1 ), |
| 306 | .din ( lsu_ifu_ctxt_data[12:0]), |
| 307 | .dout( ifu_ctx_data_ff[12:0] ), |
| 308 | .se(se), |
| 309 | .siclk(siclk), |
| 310 | .soclk(soclk), |
| 311 | .pce_ov(pce_ov), |
| 312 | .stop(stop)); |
| 313 | |
| 314 | ifu_ftu_ctx_dp_prty_macro__width_16 pgen_lsu_ctxt ( |
| 315 | .din ({1'b0,ifu_ctx_data_ff[12:0],2'b00}), |
| 316 | .dout (prty_ctxt) |
| 317 | ); |
| 318 | |
| 319 | /////////////////////////////////////////////////////////////////////// |
| 320 | // Parity muxing. // |
| 321 | /////////////////////////////////////////////////////////////////////// |
| 322 | // Thr0 // |
| 323 | /////////////////////////////////////////////////////////////////////// |
| 324 | ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr0_cntx_0_parity_mux ( |
| 325 | .din0( prty_ctxt), // new parity |
| 326 | .din1( thr0_cntx_0[13]), // Hold the old value |
| 327 | .sel0( agc_thr0_cntx_0_sel_ff), |
| 328 | .dout( thr0_prty_ctx_0 )); |
| 329 | |
| 330 | ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr0_cntx_1_parity_mux ( |
| 331 | .din0( prty_ctxt), // new parity |
| 332 | .din1( thr0_cntx_1[13]), // Hold the old value |
| 333 | .sel0( agc_thr0_cntx_1_sel_ff), |
| 334 | .dout( thr0_prty_ctx_1 )); |
| 335 | /////////////////////////////////////////////////////////////////////// |
| 336 | // Thr1 // |
| 337 | /////////////////////////////////////////////////////////////////////// |
| 338 | ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr1_cntx_0_parity_mux ( |
| 339 | .din0( prty_ctxt), // new parity |
| 340 | .din1( thr1_cntx_0[13]), // Hold the old value |
| 341 | .sel0( agc_thr1_cntx_0_sel_ff), |
| 342 | .dout( thr1_prty_ctx_0 )); |
| 343 | |
| 344 | ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr1_cntx_1_parity_mux ( |
| 345 | .din0( prty_ctxt), // new parity |
| 346 | .din1( thr1_cntx_1[13]), // Hold the old value |
| 347 | .sel0( agc_thr1_cntx_1_sel_ff), |
| 348 | .dout( thr1_prty_ctx_1 )); |
| 349 | |
| 350 | /////////////////////////////////////////////////////////////////////// |
| 351 | // Thr2 // |
| 352 | /////////////////////////////////////////////////////////////////////// |
| 353 | ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr2_cntx_0_parity_mux ( |
| 354 | .din0( prty_ctxt), // new parity |
| 355 | .din1( thr2_cntx_0[13]), // Hold the old value |
| 356 | .sel0( agc_thr2_cntx_0_sel_ff), |
| 357 | .dout( thr2_prty_ctx_0 )); |
| 358 | |
| 359 | ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr2_cntx_1_parity_mux ( |
| 360 | .din0( prty_ctxt), // new parity |
| 361 | .din1( thr2_cntx_1[13]), // Hold the old value |
| 362 | .sel0( agc_thr2_cntx_1_sel_ff), |
| 363 | .dout( thr2_prty_ctx_1 )); |
| 364 | /////////////////////////////////////////////////////////////////////// |
| 365 | // Thr3 // |
| 366 | /////////////////////////////////////////////////////////////////////// |
| 367 | ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr3_cntx_0_parity_mux ( |
| 368 | .din0( prty_ctxt), // new parity |
| 369 | .din1( thr3_cntx_0[13]), // Hold the old value |
| 370 | .sel0( agc_thr3_cntx_0_sel_ff), |
| 371 | .dout( thr3_prty_ctx_0 )); |
| 372 | |
| 373 | ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr3_cntx_1_parity_mux ( |
| 374 | .din0( prty_ctxt), // new parity |
| 375 | .din1( thr3_cntx_1[13]), // Hold the old value |
| 376 | .sel0( agc_thr3_cntx_1_sel_ff), |
| 377 | .dout( thr3_prty_ctx_1 )); |
| 378 | |
| 379 | /////////////////////////////////////////////////////////////////////// |
| 380 | // Thr4 // |
| 381 | /////////////////////////////////////////////////////////////////////// |
| 382 | ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr4_cntx_0_parity_mux ( |
| 383 | .din0( prty_ctxt), // new parity |
| 384 | .din1( thr4_cntx_0[13]), // Hold the old value |
| 385 | .sel0( agc_thr4_cntx_0_sel_ff), |
| 386 | .dout( thr4_prty_ctx_0 )); |
| 387 | |
| 388 | ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr4_cntx_1_parity_mux ( |
| 389 | .din0( prty_ctxt), // new parity |
| 390 | .din1( thr4_cntx_1[13]), // Hold the old value |
| 391 | .sel0( agc_thr4_cntx_1_sel_ff), |
| 392 | .dout( thr4_prty_ctx_1 )); |
| 393 | /////////////////////////////////////////////////////////////////////// |
| 394 | // Thr5 // |
| 395 | /////////////////////////////////////////////////////////////////////// |
| 396 | ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr5_cntx_0_parity_mux ( |
| 397 | .din0( prty_ctxt), // new parity |
| 398 | .din1( thr5_cntx_0[13]), // Hold the old value |
| 399 | .sel0( agc_thr5_cntx_0_sel_ff), |
| 400 | .dout( thr5_prty_ctx_0 )); |
| 401 | |
| 402 | ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr5_cntx_1_parity_mux ( |
| 403 | .din0( prty_ctxt), // new parity |
| 404 | .din1( thr5_cntx_1[13]), // Hold the old value |
| 405 | .sel0( agc_thr5_cntx_1_sel_ff), |
| 406 | .dout( thr5_prty_ctx_1 )); |
| 407 | |
| 408 | /////////////////////////////////////////////////////////////////////// |
| 409 | // Thr6 // |
| 410 | /////////////////////////////////////////////////////////////////////// |
| 411 | ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr6_cntx_0_parity_mux ( |
| 412 | .din0( prty_ctxt), // new parity |
| 413 | .din1( thr6_cntx_0[13]), // Hold the old value |
| 414 | .sel0( agc_thr6_cntx_0_sel_ff), |
| 415 | .dout( thr6_prty_ctx_0 )); |
| 416 | |
| 417 | ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr6_cntx_1_parity_mux ( |
| 418 | .din0( prty_ctxt), // new parity |
| 419 | .din1( thr6_cntx_1[13]), // Hold the old value |
| 420 | .sel0( agc_thr6_cntx_1_sel_ff), |
| 421 | .dout( thr6_prty_ctx_1 )); |
| 422 | /////////////////////////////////////////////////////////////////////// |
| 423 | // Thr7 // |
| 424 | /////////////////////////////////////////////////////////////////////// |
| 425 | ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr7_cntx_0_parity_mux ( |
| 426 | .din0( prty_ctxt), // new parity |
| 427 | .din1( thr7_cntx_0[13]), // Hold the old value |
| 428 | .sel0( agc_thr7_cntx_0_sel_ff), |
| 429 | .dout( thr7_prty_ctx_0 )); |
| 430 | |
| 431 | ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr7_cntx_1_parity_mux ( |
| 432 | .din0( prty_ctxt), // new parity |
| 433 | .din1( thr7_cntx_1[13]), // Hold the old value |
| 434 | .sel0( agc_thr7_cntx_1_sel_ff), |
| 435 | .dout( thr7_prty_ctx_1 )); |
| 436 | |
| 437 | //////////////////////////////////////////////// |
| 438 | // Thread 0 context muxing // |
| 439 | //////////////////////////////////////////////// |
| 440 | ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr0_cntx_0_mux ( |
| 441 | .din0( {1'b0 ,lsu_ifu_ctxt_data[12:0]}), // new context from lsu |
| 442 | .din1( {thr0_prty_ctx_0, thr0_cntx_0[12:0]}), // Hold the old context |
| 443 | .sel0( agc_thr0_cntx_0_sel[0]), |
| 444 | .sel1( agc_thr0_cntx_0_sel[1]), |
| 445 | .dout( next_thr0_cnxt_0_data[13:0] )); |
| 446 | |
| 447 | ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr0_cntx_1_mux ( |
| 448 | .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu |
| 449 | .din1( {thr0_prty_ctx_1, thr0_cntx_1[12:0]}), // Hold the old context |
| 450 | .sel0( agc_thr0_cntx_1_sel[0]), |
| 451 | .sel1( agc_thr0_cntx_1_sel[1]), |
| 452 | .dout( next_thr0_cnxt_1_data[13:0] )); |
| 453 | |
| 454 | //////////////////////////////////////////////// |
| 455 | // Thread 1 context muxing // |
| 456 | //////////////////////////////////////////////// |
| 457 | ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr1_cntx_0_mux ( |
| 458 | .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu |
| 459 | .din1( {thr1_prty_ctx_0, thr1_cntx_0[12:0]}), // Hold the old context |
| 460 | .sel0( agc_thr1_cntx_0_sel[0]), |
| 461 | .sel1( agc_thr1_cntx_0_sel[1]), |
| 462 | .dout( next_thr1_cnxt_0_data[13:0] )); |
| 463 | |
| 464 | ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr1_cntx_1_mux ( |
| 465 | .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu |
| 466 | .din1( {thr1_prty_ctx_1, thr1_cntx_1[12:0]}), // Hold the old context |
| 467 | .sel0( agc_thr1_cntx_1_sel[0]), |
| 468 | .sel1( agc_thr1_cntx_1_sel[1]), |
| 469 | .dout( next_thr1_cnxt_1_data[13:0] )); |
| 470 | |
| 471 | |
| 472 | //////////////////////////////////////////////// |
| 473 | // Thread 2 context muxing // |
| 474 | //////////////////////////////////////////////// |
| 475 | ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr2_cntx_0_mux ( |
| 476 | .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu |
| 477 | .din1( {thr2_prty_ctx_0, thr2_cntx_0[12:0]}), // Hold the old context |
| 478 | .sel0( agc_thr2_cntx_0_sel[0]), |
| 479 | .sel1( agc_thr2_cntx_0_sel[1]), |
| 480 | .dout( next_thr2_cnxt_0_data[13:0] )); |
| 481 | |
| 482 | ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr2_cntx_1_mux ( |
| 483 | .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu |
| 484 | .din1( {thr2_prty_ctx_1, thr2_cntx_1[12:0]}), // Hold the old context |
| 485 | .sel0( agc_thr2_cntx_1_sel[0]), |
| 486 | .sel1( agc_thr2_cntx_1_sel[1]), |
| 487 | .dout( next_thr2_cnxt_1_data[13:0] )); |
| 488 | |
| 489 | //////////////////////////////////////////////// |
| 490 | // Thread 3 context muxing // |
| 491 | //////////////////////////////////////////////// |
| 492 | ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr3_cntx_0_mux ( |
| 493 | .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu |
| 494 | .din1( {thr3_prty_ctx_0, thr3_cntx_0[12:0]}), // Hold the old context |
| 495 | .sel0( agc_thr3_cntx_0_sel[0]), |
| 496 | .sel1( agc_thr3_cntx_0_sel[1]), |
| 497 | .dout( next_thr3_cnxt_0_data[13:0] )); |
| 498 | |
| 499 | ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr3_cntx_1_mux ( |
| 500 | .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu |
| 501 | .din1( {thr3_prty_ctx_1, thr3_cntx_1[12:0]}), // Hold the old context |
| 502 | .sel0( agc_thr3_cntx_1_sel[0]), |
| 503 | .sel1( agc_thr3_cntx_1_sel[1]), |
| 504 | .dout( next_thr3_cnxt_1_data[13:0] )); |
| 505 | |
| 506 | //////////////////////////////////////////////// |
| 507 | // Thread 4 context muxing // |
| 508 | //////////////////////////////////////////////// |
| 509 | ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr4_cntx_0_mux ( |
| 510 | .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu |
| 511 | .din1( {thr4_prty_ctx_0, thr4_cntx_0[12:0]}), // Hold the old context |
| 512 | .sel0( agc_thr4_cntx_0_sel[0]), |
| 513 | .sel1( agc_thr4_cntx_0_sel[1]), |
| 514 | .dout( next_thr4_cnxt_0_data[13:0] )); |
| 515 | |
| 516 | ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr4_cntx_1_mux ( |
| 517 | .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu |
| 518 | .din1( {thr4_prty_ctx_1, thr4_cntx_1[12:0]}), // Hold the old context |
| 519 | .sel0( agc_thr4_cntx_1_sel[0]), |
| 520 | .sel1( agc_thr4_cntx_1_sel[1]), |
| 521 | .dout( next_thr4_cnxt_1_data[13:0] )); |
| 522 | |
| 523 | //////////////////////////////////////////////// |
| 524 | // Thread 5 context muxing // |
| 525 | //////////////////////////////////////////////// |
| 526 | ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr5_cntx_0_mux ( |
| 527 | .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu |
| 528 | .din1( {thr5_prty_ctx_0, thr5_cntx_0[12:0]}), // Hold the old context |
| 529 | .sel0( agc_thr5_cntx_0_sel[0]), |
| 530 | .sel1( agc_thr5_cntx_0_sel[1]), |
| 531 | .dout( next_thr5_cnxt_0_data[13:0] )); |
| 532 | |
| 533 | ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr5_cntx_1_mux ( |
| 534 | .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu |
| 535 | .din1( {thr5_prty_ctx_1, thr5_cntx_1[12:0]}), // Hold the old context |
| 536 | .sel0( agc_thr5_cntx_1_sel[0]), |
| 537 | .sel1( agc_thr5_cntx_1_sel[1]), |
| 538 | .dout( next_thr5_cnxt_1_data[13:0] )); |
| 539 | |
| 540 | |
| 541 | //////////////////////////////////////////////// |
| 542 | // Thread 6 context muxing // |
| 543 | //////////////////////////////////////////////// |
| 544 | ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr6_cntx_0_mux ( |
| 545 | .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu |
| 546 | .din1( {thr6_prty_ctx_0, thr6_cntx_0[12:0]}), // Hold the old context |
| 547 | .sel0( agc_thr6_cntx_0_sel[0]), |
| 548 | .sel1( agc_thr6_cntx_0_sel[1]), |
| 549 | .dout( next_thr6_cnxt_0_data[13:0] )); |
| 550 | |
| 551 | ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr6_cntx_1_mux ( |
| 552 | .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu |
| 553 | .din1( {thr6_prty_ctx_1, thr6_cntx_1[12:0]}), // Hold the old context |
| 554 | .sel0( agc_thr6_cntx_1_sel[0]), |
| 555 | .sel1( agc_thr6_cntx_1_sel[1]), |
| 556 | .dout( next_thr6_cnxt_1_data[13:0] )); |
| 557 | |
| 558 | //////////////////////////////////////////////// |
| 559 | // Thread 7 context muxing // |
| 560 | //////////////////////////////////////////////// |
| 561 | ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr7_cntx_0_mux ( |
| 562 | .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu |
| 563 | .din1( {thr7_prty_ctx_0, thr7_cntx_0[12:0]}), // Hold the old context |
| 564 | .sel0( agc_thr7_cntx_0_sel[0]), |
| 565 | .sel1( agc_thr7_cntx_0_sel[1]), |
| 566 | .dout( next_thr7_cnxt_0_data[13:0] )); |
| 567 | |
| 568 | ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr7_cntx_1_mux ( |
| 569 | .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}), // new context from lsu |
| 570 | .din1( {thr7_prty_ctx_1, thr7_cntx_1[12:0]}), // Hold the old context |
| 571 | .sel0( agc_thr7_cntx_1_sel[0]), |
| 572 | .sel1( agc_thr7_cntx_1_sel[1]), |
| 573 | .dout( next_thr7_cnxt_1_data[13:0] )); |
| 574 | |
| 575 | /////////////////////////////////////////////////////////////////////// |
| 576 | // Context registers // |
| 577 | /////////////////////////////////////////////////////////////////////// |
| 578 | //////////////////////////////////// |
| 579 | // Thread 0 context registers // |
| 580 | //////////////////////////////////// |
| 581 | ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr0_cntx_0_reg ( // FS:wmr_protect |
| 582 | .scan_in(thr0_cntx_0_reg_wmr_scanin), |
| 583 | .scan_out(thr0_cntx_0_reg_wmr_scanout), |
| 584 | .siclk(spc_aclk_wmr), |
| 585 | .clk ( l2clk ), |
| 586 | .en ( 1'b1 ), |
| 587 | .din ( next_thr0_cnxt_0_data[13:0]), |
| 588 | .dout( thr0_cntx_0[13:0] ), |
| 589 | .se(se), |
| 590 | .soclk(soclk), |
| 591 | .pce_ov(pce_ov), |
| 592 | .stop(stop)); |
| 593 | |
| 594 | // assign thr0_cntx_0_q[13:0] = thr0_cntx_0[13:0] & {13{~gt_t_zero[0]}} ; |
| 595 | |
| 596 | ifu_ftu_ctx_dp_nand_macro__ports_2__stack_14c__width_8 gt_z_nand ( |
| 597 | .din0(gt_t_zero[7:0]), |
| 598 | .din1({8{ftp_itlb_probe_req_l}}), |
| 599 | .dout(ctx_gt_zero_0_[7:0]) |
| 600 | ); |
| 601 | |
| 602 | ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr0_cntx_0_and ( |
| 603 | .din0({13{ctx_gt_zero_0_[0]}}), |
| 604 | .din1(thr0_cntx_0[12:0]), |
| 605 | .dout(thr0_cntx_0_q[12:0]) |
| 606 | ); |
| 607 | |
| 608 | |
| 609 | |
| 610 | ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr0_cntx_1_reg ( // FS:wmr_protect |
| 611 | .scan_in(thr0_cntx_1_reg_wmr_scanin), |
| 612 | .scan_out(thr0_cntx_1_reg_wmr_scanout), |
| 613 | .siclk(spc_aclk_wmr), |
| 614 | .clk ( l2clk ), |
| 615 | .en ( 1'b1 ), |
| 616 | .din ( next_thr0_cnxt_1_data[13:0]), |
| 617 | .dout( thr0_cntx_1[13:0] ), |
| 618 | .se(se), |
| 619 | .soclk(soclk), |
| 620 | .pce_ov(pce_ov), |
| 621 | .stop(stop)); |
| 622 | |
| 623 | |
| 624 | ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr0_cntx_1_and ( |
| 625 | .din0({13{ctx_gt_zero_0_[0]}}), |
| 626 | .din1(thr0_cntx_1[12:0]), |
| 627 | .dout(thr0_cntx_1_q[12:0]) |
| 628 | ); |
| 629 | |
| 630 | |
| 631 | // assign thr0_cntx_1_q[13:0] = thr0_cntx_1[13:0] & {13{~gt_t_zero[0]}} ; |
| 632 | |
| 633 | //////////////////////////////////// |
| 634 | // Thread 1 context registers // |
| 635 | //////////////////////////////////// |
| 636 | ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr1_cntx_0_reg ( // FS:wmr_protect |
| 637 | .scan_in(thr1_cntx_0_reg_wmr_scanin), |
| 638 | .scan_out(thr1_cntx_0_reg_wmr_scanout), |
| 639 | .siclk(spc_aclk_wmr), |
| 640 | .clk ( l2clk ), |
| 641 | .en ( 1'b1 ), |
| 642 | .din ( next_thr1_cnxt_0_data[13:0]), |
| 643 | .dout( thr1_cntx_0[13:0] ), |
| 644 | .se(se), |
| 645 | .soclk(soclk), |
| 646 | .pce_ov(pce_ov), |
| 647 | .stop(stop)); |
| 648 | |
| 649 | // assign thr1_cntx_0_q[13:0] = thr1_cntx_0[13:0] & {13{~gt_t_zero[1]}} ; |
| 650 | |
| 651 | |
| 652 | ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr1_cntx_0_and ( |
| 653 | .din0({13{ctx_gt_zero_0_[1]}}), |
| 654 | .din1(thr1_cntx_0[12:0]), |
| 655 | .dout(thr1_cntx_0_q[12:0]) |
| 656 | ); |
| 657 | |
| 658 | |
| 659 | ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr1_cntx_1_reg ( // FS:wmr_protect |
| 660 | .scan_in(thr1_cntx_1_reg_wmr_scanin), |
| 661 | .scan_out(thr1_cntx_1_reg_wmr_scanout), |
| 662 | .siclk(spc_aclk_wmr), |
| 663 | .clk ( l2clk ), |
| 664 | .en ( 1'b1 ), |
| 665 | .din ( next_thr1_cnxt_1_data[13:0]), |
| 666 | .dout( thr1_cntx_1[13:0] ), |
| 667 | .se(se), |
| 668 | .soclk(soclk), |
| 669 | .pce_ov(pce_ov), |
| 670 | .stop(stop)); |
| 671 | |
| 672 | // assign thr1_cntx_1_q[13:0] = thr1_cntx_1[13:0] & {13{~gt_t_zero[1]}} ; |
| 673 | |
| 674 | ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr1_cntx_1_and ( |
| 675 | .din0({13{ctx_gt_zero_0_[1]}}), |
| 676 | .din1(thr1_cntx_1[12:0]), |
| 677 | .dout(thr1_cntx_1_q[12:0]) |
| 678 | ); |
| 679 | |
| 680 | |
| 681 | //////////////////////////////////// |
| 682 | // Thread 2 context registers // |
| 683 | //////////////////////////////////// |
| 684 | ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr2_cntx_0_reg ( // FS:wmr_protect |
| 685 | .scan_in(thr2_cntx_0_reg_wmr_scanin), |
| 686 | .scan_out(thr2_cntx_0_reg_wmr_scanout), |
| 687 | .siclk(spc_aclk_wmr), |
| 688 | .clk ( l2clk ), |
| 689 | .en ( 1'b1 ), |
| 690 | .din ( next_thr2_cnxt_0_data[13:0]), |
| 691 | .dout( thr2_cntx_0[13:0] ), |
| 692 | .se(se), |
| 693 | .soclk(soclk), |
| 694 | .pce_ov(pce_ov), |
| 695 | .stop(stop)); |
| 696 | |
| 697 | // assign thr2_cntx_0_q[13:0] = thr2_cntx_0[13:0] & {13{~gt_t_zero[2]}} ; |
| 698 | |
| 699 | ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr2_cntx_0_and ( |
| 700 | .din0({13{ctx_gt_zero_0_[2]}}), |
| 701 | .din1(thr2_cntx_0[12:0]), |
| 702 | .dout(thr2_cntx_0_q[12:0]) |
| 703 | ); |
| 704 | |
| 705 | ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr2_cntx_1_reg ( // FS:wmr_protect |
| 706 | .scan_in(thr2_cntx_1_reg_wmr_scanin), |
| 707 | .scan_out(thr2_cntx_1_reg_wmr_scanout), |
| 708 | .siclk(spc_aclk_wmr), |
| 709 | .clk ( l2clk ), |
| 710 | .en ( 1'b1 ), |
| 711 | .din ( next_thr2_cnxt_1_data[13:0]), |
| 712 | .dout( thr2_cntx_1[13:0] ), |
| 713 | .se(se), |
| 714 | .soclk(soclk), |
| 715 | .pce_ov(pce_ov), |
| 716 | .stop(stop)); |
| 717 | |
| 718 | // assign thr2_cntx_1_q[13:0] = thr2_cntx_1[13:0] & {13{~gt_t_zero[2]}} ; |
| 719 | |
| 720 | ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr2_cntx_1_and ( |
| 721 | .din0({13{ctx_gt_zero_0_[2]}}), |
| 722 | .din1(thr2_cntx_1[12:0]), |
| 723 | .dout(thr2_cntx_1_q[12:0]) |
| 724 | ); |
| 725 | |
| 726 | |
| 727 | //////////////////////////////////// |
| 728 | // Thread 3 context registers // |
| 729 | //////////////////////////////////// |
| 730 | ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr3_cntx_0_reg ( // FS:wmr_protect |
| 731 | .scan_in(thr3_cntx_0_reg_wmr_scanin), |
| 732 | .scan_out(thr3_cntx_0_reg_wmr_scanout), |
| 733 | .siclk(spc_aclk_wmr), |
| 734 | .clk ( l2clk ), |
| 735 | .en ( 1'b1 ), |
| 736 | .din ( next_thr3_cnxt_0_data[13:0]), |
| 737 | .dout( thr3_cntx_0[13:0] ), |
| 738 | .se(se), |
| 739 | .soclk(soclk), |
| 740 | .pce_ov(pce_ov), |
| 741 | .stop(stop)); |
| 742 | |
| 743 | // assign thr3_cntx_0_q[13:0] = thr3_cntx_0[13:0] & {13{~gt_t_zero[3]}} ; |
| 744 | |
| 745 | ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr3_cntx_0_and ( |
| 746 | .din0({13{ctx_gt_zero_0_[3]}}), |
| 747 | .din1(thr3_cntx_0[12:0]), |
| 748 | .dout(thr3_cntx_0_q[12:0]) |
| 749 | ); |
| 750 | |
| 751 | |
| 752 | ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr3_cntx_1_reg ( // FS:wmr_protect |
| 753 | .scan_in(thr3_cntx_1_reg_wmr_scanin), |
| 754 | .scan_out(thr3_cntx_1_reg_wmr_scanout), |
| 755 | .siclk(spc_aclk_wmr), |
| 756 | .clk ( l2clk ), |
| 757 | .en ( 1'b1 ), |
| 758 | .din ( next_thr3_cnxt_1_data[13:0]), |
| 759 | .dout( thr3_cntx_1[13:0] ), |
| 760 | .se(se), |
| 761 | .soclk(soclk), |
| 762 | .pce_ov(pce_ov), |
| 763 | .stop(stop)); |
| 764 | |
| 765 | // assign thr3_cntx_1_q[13:0] = thr3_cntx_1[13:0] & {13{~gt_t_zero[3]}} ; |
| 766 | |
| 767 | ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr3_cntx_1_and ( |
| 768 | .din0({13{ctx_gt_zero_0_[3]}}), |
| 769 | .din1(thr3_cntx_1[12:0]), |
| 770 | .dout(thr3_cntx_1_q[12:0]) |
| 771 | ); |
| 772 | |
| 773 | |
| 774 | //////////////////////////////////// |
| 775 | // Thread 4 context registers // |
| 776 | //////////////////////////////////// |
| 777 | ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr4_cntx_0_reg ( // FS:wmr_protect |
| 778 | .scan_in(thr4_cntx_0_reg_wmr_scanin), |
| 779 | .scan_out(thr4_cntx_0_reg_wmr_scanout), |
| 780 | .siclk(spc_aclk_wmr), |
| 781 | .clk ( l2clk ), |
| 782 | .en ( 1'b1 ), |
| 783 | .din ( next_thr4_cnxt_0_data[13:0]), |
| 784 | .dout( thr4_cntx_0[13:0] ), |
| 785 | .se(se), |
| 786 | .soclk(soclk), |
| 787 | .pce_ov(pce_ov), |
| 788 | .stop(stop)); |
| 789 | |
| 790 | // assign thr4_cntx_0_q[13:0] = thr4_cntx_0[13:0] & {13{~gt_t_zero[4]}} ; |
| 791 | |
| 792 | ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr4_cntx_0_and ( |
| 793 | .din0({13{ctx_gt_zero_0_[4]}}), |
| 794 | .din1(thr4_cntx_0[12:0]), |
| 795 | .dout(thr4_cntx_0_q[12:0]) |
| 796 | ); |
| 797 | |
| 798 | |
| 799 | ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr4_cntx_1_reg ( // FS:wmr_protect |
| 800 | .scan_in(thr4_cntx_1_reg_wmr_scanin), |
| 801 | .scan_out(thr4_cntx_1_reg_wmr_scanout), |
| 802 | .siclk(spc_aclk_wmr), |
| 803 | .clk ( l2clk ), |
| 804 | .en ( 1'b1 ), |
| 805 | .din ( next_thr4_cnxt_1_data[13:0]), |
| 806 | .dout( thr4_cntx_1[13:0] ), |
| 807 | .se(se), |
| 808 | .soclk(soclk), |
| 809 | .pce_ov(pce_ov), |
| 810 | .stop(stop)); |
| 811 | |
| 812 | // assign thr4_cntx_1_q[13:0] = thr4_cntx_1[13:0] & {13{~gt_t_zero[4]}} ; |
| 813 | |
| 814 | ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr4_cntx_1_and ( |
| 815 | .din0({13{ctx_gt_zero_0_[4]}}), |
| 816 | .din1(thr4_cntx_1[12:0]), |
| 817 | .dout(thr4_cntx_1_q[12:0]) |
| 818 | ); |
| 819 | |
| 820 | |
| 821 | //////////////////////////////////// |
| 822 | // Thread 5 context registers // |
| 823 | //////////////////////////////////// |
| 824 | ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr5_cntx_0_reg ( // FS:wmr_protect |
| 825 | .scan_in(thr5_cntx_0_reg_wmr_scanin), |
| 826 | .scan_out(thr5_cntx_0_reg_wmr_scanout), |
| 827 | .siclk(spc_aclk_wmr), |
| 828 | .clk ( l2clk ), |
| 829 | .en ( 1'b1 ), |
| 830 | .din ( next_thr5_cnxt_0_data[13:0]), |
| 831 | .dout( thr5_cntx_0[13:0] ), |
| 832 | .se(se), |
| 833 | .soclk(soclk), |
| 834 | .pce_ov(pce_ov), |
| 835 | .stop(stop)); |
| 836 | |
| 837 | // assign thr5_cntx_0_q[13:0] = thr5_cntx_0[13:0] & {13{~gt_t_zero[5]}} ; |
| 838 | |
| 839 | ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr5_cntx_0_and ( |
| 840 | .din0({13{ctx_gt_zero_0_[5]}}), |
| 841 | .din1(thr5_cntx_0[12:0]), |
| 842 | .dout(thr5_cntx_0_q[12:0]) |
| 843 | ); |
| 844 | |
| 845 | |
| 846 | ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr5_cntx_1_reg ( // FS:wmr_protect |
| 847 | .scan_in(thr5_cntx_1_reg_wmr_scanin), |
| 848 | .scan_out(thr5_cntx_1_reg_wmr_scanout), |
| 849 | .siclk(spc_aclk_wmr), |
| 850 | .clk ( l2clk ), |
| 851 | .en ( 1'b1 ), |
| 852 | .din ( next_thr5_cnxt_1_data[13:0]), |
| 853 | .dout( thr5_cntx_1[13:0] ), |
| 854 | .se(se), |
| 855 | .soclk(soclk), |
| 856 | .pce_ov(pce_ov), |
| 857 | .stop(stop)); |
| 858 | |
| 859 | // assign thr5_cntx_1_q[13:0] = thr5_cntx_1[13:0] & {13{~gt_t_zero[5]}} ; |
| 860 | |
| 861 | ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr5_cntx_1_and ( |
| 862 | .din0({13{ctx_gt_zero_0_[5]}}), |
| 863 | .din1(thr5_cntx_1[12:0]), |
| 864 | .dout(thr5_cntx_1_q[12:0]) |
| 865 | ); |
| 866 | |
| 867 | |
| 868 | //////////////////////////////////// |
| 869 | // Thread 6 context registers // |
| 870 | //////////////////////////////////// |
| 871 | ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr6_cntx_0_reg ( // FS:wmr_protect |
| 872 | .scan_in(thr6_cntx_0_reg_wmr_scanin), |
| 873 | .scan_out(thr6_cntx_0_reg_wmr_scanout), |
| 874 | .siclk(spc_aclk_wmr), |
| 875 | .clk ( l2clk ), |
| 876 | .en ( 1'b1 ), |
| 877 | .din ( next_thr6_cnxt_0_data[13:0]), |
| 878 | .dout( thr6_cntx_0[13:0] ), |
| 879 | .se(se), |
| 880 | .soclk(soclk), |
| 881 | .pce_ov(pce_ov), |
| 882 | .stop(stop)); |
| 883 | |
| 884 | // assign thr6_cntx_0_q[13:0] = thr6_cntx_0[13:0] & {13{~gt_t_zero[6]}} ; |
| 885 | |
| 886 | ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr6_cntx_0_and ( |
| 887 | .din0({13{ctx_gt_zero_0_[6]}}), |
| 888 | .din1(thr6_cntx_0[12:0]), |
| 889 | .dout(thr6_cntx_0_q[12:0]) |
| 890 | ); |
| 891 | |
| 892 | |
| 893 | ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr6_cntx_1_reg ( // FS:wmr_protect |
| 894 | .scan_in(thr6_cntx_1_reg_wmr_scanin), |
| 895 | .scan_out(thr6_cntx_1_reg_wmr_scanout), |
| 896 | .siclk(spc_aclk_wmr), |
| 897 | .clk ( l2clk ), |
| 898 | .en ( 1'b1 ), |
| 899 | .din ( next_thr6_cnxt_1_data[13:0]), |
| 900 | .dout( thr6_cntx_1[13:0] ), |
| 901 | .se(se), |
| 902 | .soclk(soclk), |
| 903 | .pce_ov(pce_ov), |
| 904 | .stop(stop)); |
| 905 | |
| 906 | // assign thr6_cntx_1_q[13:0] = thr6_cntx_1[13:0] & {13{~gt_t_zero[6]}} ; |
| 907 | |
| 908 | ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr6_cntx_1_and ( |
| 909 | .din0({13{ctx_gt_zero_0_[6]}}), |
| 910 | .din1(thr6_cntx_1[12:0]), |
| 911 | .dout(thr6_cntx_1_q[12:0]) |
| 912 | ); |
| 913 | |
| 914 | |
| 915 | //////////////////////////////////// |
| 916 | // Thread 7 context registers // |
| 917 | //////////////////////////////////// |
| 918 | ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr7_cntx_0_reg ( // FS:wmr_protect |
| 919 | .scan_in(thr7_cntx_0_reg_wmr_scanin), |
| 920 | .scan_out(thr7_cntx_0_reg_wmr_scanout), |
| 921 | .siclk(spc_aclk_wmr), |
| 922 | .clk ( l2clk ), |
| 923 | .en ( 1'b1 ), |
| 924 | .din ( next_thr7_cnxt_0_data[13:0]), |
| 925 | .dout( thr7_cntx_0[13:0] ), |
| 926 | .se(se), |
| 927 | .soclk(soclk), |
| 928 | .pce_ov(pce_ov), |
| 929 | .stop(stop)); |
| 930 | |
| 931 | // assign thr7_cntx_0_q[13:0] = thr7_cntx_0[13:0] & {13{~gt_t_zero[7]}} ; |
| 932 | |
| 933 | ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr7_cntx_0_and ( |
| 934 | .din0({13{ctx_gt_zero_0_[7]}}), |
| 935 | .din1(thr7_cntx_0[12:0]), |
| 936 | .dout(thr7_cntx_0_q[12:0]) |
| 937 | ); |
| 938 | |
| 939 | |
| 940 | ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr7_cntx_1_reg ( // FS:wmr_protect |
| 941 | .scan_in(thr7_cntx_1_reg_wmr_scanin), |
| 942 | .scan_out(thr7_cntx_1_reg_wmr_scanout), |
| 943 | .siclk(spc_aclk_wmr), |
| 944 | .clk ( l2clk ), |
| 945 | .en ( 1'b1 ), |
| 946 | .din ( next_thr7_cnxt_1_data[13:0]), |
| 947 | .dout( thr7_cntx_1[13:0] ), |
| 948 | .se(se), |
| 949 | .soclk(soclk), |
| 950 | .pce_ov(pce_ov), |
| 951 | .stop(stop)); |
| 952 | |
| 953 | // assign thr7_cntx_1_q[13:0] = thr7_cntx_1[13:0] & {13{~gt_t_zero[7]}} ; |
| 954 | |
| 955 | ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr7_cntx_1_and ( |
| 956 | .din0({13{ctx_gt_zero_0_[7]}}), |
| 957 | .din1(thr7_cntx_1[12:0]), |
| 958 | .dout(thr7_cntx_1_q[12:0]) |
| 959 | ); |
| 960 | |
| 961 | |
| 962 | ///////////////////////////////////////////////////////////////////// |
| 963 | // Mux out the current context for the thread currently in bf // |
| 964 | ///////////////////////////////////////////////////////////////////// |
| 965 | |
| 966 | |
| 967 | //buff_macro tst_mux_rep0 (width=1,dbuff=24x) ( |
| 968 | // .din ( tcu_muxtest ), |
| 969 | //.dout( tcu_muxtest_rep0 )); |
| 970 | |
| 971 | |
| 972 | |
| 973 | ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_8__stack_14c__width_13 curr_cntx_0_mux ( |
| 974 | .din0( thr0_cntx_0_q[12:0]), // |
| 975 | .din1( thr1_cntx_0_q[12:0]), // |
| 976 | .din2( thr2_cntx_0_q[12:0]), // |
| 977 | .din3( thr3_cntx_0_q[12:0]), // |
| 978 | .din4( thr4_cntx_0_q[12:0]), // |
| 979 | .din5( thr5_cntx_0_q[12:0]), // |
| 980 | .din6( thr6_cntx_0_q[12:0]), // |
| 981 | .din7( thr7_cntx_0_q[12:0]), // |
| 982 | // .muxtst (tcu_muxtest_rep0), |
| 983 | .sel0( ftp_itb_fetch_thr_bf[0]), |
| 984 | .sel1( ftp_itb_fetch_thr_bf[1]), |
| 985 | .sel2( ftp_itb_fetch_thr_bf[2]), |
| 986 | .sel3( ftp_itb_fetch_thr_bf[3]), |
| 987 | .sel4( ftp_itb_fetch_thr_bf[4]), |
| 988 | .sel5( ftp_itb_fetch_thr_bf[5]), |
| 989 | .sel6( ftp_itb_fetch_thr_bf[6]), |
| 990 | .sel7( ftp_itb_fetch_thr_bf[7]), |
| 991 | .dout( ctx_curr_cntx_0_to_buf[12:0] )); |
| 992 | |
| 993 | ifu_ftu_ctx_dp_buff_macro__stack_14c__width_13 curr_cntx_0_buff ( |
| 994 | .din(ctx_curr_cntx_0_to_buf[12:0]), |
| 995 | .dout(ctx_curr_cntx_0_bf[12:0])); |
| 996 | //assign ctx_curr_cntx_0_bf[13:0] = ctx_curr_cntx_0_to_buf[13:0] ; |
| 997 | |
| 998 | // buff_macro tst_mux_rep1 (width=1,dbuff=24x) ( |
| 999 | // .din ( tcu_muxtest ), |
| 1000 | // .dout( tcu_muxtest_rep1 )); |
| 1001 | |
| 1002 | ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_8__stack_14c__width_13 curr_cntx_1_mux ( |
| 1003 | .din0( thr0_cntx_1_q[12:0]), // |
| 1004 | .din1( thr1_cntx_1_q[12:0]), // |
| 1005 | .din2( thr2_cntx_1_q[12:0]), // |
| 1006 | .din3( thr3_cntx_1_q[12:0]), // |
| 1007 | .din4( thr4_cntx_1_q[12:0]), // |
| 1008 | .din5( thr5_cntx_1_q[12:0]), // |
| 1009 | .din6( thr6_cntx_1_q[12:0]), // |
| 1010 | .din7( thr7_cntx_1_q[12:0]), // |
| 1011 | // .muxtst (tcu_muxtest_rep1), |
| 1012 | .sel0( ftp_itb_fetch_thr_bf[0]), |
| 1013 | .sel1( ftp_itb_fetch_thr_bf[1]), |
| 1014 | .sel2( ftp_itb_fetch_thr_bf[2]), |
| 1015 | .sel3( ftp_itb_fetch_thr_bf[3]), |
| 1016 | .sel4( ftp_itb_fetch_thr_bf[4]), |
| 1017 | .sel5( ftp_itb_fetch_thr_bf[5]), |
| 1018 | .sel6( ftp_itb_fetch_thr_bf[6]), |
| 1019 | .sel7( ftp_itb_fetch_thr_bf[7]), |
| 1020 | .dout( ctx_curr_cntx_1_to_buf[12:0] )); |
| 1021 | |
| 1022 | ifu_ftu_ctx_dp_buff_macro__stack_14c__width_13 curr_cntx_1_buff ( |
| 1023 | .din(ctx_curr_cntx_1_to_buf[12:0]), |
| 1024 | .dout(ctx_curr_cntx_1_bf[12:0])); |
| 1025 | |
| 1026 | // assign ctx_curr_cntx_1_bf[12:0] = ctx_curr_cntx_1_to_buf[12:0] ; |
| 1027 | |
| 1028 | ///////////////////////////////////////////////////////////////////// |
| 1029 | // Mux out the context to_write // |
| 1030 | ///////////////////////////////////////////////////////////////////// |
| 1031 | ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_8__stack_14c__width_14 cntx_0_to_write_mux ( |
| 1032 | .din0( thr0_cntx_0[13:0]), // |
| 1033 | .din1( thr1_cntx_0[13:0]), // |
| 1034 | .din2( thr2_cntx_0[13:0]), // |
| 1035 | .din3( thr3_cntx_0[13:0]), // |
| 1036 | .din4( thr4_cntx_0[13:0]), // |
| 1037 | .din5( thr5_cntx_0[13:0]), // |
| 1038 | .din6( thr6_cntx_0[13:0]), // |
| 1039 | .din7( thr7_cntx_0[13:0]), // |
| 1040 | .sel0( itc_thr_to_write[0]), |
| 1041 | .sel1( itc_thr_to_write[1]), |
| 1042 | .sel2( itc_thr_to_write[2]), |
| 1043 | .sel3( itc_thr_to_write[3]), |
| 1044 | .sel4( itc_thr_to_write[4]), |
| 1045 | .sel5( itc_thr_to_write[5]), |
| 1046 | .sel6( itc_thr_to_write[6]), |
| 1047 | .sel7( itc_thr_to_write[7]), |
| 1048 | .dout( ctx_cntx_0_to_write_to_buf[13:0] )); |
| 1049 | |
| 1050 | ifu_ftu_ctx_dp_buff_macro__stack_14c__width_14 cntx_0_to_write_buf ( |
| 1051 | .din(ctx_cntx_0_to_write_to_buf[13:0]), |
| 1052 | .dout(ctx_cntx_0_to_write_bf[13:0])); |
| 1053 | |
| 1054 | ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_8__stack_14c__width_14 cntx_1_to_write_mux ( |
| 1055 | .din0( thr0_cntx_1[13:0]), // |
| 1056 | .din1( thr1_cntx_1[13:0]), // |
| 1057 | .din2( thr2_cntx_1[13:0]), // |
| 1058 | .din3( thr3_cntx_1[13:0]), // |
| 1059 | .din4( thr4_cntx_1[13:0]), // |
| 1060 | .din5( thr5_cntx_1[13:0]), // |
| 1061 | .din6( thr6_cntx_1[13:0]), // |
| 1062 | .din7( thr7_cntx_1[13:0]), // |
| 1063 | .sel0( itc_thr_to_write[0]), |
| 1064 | .sel1( itc_thr_to_write[1]), |
| 1065 | .sel2( itc_thr_to_write[2]), |
| 1066 | .sel3( itc_thr_to_write[3]), |
| 1067 | .sel4( itc_thr_to_write[4]), |
| 1068 | .sel5( itc_thr_to_write[5]), |
| 1069 | .sel6( itc_thr_to_write[6]), |
| 1070 | .sel7( itc_thr_to_write[7]), |
| 1071 | .dout( ctx_cntx_1_to_write_to_buf[13:0] )); |
| 1072 | |
| 1073 | ifu_ftu_ctx_dp_buff_macro__stack_14c__width_14 cntx_1_to_write_buf ( |
| 1074 | .din(ctx_cntx_1_to_write_to_buf[13:0]), |
| 1075 | .dout(ctx_cntx_1_to_write_bf[13:0])); |
| 1076 | |
| 1077 | |
| 1078 | // assign se = tcu_scan_en ; |
| 1079 | // fixscan start: |
| 1080 | assign tlu_tl_gt_0_reg_scanin = scan_in ; |
| 1081 | assign lsu_ifu_data_reg_scanin = tlu_tl_gt_0_reg_scanout ; |
| 1082 | assign scan_out = lsu_ifu_data_reg_scanout ; |
| 1083 | |
| 1084 | assign thr0_cntx_0_reg_wmr_scanin = wmr_scan_in ; |
| 1085 | assign thr0_cntx_1_reg_wmr_scanin = thr0_cntx_0_reg_wmr_scanout; |
| 1086 | assign thr1_cntx_0_reg_wmr_scanin = thr0_cntx_1_reg_wmr_scanout; |
| 1087 | assign thr1_cntx_1_reg_wmr_scanin = thr1_cntx_0_reg_wmr_scanout; |
| 1088 | assign thr2_cntx_0_reg_wmr_scanin = thr1_cntx_1_reg_wmr_scanout; |
| 1089 | assign thr2_cntx_1_reg_wmr_scanin = thr2_cntx_0_reg_wmr_scanout; |
| 1090 | assign thr3_cntx_0_reg_wmr_scanin = thr2_cntx_1_reg_wmr_scanout; |
| 1091 | assign thr3_cntx_1_reg_wmr_scanin = thr3_cntx_0_reg_wmr_scanout; |
| 1092 | assign thr4_cntx_0_reg_wmr_scanin = thr3_cntx_1_reg_wmr_scanout; |
| 1093 | assign thr4_cntx_1_reg_wmr_scanin = thr4_cntx_0_reg_wmr_scanout; |
| 1094 | assign thr5_cntx_0_reg_wmr_scanin = thr4_cntx_1_reg_wmr_scanout; |
| 1095 | assign thr5_cntx_1_reg_wmr_scanin = thr5_cntx_0_reg_wmr_scanout; |
| 1096 | assign thr6_cntx_0_reg_wmr_scanin = thr5_cntx_1_reg_wmr_scanout; |
| 1097 | assign thr6_cntx_1_reg_wmr_scanin = thr6_cntx_0_reg_wmr_scanout; |
| 1098 | assign thr7_cntx_0_reg_wmr_scanin = thr6_cntx_1_reg_wmr_scanout; |
| 1099 | assign thr7_cntx_1_reg_wmr_scanin = thr7_cntx_0_reg_wmr_scanout; |
| 1100 | assign wmr_scan_out = thr7_cntx_1_reg_wmr_scanout; |
| 1101 | // fixscan end: |
| 1102 | endmodule |
| 1103 | |
| 1104 | |
| 1105 | |
| 1106 | // |
| 1107 | // buff macro |
| 1108 | // |
| 1109 | // |
| 1110 | |
| 1111 | |
| 1112 | |
| 1113 | |
| 1114 | |
| 1115 | module ifu_ftu_ctx_dp_buff_macro__dbuff_32x__stack_none__width_4 ( |
| 1116 | din, |
| 1117 | dout); |
| 1118 | input [3:0] din; |
| 1119 | output [3:0] dout; |
| 1120 | |
| 1121 | |
| 1122 | |
| 1123 | |
| 1124 | |
| 1125 | |
| 1126 | buff #(4) d0_0 ( |
| 1127 | .in(din[3:0]), |
| 1128 | .out(dout[3:0]) |
| 1129 | ); |
| 1130 | |
| 1131 | |
| 1132 | |
| 1133 | |
| 1134 | |
| 1135 | |
| 1136 | |
| 1137 | |
| 1138 | endmodule |
| 1139 | |
| 1140 | |
| 1141 | |
| 1142 | |
| 1143 | |
| 1144 | |
| 1145 | |
| 1146 | |
| 1147 | |
| 1148 | // any PARAMS parms go into naming of macro |
| 1149 | |
| 1150 | module ifu_ftu_ctx_dp_msff_macro__stack_14c__width_8 ( |
| 1151 | din, |
| 1152 | clk, |
| 1153 | en, |
| 1154 | se, |
| 1155 | scan_in, |
| 1156 | siclk, |
| 1157 | soclk, |
| 1158 | pce_ov, |
| 1159 | stop, |
| 1160 | dout, |
| 1161 | scan_out); |
| 1162 | wire l1clk; |
| 1163 | wire siclk_out; |
| 1164 | wire soclk_out; |
| 1165 | wire [6:0] so; |
| 1166 | |
| 1167 | input [7:0] din; |
| 1168 | |
| 1169 | |
| 1170 | input clk; |
| 1171 | input en; |
| 1172 | input se; |
| 1173 | input scan_in; |
| 1174 | input siclk; |
| 1175 | input soclk; |
| 1176 | input pce_ov; |
| 1177 | input stop; |
| 1178 | |
| 1179 | |
| 1180 | |
| 1181 | output [7:0] dout; |
| 1182 | |
| 1183 | |
| 1184 | output scan_out; |
| 1185 | |
| 1186 | |
| 1187 | |
| 1188 | |
| 1189 | cl_dp1_l1hdr_8x c0_0 ( |
| 1190 | .l2clk(clk), |
| 1191 | .pce(en), |
| 1192 | .aclk(siclk), |
| 1193 | .bclk(soclk), |
| 1194 | .l1clk(l1clk), |
| 1195 | .se(se), |
| 1196 | .pce_ov(pce_ov), |
| 1197 | .stop(stop), |
| 1198 | .siclk_out(siclk_out), |
| 1199 | .soclk_out(soclk_out) |
| 1200 | ); |
| 1201 | dff #(8) d0_0 ( |
| 1202 | .l1clk(l1clk), |
| 1203 | .siclk(siclk_out), |
| 1204 | .soclk(soclk_out), |
| 1205 | .d(din[7:0]), |
| 1206 | .si({scan_in,so[6:0]}), |
| 1207 | .so({so[6:0],scan_out}), |
| 1208 | .q(dout[7:0]) |
| 1209 | ); |
| 1210 | |
| 1211 | |
| 1212 | |
| 1213 | |
| 1214 | |
| 1215 | |
| 1216 | |
| 1217 | |
| 1218 | |
| 1219 | |
| 1220 | |
| 1221 | |
| 1222 | |
| 1223 | |
| 1224 | |
| 1225 | |
| 1226 | |
| 1227 | |
| 1228 | |
| 1229 | |
| 1230 | endmodule |
| 1231 | |
| 1232 | |
| 1233 | |
| 1234 | |
| 1235 | |
| 1236 | |
| 1237 | |
| 1238 | |
| 1239 | |
| 1240 | // |
| 1241 | // buff macro |
| 1242 | // |
| 1243 | // |
| 1244 | |
| 1245 | |
| 1246 | |
| 1247 | |
| 1248 | |
| 1249 | module ifu_ftu_ctx_dp_buff_macro__stack_14c__width_8 ( |
| 1250 | din, |
| 1251 | dout); |
| 1252 | input [7:0] din; |
| 1253 | output [7:0] dout; |
| 1254 | |
| 1255 | |
| 1256 | |
| 1257 | |
| 1258 | |
| 1259 | |
| 1260 | buff #(8) d0_0 ( |
| 1261 | .in(din[7:0]), |
| 1262 | .out(dout[7:0]) |
| 1263 | ); |
| 1264 | |
| 1265 | |
| 1266 | |
| 1267 | |
| 1268 | |
| 1269 | |
| 1270 | |
| 1271 | |
| 1272 | endmodule |
| 1273 | |
| 1274 | |
| 1275 | |
| 1276 | |
| 1277 | |
| 1278 | |
| 1279 | |
| 1280 | |
| 1281 | |
| 1282 | // any PARAMS parms go into naming of macro |
| 1283 | |
| 1284 | module ifu_ftu_ctx_dp_msff_macro__stack_14c__width_13 ( |
| 1285 | din, |
| 1286 | clk, |
| 1287 | en, |
| 1288 | se, |
| 1289 | scan_in, |
| 1290 | siclk, |
| 1291 | soclk, |
| 1292 | pce_ov, |
| 1293 | stop, |
| 1294 | dout, |
| 1295 | scan_out); |
| 1296 | wire l1clk; |
| 1297 | wire siclk_out; |
| 1298 | wire soclk_out; |
| 1299 | wire [11:0] so; |
| 1300 | |
| 1301 | input [12:0] din; |
| 1302 | |
| 1303 | |
| 1304 | input clk; |
| 1305 | input en; |
| 1306 | input se; |
| 1307 | input scan_in; |
| 1308 | input siclk; |
| 1309 | input soclk; |
| 1310 | input pce_ov; |
| 1311 | input stop; |
| 1312 | |
| 1313 | |
| 1314 | |
| 1315 | output [12:0] dout; |
| 1316 | |
| 1317 | |
| 1318 | output scan_out; |
| 1319 | |
| 1320 | |
| 1321 | |
| 1322 | |
| 1323 | cl_dp1_l1hdr_8x c0_0 ( |
| 1324 | .l2clk(clk), |
| 1325 | .pce(en), |
| 1326 | .aclk(siclk), |
| 1327 | .bclk(soclk), |
| 1328 | .l1clk(l1clk), |
| 1329 | .se(se), |
| 1330 | .pce_ov(pce_ov), |
| 1331 | .stop(stop), |
| 1332 | .siclk_out(siclk_out), |
| 1333 | .soclk_out(soclk_out) |
| 1334 | ); |
| 1335 | dff #(13) d0_0 ( |
| 1336 | .l1clk(l1clk), |
| 1337 | .siclk(siclk_out), |
| 1338 | .soclk(soclk_out), |
| 1339 | .d(din[12:0]), |
| 1340 | .si({scan_in,so[11:0]}), |
| 1341 | .so({so[11:0],scan_out}), |
| 1342 | .q(dout[12:0]) |
| 1343 | ); |
| 1344 | |
| 1345 | |
| 1346 | |
| 1347 | |
| 1348 | |
| 1349 | |
| 1350 | |
| 1351 | |
| 1352 | |
| 1353 | |
| 1354 | |
| 1355 | |
| 1356 | |
| 1357 | |
| 1358 | |
| 1359 | |
| 1360 | |
| 1361 | |
| 1362 | |
| 1363 | |
| 1364 | endmodule |
| 1365 | |
| 1366 | |
| 1367 | |
| 1368 | |
| 1369 | |
| 1370 | |
| 1371 | |
| 1372 | |
| 1373 | |
| 1374 | // |
| 1375 | // parity macro (even parity) |
| 1376 | // |
| 1377 | // |
| 1378 | |
| 1379 | |
| 1380 | |
| 1381 | |
| 1382 | |
| 1383 | module ifu_ftu_ctx_dp_prty_macro__width_16 ( |
| 1384 | din, |
| 1385 | dout); |
| 1386 | input [15:0] din; |
| 1387 | output dout; |
| 1388 | |
| 1389 | |
| 1390 | |
| 1391 | |
| 1392 | |
| 1393 | |
| 1394 | |
| 1395 | prty #(16) m0_0 ( |
| 1396 | .in(din[15:0]), |
| 1397 | .out(dout) |
| 1398 | ); |
| 1399 | |
| 1400 | |
| 1401 | |
| 1402 | |
| 1403 | |
| 1404 | |
| 1405 | |
| 1406 | |
| 1407 | |
| 1408 | |
| 1409 | endmodule |
| 1410 | |
| 1411 | |
| 1412 | |
| 1413 | |
| 1414 | |
| 1415 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1416 | // also for pass-gate with decoder |
| 1417 | |
| 1418 | |
| 1419 | |
| 1420 | |
| 1421 | |
| 1422 | // any PARAMS parms go into naming of macro |
| 1423 | |
| 1424 | module ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 ( |
| 1425 | din0, |
| 1426 | din1, |
| 1427 | sel0, |
| 1428 | dout); |
| 1429 | wire psel0; |
| 1430 | wire psel1; |
| 1431 | |
| 1432 | input [0:0] din0; |
| 1433 | input [0:0] din1; |
| 1434 | input sel0; |
| 1435 | output [0:0] dout; |
| 1436 | |
| 1437 | |
| 1438 | |
| 1439 | |
| 1440 | |
| 1441 | cl_dp1_penc2_8x c0_0 ( |
| 1442 | .sel0(sel0), |
| 1443 | .psel0(psel0), |
| 1444 | .psel1(psel1) |
| 1445 | ); |
| 1446 | |
| 1447 | mux2s #(1) d0_0 ( |
| 1448 | .sel0(psel0), |
| 1449 | .sel1(psel1), |
| 1450 | .in0(din0[0:0]), |
| 1451 | .in1(din1[0:0]), |
| 1452 | .dout(dout[0:0]) |
| 1453 | ); |
| 1454 | |
| 1455 | |
| 1456 | |
| 1457 | |
| 1458 | |
| 1459 | |
| 1460 | |
| 1461 | |
| 1462 | |
| 1463 | |
| 1464 | |
| 1465 | |
| 1466 | |
| 1467 | endmodule |
| 1468 | |
| 1469 | |
| 1470 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1471 | // also for pass-gate with decoder |
| 1472 | |
| 1473 | |
| 1474 | |
| 1475 | |
| 1476 | |
| 1477 | // any PARAMS parms go into naming of macro |
| 1478 | |
| 1479 | module ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 ( |
| 1480 | din0, |
| 1481 | sel0, |
| 1482 | din1, |
| 1483 | sel1, |
| 1484 | dout); |
| 1485 | wire buffout0; |
| 1486 | wire buffout1; |
| 1487 | |
| 1488 | input [13:0] din0; |
| 1489 | input sel0; |
| 1490 | input [13:0] din1; |
| 1491 | input sel1; |
| 1492 | output [13:0] dout; |
| 1493 | |
| 1494 | |
| 1495 | |
| 1496 | |
| 1497 | |
| 1498 | cl_dp1_muxbuff2_8x c0_0 ( |
| 1499 | .in0(sel0), |
| 1500 | .in1(sel1), |
| 1501 | .out0(buffout0), |
| 1502 | .out1(buffout1) |
| 1503 | ); |
| 1504 | mux2s #(14) d0_0 ( |
| 1505 | .sel0(buffout0), |
| 1506 | .sel1(buffout1), |
| 1507 | .in0(din0[13:0]), |
| 1508 | .in1(din1[13:0]), |
| 1509 | .dout(dout[13:0]) |
| 1510 | ); |
| 1511 | |
| 1512 | |
| 1513 | |
| 1514 | |
| 1515 | |
| 1516 | |
| 1517 | |
| 1518 | |
| 1519 | |
| 1520 | |
| 1521 | |
| 1522 | |
| 1523 | |
| 1524 | endmodule |
| 1525 | |
| 1526 | |
| 1527 | |
| 1528 | |
| 1529 | |
| 1530 | |
| 1531 | // any PARAMS parms go into naming of macro |
| 1532 | |
| 1533 | module ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 ( |
| 1534 | din, |
| 1535 | clk, |
| 1536 | en, |
| 1537 | se, |
| 1538 | scan_in, |
| 1539 | siclk, |
| 1540 | soclk, |
| 1541 | pce_ov, |
| 1542 | stop, |
| 1543 | dout, |
| 1544 | scan_out); |
| 1545 | wire l1clk; |
| 1546 | wire siclk_out; |
| 1547 | wire soclk_out; |
| 1548 | wire [12:0] so; |
| 1549 | |
| 1550 | input [13:0] din; |
| 1551 | |
| 1552 | |
| 1553 | input clk; |
| 1554 | input en; |
| 1555 | input se; |
| 1556 | input scan_in; |
| 1557 | input siclk; |
| 1558 | input soclk; |
| 1559 | input pce_ov; |
| 1560 | input stop; |
| 1561 | |
| 1562 | |
| 1563 | |
| 1564 | output [13:0] dout; |
| 1565 | |
| 1566 | |
| 1567 | output scan_out; |
| 1568 | |
| 1569 | |
| 1570 | |
| 1571 | |
| 1572 | cl_dp1_l1hdr_8x c0_0 ( |
| 1573 | .l2clk(clk), |
| 1574 | .pce(en), |
| 1575 | .aclk(siclk), |
| 1576 | .bclk(soclk), |
| 1577 | .l1clk(l1clk), |
| 1578 | .se(se), |
| 1579 | .pce_ov(pce_ov), |
| 1580 | .stop(stop), |
| 1581 | .siclk_out(siclk_out), |
| 1582 | .soclk_out(soclk_out) |
| 1583 | ); |
| 1584 | dff #(14) d0_0 ( |
| 1585 | .l1clk(l1clk), |
| 1586 | .siclk(siclk_out), |
| 1587 | .soclk(soclk_out), |
| 1588 | .d(din[13:0]), |
| 1589 | .si({scan_in,so[12:0]}), |
| 1590 | .so({so[12:0],scan_out}), |
| 1591 | .q(dout[13:0]) |
| 1592 | ); |
| 1593 | |
| 1594 | |
| 1595 | |
| 1596 | |
| 1597 | |
| 1598 | |
| 1599 | |
| 1600 | |
| 1601 | |
| 1602 | |
| 1603 | |
| 1604 | |
| 1605 | |
| 1606 | |
| 1607 | |
| 1608 | |
| 1609 | |
| 1610 | |
| 1611 | |
| 1612 | |
| 1613 | endmodule |
| 1614 | |
| 1615 | |
| 1616 | |
| 1617 | |
| 1618 | |
| 1619 | |
| 1620 | |
| 1621 | |
| 1622 | |
| 1623 | // |
| 1624 | // nand macro for ports = 2,3,4 |
| 1625 | // |
| 1626 | // |
| 1627 | |
| 1628 | |
| 1629 | |
| 1630 | |
| 1631 | |
| 1632 | module ifu_ftu_ctx_dp_nand_macro__ports_2__stack_14c__width_8 ( |
| 1633 | din0, |
| 1634 | din1, |
| 1635 | dout); |
| 1636 | input [7:0] din0; |
| 1637 | input [7:0] din1; |
| 1638 | output [7:0] dout; |
| 1639 | |
| 1640 | |
| 1641 | |
| 1642 | |
| 1643 | |
| 1644 | |
| 1645 | nand2 #(8) d0_0 ( |
| 1646 | .in0(din0[7:0]), |
| 1647 | .in1(din1[7:0]), |
| 1648 | .out(dout[7:0]) |
| 1649 | ); |
| 1650 | |
| 1651 | |
| 1652 | |
| 1653 | |
| 1654 | |
| 1655 | |
| 1656 | |
| 1657 | |
| 1658 | |
| 1659 | endmodule |
| 1660 | |
| 1661 | |
| 1662 | |
| 1663 | |
| 1664 | |
| 1665 | // |
| 1666 | // and macro for ports = 2,3,4 |
| 1667 | // |
| 1668 | // |
| 1669 | |
| 1670 | |
| 1671 | |
| 1672 | |
| 1673 | |
| 1674 | module ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 ( |
| 1675 | din0, |
| 1676 | din1, |
| 1677 | dout); |
| 1678 | input [12:0] din0; |
| 1679 | input [12:0] din1; |
| 1680 | output [12:0] dout; |
| 1681 | |
| 1682 | |
| 1683 | |
| 1684 | |
| 1685 | |
| 1686 | |
| 1687 | and2 #(13) d0_0 ( |
| 1688 | .in0(din0[12:0]), |
| 1689 | .in1(din1[12:0]), |
| 1690 | .out(dout[12:0]) |
| 1691 | ); |
| 1692 | |
| 1693 | |
| 1694 | |
| 1695 | |
| 1696 | |
| 1697 | |
| 1698 | |
| 1699 | |
| 1700 | |
| 1701 | endmodule |
| 1702 | |
| 1703 | |
| 1704 | |
| 1705 | |
| 1706 | |
| 1707 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1708 | // also for pass-gate with decoder |
| 1709 | |
| 1710 | |
| 1711 | |
| 1712 | |
| 1713 | |
| 1714 | // any PARAMS parms go into naming of macro |
| 1715 | |
| 1716 | module ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_8__stack_14c__width_13 ( |
| 1717 | din0, |
| 1718 | sel0, |
| 1719 | din1, |
| 1720 | sel1, |
| 1721 | din2, |
| 1722 | sel2, |
| 1723 | din3, |
| 1724 | sel3, |
| 1725 | din4, |
| 1726 | sel4, |
| 1727 | din5, |
| 1728 | sel5, |
| 1729 | din6, |
| 1730 | sel6, |
| 1731 | din7, |
| 1732 | sel7, |
| 1733 | dout); |
| 1734 | wire buffout0; |
| 1735 | wire buffout1; |
| 1736 | wire buffout2; |
| 1737 | wire buffout3; |
| 1738 | wire buffout4; |
| 1739 | wire buffout5; |
| 1740 | wire buffout6; |
| 1741 | wire buffout7; |
| 1742 | |
| 1743 | input [12:0] din0; |
| 1744 | input sel0; |
| 1745 | input [12:0] din1; |
| 1746 | input sel1; |
| 1747 | input [12:0] din2; |
| 1748 | input sel2; |
| 1749 | input [12:0] din3; |
| 1750 | input sel3; |
| 1751 | input [12:0] din4; |
| 1752 | input sel4; |
| 1753 | input [12:0] din5; |
| 1754 | input sel5; |
| 1755 | input [12:0] din6; |
| 1756 | input sel6; |
| 1757 | input [12:0] din7; |
| 1758 | input sel7; |
| 1759 | output [12:0] dout; |
| 1760 | |
| 1761 | |
| 1762 | |
| 1763 | |
| 1764 | |
| 1765 | cl_dp1_muxbuff8_8x c0_0 ( |
| 1766 | .in0(sel0), |
| 1767 | .in1(sel1), |
| 1768 | .in2(sel2), |
| 1769 | .in3(sel3), |
| 1770 | .in4(sel4), |
| 1771 | .in5(sel5), |
| 1772 | .in6(sel6), |
| 1773 | .in7(sel7), |
| 1774 | .out0(buffout0), |
| 1775 | .out1(buffout1), |
| 1776 | .out2(buffout2), |
| 1777 | .out3(buffout3), |
| 1778 | .out4(buffout4), |
| 1779 | .out5(buffout5), |
| 1780 | .out6(buffout6), |
| 1781 | .out7(buffout7) |
| 1782 | ); |
| 1783 | mux8s #(13) d0_0 ( |
| 1784 | .sel0(buffout0), |
| 1785 | .sel1(buffout1), |
| 1786 | .sel2(buffout2), |
| 1787 | .sel3(buffout3), |
| 1788 | .sel4(buffout4), |
| 1789 | .sel5(buffout5), |
| 1790 | .sel6(buffout6), |
| 1791 | .sel7(buffout7), |
| 1792 | .in0(din0[12:0]), |
| 1793 | .in1(din1[12:0]), |
| 1794 | .in2(din2[12:0]), |
| 1795 | .in3(din3[12:0]), |
| 1796 | .in4(din4[12:0]), |
| 1797 | .in5(din5[12:0]), |
| 1798 | .in6(din6[12:0]), |
| 1799 | .in7(din7[12:0]), |
| 1800 | .dout(dout[12:0]) |
| 1801 | ); |
| 1802 | |
| 1803 | |
| 1804 | |
| 1805 | |
| 1806 | |
| 1807 | |
| 1808 | |
| 1809 | |
| 1810 | |
| 1811 | |
| 1812 | |
| 1813 | |
| 1814 | |
| 1815 | endmodule |
| 1816 | |
| 1817 | |
| 1818 | // |
| 1819 | // buff macro |
| 1820 | // |
| 1821 | // |
| 1822 | |
| 1823 | |
| 1824 | |
| 1825 | |
| 1826 | |
| 1827 | module ifu_ftu_ctx_dp_buff_macro__stack_14c__width_13 ( |
| 1828 | din, |
| 1829 | dout); |
| 1830 | input [12:0] din; |
| 1831 | output [12:0] dout; |
| 1832 | |
| 1833 | |
| 1834 | |
| 1835 | |
| 1836 | |
| 1837 | |
| 1838 | buff #(13) d0_0 ( |
| 1839 | .in(din[12:0]), |
| 1840 | .out(dout[12:0]) |
| 1841 | ); |
| 1842 | |
| 1843 | |
| 1844 | |
| 1845 | |
| 1846 | |
| 1847 | |
| 1848 | |
| 1849 | |
| 1850 | endmodule |
| 1851 | |
| 1852 | |
| 1853 | |
| 1854 | |
| 1855 | |
| 1856 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1857 | // also for pass-gate with decoder |
| 1858 | |
| 1859 | |
| 1860 | |
| 1861 | |
| 1862 | |
| 1863 | // any PARAMS parms go into naming of macro |
| 1864 | |
| 1865 | module ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_8__stack_14c__width_14 ( |
| 1866 | din0, |
| 1867 | sel0, |
| 1868 | din1, |
| 1869 | sel1, |
| 1870 | din2, |
| 1871 | sel2, |
| 1872 | din3, |
| 1873 | sel3, |
| 1874 | din4, |
| 1875 | sel4, |
| 1876 | din5, |
| 1877 | sel5, |
| 1878 | din6, |
| 1879 | sel6, |
| 1880 | din7, |
| 1881 | sel7, |
| 1882 | dout); |
| 1883 | wire buffout0; |
| 1884 | wire buffout1; |
| 1885 | wire buffout2; |
| 1886 | wire buffout3; |
| 1887 | wire buffout4; |
| 1888 | wire buffout5; |
| 1889 | wire buffout6; |
| 1890 | wire buffout7; |
| 1891 | |
| 1892 | input [13:0] din0; |
| 1893 | input sel0; |
| 1894 | input [13:0] din1; |
| 1895 | input sel1; |
| 1896 | input [13:0] din2; |
| 1897 | input sel2; |
| 1898 | input [13:0] din3; |
| 1899 | input sel3; |
| 1900 | input [13:0] din4; |
| 1901 | input sel4; |
| 1902 | input [13:0] din5; |
| 1903 | input sel5; |
| 1904 | input [13:0] din6; |
| 1905 | input sel6; |
| 1906 | input [13:0] din7; |
| 1907 | input sel7; |
| 1908 | output [13:0] dout; |
| 1909 | |
| 1910 | |
| 1911 | |
| 1912 | |
| 1913 | |
| 1914 | cl_dp1_muxbuff8_8x c0_0 ( |
| 1915 | .in0(sel0), |
| 1916 | .in1(sel1), |
| 1917 | .in2(sel2), |
| 1918 | .in3(sel3), |
| 1919 | .in4(sel4), |
| 1920 | .in5(sel5), |
| 1921 | .in6(sel6), |
| 1922 | .in7(sel7), |
| 1923 | .out0(buffout0), |
| 1924 | .out1(buffout1), |
| 1925 | .out2(buffout2), |
| 1926 | .out3(buffout3), |
| 1927 | .out4(buffout4), |
| 1928 | .out5(buffout5), |
| 1929 | .out6(buffout6), |
| 1930 | .out7(buffout7) |
| 1931 | ); |
| 1932 | mux8s #(14) d0_0 ( |
| 1933 | .sel0(buffout0), |
| 1934 | .sel1(buffout1), |
| 1935 | .sel2(buffout2), |
| 1936 | .sel3(buffout3), |
| 1937 | .sel4(buffout4), |
| 1938 | .sel5(buffout5), |
| 1939 | .sel6(buffout6), |
| 1940 | .sel7(buffout7), |
| 1941 | .in0(din0[13:0]), |
| 1942 | .in1(din1[13:0]), |
| 1943 | .in2(din2[13:0]), |
| 1944 | .in3(din3[13:0]), |
| 1945 | .in4(din4[13:0]), |
| 1946 | .in5(din5[13:0]), |
| 1947 | .in6(din6[13:0]), |
| 1948 | .in7(din7[13:0]), |
| 1949 | .dout(dout[13:0]) |
| 1950 | ); |
| 1951 | |
| 1952 | |
| 1953 | |
| 1954 | |
| 1955 | |
| 1956 | |
| 1957 | |
| 1958 | |
| 1959 | |
| 1960 | |
| 1961 | |
| 1962 | |
| 1963 | |
| 1964 | endmodule |
| 1965 | |
| 1966 | |
| 1967 | // |
| 1968 | // buff macro |
| 1969 | // |
| 1970 | // |
| 1971 | |
| 1972 | |
| 1973 | |
| 1974 | |
| 1975 | |
| 1976 | module ifu_ftu_ctx_dp_buff_macro__stack_14c__width_14 ( |
| 1977 | din, |
| 1978 | dout); |
| 1979 | input [13:0] din; |
| 1980 | output [13:0] dout; |
| 1981 | |
| 1982 | |
| 1983 | |
| 1984 | |
| 1985 | |
| 1986 | |
| 1987 | buff #(14) d0_0 ( |
| 1988 | .in(din[13:0]), |
| 1989 | .out(dout[13:0]) |
| 1990 | ); |
| 1991 | |
| 1992 | |
| 1993 | |
| 1994 | |
| 1995 | |
| 1996 | |
| 1997 | |
| 1998 | |
| 1999 | endmodule |
| 2000 | |
| 2001 | |
| 2002 | |
| 2003 | |