| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: lsu_dac_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module lsu_dac_ctl ( |
| 36 | dcc_ld_inst_vld_m, |
| 37 | dcc_l2fill_vld_m, |
| 38 | dcc_lendian_pre_m, |
| 39 | dcc_bendian_byp_m, |
| 40 | dcc_baddr_m, |
| 41 | dcc_ld_sz_m, |
| 42 | dcc_signed_m, |
| 43 | lmc_asi_bypass_m, |
| 44 | lmc_byp_vld_m, |
| 45 | tlb_cache_way_hit_b, |
| 46 | lmd_misc_msb_m, |
| 47 | dca_msb_w0_b, |
| 48 | dca_msb_w1_b, |
| 49 | dca_msb_w2_b, |
| 50 | dca_msb_w3_b, |
| 51 | dac_swap7_byte0_l, |
| 52 | dac_swap7_byte3_l, |
| 53 | dac_swap7_byte4_l, |
| 54 | dac_swap7_byte7_l, |
| 55 | dac_swap6_byte1_l, |
| 56 | dac_swap6_byte2_l, |
| 57 | dac_swap6_byte5_l, |
| 58 | dac_swap6_byte6_l, |
| 59 | dac_swap5_byte1_l, |
| 60 | dac_swap5_byte2_l, |
| 61 | dac_swap5_byte5_l, |
| 62 | dac_swap5_byte6_l, |
| 63 | dac_swap4_byte0_l, |
| 64 | dac_swap4_byte3_l, |
| 65 | dac_swap4_byte4_l, |
| 66 | dac_swap4_byte7_l, |
| 67 | dac_swap3_byte0_r, |
| 68 | dac_swap3_byte3_r, |
| 69 | dac_swap3_byte4_r, |
| 70 | dac_swap3_byte7_r, |
| 71 | dac_swap2_byte1_r, |
| 72 | dac_swap2_byte2_r, |
| 73 | dac_swap2_byte5_r, |
| 74 | dac_swap2_byte6_r, |
| 75 | dac_swap1_byte0_r, |
| 76 | dac_swap1_byte1_r, |
| 77 | dac_swap1_byte2_r, |
| 78 | dac_swap1_byte3_r, |
| 79 | dac_swap1_byte4_r, |
| 80 | dac_swap1_byte5_r, |
| 81 | dac_swap1_byte6_r, |
| 82 | dac_swap1_byte7_r, |
| 83 | dac_swap0_byte0_r, |
| 84 | dac_swap0_byte1_r, |
| 85 | dac_swap0_byte2_r, |
| 86 | dac_swap0_byte3_r, |
| 87 | dac_swap0_byte4_r, |
| 88 | dac_swap0_byte5_r, |
| 89 | dac_swap0_byte6_r, |
| 90 | dac_swap0_byte7_r, |
| 91 | dac_byte_one_extend, |
| 92 | dac_byte_sel_data, |
| 93 | l2clk, |
| 94 | scan_in, |
| 95 | tcu_pce_ov, |
| 96 | tcu_scan_en, |
| 97 | spc_aclk, |
| 98 | spc_bclk, |
| 99 | scan_out, |
| 100 | lbist_run, |
| 101 | mbi_run, |
| 102 | bist_wdata_1, |
| 103 | dac_bist_cmp_data, |
| 104 | lsu_lsu_pmen_, |
| 105 | dmo_coresel, |
| 106 | dmo_dcmuxctl); |
| 107 | wire se; |
| 108 | wire pce_ov; |
| 109 | wire stop; |
| 110 | wire siclk; |
| 111 | wire soclk; |
| 112 | wire l1clk_en; |
| 113 | wire mbi_run_local; |
| 114 | wire l1clk_pm1; |
| 115 | wire dmo_coresel_qual; |
| 116 | wire dmo_dcmuxctl_qual; |
| 117 | wire dff_dac_b_scanin; |
| 118 | wire dff_dac_b_scanout; |
| 119 | wire ld_inst_vld_b; |
| 120 | wire bendian_m; |
| 121 | wire dff_endian_b_scanin; |
| 122 | wire dff_endian_b_scanout; |
| 123 | wire bendian_b; |
| 124 | wire lendian_b; |
| 125 | wire [7:0] offset_m; |
| 126 | wire [7:0] offset_bist_data_in; |
| 127 | wire dff_baddr_b_scanin; |
| 128 | wire dff_baddr_b_scanout; |
| 129 | wire [7:0] offset_bist_data_out; |
| 130 | wire offset_b4_data_out; |
| 131 | wire offset_b0_data_out; |
| 132 | wire [7:0] offset; |
| 133 | wire [1:0] ld_sz_m; |
| 134 | wire byte_sz_m; |
| 135 | wire hw_sz_m; |
| 136 | wire word_sz_m; |
| 137 | wire dw_sz_m; |
| 138 | wire dff_ld_sz_b_scanin; |
| 139 | wire dff_ld_sz_b_scanout; |
| 140 | wire byte_sz; |
| 141 | wire hw_sz; |
| 142 | wire word_sz; |
| 143 | wire dw_sz; |
| 144 | wire dff_sext_b_scanin; |
| 145 | wire dff_sext_b_scanout; |
| 146 | wire signed_b; |
| 147 | wire dff_misc_msb_b_scanin; |
| 148 | wire dff_misc_msb_b_scanout; |
| 149 | wire [7:0] misc_msb_b; |
| 150 | wire sign_bit_w0; |
| 151 | wire sel_msb0; |
| 152 | wire sel_msb1; |
| 153 | wire sel_msb2; |
| 154 | wire sel_msb3; |
| 155 | wire sel_msb4; |
| 156 | wire sel_msb5; |
| 157 | wire sel_msb6; |
| 158 | wire sel_msb7; |
| 159 | wire sign_bit_w1; |
| 160 | wire sign_bit_w2; |
| 161 | wire sign_bit_w3; |
| 162 | wire sign_bit_xx; |
| 163 | wire sign_bit; |
| 164 | wire bendian; |
| 165 | wire lendian; |
| 166 | wire sign_ext; |
| 167 | wire swap7_byte0; |
| 168 | wire swap7_byte3; |
| 169 | wire swap7_byte4; |
| 170 | wire swap7_byte7; |
| 171 | wire swap6_byte1; |
| 172 | wire swap6_byte2; |
| 173 | wire swap6_byte5; |
| 174 | wire swap6_byte6; |
| 175 | wire swap5_byte1; |
| 176 | wire swap5_byte2; |
| 177 | wire swap5_byte5; |
| 178 | wire swap5_byte6; |
| 179 | wire swap4_byte0; |
| 180 | wire swap4_byte3; |
| 181 | wire swap4_byte4; |
| 182 | wire swap4_byte7; |
| 183 | wire swap3_byte0; |
| 184 | wire swap3_byte3; |
| 185 | wire swap3_byte4; |
| 186 | wire swap3_byte7; |
| 187 | wire swap2_byte1; |
| 188 | wire swap2_byte2; |
| 189 | wire swap2_byte5; |
| 190 | wire swap2_byte6; |
| 191 | wire swap1_byte0; |
| 192 | wire swap1_byte1; |
| 193 | wire swap1_byte2; |
| 194 | wire swap1_byte3; |
| 195 | wire swap1_byte4; |
| 196 | wire swap1_byte5; |
| 197 | wire swap1_byte6; |
| 198 | wire swap1_byte7; |
| 199 | wire swap0_byte0; |
| 200 | wire swap0_byte1; |
| 201 | wire swap0_byte2; |
| 202 | wire swap0_byte3; |
| 203 | wire swap0_byte4; |
| 204 | wire swap0_byte5; |
| 205 | wire swap0_byte6; |
| 206 | wire swap0_byte7; |
| 207 | wire spares_scanin; |
| 208 | wire spares_scanout; |
| 209 | |
| 210 | |
| 211 | input dcc_ld_inst_vld_m; |
| 212 | input dcc_l2fill_vld_m; |
| 213 | input dcc_lendian_pre_m; |
| 214 | input dcc_bendian_byp_m; |
| 215 | input [2:0] dcc_baddr_m; |
| 216 | input [1:0] dcc_ld_sz_m; |
| 217 | input dcc_signed_m; |
| 218 | |
| 219 | input lmc_asi_bypass_m; |
| 220 | input lmc_byp_vld_m; |
| 221 | |
| 222 | input [3:0] tlb_cache_way_hit_b; |
| 223 | |
| 224 | input [7:0] lmd_misc_msb_m; |
| 225 | input [7:0] dca_msb_w0_b; |
| 226 | input [7:0] dca_msb_w1_b; |
| 227 | input [7:0] dca_msb_w2_b; |
| 228 | input [7:0] dca_msb_w3_b; |
| 229 | |
| 230 | output dac_swap7_byte0_l; |
| 231 | output dac_swap7_byte3_l; |
| 232 | output dac_swap7_byte4_l; |
| 233 | output dac_swap7_byte7_l; |
| 234 | output dac_swap6_byte1_l; |
| 235 | output dac_swap6_byte2_l; |
| 236 | output dac_swap6_byte5_l; |
| 237 | output dac_swap6_byte6_l; |
| 238 | output dac_swap5_byte1_l; |
| 239 | output dac_swap5_byte2_l; |
| 240 | output dac_swap5_byte5_l; |
| 241 | output dac_swap5_byte6_l; |
| 242 | output dac_swap4_byte0_l; |
| 243 | output dac_swap4_byte3_l; |
| 244 | output dac_swap4_byte4_l; |
| 245 | output dac_swap4_byte7_l; |
| 246 | output dac_swap3_byte0_r; |
| 247 | output dac_swap3_byte3_r; |
| 248 | output dac_swap3_byte4_r; |
| 249 | output dac_swap3_byte7_r; |
| 250 | output dac_swap2_byte1_r; |
| 251 | output dac_swap2_byte2_r; |
| 252 | output dac_swap2_byte5_r; |
| 253 | output dac_swap2_byte6_r; |
| 254 | output dac_swap1_byte0_r; |
| 255 | output dac_swap1_byte1_r; |
| 256 | output dac_swap1_byte2_r; |
| 257 | output dac_swap1_byte3_r; |
| 258 | output dac_swap1_byte4_r; |
| 259 | output dac_swap1_byte5_r; |
| 260 | output dac_swap1_byte6_r; |
| 261 | output dac_swap1_byte7_r; |
| 262 | output dac_swap0_byte0_r; |
| 263 | output dac_swap0_byte1_r; |
| 264 | output dac_swap0_byte2_r; |
| 265 | output dac_swap0_byte3_r; |
| 266 | output dac_swap0_byte4_r; |
| 267 | output dac_swap0_byte5_r; |
| 268 | output dac_swap0_byte6_r; |
| 269 | output dac_swap0_byte7_r; |
| 270 | |
| 271 | output [7:1] dac_byte_one_extend; |
| 272 | output [7:1] dac_byte_sel_data; |
| 273 | |
| 274 | input l2clk; |
| 275 | input scan_in; |
| 276 | input tcu_pce_ov; // scan signals |
| 277 | input tcu_scan_en; |
| 278 | input spc_aclk; |
| 279 | input spc_bclk; |
| 280 | output scan_out; |
| 281 | |
| 282 | input lbist_run; |
| 283 | input mbi_run; |
| 284 | input [7:0] bist_wdata_1; |
| 285 | output [7:0] dac_bist_cmp_data; |
| 286 | |
| 287 | input lsu_lsu_pmen_; |
| 288 | |
| 289 | input dmo_coresel; // THIS IS ACTIVE LOW!!!!! |
| 290 | input dmo_dcmuxctl; |
| 291 | |
| 292 | // scan renames |
| 293 | assign se = tcu_scan_en; |
| 294 | assign pce_ov = tcu_pce_ov; |
| 295 | assign stop = 1'b0; |
| 296 | assign siclk = spc_aclk; |
| 297 | assign soclk = spc_bclk; |
| 298 | // end scan |
| 299 | |
| 300 | ////////////////////////////// |
| 301 | // Clock header |
| 302 | ////////////////////////////// |
| 303 | |
| 304 | assign l1clk_en = lsu_lsu_pmen_ | dcc_ld_inst_vld_m | dcc_l2fill_vld_m | lmc_byp_vld_m | |
| 305 | mbi_run | mbi_run_local | lbist_run | ~dmo_coresel; |
| 306 | |
| 307 | lsu_dac_ctl_l1clkhdr_ctl_macro clkgen ( |
| 308 | .l2clk (l2clk ), |
| 309 | .l1en (l1clk_en ), |
| 310 | .l1clk (l1clk_pm1 ), |
| 311 | .pce_ov(pce_ov), |
| 312 | .stop(stop), |
| 313 | .se(se) |
| 314 | ); |
| 315 | |
| 316 | |
| 317 | // Qual core inputs with lbist run to prevent X propagation |
| 318 | assign dmo_coresel_qual = ~dmo_coresel & mbi_run_local & ~lbist_run; |
| 319 | assign dmo_dcmuxctl_qual = dmo_dcmuxctl & ~lbist_run; |
| 320 | |
| 321 | // Data alignment and sign extension is part of the critical path with |
| 322 | // load data returning to the register files. When possible, all inputs |
| 323 | // to this block should come from the M stage so that work can begin |
| 324 | // at the start of B. |
| 325 | |
| 326 | lsu_dac_ctl_msff_ctl_macro__width_2 dff_dac_b ( |
| 327 | .scan_in(dff_dac_b_scanin), |
| 328 | .scan_out(dff_dac_b_scanout), |
| 329 | .l1clk (l1clk_pm1), |
| 330 | .din ({dcc_ld_inst_vld_m, mbi_run}), |
| 331 | .dout ({ld_inst_vld_b, mbi_run_local}), |
| 332 | .siclk(siclk), |
| 333 | .soclk(soclk) |
| 334 | ); |
| 335 | |
| 336 | ///////////////////////////////////////////////////////////// |
| 337 | // NOTE: DMO operation requires data alignment such that |
| 338 | // bits 63:32 are either 63:32 (no swapping) or 31:0 (bendian |
| 339 | // word at offset 4. |
| 340 | ///////////////////////////////////////////////////////////// |
| 341 | |
| 342 | // Endianess |
| 343 | // Endianess is controlled by the following rules |
| 344 | // 1. Internal ASI's are all big endian. |
| 345 | // 2. Accesses with implicit ASI's are controlled by (PSTATE.CLE ^ TTE.IE) |
| 346 | // 3. Accesses with explicit ASI's are controlled by (ASI value ^ TTE.IE) |
| 347 | // Most of the work is done ahead of time in dcc. |
| 348 | // Accesses with TTE.IE=1 always miss the D$, so it doesn't factor in the hit path |
| 349 | |
| 350 | assign bendian_m = (dcc_ld_inst_vld_m & ~dcc_lendian_pre_m) | // ld hit |
| 351 | dcc_bendian_byp_m | // fill or bypass |
| 352 | dmo_coresel_qual; // DMO |
| 353 | |
| 354 | lsu_dac_ctl_msff_ctl_macro__width_2 dff_endian_b ( |
| 355 | .scan_in(dff_endian_b_scanin), |
| 356 | .scan_out(dff_endian_b_scanout), |
| 357 | .l1clk (l1clk_pm1), |
| 358 | .din ({(bendian_m | dmo_coresel_qual),~(bendian_m | dmo_coresel_qual)}), |
| 359 | .dout ({bendian_b, lendian_b}), |
| 360 | .siclk(siclk), |
| 361 | .soclk(soclk) |
| 362 | ); |
| 363 | |
| 364 | |
| 365 | // Byte offset |
| 366 | |
| 367 | assign offset_m[0] = ~dcc_baddr_m[2] & ~dcc_baddr_m[1] & ~dcc_baddr_m[0]; |
| 368 | assign offset_m[1] = ~dcc_baddr_m[2] & ~dcc_baddr_m[1] & dcc_baddr_m[0]; |
| 369 | assign offset_m[2] = ~dcc_baddr_m[2] & dcc_baddr_m[1] & ~dcc_baddr_m[0]; |
| 370 | assign offset_m[3] = ~dcc_baddr_m[2] & dcc_baddr_m[1] & dcc_baddr_m[0]; |
| 371 | assign offset_m[4] = dcc_baddr_m[2] & ~dcc_baddr_m[1] & ~dcc_baddr_m[0]; |
| 372 | assign offset_m[5] = dcc_baddr_m[2] & ~dcc_baddr_m[1] & dcc_baddr_m[0]; |
| 373 | assign offset_m[6] = dcc_baddr_m[2] & dcc_baddr_m[1] & ~dcc_baddr_m[0]; |
| 374 | assign offset_m[7] = dcc_baddr_m[2] & dcc_baddr_m[1] & dcc_baddr_m[0]; |
| 375 | |
| 376 | // Reuse this mux for bist data when in BIST mode |
| 377 | assign offset_bist_data_in[7:0] = mbi_run_local ? bist_wdata_1[7:0] : offset_m[7:0]; |
| 378 | |
| 379 | // offset[4,0] needs to factor the dmo_dcmuxctl so I can't share the flop between bist & functional |
| 380 | |
| 381 | lsu_dac_ctl_msff_ctl_macro__width_10 dff_baddr_b ( |
| 382 | .scan_in(dff_baddr_b_scanin), |
| 383 | .scan_out(dff_baddr_b_scanout), |
| 384 | .l1clk (l1clk_pm1), |
| 385 | .din ({offset_bist_data_in[7:0],(offset_m[4] | (dmo_coresel_qual & ~dmo_dcmuxctl_qual)), |
| 386 | (offset_m[0] & ~(dmo_coresel_qual & ~dmo_dcmuxctl_qual))}), |
| 387 | .dout ({offset_bist_data_out[7:0],offset_b4_data_out,offset_b0_data_out}), |
| 388 | .siclk(siclk), |
| 389 | .soclk(soclk) |
| 390 | ); |
| 391 | |
| 392 | assign offset[7:0] = {offset_bist_data_out[7:5],offset_b4_data_out,offset_bist_data_out[3:1],offset_b0_data_out}; |
| 393 | assign dac_bist_cmp_data[7:0] = offset_bist_data_out[7:0]; |
| 394 | |
| 395 | // Data Size |
| 396 | // Size for internal ASI accesses is always 64 bits (sz==11) |
| 397 | assign ld_sz_m[1:0] = dcc_ld_sz_m[1:0] | {2{lmc_asi_bypass_m}}; |
| 398 | |
| 399 | assign byte_sz_m = ~ld_sz_m[1] & ~ld_sz_m[0] & ~dmo_coresel_qual; |
| 400 | assign hw_sz_m = ~ld_sz_m[1] & ld_sz_m[0] & ~dmo_coresel_qual; |
| 401 | assign word_sz_m = (ld_sz_m[1] & ~ld_sz_m[0] & ~dmo_coresel_qual) | (dmo_coresel_qual & ~dmo_dcmuxctl_qual); |
| 402 | assign dw_sz_m = (ld_sz_m[1] & ld_sz_m[0] & ~dmo_coresel_qual) | (dmo_coresel_qual & dmo_dcmuxctl_qual); |
| 403 | |
| 404 | lsu_dac_ctl_msff_ctl_macro__width_4 dff_ld_sz_b ( |
| 405 | .scan_in(dff_ld_sz_b_scanin), |
| 406 | .scan_out(dff_ld_sz_b_scanout), |
| 407 | .l1clk (l1clk_pm1), |
| 408 | .din ({byte_sz_m,hw_sz_m,word_sz_m,dw_sz_m}), |
| 409 | .dout ({byte_sz ,hw_sz ,word_sz ,dw_sz }), |
| 410 | .siclk(siclk), |
| 411 | .soclk(soclk) |
| 412 | ); |
| 413 | |
| 414 | |
| 415 | // Sign extend |
| 416 | lsu_dac_ctl_msff_ctl_macro__width_1 dff_sext_b ( |
| 417 | .scan_in(dff_sext_b_scanin), |
| 418 | .scan_out(dff_sext_b_scanout), |
| 419 | .l1clk (l1clk_pm1), |
| 420 | .din (dcc_signed_m & ~mbi_run_local), |
| 421 | .dout (signed_b), |
| 422 | .siclk(siclk), |
| 423 | .soclk(soclk) |
| 424 | ); |
| 425 | |
| 426 | // Sign bit derivation |
| 427 | // Figure the correct sign bit for each way and the bypass path |
| 428 | // separately. Then, once the hit way is known, mux the result. |
| 429 | |
| 430 | lsu_dac_ctl_msff_ctl_macro__width_8 dff_misc_msb_b ( |
| 431 | .scan_in(dff_misc_msb_b_scanin), |
| 432 | .scan_out(dff_misc_msb_b_scanout), |
| 433 | .l1clk (l1clk_pm1), |
| 434 | .din (lmd_misc_msb_m[7:0]), |
| 435 | .dout (misc_msb_b[7:0]), |
| 436 | .siclk(siclk), |
| 437 | .soclk(soclk) |
| 438 | ); |
| 439 | |
| 440 | assign sign_bit_w0 = sel_msb0 & dca_msb_w0_b[0] | |
| 441 | sel_msb1 & dca_msb_w0_b[1] | |
| 442 | sel_msb2 & dca_msb_w0_b[2] | |
| 443 | sel_msb3 & dca_msb_w0_b[3] | |
| 444 | sel_msb4 & dca_msb_w0_b[4] | |
| 445 | sel_msb5 & dca_msb_w0_b[5] | |
| 446 | sel_msb6 & dca_msb_w0_b[6] | |
| 447 | sel_msb7 & dca_msb_w0_b[7] ; |
| 448 | |
| 449 | assign sign_bit_w1 = sel_msb0 & dca_msb_w1_b[0] | |
| 450 | sel_msb1 & dca_msb_w1_b[1] | |
| 451 | sel_msb2 & dca_msb_w1_b[2] | |
| 452 | sel_msb3 & dca_msb_w1_b[3] | |
| 453 | sel_msb4 & dca_msb_w1_b[4] | |
| 454 | sel_msb5 & dca_msb_w1_b[5] | |
| 455 | sel_msb6 & dca_msb_w1_b[6] | |
| 456 | sel_msb7 & dca_msb_w1_b[7] ; |
| 457 | |
| 458 | assign sign_bit_w2 = sel_msb0 & dca_msb_w2_b[0] | |
| 459 | sel_msb1 & dca_msb_w2_b[1] | |
| 460 | sel_msb2 & dca_msb_w2_b[2] | |
| 461 | sel_msb3 & dca_msb_w2_b[3] | |
| 462 | sel_msb4 & dca_msb_w2_b[4] | |
| 463 | sel_msb5 & dca_msb_w2_b[5] | |
| 464 | sel_msb6 & dca_msb_w2_b[6] | |
| 465 | sel_msb7 & dca_msb_w2_b[7] ; |
| 466 | |
| 467 | assign sign_bit_w3 = sel_msb0 & dca_msb_w3_b[0] | |
| 468 | sel_msb1 & dca_msb_w3_b[1] | |
| 469 | sel_msb2 & dca_msb_w3_b[2] | |
| 470 | sel_msb3 & dca_msb_w3_b[3] | |
| 471 | sel_msb4 & dca_msb_w3_b[4] | |
| 472 | sel_msb5 & dca_msb_w3_b[5] | |
| 473 | sel_msb6 & dca_msb_w3_b[6] | |
| 474 | sel_msb7 & dca_msb_w3_b[7] ; |
| 475 | |
| 476 | assign sign_bit_xx = sel_msb0 & misc_msb_b[0] | |
| 477 | sel_msb1 & misc_msb_b[1] | |
| 478 | sel_msb2 & misc_msb_b[2] | |
| 479 | sel_msb3 & misc_msb_b[3] | |
| 480 | sel_msb4 & misc_msb_b[4] | |
| 481 | sel_msb5 & misc_msb_b[5] | |
| 482 | sel_msb6 & misc_msb_b[6] | |
| 483 | sel_msb7 & misc_msb_b[7] ; |
| 484 | |
| 485 | assign sign_bit = ld_inst_vld_b & tlb_cache_way_hit_b[0] & sign_bit_w0 | |
| 486 | ld_inst_vld_b & tlb_cache_way_hit_b[1] & sign_bit_w1 | |
| 487 | ld_inst_vld_b & tlb_cache_way_hit_b[2] & sign_bit_w2 | |
| 488 | ld_inst_vld_b & tlb_cache_way_hit_b[3] & sign_bit_w3 | |
| 489 | ~ld_inst_vld_b & sign_bit_xx; |
| 490 | |
| 491 | |
| 492 | assign bendian = bendian_b; |
| 493 | assign lendian = lendian_b; |
| 494 | assign sign_ext = signed_b; |
| 495 | |
| 496 | // Byte Alignment |
| 497 | // dcc_swapX_byteY indicates that the aligned data will have byteY as |
| 498 | // returned from the dcache muxed into the byteX position. This data |
| 499 | // may be overridden by sign extesion in the next step. |
| 500 | // |
| 501 | // See the espresso input file align_byte.pla for the truth table. |
| 502 | // espresso -Dso -o eqntott align_byte.pla |
| 503 | |
| 504 | assign swap7_byte0 = (lendian&word_sz&offset[4]) | (lendian&dw_sz); |
| 505 | |
| 506 | assign swap7_byte3 = (bendian&word_sz&offset[4]); // DMOl |
| 507 | |
| 508 | assign swap7_byte4 = (lendian&word_sz&offset[0]); |
| 509 | |
| 510 | assign swap7_byte7 = (bendian&word_sz&offset[0]) | (bendian&dw_sz); // DMOh |
| 511 | |
| 512 | assign swap6_byte1 = (lendian&word_sz&offset[4]) | (lendian&dw_sz); |
| 513 | |
| 514 | assign swap6_byte2 = (bendian&word_sz&offset[4]); // DMOl |
| 515 | |
| 516 | assign swap6_byte5 = (lendian&word_sz&offset[0]); |
| 517 | |
| 518 | assign swap6_byte6 = (bendian&word_sz&offset[0]) | (bendian&dw_sz); // DMOh |
| 519 | |
| 520 | assign swap5_byte1 = (bendian&word_sz&offset[4]); // DMOl |
| 521 | |
| 522 | assign swap5_byte2 = (lendian&word_sz&offset[4]) | (lendian&dw_sz); |
| 523 | |
| 524 | assign swap5_byte5 = (bendian&word_sz&offset[0]) | (bendian&dw_sz); // DMOh |
| 525 | |
| 526 | assign swap5_byte6 = (lendian&word_sz&offset[0]); |
| 527 | |
| 528 | assign swap4_byte0 = (bendian&word_sz&offset[4]); // DMOl |
| 529 | |
| 530 | assign swap4_byte3 = (lendian&word_sz&offset[4]) | (lendian&dw_sz); |
| 531 | |
| 532 | assign swap4_byte4 = (bendian&word_sz&offset[0]) | (bendian&dw_sz); // DMOh |
| 533 | |
| 534 | assign swap4_byte7 = (lendian&word_sz&offset[0]); |
| 535 | |
| 536 | assign swap3_byte0 = (lendian&word_sz&offset[4]); |
| 537 | |
| 538 | assign swap3_byte3 = (bendian&word_sz&offset[4]) | (bendian&dw_sz); |
| 539 | |
| 540 | assign swap3_byte4 = (lendian&word_sz&offset[0]) | (lendian&dw_sz); |
| 541 | |
| 542 | assign swap3_byte7 = (bendian&word_sz&offset[0]); |
| 543 | |
| 544 | assign swap2_byte1 = (lendian&word_sz&offset[4]); |
| 545 | |
| 546 | assign swap2_byte2 = (bendian&word_sz&offset[4]) | (bendian&dw_sz); |
| 547 | |
| 548 | assign swap2_byte5 = (lendian&word_sz&offset[0]) | (lendian&dw_sz); |
| 549 | |
| 550 | assign swap2_byte6 = (bendian&word_sz&offset[0]); |
| 551 | |
| 552 | assign swap1_byte0 = (lendian&hw_sz&offset[6]); |
| 553 | |
| 554 | assign swap1_byte1 = (bendian&hw_sz&offset[6]) | (bendian&word_sz&offset[4]) | ( |
| 555 | bendian&dw_sz); |
| 556 | |
| 557 | assign swap1_byte2 = (lendian&word_sz&offset[4]) | (lendian&hw_sz&offset[4]); |
| 558 | |
| 559 | assign swap1_byte3 = (bendian&hw_sz&offset[4]); |
| 560 | |
| 561 | assign swap1_byte4 = (lendian&hw_sz&offset[2]); |
| 562 | |
| 563 | assign swap1_byte5 = (bendian&hw_sz&offset[2]) | (bendian&word_sz&offset[0]); |
| 564 | |
| 565 | assign swap1_byte6 = (lendian&word_sz&offset[0]) | (lendian&hw_sz&offset[0]) | ( |
| 566 | lendian&dw_sz); |
| 567 | |
| 568 | assign swap1_byte7 = (bendian&hw_sz&offset[0]); |
| 569 | |
| 570 | assign swap0_byte0 = (bendian&hw_sz&offset[6]) | (bendian&word_sz&offset[4]) | ( |
| 571 | byte_sz&offset[7]) | (bendian&dw_sz); |
| 572 | |
| 573 | assign swap0_byte1 = (lendian&hw_sz&offset[6]) | (byte_sz&offset[6]); |
| 574 | |
| 575 | assign swap0_byte2 = (bendian&hw_sz&offset[4]) | (byte_sz&offset[5]); |
| 576 | |
| 577 | assign swap0_byte3 = (lendian&word_sz&offset[4]) | (lendian&hw_sz&offset[4]) | ( |
| 578 | byte_sz&offset[4]); |
| 579 | |
| 580 | assign swap0_byte4 = (bendian&hw_sz&offset[2]) | (bendian&word_sz&offset[0]) | ( |
| 581 | byte_sz&offset[3]); |
| 582 | |
| 583 | assign swap0_byte5 = (lendian&hw_sz&offset[2]) | (byte_sz&offset[2]); |
| 584 | |
| 585 | assign swap0_byte6 = (bendian&hw_sz&offset[0]) | (byte_sz&offset[1]); |
| 586 | |
| 587 | assign swap0_byte7 = (lendian&word_sz&offset[0]) | (lendian&hw_sz&offset[0]) | ( |
| 588 | byte_sz&offset[0]) | (lendian&dw_sz); |
| 589 | |
| 590 | // Left and right side outputs |
| 591 | assign dac_swap7_byte0_l = swap7_byte0; |
| 592 | assign dac_swap7_byte3_l = swap7_byte3; |
| 593 | assign dac_swap7_byte4_l = swap7_byte4; |
| 594 | assign dac_swap7_byte7_l = swap7_byte7; |
| 595 | assign dac_swap6_byte1_l = swap6_byte1; |
| 596 | assign dac_swap6_byte2_l = swap6_byte2; |
| 597 | assign dac_swap6_byte5_l = swap6_byte5; |
| 598 | assign dac_swap6_byte6_l = swap6_byte6; |
| 599 | assign dac_swap5_byte1_l = swap5_byte1; |
| 600 | assign dac_swap5_byte2_l = swap5_byte2; |
| 601 | assign dac_swap5_byte5_l = swap5_byte5; |
| 602 | assign dac_swap5_byte6_l = swap5_byte6; |
| 603 | assign dac_swap4_byte0_l = swap4_byte0; |
| 604 | assign dac_swap4_byte3_l = swap4_byte3; |
| 605 | assign dac_swap4_byte4_l = swap4_byte4; |
| 606 | assign dac_swap4_byte7_l = swap4_byte7; |
| 607 | assign dac_swap3_byte0_r = swap3_byte0; |
| 608 | assign dac_swap3_byte3_r = swap3_byte3; |
| 609 | assign dac_swap3_byte4_r = swap3_byte4; |
| 610 | assign dac_swap3_byte7_r = swap3_byte7; |
| 611 | assign dac_swap2_byte1_r = swap2_byte1; |
| 612 | assign dac_swap2_byte2_r = swap2_byte2; |
| 613 | assign dac_swap2_byte5_r = swap2_byte5; |
| 614 | assign dac_swap2_byte6_r = swap2_byte6; |
| 615 | assign dac_swap1_byte0_r = swap1_byte0; |
| 616 | assign dac_swap1_byte1_r = swap1_byte1; |
| 617 | assign dac_swap1_byte2_r = swap1_byte2; |
| 618 | assign dac_swap1_byte3_r = swap1_byte3; |
| 619 | assign dac_swap1_byte4_r = swap1_byte4; |
| 620 | assign dac_swap1_byte5_r = swap1_byte5; |
| 621 | assign dac_swap1_byte6_r = swap1_byte6; |
| 622 | assign dac_swap1_byte7_r = swap1_byte7; |
| 623 | assign dac_swap0_byte0_r = swap0_byte0; |
| 624 | assign dac_swap0_byte1_r = swap0_byte1; |
| 625 | assign dac_swap0_byte2_r = swap0_byte2; |
| 626 | assign dac_swap0_byte3_r = swap0_byte3; |
| 627 | assign dac_swap0_byte4_r = swap0_byte4; |
| 628 | assign dac_swap0_byte5_r = swap0_byte5; |
| 629 | assign dac_swap0_byte6_r = swap0_byte6; |
| 630 | assign dac_swap0_byte7_r = swap0_byte7; |
| 631 | |
| 632 | // Sign extension |
| 633 | // dac_byte_one_extend indicates a byte is to be filled with ones. |
| 634 | // dac_byte_sel_data indicates that the aligned data is to be passed. |
| 635 | // An aomux is used for this step, so the absence of one_extend or sel_data |
| 636 | // means that the byte will be zero filled. |
| 637 | // Byte 0 is never zero/one filled, so no control exists for it. |
| 638 | // |
| 639 | // See the espresso input file sext_byte.pla for the truth table. |
| 640 | // espresso -Dso -o eqntott sext_byte.pla |
| 641 | |
| 642 | assign dac_byte_one_extend[7] = (sign_ext&sign_bit&!dw_sz); |
| 643 | |
| 644 | assign dac_byte_sel_data[7] = dw_sz | dmo_coresel_qual; |
| 645 | |
| 646 | assign dac_byte_one_extend[6] = (sign_ext&sign_bit&!dw_sz); |
| 647 | |
| 648 | assign dac_byte_sel_data[6] = dw_sz | dmo_coresel_qual; |
| 649 | |
| 650 | assign dac_byte_one_extend[5] = (sign_ext&sign_bit&!dw_sz); |
| 651 | |
| 652 | assign dac_byte_sel_data[5] = dw_sz | dmo_coresel_qual; |
| 653 | |
| 654 | assign dac_byte_one_extend[4] = (sign_ext&sign_bit&!dw_sz); |
| 655 | |
| 656 | assign dac_byte_sel_data[4] = dw_sz | dmo_coresel_qual; |
| 657 | |
| 658 | assign dac_byte_one_extend[3] = (sign_ext&sign_bit&!word_sz&!dw_sz); |
| 659 | |
| 660 | assign dac_byte_sel_data[3] = (!byte_sz&!hw_sz); |
| 661 | |
| 662 | assign dac_byte_one_extend[2] = (sign_ext&sign_bit&!word_sz&!dw_sz); |
| 663 | |
| 664 | assign dac_byte_sel_data[2] = (!byte_sz&!hw_sz); |
| 665 | |
| 666 | assign dac_byte_one_extend[1] = (sign_ext&sign_bit&byte_sz); |
| 667 | |
| 668 | assign dac_byte_sel_data[1] = (!byte_sz); |
| 669 | |
| 670 | // The sign bit is determined by first figuring out which byte will be |
| 671 | // the most significant based on access size, byte offset address, and |
| 672 | // endianess. The msb of that byte is the sign bit. |
| 673 | |
| 674 | assign sel_msb0 = (lendian & word_sz & offset[4]) | // LE word @4 |
| 675 | (lendian & hw_sz & offset[6]) | // LE hw @6 |
| 676 | (offset[7]); // byte @7 |
| 677 | |
| 678 | assign sel_msb1 = (bendian & offset[6]) | // BE hw @6 |
| 679 | (byte_sz & offset[6]); // byte @6 |
| 680 | |
| 681 | assign sel_msb2 = (lendian & hw_sz & offset[4]) | // LE hw @4 |
| 682 | (offset[5]); // byte @5 |
| 683 | |
| 684 | assign sel_msb3 = (bendian & offset[4]) | // BE hw or word @4 |
| 685 | (byte_sz & offset[4]); // byte @4 |
| 686 | |
| 687 | assign sel_msb4 = (lendian & word_sz & offset[0]) | // LE word @0 |
| 688 | (lendian & hw_sz & offset[2]) | // LE hw @2 |
| 689 | (offset[3]); // byte @3 |
| 690 | |
| 691 | assign sel_msb5 = (bendian & offset[2]) | // BE hw@2 |
| 692 | (byte_sz & offset[2]); // byte @2 |
| 693 | |
| 694 | assign sel_msb6 = (lendian & hw_sz & offset[0]) | // LE hw @0 |
| 695 | (offset[1]); // byte @1 |
| 696 | |
| 697 | assign sel_msb7 = (bendian & offset[0]) | // BE hw or word @0 |
| 698 | (byte_sz & offset[0]); // byte @0 |
| 699 | |
| 700 | |
| 701 | lsu_dac_ctl_spare_ctl_macro__num_1 spares ( |
| 702 | .scan_in(spares_scanin), |
| 703 | .scan_out(spares_scanout), |
| 704 | .l1clk (l1clk_pm1), |
| 705 | .siclk(siclk), |
| 706 | .soclk(soclk) |
| 707 | ); |
| 708 | |
| 709 | supply0 vss; |
| 710 | supply1 vdd; |
| 711 | // fixscan start: |
| 712 | assign dff_dac_b_scanin = scan_in ; |
| 713 | assign dff_endian_b_scanin = dff_dac_b_scanout ; |
| 714 | assign dff_baddr_b_scanin = dff_endian_b_scanout ; |
| 715 | assign dff_ld_sz_b_scanin = dff_baddr_b_scanout ; |
| 716 | assign dff_sext_b_scanin = dff_ld_sz_b_scanout ; |
| 717 | assign dff_misc_msb_b_scanin = dff_sext_b_scanout ; |
| 718 | assign spares_scanin = dff_misc_msb_b_scanout ; |
| 719 | assign scan_out = spares_scanout ; |
| 720 | // fixscan end: |
| 721 | endmodule |
| 722 | |
| 723 | |
| 724 | |
| 725 | |
| 726 | |
| 727 | |
| 728 | // any PARAMS parms go into naming of macro |
| 729 | |
| 730 | module lsu_dac_ctl_l1clkhdr_ctl_macro ( |
| 731 | l2clk, |
| 732 | l1en, |
| 733 | pce_ov, |
| 734 | stop, |
| 735 | se, |
| 736 | l1clk); |
| 737 | |
| 738 | |
| 739 | input l2clk; |
| 740 | input l1en; |
| 741 | input pce_ov; |
| 742 | input stop; |
| 743 | input se; |
| 744 | output l1clk; |
| 745 | |
| 746 | |
| 747 | |
| 748 | |
| 749 | |
| 750 | cl_sc1_l1hdr_8x c_0 ( |
| 751 | |
| 752 | |
| 753 | .l2clk(l2clk), |
| 754 | .pce(l1en), |
| 755 | .l1clk(l1clk), |
| 756 | .se(se), |
| 757 | .pce_ov(pce_ov), |
| 758 | .stop(stop) |
| 759 | ); |
| 760 | |
| 761 | |
| 762 | |
| 763 | endmodule |
| 764 | |
| 765 | |
| 766 | |
| 767 | |
| 768 | |
| 769 | |
| 770 | |
| 771 | |
| 772 | |
| 773 | |
| 774 | |
| 775 | |
| 776 | |
| 777 | // any PARAMS parms go into naming of macro |
| 778 | |
| 779 | module lsu_dac_ctl_msff_ctl_macro__width_2 ( |
| 780 | din, |
| 781 | l1clk, |
| 782 | scan_in, |
| 783 | siclk, |
| 784 | soclk, |
| 785 | dout, |
| 786 | scan_out); |
| 787 | wire [1:0] fdin; |
| 788 | wire [0:0] so; |
| 789 | |
| 790 | input [1:0] din; |
| 791 | input l1clk; |
| 792 | input scan_in; |
| 793 | |
| 794 | |
| 795 | input siclk; |
| 796 | input soclk; |
| 797 | |
| 798 | output [1:0] dout; |
| 799 | output scan_out; |
| 800 | assign fdin[1:0] = din[1:0]; |
| 801 | |
| 802 | |
| 803 | |
| 804 | |
| 805 | |
| 806 | |
| 807 | dff #(2) d0_0 ( |
| 808 | .l1clk(l1clk), |
| 809 | .siclk(siclk), |
| 810 | .soclk(soclk), |
| 811 | .d(fdin[1:0]), |
| 812 | .si({scan_in,so[0:0]}), |
| 813 | .so({so[0:0],scan_out}), |
| 814 | .q(dout[1:0]) |
| 815 | ); |
| 816 | |
| 817 | |
| 818 | |
| 819 | |
| 820 | |
| 821 | |
| 822 | |
| 823 | |
| 824 | |
| 825 | |
| 826 | |
| 827 | |
| 828 | endmodule |
| 829 | |
| 830 | |
| 831 | |
| 832 | |
| 833 | |
| 834 | |
| 835 | |
| 836 | |
| 837 | |
| 838 | |
| 839 | |
| 840 | |
| 841 | |
| 842 | // any PARAMS parms go into naming of macro |
| 843 | |
| 844 | module lsu_dac_ctl_msff_ctl_macro__width_10 ( |
| 845 | din, |
| 846 | l1clk, |
| 847 | scan_in, |
| 848 | siclk, |
| 849 | soclk, |
| 850 | dout, |
| 851 | scan_out); |
| 852 | wire [9:0] fdin; |
| 853 | wire [8:0] so; |
| 854 | |
| 855 | input [9:0] din; |
| 856 | input l1clk; |
| 857 | input scan_in; |
| 858 | |
| 859 | |
| 860 | input siclk; |
| 861 | input soclk; |
| 862 | |
| 863 | output [9:0] dout; |
| 864 | output scan_out; |
| 865 | assign fdin[9:0] = din[9:0]; |
| 866 | |
| 867 | |
| 868 | |
| 869 | |
| 870 | |
| 871 | |
| 872 | dff #(10) d0_0 ( |
| 873 | .l1clk(l1clk), |
| 874 | .siclk(siclk), |
| 875 | .soclk(soclk), |
| 876 | .d(fdin[9:0]), |
| 877 | .si({scan_in,so[8:0]}), |
| 878 | .so({so[8:0],scan_out}), |
| 879 | .q(dout[9:0]) |
| 880 | ); |
| 881 | |
| 882 | |
| 883 | |
| 884 | |
| 885 | |
| 886 | |
| 887 | |
| 888 | |
| 889 | |
| 890 | |
| 891 | |
| 892 | |
| 893 | endmodule |
| 894 | |
| 895 | |
| 896 | |
| 897 | |
| 898 | |
| 899 | |
| 900 | |
| 901 | |
| 902 | |
| 903 | |
| 904 | |
| 905 | |
| 906 | |
| 907 | // any PARAMS parms go into naming of macro |
| 908 | |
| 909 | module lsu_dac_ctl_msff_ctl_macro__width_4 ( |
| 910 | din, |
| 911 | l1clk, |
| 912 | scan_in, |
| 913 | siclk, |
| 914 | soclk, |
| 915 | dout, |
| 916 | scan_out); |
| 917 | wire [3:0] fdin; |
| 918 | wire [2:0] so; |
| 919 | |
| 920 | input [3:0] din; |
| 921 | input l1clk; |
| 922 | input scan_in; |
| 923 | |
| 924 | |
| 925 | input siclk; |
| 926 | input soclk; |
| 927 | |
| 928 | output [3:0] dout; |
| 929 | output scan_out; |
| 930 | assign fdin[3:0] = din[3:0]; |
| 931 | |
| 932 | |
| 933 | |
| 934 | |
| 935 | |
| 936 | |
| 937 | dff #(4) d0_0 ( |
| 938 | .l1clk(l1clk), |
| 939 | .siclk(siclk), |
| 940 | .soclk(soclk), |
| 941 | .d(fdin[3:0]), |
| 942 | .si({scan_in,so[2:0]}), |
| 943 | .so({so[2:0],scan_out}), |
| 944 | .q(dout[3:0]) |
| 945 | ); |
| 946 | |
| 947 | |
| 948 | |
| 949 | |
| 950 | |
| 951 | |
| 952 | |
| 953 | |
| 954 | |
| 955 | |
| 956 | |
| 957 | |
| 958 | endmodule |
| 959 | |
| 960 | |
| 961 | |
| 962 | |
| 963 | |
| 964 | |
| 965 | |
| 966 | |
| 967 | |
| 968 | |
| 969 | |
| 970 | |
| 971 | |
| 972 | // any PARAMS parms go into naming of macro |
| 973 | |
| 974 | module lsu_dac_ctl_msff_ctl_macro__width_1 ( |
| 975 | din, |
| 976 | l1clk, |
| 977 | scan_in, |
| 978 | siclk, |
| 979 | soclk, |
| 980 | dout, |
| 981 | scan_out); |
| 982 | wire [0:0] fdin; |
| 983 | |
| 984 | input [0:0] din; |
| 985 | input l1clk; |
| 986 | input scan_in; |
| 987 | |
| 988 | |
| 989 | input siclk; |
| 990 | input soclk; |
| 991 | |
| 992 | output [0:0] dout; |
| 993 | output scan_out; |
| 994 | assign fdin[0:0] = din[0:0]; |
| 995 | |
| 996 | |
| 997 | |
| 998 | |
| 999 | |
| 1000 | |
| 1001 | dff #(1) d0_0 ( |
| 1002 | .l1clk(l1clk), |
| 1003 | .siclk(siclk), |
| 1004 | .soclk(soclk), |
| 1005 | .d(fdin[0:0]), |
| 1006 | .si(scan_in), |
| 1007 | .so(scan_out), |
| 1008 | .q(dout[0:0]) |
| 1009 | ); |
| 1010 | |
| 1011 | |
| 1012 | |
| 1013 | |
| 1014 | |
| 1015 | |
| 1016 | |
| 1017 | |
| 1018 | |
| 1019 | |
| 1020 | |
| 1021 | |
| 1022 | endmodule |
| 1023 | |
| 1024 | |
| 1025 | |
| 1026 | |
| 1027 | |
| 1028 | |
| 1029 | |
| 1030 | |
| 1031 | |
| 1032 | |
| 1033 | |
| 1034 | |
| 1035 | |
| 1036 | // any PARAMS parms go into naming of macro |
| 1037 | |
| 1038 | module lsu_dac_ctl_msff_ctl_macro__width_8 ( |
| 1039 | din, |
| 1040 | l1clk, |
| 1041 | scan_in, |
| 1042 | siclk, |
| 1043 | soclk, |
| 1044 | dout, |
| 1045 | scan_out); |
| 1046 | wire [7:0] fdin; |
| 1047 | wire [6:0] so; |
| 1048 | |
| 1049 | input [7:0] din; |
| 1050 | input l1clk; |
| 1051 | input scan_in; |
| 1052 | |
| 1053 | |
| 1054 | input siclk; |
| 1055 | input soclk; |
| 1056 | |
| 1057 | output [7:0] dout; |
| 1058 | output scan_out; |
| 1059 | assign fdin[7:0] = din[7:0]; |
| 1060 | |
| 1061 | |
| 1062 | |
| 1063 | |
| 1064 | |
| 1065 | |
| 1066 | dff #(8) d0_0 ( |
| 1067 | .l1clk(l1clk), |
| 1068 | .siclk(siclk), |
| 1069 | .soclk(soclk), |
| 1070 | .d(fdin[7:0]), |
| 1071 | .si({scan_in,so[6:0]}), |
| 1072 | .so({so[6:0],scan_out}), |
| 1073 | .q(dout[7:0]) |
| 1074 | ); |
| 1075 | |
| 1076 | |
| 1077 | |
| 1078 | |
| 1079 | |
| 1080 | |
| 1081 | |
| 1082 | |
| 1083 | |
| 1084 | |
| 1085 | |
| 1086 | |
| 1087 | endmodule |
| 1088 | |
| 1089 | |
| 1090 | |
| 1091 | |
| 1092 | |
| 1093 | |
| 1094 | |
| 1095 | |
| 1096 | |
| 1097 | // Description: Spare gate macro for control blocks |
| 1098 | // |
| 1099 | // Param num controls the number of times the macro is added |
| 1100 | // flops=0 can be used to use only combination spare logic |
| 1101 | |
| 1102 | |
| 1103 | module lsu_dac_ctl_spare_ctl_macro__num_1 ( |
| 1104 | l1clk, |
| 1105 | scan_in, |
| 1106 | siclk, |
| 1107 | soclk, |
| 1108 | scan_out); |
| 1109 | wire si_0; |
| 1110 | wire so_0; |
| 1111 | wire spare0_flop_unused; |
| 1112 | wire spare0_buf_32x_unused; |
| 1113 | wire spare0_nand3_8x_unused; |
| 1114 | wire spare0_inv_8x_unused; |
| 1115 | wire spare0_aoi22_4x_unused; |
| 1116 | wire spare0_buf_8x_unused; |
| 1117 | wire spare0_oai22_4x_unused; |
| 1118 | wire spare0_inv_16x_unused; |
| 1119 | wire spare0_nand2_16x_unused; |
| 1120 | wire spare0_nor3_4x_unused; |
| 1121 | wire spare0_nand2_8x_unused; |
| 1122 | wire spare0_buf_16x_unused; |
| 1123 | wire spare0_nor2_16x_unused; |
| 1124 | wire spare0_inv_32x_unused; |
| 1125 | |
| 1126 | |
| 1127 | input l1clk; |
| 1128 | input scan_in; |
| 1129 | input siclk; |
| 1130 | input soclk; |
| 1131 | output scan_out; |
| 1132 | |
| 1133 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), |
| 1134 | .siclk(siclk), |
| 1135 | .soclk(soclk), |
| 1136 | .si(si_0), |
| 1137 | .so(so_0), |
| 1138 | .d(1'b0), |
| 1139 | .q(spare0_flop_unused)); |
| 1140 | assign si_0 = scan_in; |
| 1141 | |
| 1142 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), |
| 1143 | .out(spare0_buf_32x_unused)); |
| 1144 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), |
| 1145 | .in1(1'b1), |
| 1146 | .in2(1'b1), |
| 1147 | .out(spare0_nand3_8x_unused)); |
| 1148 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), |
| 1149 | .out(spare0_inv_8x_unused)); |
| 1150 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), |
| 1151 | .in01(1'b1), |
| 1152 | .in10(1'b1), |
| 1153 | .in11(1'b1), |
| 1154 | .out(spare0_aoi22_4x_unused)); |
| 1155 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), |
| 1156 | .out(spare0_buf_8x_unused)); |
| 1157 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), |
| 1158 | .in01(1'b1), |
| 1159 | .in10(1'b1), |
| 1160 | .in11(1'b1), |
| 1161 | .out(spare0_oai22_4x_unused)); |
| 1162 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), |
| 1163 | .out(spare0_inv_16x_unused)); |
| 1164 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), |
| 1165 | .in1(1'b1), |
| 1166 | .out(spare0_nand2_16x_unused)); |
| 1167 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), |
| 1168 | .in1(1'b0), |
| 1169 | .in2(1'b0), |
| 1170 | .out(spare0_nor3_4x_unused)); |
| 1171 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), |
| 1172 | .in1(1'b1), |
| 1173 | .out(spare0_nand2_8x_unused)); |
| 1174 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), |
| 1175 | .out(spare0_buf_16x_unused)); |
| 1176 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), |
| 1177 | .in1(1'b0), |
| 1178 | .out(spare0_nor2_16x_unused)); |
| 1179 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), |
| 1180 | .out(spare0_inv_32x_unused)); |
| 1181 | assign scan_out = so_0; |
| 1182 | |
| 1183 | |
| 1184 | |
| 1185 | endmodule |
| 1186 | |