| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: lsu_dcd_dp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module lsu_dcd_dp ( |
| 36 | l2clk, |
| 37 | scan_in, |
| 38 | tcu_pce_ov, |
| 39 | tcu_scan_en, |
| 40 | spc_aclk, |
| 41 | spc_bclk, |
| 42 | scan_out, |
| 43 | dca_ld_data_b, |
| 44 | dac_byte_one_extend, |
| 45 | dac_byte_sel_data, |
| 46 | dac_swap7_byte0_l, |
| 47 | dac_swap7_byte3_l, |
| 48 | dac_swap7_byte4_l, |
| 49 | dac_swap7_byte7_l, |
| 50 | dac_swap6_byte1_l, |
| 51 | dac_swap6_byte2_l, |
| 52 | dac_swap6_byte5_l, |
| 53 | dac_swap6_byte6_l, |
| 54 | dac_swap5_byte1_l, |
| 55 | dac_swap5_byte2_l, |
| 56 | dac_swap5_byte5_l, |
| 57 | dac_swap5_byte6_l, |
| 58 | dac_swap4_byte0_l, |
| 59 | dac_swap4_byte3_l, |
| 60 | dac_swap4_byte4_l, |
| 61 | dac_swap4_byte7_l, |
| 62 | dac_swap3_byte0_r, |
| 63 | dac_swap3_byte3_r, |
| 64 | dac_swap3_byte4_r, |
| 65 | dac_swap3_byte7_r, |
| 66 | dac_swap2_byte1_r, |
| 67 | dac_swap2_byte2_r, |
| 68 | dac_swap2_byte5_r, |
| 69 | dac_swap2_byte6_r, |
| 70 | dac_swap1_byte0_r, |
| 71 | dac_swap1_byte1_r, |
| 72 | dac_swap1_byte2_r, |
| 73 | dac_swap1_byte3_r, |
| 74 | dac_swap1_byte4_r, |
| 75 | dac_swap1_byte5_r, |
| 76 | dac_swap1_byte6_r, |
| 77 | dac_swap1_byte7_r, |
| 78 | dac_swap0_byte0_r, |
| 79 | dac_swap0_byte1_r, |
| 80 | dac_swap0_byte2_r, |
| 81 | dac_swap0_byte3_r, |
| 82 | dac_swap0_byte4_r, |
| 83 | dac_swap0_byte5_r, |
| 84 | dac_swap0_byte6_r, |
| 85 | dac_swap0_byte7_r, |
| 86 | lsu_exu_ld_data_b, |
| 87 | lsu_fgu_fld_data_b, |
| 88 | bist_cmp_data, |
| 89 | dcd_dca_data_compare, |
| 90 | dcs_memref_m, |
| 91 | lsu_mmu_va_m, |
| 92 | lsu_mmu_va_b); |
| 93 | wire se; |
| 94 | wire pce_ov; |
| 95 | wire stop; |
| 96 | wire siclk; |
| 97 | wire soclk; |
| 98 | wire clk; |
| 99 | wire [63:0] prealign_load_data; |
| 100 | wire [7:0] byte7; |
| 101 | wire [7:0] byte6; |
| 102 | wire [7:0] byte5; |
| 103 | wire [7:0] byte4; |
| 104 | wire [7:0] byte3; |
| 105 | wire [7:0] byte2; |
| 106 | wire [7:0] byte1; |
| 107 | wire [7:0] byte0; |
| 108 | wire [7:0] align_byte0; |
| 109 | wire [63:0] final_data; |
| 110 | wire [7:0] align_byte1; |
| 111 | wire [7:0] align_byte2; |
| 112 | wire [7:0] align_byte3; |
| 113 | wire [7:0] align_byte4; |
| 114 | wire [7:0] align_byte5; |
| 115 | wire [7:0] align_byte6; |
| 116 | wire [7:0] align_byte7; |
| 117 | wire [1:0] data_compare; |
| 118 | wire [7:0] bist_cmp_data_local; |
| 119 | wire mmu_va_b_lat_scanin; |
| 120 | wire mmu_va_b_lat_scanout; |
| 121 | wire [47:0] va_b; |
| 122 | |
| 123 | |
| 124 | // globals |
| 125 | input l2clk; |
| 126 | input scan_in; |
| 127 | input tcu_pce_ov; // scan signals |
| 128 | input tcu_scan_en; |
| 129 | input spc_aclk; |
| 130 | input spc_bclk; |
| 131 | output scan_out; |
| 132 | |
| 133 | // Data sources |
| 134 | input [63:0] dca_ld_data_b; // data from dcache array |
| 135 | |
| 136 | // Sign/zero extend controls |
| 137 | input [7:1] dac_byte_one_extend; |
| 138 | input [7:1] dac_byte_sel_data; |
| 139 | |
| 140 | // Byte alignment controls |
| 141 | input dac_swap7_byte0_l; |
| 142 | input dac_swap7_byte3_l; |
| 143 | input dac_swap7_byte4_l; |
| 144 | input dac_swap7_byte7_l; |
| 145 | input dac_swap6_byte1_l; |
| 146 | input dac_swap6_byte2_l; |
| 147 | input dac_swap6_byte5_l; |
| 148 | input dac_swap6_byte6_l; |
| 149 | input dac_swap5_byte1_l; |
| 150 | input dac_swap5_byte2_l; |
| 151 | input dac_swap5_byte5_l; |
| 152 | input dac_swap5_byte6_l; |
| 153 | input dac_swap4_byte0_l; |
| 154 | input dac_swap4_byte3_l; |
| 155 | input dac_swap4_byte4_l; |
| 156 | input dac_swap4_byte7_l; |
| 157 | |
| 158 | input dac_swap3_byte0_r; |
| 159 | input dac_swap3_byte3_r; |
| 160 | input dac_swap3_byte4_r; |
| 161 | input dac_swap3_byte7_r; |
| 162 | input dac_swap2_byte1_r; |
| 163 | input dac_swap2_byte2_r; |
| 164 | input dac_swap2_byte5_r; |
| 165 | input dac_swap2_byte6_r; |
| 166 | input dac_swap1_byte0_r; |
| 167 | input dac_swap1_byte1_r; |
| 168 | input dac_swap1_byte2_r; |
| 169 | input dac_swap1_byte3_r; |
| 170 | input dac_swap1_byte4_r; |
| 171 | input dac_swap1_byte5_r; |
| 172 | input dac_swap1_byte6_r; |
| 173 | input dac_swap1_byte7_r; |
| 174 | input dac_swap0_byte0_r; |
| 175 | input dac_swap0_byte1_r; |
| 176 | input dac_swap0_byte2_r; |
| 177 | input dac_swap0_byte3_r; |
| 178 | input dac_swap0_byte4_r; |
| 179 | input dac_swap0_byte5_r; |
| 180 | input dac_swap0_byte6_r; |
| 181 | input dac_swap0_byte7_r; |
| 182 | |
| 183 | // Outputs to exu and fgu |
| 184 | output [63:0] lsu_exu_ld_data_b; |
| 185 | output [63:0] lsu_fgu_fld_data_b; |
| 186 | |
| 187 | input [7:0] bist_cmp_data; |
| 188 | output [1:0] dcd_dca_data_compare; |
| 189 | |
| 190 | input dcs_memref_m; |
| 191 | input [47:0] lsu_mmu_va_m; |
| 192 | output [47:0] lsu_mmu_va_b; |
| 193 | |
| 194 | assign se = tcu_scan_en; |
| 195 | assign pce_ov = tcu_pce_ov; |
| 196 | assign stop = 1'b0; |
| 197 | assign siclk = spc_aclk; |
| 198 | assign soclk = spc_bclk; |
| 199 | assign clk = l2clk; |
| 200 | |
| 201 | |
| 202 | assign prealign_load_data[63:0] = dca_ld_data_b[63:0]; |
| 203 | |
| 204 | //========================================================================================= |
| 205 | // Alignment of Load Return Data |
| 206 | //========================================================================================= |
| 207 | |
| 208 | // All data returning to the register files must be aligned |
| 209 | // and sign extended here. Formatting occurs in two steps. |
| 210 | // 1st: Swizzle the bytes based on endianess, size, and address. |
| 211 | // 2nd: Pass the data or replace with zero/one extention. |
| 212 | // In the layout, bits should be interleaved to (1) minmize wire |
| 213 | // usage and (2) keep msb's close to the dac block. |
| 214 | |
| 215 | // Because the fgu is flipped in the spc floorplan, it's alignment muxes are separate |
| 216 | // so that the mux ordering matches the fgu bit ordering. |
| 217 | |
| 218 | assign byte7[7:0] = prealign_load_data[63:56]; |
| 219 | assign byte6[7:0] = prealign_load_data[55:48]; |
| 220 | assign byte5[7:0] = prealign_load_data[47:40]; |
| 221 | assign byte4[7:0] = prealign_load_data[39:32]; |
| 222 | assign byte3[7:0] = prealign_load_data[31:24]; |
| 223 | assign byte2[7:0] = prealign_load_data[23:16]; |
| 224 | assign byte1[7:0] = prealign_load_data[15:8]; |
| 225 | assign byte0[7:0] = prealign_load_data[7:0]; |
| 226 | |
| 227 | // INT muxes |
| 228 | |
| 229 | // Byte 0. |
| 230 | lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_8__stack_8c__width_8 i_swap_byte0 ( |
| 231 | .din0 (byte0[7:0]), |
| 232 | .din1 (byte1[7:0]), |
| 233 | .din2 (byte2[7:0]), |
| 234 | .din3 (byte3[7:0]), |
| 235 | .din4 (byte4[7:0]), |
| 236 | .din5 (byte5[7:0]), |
| 237 | .din6 (byte6[7:0]), |
| 238 | .din7 (byte7[7:0]), |
| 239 | .sel0 (dac_swap0_byte0_r), |
| 240 | .sel1 (dac_swap0_byte1_r), |
| 241 | .sel2 (dac_swap0_byte2_r), |
| 242 | .sel3 (dac_swap0_byte3_r), |
| 243 | .sel4 (dac_swap0_byte4_r), |
| 244 | .sel5 (dac_swap0_byte5_r), |
| 245 | .sel6 (dac_swap0_byte6_r), |
| 246 | .sel7 (dac_swap0_byte7_r), |
| 247 | .dout (align_byte0[7:0]) |
| 248 | ); |
| 249 | |
| 250 | // No sign-extension for byte0. It always has "real" data. |
| 251 | assign final_data[7:0] = align_byte0[7:0]; |
| 252 | |
| 253 | |
| 254 | // Byte 1. |
| 255 | lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_8__stack_8c__width_8 i_swap_byte1 ( |
| 256 | .din0 (byte0[7:0]), |
| 257 | .din1 (byte1[7:0]), |
| 258 | .din2 (byte2[7:0]), |
| 259 | .din3 (byte3[7:0]), |
| 260 | .din4 (byte4[7:0]), |
| 261 | .din5 (byte5[7:0]), |
| 262 | .din6 (byte6[7:0]), |
| 263 | .din7 (byte7[7:0]), |
| 264 | .sel0 (dac_swap1_byte0_r), |
| 265 | .sel1 (dac_swap1_byte1_r), |
| 266 | .sel2 (dac_swap1_byte2_r), |
| 267 | .sel3 (dac_swap1_byte3_r), |
| 268 | .sel4 (dac_swap1_byte4_r), |
| 269 | .sel5 (dac_swap1_byte5_r), |
| 270 | .sel6 (dac_swap1_byte6_r), |
| 271 | .sel7 (dac_swap1_byte7_r), |
| 272 | .dout (align_byte1[7:0]) |
| 273 | ); |
| 274 | |
| 275 | lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 sext_byte1 ( |
| 276 | .din0 (align_byte1[7:0]), |
| 277 | .din1 (8'hff), |
| 278 | .sel0 (dac_byte_sel_data[1]), |
| 279 | .sel1 (dac_byte_one_extend[1]), |
| 280 | .dout (final_data[15:8]) |
| 281 | ); |
| 282 | |
| 283 | |
| 284 | // Byte 2. |
| 285 | lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_4__stack_8c__width_8 i_swap_byte2 ( |
| 286 | .din0 (byte1[7:0]), |
| 287 | .din1 (byte2[7:0]), |
| 288 | .din2 (byte5[7:0]), |
| 289 | .din3 (byte6[7:0]), |
| 290 | .sel0 (dac_swap2_byte1_r), |
| 291 | .sel1 (dac_swap2_byte2_r), |
| 292 | .sel2 (dac_swap2_byte5_r), |
| 293 | .sel3 (dac_swap2_byte6_r), |
| 294 | .dout (align_byte2[7:0]) |
| 295 | ); |
| 296 | |
| 297 | lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 sext_byte2 ( |
| 298 | .din0 (align_byte2[7:0]), |
| 299 | .din1 (8'hff), |
| 300 | .sel0 (dac_byte_sel_data[2]), |
| 301 | .sel1 (dac_byte_one_extend[2]), |
| 302 | .dout (final_data[23:16]) |
| 303 | ); |
| 304 | |
| 305 | |
| 306 | // Byte 3. |
| 307 | lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_4__stack_8c__width_8 i_swap_byte3 ( |
| 308 | .din0 (byte0[7:0]), |
| 309 | .din1 (byte3[7:0]), |
| 310 | .din2 (byte4[7:0]), |
| 311 | .din3 (byte7[7:0]), |
| 312 | .sel0 (dac_swap3_byte0_r), |
| 313 | .sel1 (dac_swap3_byte3_r), |
| 314 | .sel2 (dac_swap3_byte4_r), |
| 315 | .sel3 (dac_swap3_byte7_r), |
| 316 | .dout (align_byte3[7:0]) |
| 317 | ); |
| 318 | |
| 319 | lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 sext_byte3 ( |
| 320 | .din0 (align_byte3[7:0]), |
| 321 | .din1 (8'hff), |
| 322 | .sel0 (dac_byte_sel_data[3]), |
| 323 | .sel1 (dac_byte_one_extend[3]), |
| 324 | .dout (final_data[31:24]) |
| 325 | ); |
| 326 | |
| 327 | |
| 328 | // Byte 4. |
| 329 | lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_4__stack_8c__width_8 i_swap_byte4 ( |
| 330 | .din0 (byte0[7:0]), |
| 331 | .din1 (byte3[7:0]), |
| 332 | .din2 (byte4[7:0]), |
| 333 | .din3 (byte7[7:0]), |
| 334 | .sel0 (dac_swap4_byte0_l), |
| 335 | .sel1 (dac_swap4_byte3_l), |
| 336 | .sel2 (dac_swap4_byte4_l), |
| 337 | .sel3 (dac_swap4_byte7_l), |
| 338 | .dout (align_byte4[7:0]) |
| 339 | ); |
| 340 | |
| 341 | lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 sext_byte4 ( |
| 342 | .din0 (align_byte4[7:0]), |
| 343 | .din1 (8'hff), |
| 344 | .sel0 (dac_byte_sel_data[4]), |
| 345 | .sel1 (dac_byte_one_extend[4]), |
| 346 | .dout (final_data[39:32]) |
| 347 | ); |
| 348 | |
| 349 | |
| 350 | // Byte 5. |
| 351 | lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_4__stack_8c__width_8 i_swap_byte5 ( |
| 352 | .din0 (byte1[7:0]), |
| 353 | .din1 (byte2[7:0]), |
| 354 | .din2 (byte5[7:0]), |
| 355 | .din3 (byte6[7:0]), |
| 356 | .sel0 (dac_swap5_byte1_l), |
| 357 | .sel1 (dac_swap5_byte2_l), |
| 358 | .sel2 (dac_swap5_byte5_l), |
| 359 | .sel3 (dac_swap5_byte6_l), |
| 360 | .dout (align_byte5[7:0]) |
| 361 | ); |
| 362 | |
| 363 | lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 sext_byte5 ( |
| 364 | .din0 (align_byte5[7:0]), |
| 365 | .din1 (8'hff), |
| 366 | .sel0 (dac_byte_sel_data[5]), |
| 367 | .sel1 (dac_byte_one_extend[5]), |
| 368 | .dout (final_data[47:40]) |
| 369 | ); |
| 370 | |
| 371 | |
| 372 | // Byte 6. |
| 373 | lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_4__stack_8c__width_8 i_swap_byte6 ( |
| 374 | .din0 (byte1[7:0]), |
| 375 | .din1 (byte2[7:0]), |
| 376 | .din2 (byte5[7:0]), |
| 377 | .din3 (byte6[7:0]), |
| 378 | .sel0 (dac_swap6_byte1_l), |
| 379 | .sel1 (dac_swap6_byte2_l), |
| 380 | .sel2 (dac_swap6_byte5_l), |
| 381 | .sel3 (dac_swap6_byte6_l), |
| 382 | .dout (align_byte6[7:0]) |
| 383 | ); |
| 384 | |
| 385 | lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 sext_byte6 ( |
| 386 | .din0 (align_byte6[7:0]), |
| 387 | .din1 (8'hff), |
| 388 | .sel0 (dac_byte_sel_data[6]), |
| 389 | .sel1 (dac_byte_one_extend[6]), |
| 390 | .dout (final_data[55:48]) |
| 391 | ); |
| 392 | |
| 393 | |
| 394 | // Byte 7. |
| 395 | lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_4__stack_8c__width_8 i_swap_byte7 ( |
| 396 | .din0 (byte0[7:0]), |
| 397 | .din1 (byte3[7:0]), |
| 398 | .din2 (byte4[7:0]), |
| 399 | .din3 (byte7[7:0]), |
| 400 | .sel0 (dac_swap7_byte0_l), |
| 401 | .sel1 (dac_swap7_byte3_l), |
| 402 | .sel2 (dac_swap7_byte4_l), |
| 403 | .sel3 (dac_swap7_byte7_l), |
| 404 | .dout (align_byte7[7:0]) |
| 405 | ); |
| 406 | |
| 407 | lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 sext_byte7 ( |
| 408 | .din0 (align_byte7[7:0]), |
| 409 | .din1 (8'hff), |
| 410 | .sel0 (dac_byte_sel_data[7]), |
| 411 | .sel1 (dac_byte_one_extend[7]), |
| 412 | .dout (final_data[63:56]) |
| 413 | ); |
| 414 | |
| 415 | |
| 416 | lsu_dcd_dp_buff_macro__dbuff_32x__rep_1__width_64 exu_data ( |
| 417 | .din (final_data[63:0]), |
| 418 | .dout (lsu_exu_ld_data_b[63:0]) |
| 419 | ); |
| 420 | |
| 421 | lsu_dcd_dp_buff_macro__dbuff_32x__rep_1__width_64 fgu_data ( |
| 422 | .din ({align_byte7[7:0],align_byte6[7:0],align_byte5[7:0],align_byte4[7:0], |
| 423 | align_byte3[7:0],align_byte2[7:0],align_byte1[7:0],align_byte0[7:0]}), |
| 424 | .dout (lsu_fgu_fld_data_b[63:0]) |
| 425 | ); |
| 426 | |
| 427 | /////////// |
| 428 | // BIST |
| 429 | |
| 430 | lsu_dcd_dp_buff_macro__width_10 cmp_buff ( |
| 431 | .din ({ data_compare[1:0],bist_cmp_data[7:0]}), |
| 432 | .dout ({dcd_dca_data_compare[1:0],bist_cmp_data_local[7:0]}) |
| 433 | ); |
| 434 | |
| 435 | lsu_dcd_dp_cmp_macro__width_32 bist_cmp0 ( |
| 436 | .din0 ({4{bist_cmp_data_local[7:0]}}), |
| 437 | .din1 (dca_ld_data_b[63:32]), |
| 438 | .dout (data_compare[0]) |
| 439 | ); |
| 440 | |
| 441 | lsu_dcd_dp_cmp_macro__width_32 bist_cmp1 ( |
| 442 | .din0 ({4{bist_cmp_data_local[7:0]}}), |
| 443 | .din1 (dca_ld_data_b[31:0]), |
| 444 | .dout (data_compare[1]) |
| 445 | ); |
| 446 | |
| 447 | ////////////////////////////// |
| 448 | // Flop for VA to send to MMU |
| 449 | lsu_dcd_dp_msff_macro__minbuff_1__stack_48c__width_48 mmu_va_b_lat ( |
| 450 | .scan_in(mmu_va_b_lat_scanin), |
| 451 | .scan_out(mmu_va_b_lat_scanout), |
| 452 | .en (dcs_memref_m), |
| 453 | .din (lsu_mmu_va_m[47:0]), |
| 454 | .dout (va_b[47:0]), |
| 455 | .clk(clk), |
| 456 | .se(se), |
| 457 | .siclk(siclk), |
| 458 | .soclk(soclk), |
| 459 | .pce_ov(pce_ov), |
| 460 | .stop(stop) |
| 461 | ); |
| 462 | lsu_dcd_dp_buff_macro__dbuff_32x__stack_48c__width_48 mmu_va_b_buf ( |
| 463 | .din (va_b[47:0]), |
| 464 | .dout (lsu_mmu_va_b[47:0]) |
| 465 | ); |
| 466 | |
| 467 | |
| 468 | // fixscan start: |
| 469 | assign mmu_va_b_lat_scanin = scan_in ; |
| 470 | assign scan_out = mmu_va_b_lat_scanout ; |
| 471 | // fixscan end: |
| 472 | endmodule |
| 473 | |
| 474 | |
| 475 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 476 | // also for pass-gate with decoder |
| 477 | |
| 478 | |
| 479 | |
| 480 | |
| 481 | |
| 482 | // any PARAMS parms go into naming of macro |
| 483 | |
| 484 | module lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_8__stack_8c__width_8 ( |
| 485 | din0, |
| 486 | sel0, |
| 487 | din1, |
| 488 | sel1, |
| 489 | din2, |
| 490 | sel2, |
| 491 | din3, |
| 492 | sel3, |
| 493 | din4, |
| 494 | sel4, |
| 495 | din5, |
| 496 | sel5, |
| 497 | din6, |
| 498 | sel6, |
| 499 | din7, |
| 500 | sel7, |
| 501 | dout); |
| 502 | input [7:0] din0; |
| 503 | input sel0; |
| 504 | input [7:0] din1; |
| 505 | input sel1; |
| 506 | input [7:0] din2; |
| 507 | input sel2; |
| 508 | input [7:0] din3; |
| 509 | input sel3; |
| 510 | input [7:0] din4; |
| 511 | input sel4; |
| 512 | input [7:0] din5; |
| 513 | input sel5; |
| 514 | input [7:0] din6; |
| 515 | input sel6; |
| 516 | input [7:0] din7; |
| 517 | input sel7; |
| 518 | output [7:0] dout; |
| 519 | |
| 520 | |
| 521 | |
| 522 | |
| 523 | |
| 524 | mux8s #(8) d0_0 ( |
| 525 | .sel0(sel0), |
| 526 | .sel1(sel1), |
| 527 | .sel2(sel2), |
| 528 | .sel3(sel3), |
| 529 | .sel4(sel4), |
| 530 | .sel5(sel5), |
| 531 | .sel6(sel6), |
| 532 | .sel7(sel7), |
| 533 | .in0(din0[7:0]), |
| 534 | .in1(din1[7:0]), |
| 535 | .in2(din2[7:0]), |
| 536 | .in3(din3[7:0]), |
| 537 | .in4(din4[7:0]), |
| 538 | .in5(din5[7:0]), |
| 539 | .in6(din6[7:0]), |
| 540 | .in7(din7[7:0]), |
| 541 | .dout(dout[7:0]) |
| 542 | ); |
| 543 | |
| 544 | |
| 545 | |
| 546 | |
| 547 | |
| 548 | |
| 549 | |
| 550 | |
| 551 | |
| 552 | |
| 553 | |
| 554 | |
| 555 | |
| 556 | endmodule |
| 557 | |
| 558 | |
| 559 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 560 | // also for pass-gate with decoder |
| 561 | |
| 562 | |
| 563 | |
| 564 | |
| 565 | |
| 566 | // any PARAMS parms go into naming of macro |
| 567 | |
| 568 | module lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 ( |
| 569 | din0, |
| 570 | sel0, |
| 571 | din1, |
| 572 | sel1, |
| 573 | dout); |
| 574 | input [7:0] din0; |
| 575 | input sel0; |
| 576 | input [7:0] din1; |
| 577 | input sel1; |
| 578 | output [7:0] dout; |
| 579 | |
| 580 | |
| 581 | |
| 582 | |
| 583 | |
| 584 | mux2s #(8) d0_0 ( |
| 585 | .sel0(sel0), |
| 586 | .sel1(sel1), |
| 587 | .in0(din0[7:0]), |
| 588 | .in1(din1[7:0]), |
| 589 | .dout(dout[7:0]) |
| 590 | ); |
| 591 | |
| 592 | |
| 593 | |
| 594 | |
| 595 | |
| 596 | |
| 597 | |
| 598 | |
| 599 | |
| 600 | |
| 601 | |
| 602 | |
| 603 | |
| 604 | endmodule |
| 605 | |
| 606 | |
| 607 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 608 | // also for pass-gate with decoder |
| 609 | |
| 610 | |
| 611 | |
| 612 | |
| 613 | |
| 614 | // any PARAMS parms go into naming of macro |
| 615 | |
| 616 | module lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_4__stack_8c__width_8 ( |
| 617 | din0, |
| 618 | sel0, |
| 619 | din1, |
| 620 | sel1, |
| 621 | din2, |
| 622 | sel2, |
| 623 | din3, |
| 624 | sel3, |
| 625 | dout); |
| 626 | input [7:0] din0; |
| 627 | input sel0; |
| 628 | input [7:0] din1; |
| 629 | input sel1; |
| 630 | input [7:0] din2; |
| 631 | input sel2; |
| 632 | input [7:0] din3; |
| 633 | input sel3; |
| 634 | output [7:0] dout; |
| 635 | |
| 636 | |
| 637 | |
| 638 | |
| 639 | |
| 640 | mux4s #(8) d0_0 ( |
| 641 | .sel0(sel0), |
| 642 | .sel1(sel1), |
| 643 | .sel2(sel2), |
| 644 | .sel3(sel3), |
| 645 | .in0(din0[7:0]), |
| 646 | .in1(din1[7:0]), |
| 647 | .in2(din2[7:0]), |
| 648 | .in3(din3[7:0]), |
| 649 | .dout(dout[7:0]) |
| 650 | ); |
| 651 | |
| 652 | |
| 653 | |
| 654 | |
| 655 | |
| 656 | |
| 657 | |
| 658 | |
| 659 | |
| 660 | |
| 661 | |
| 662 | |
| 663 | |
| 664 | endmodule |
| 665 | |
| 666 | |
| 667 | // |
| 668 | // buff macro |
| 669 | // |
| 670 | // |
| 671 | |
| 672 | |
| 673 | |
| 674 | |
| 675 | |
| 676 | module lsu_dcd_dp_buff_macro__dbuff_32x__rep_1__width_64 ( |
| 677 | din, |
| 678 | dout); |
| 679 | input [63:0] din; |
| 680 | output [63:0] dout; |
| 681 | |
| 682 | |
| 683 | |
| 684 | |
| 685 | |
| 686 | |
| 687 | buff #(64) d0_0 ( |
| 688 | .in(din[63:0]), |
| 689 | .out(dout[63:0]) |
| 690 | ); |
| 691 | |
| 692 | |
| 693 | |
| 694 | |
| 695 | |
| 696 | |
| 697 | |
| 698 | |
| 699 | endmodule |
| 700 | |
| 701 | |
| 702 | |
| 703 | |
| 704 | |
| 705 | // |
| 706 | // buff macro |
| 707 | // |
| 708 | // |
| 709 | |
| 710 | |
| 711 | |
| 712 | |
| 713 | |
| 714 | module lsu_dcd_dp_buff_macro__width_10 ( |
| 715 | din, |
| 716 | dout); |
| 717 | input [9:0] din; |
| 718 | output [9:0] dout; |
| 719 | |
| 720 | |
| 721 | |
| 722 | |
| 723 | |
| 724 | |
| 725 | buff #(10) d0_0 ( |
| 726 | .in(din[9:0]), |
| 727 | .out(dout[9:0]) |
| 728 | ); |
| 729 | |
| 730 | |
| 731 | |
| 732 | |
| 733 | |
| 734 | |
| 735 | |
| 736 | |
| 737 | endmodule |
| 738 | |
| 739 | |
| 740 | |
| 741 | |
| 742 | |
| 743 | // |
| 744 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) |
| 745 | // |
| 746 | // |
| 747 | |
| 748 | |
| 749 | |
| 750 | |
| 751 | |
| 752 | module lsu_dcd_dp_cmp_macro__width_32 ( |
| 753 | din0, |
| 754 | din1, |
| 755 | dout); |
| 756 | input [31:0] din0; |
| 757 | input [31:0] din1; |
| 758 | output dout; |
| 759 | |
| 760 | |
| 761 | |
| 762 | |
| 763 | |
| 764 | |
| 765 | cmp #(32) m0_0 ( |
| 766 | .in0(din0[31:0]), |
| 767 | .in1(din1[31:0]), |
| 768 | .out(dout) |
| 769 | ); |
| 770 | |
| 771 | |
| 772 | |
| 773 | |
| 774 | |
| 775 | |
| 776 | |
| 777 | |
| 778 | |
| 779 | |
| 780 | endmodule |
| 781 | |
| 782 | |
| 783 | |
| 784 | |
| 785 | |
| 786 | |
| 787 | |
| 788 | |
| 789 | |
| 790 | // any PARAMS parms go into naming of macro |
| 791 | |
| 792 | module lsu_dcd_dp_msff_macro__minbuff_1__stack_48c__width_48 ( |
| 793 | din, |
| 794 | clk, |
| 795 | en, |
| 796 | se, |
| 797 | scan_in, |
| 798 | siclk, |
| 799 | soclk, |
| 800 | pce_ov, |
| 801 | stop, |
| 802 | dout, |
| 803 | scan_out); |
| 804 | wire l1clk; |
| 805 | wire siclk_out; |
| 806 | wire soclk_out; |
| 807 | wire [46:0] so; |
| 808 | |
| 809 | input [47:0] din; |
| 810 | |
| 811 | |
| 812 | input clk; |
| 813 | input en; |
| 814 | input se; |
| 815 | input scan_in; |
| 816 | input siclk; |
| 817 | input soclk; |
| 818 | input pce_ov; |
| 819 | input stop; |
| 820 | |
| 821 | |
| 822 | |
| 823 | output [47:0] dout; |
| 824 | |
| 825 | |
| 826 | output scan_out; |
| 827 | |
| 828 | |
| 829 | |
| 830 | |
| 831 | cl_dp1_l1hdr_8x c0_0 ( |
| 832 | .l2clk(clk), |
| 833 | .pce(en), |
| 834 | .aclk(siclk), |
| 835 | .bclk(soclk), |
| 836 | .l1clk(l1clk), |
| 837 | .se(se), |
| 838 | .pce_ov(pce_ov), |
| 839 | .stop(stop), |
| 840 | .siclk_out(siclk_out), |
| 841 | .soclk_out(soclk_out) |
| 842 | ); |
| 843 | dff #(48) d0_0 ( |
| 844 | .l1clk(l1clk), |
| 845 | .siclk(siclk_out), |
| 846 | .soclk(soclk_out), |
| 847 | .d(din[47:0]), |
| 848 | .si({scan_in,so[46:0]}), |
| 849 | .so({so[46:0],scan_out}), |
| 850 | .q(dout[47:0]) |
| 851 | ); |
| 852 | |
| 853 | |
| 854 | |
| 855 | |
| 856 | |
| 857 | |
| 858 | |
| 859 | |
| 860 | |
| 861 | |
| 862 | |
| 863 | |
| 864 | |
| 865 | |
| 866 | |
| 867 | |
| 868 | |
| 869 | |
| 870 | |
| 871 | |
| 872 | endmodule |
| 873 | |
| 874 | |
| 875 | |
| 876 | |
| 877 | |
| 878 | |
| 879 | |
| 880 | |
| 881 | |
| 882 | // |
| 883 | // buff macro |
| 884 | // |
| 885 | // |
| 886 | |
| 887 | |
| 888 | |
| 889 | |
| 890 | |
| 891 | module lsu_dcd_dp_buff_macro__dbuff_32x__stack_48c__width_48 ( |
| 892 | din, |
| 893 | dout); |
| 894 | input [47:0] din; |
| 895 | output [47:0] dout; |
| 896 | |
| 897 | |
| 898 | |
| 899 | |
| 900 | |
| 901 | |
| 902 | buff #(48) d0_0 ( |
| 903 | .in(din[47:0]), |
| 904 | .out(dout[47:0]) |
| 905 | ); |
| 906 | |
| 907 | |
| 908 | |
| 909 | |
| 910 | |
| 911 | |
| 912 | |
| 913 | |
| 914 | endmodule |
| 915 | |
| 916 | |
| 917 | |
| 918 | |