| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: lsu_tld_dp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module lsu_tld_dp ( |
| 36 | l2clk, |
| 37 | scan_in, |
| 38 | tcu_pce_ov, |
| 39 | tcu_scan_en, |
| 40 | tcu_se_scancollar_in, |
| 41 | spc_aclk, |
| 42 | spc_bclk, |
| 43 | exu_lsu_address_e, |
| 44 | default_tag, |
| 45 | tlc_sel_write_tag, |
| 46 | tlc_sel_dm_tag, |
| 47 | tlc_sel_wr_dm_bist, |
| 48 | tlc_write_next, |
| 49 | tlc_tte0_clken, |
| 50 | tlc_tte1_clken, |
| 51 | tlc_tag_error_inj, |
| 52 | tlc_data_error_inj, |
| 53 | tlu_tte, |
| 54 | tlc_mbi_run, |
| 55 | mbi_wdata, |
| 56 | mbi_addr, |
| 57 | mbi_cambist_run, |
| 58 | mbi_cambist_shift, |
| 59 | mbi_init_to_zero, |
| 60 | mbi_dtb_write_en, |
| 61 | mbi_repl_write, |
| 62 | mbi_dis_clr_ubit, |
| 63 | mbi_dtb_demap_en, |
| 64 | mbi_demap_type, |
| 65 | tld_mbi_dtb_write_en, |
| 66 | tld_mbi_repl_write, |
| 67 | tld_mbi_dis_clr_ubit, |
| 68 | tld_mbi_dtb_demap_en, |
| 69 | tld_mbi_demap_type, |
| 70 | tgd_tag_c0, |
| 71 | tgd_tag_c1, |
| 72 | scan_out, |
| 73 | tld_ubit, |
| 74 | tld_tag_pid, |
| 75 | tld_tag_c0, |
| 76 | tld_tag_c1, |
| 77 | tld_tag_real, |
| 78 | tld_tag_valid, |
| 79 | tld_tag_mask, |
| 80 | tld_data, |
| 81 | tld_demap_control0, |
| 82 | tld_demap_control1, |
| 83 | tld_use_secondary_context0, |
| 84 | tld_tid, |
| 85 | tld_index_valid, |
| 86 | tld_rw_index, |
| 87 | tld_prty_256m, |
| 88 | tld_prty_4m, |
| 89 | tld_prty_64k, |
| 90 | tld_prty_8k, |
| 91 | tld_prty_ctxt0, |
| 92 | tld_prty_ctxt1, |
| 93 | tld_va_m_eq_zero, |
| 94 | lsu_va_m, |
| 95 | lsu_mmu_va_m, |
| 96 | lsu_exu_address_e); |
| 97 | wire stop; |
| 98 | wire en; |
| 99 | wire clk; |
| 100 | wire se; |
| 101 | wire pce_ov; |
| 102 | wire siclk; |
| 103 | wire soclk; |
| 104 | wire tte0_lat_scanin; |
| 105 | wire tte0_lat_scanout; |
| 106 | wire [54:0] tte0; |
| 107 | wire [12:0] context_to_write; |
| 108 | wire tte1_lat_scanin; |
| 109 | wire tte1_lat_scanout; |
| 110 | wire [54:0] tte1; |
| 111 | wire tte2_lat_scanin; |
| 112 | wire tte2_lat_scanout; |
| 113 | wire [2:0] partition_id1; |
| 114 | wire [51:0] tte2_lat_out; |
| 115 | wire [54:0] tte2; |
| 116 | wire [2:0] partition_id2; |
| 117 | wire wrdata_sel; |
| 118 | wire wrdata_sel_; |
| 119 | wire [68:0] access_tag_m; |
| 120 | wire [68:0] tag_to_demap_d; |
| 121 | wire [68:0] tag_to_write; |
| 122 | wire [7:0] bist_data_0; |
| 123 | wire [69:0] mbist_wdata; |
| 124 | wire test_data_mux_scanin; |
| 125 | wire test_data_mux_scanout; |
| 126 | wire [69:0] bist_wdata; |
| 127 | wire tld_mbi_cambist_run; |
| 128 | wire [27:0] tag0; |
| 129 | wire [55:13] tld_tag_0; |
| 130 | wire default_unused; |
| 131 | wire [6:0] tld_mbi_addr; |
| 132 | wire mask_va_27_22_; |
| 133 | wire mask_va_21_16_; |
| 134 | wire mask_va_15_13_; |
| 135 | wire mask_context_; |
| 136 | wire [27:13] masked_va; |
| 137 | wire [12:0] masked_ctxt; |
| 138 | wire [47:0] va_m; |
| 139 | wire [51:0] tag_for_parity; |
| 140 | wire tag_parity_unmasked; |
| 141 | wire tag_parity_masked; |
| 142 | wire tag_parity_unmasked_; |
| 143 | wire tag_parity_masked_; |
| 144 | wire tag_parity; |
| 145 | wire prty_256m; |
| 146 | wire prty_8k_lower; |
| 147 | wire prty_va_27_22; |
| 148 | wire prty_4m; |
| 149 | wire prty_va_27_16; |
| 150 | wire prty_64k; |
| 151 | wire prty_8k; |
| 152 | wire prty_ctxt0; |
| 153 | wire prty_ctxt1; |
| 154 | wire [36:0] wr_data; |
| 155 | wire data_parity; |
| 156 | wire [7:0] bist_data_1; |
| 157 | wire data_parity_0; |
| 158 | wire data_parity_1; |
| 159 | wire va_m_lat_scanin; |
| 160 | wire va_m_lat_scanout; |
| 161 | wire bist_lat_scanin; |
| 162 | wire bist_lat_scanout; |
| 163 | |
| 164 | |
| 165 | |
| 166 | |
| 167 | input l2clk; |
| 168 | input scan_in; |
| 169 | input tcu_pce_ov; |
| 170 | input tcu_scan_en; |
| 171 | input tcu_se_scancollar_in; |
| 172 | input spc_aclk; |
| 173 | input spc_bclk; |
| 174 | |
| 175 | input [47:0] exu_lsu_address_e; // E->M flop is in this dp |
| 176 | |
| 177 | input [55:13] default_tag; |
| 178 | |
| 179 | // The following signals indicate the |
| 180 | // first cycle of TTE transfer as well |
| 181 | // as the operation (write or demap) |
| 182 | input tlc_sel_write_tag; |
| 183 | input tlc_sel_dm_tag; |
| 184 | input tlc_sel_wr_dm_bist; |
| 185 | input tlc_write_next; |
| 186 | input tlc_tte0_clken; |
| 187 | input tlc_tte1_clken; |
| 188 | |
| 189 | input tlc_tag_error_inj; |
| 190 | input tlc_data_error_inj; |
| 191 | |
| 192 | input [54:0] tlu_tte; |
| 193 | // First cycle of transfer |
| 194 | // (part of tag, data, controls) |
| 195 | // 54 Index valid |
| 196 | // 53:47 Index to write |
| 197 | // 46 Demap / repl sec. cxt |
| 198 | // 45 Demap valid |
| 199 | // 44:43 Demap / context type |
| 200 | // 42 PS_GT_64K |
| 201 | // 41:39 VA[15:13] |
| 202 | // 38 PS_GT_8K |
| 203 | // 37:35 Thread ID |
| 204 | // 34 Real bit |
| 205 | // 33:22 PA[39:28] |
| 206 | // 21:16 PA[27:22] |
| 207 | // 15:10 PA[21:16] |
| 208 | // 09:07 PA[15:13] |
| 209 | // 06 Valid bit |
| 210 | // 05 NFO bit |
| 211 | // 04 IE bit |
| 212 | // 03 CP bit |
| 213 | // 02 X bit |
| 214 | // 01 P bit |
| 215 | // 00 W bit |
| 216 | // Second cycle of transfer |
| 217 | // (rest of tag) |
| 218 | // 47:28 VA[47:28] |
| 219 | // 27:22 VA[27:22] |
| 220 | // 21 PS_EQ_256M |
| 221 | // 20 Valid |
| 222 | // 19 Lock |
| 223 | // 18:13 VA[21:16] |
| 224 | // 12:00 Context |
| 225 | |
| 226 | |
| 227 | input tlc_mbi_run; |
| 228 | input [7:0] mbi_wdata; |
| 229 | input [6:0] mbi_addr; |
| 230 | input mbi_cambist_run; |
| 231 | input mbi_cambist_shift; |
| 232 | input mbi_init_to_zero; |
| 233 | |
| 234 | input mbi_dtb_write_en; |
| 235 | input mbi_repl_write; |
| 236 | input mbi_dis_clr_ubit; |
| 237 | input mbi_dtb_demap_en; |
| 238 | input [1:0] mbi_demap_type; |
| 239 | output tld_mbi_dtb_write_en; |
| 240 | output tld_mbi_repl_write; |
| 241 | output tld_mbi_dis_clr_ubit; |
| 242 | output tld_mbi_dtb_demap_en; |
| 243 | output [1:0] tld_mbi_demap_type; |
| 244 | |
| 245 | input [12:0] tgd_tag_c0; |
| 246 | input [12:0] tgd_tag_c1; |
| 247 | |
| 248 | output scan_out; |
| 249 | output tld_ubit; |
| 250 | output [2:0] tld_tag_pid; |
| 251 | output [12:0] tld_tag_c0; |
| 252 | output [12:0] tld_tag_c1; |
| 253 | output tld_tag_real; |
| 254 | output tld_tag_valid; |
| 255 | output [2:0] tld_tag_mask; |
| 256 | output [37:0] tld_data; |
| 257 | output [2:0] tld_demap_control0; |
| 258 | output [3:0] tld_demap_control1; |
| 259 | output tld_use_secondary_context0; |
| 260 | output [2:0] tld_tid; |
| 261 | output tld_index_valid; |
| 262 | output [6:0] tld_rw_index; |
| 263 | output tld_prty_256m; |
| 264 | output tld_prty_4m; |
| 265 | output tld_prty_64k; |
| 266 | output tld_prty_8k; |
| 267 | output tld_prty_ctxt0; |
| 268 | output tld_prty_ctxt1; |
| 269 | output tld_va_m_eq_zero; |
| 270 | output [47:0] lsu_va_m; |
| 271 | output [47:0] lsu_mmu_va_m; |
| 272 | |
| 273 | output [47:13] lsu_exu_address_e; |
| 274 | |
| 275 | |
| 276 | |
| 277 | assign stop = 1'b0; |
| 278 | assign en = 1'b1; |
| 279 | assign clk = l2clk; |
| 280 | |
| 281 | lsu_tld_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0 ( |
| 282 | .din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}), |
| 283 | .dout({se,pce_ov,siclk,soclk}) |
| 284 | ); |
| 285 | |
| 286 | |
| 287 | /////////////////////////////////////////////////////////////////////////////// |
| 288 | // Flop the TTE from TLU |
| 289 | |
| 290 | lsu_tld_dp_msff_macro__stack_70c__width_55 tte0_lat ( |
| 291 | .scan_in(tte0_lat_scanin), |
| 292 | .scan_out(tte0_lat_scanout), |
| 293 | .din (tlu_tte [54:0] ), |
| 294 | .dout (tte0 [54:0] ), |
| 295 | .en (tlc_tte0_clken), |
| 296 | .clk(clk), |
| 297 | .se(se), |
| 298 | .siclk(siclk), |
| 299 | .soclk(soclk), |
| 300 | .pce_ov(pce_ov), |
| 301 | .stop(stop) |
| 302 | ); |
| 303 | |
| 304 | assign tld_tid[2:0] = |
| 305 | tte0[37:35]; |
| 306 | |
| 307 | // Mux context for write tag |
| 308 | lsu_tld_dp_mux_macro__mux_aope__ports_2__stack_70c__width_13 context_to_write_mux ( |
| 309 | .din0 (tgd_tag_c0 [12:0] ), |
| 310 | .din1 (tte0 [12:0] ), |
| 311 | .sel0 (tlc_write_next ), |
| 312 | .dout (context_to_write [12:0] ) |
| 313 | ); |
| 314 | |
| 315 | assign tld_use_secondary_context0 = |
| 316 | tte0[46]; |
| 317 | |
| 318 | lsu_tld_dp_msff_macro__stack_70c__width_55 tte1_lat ( |
| 319 | .scan_in(tte1_lat_scanin), |
| 320 | .scan_out(tte1_lat_scanout), |
| 321 | .din ({tte0 [54:13], context_to_write[12:0]}), |
| 322 | .dout ( tte1 [54:0] ), |
| 323 | .en (tlc_tte1_clken), |
| 324 | .clk(clk), |
| 325 | .se(se), |
| 326 | .siclk(siclk), |
| 327 | .soclk(soclk), |
| 328 | .pce_ov(pce_ov), |
| 329 | .stop(stop) |
| 330 | ); |
| 331 | |
| 332 | // If a write will happen next cycle, flop the tte tag for write. |
| 333 | // Otherwise, flop the tag that was just used for lookup. |
| 334 | lsu_tld_dp_msff_macro__mux_aope__ports_2__stack_70c__width_52 tte2_lat ( |
| 335 | .scan_in(tte2_lat_scanin), |
| 336 | .scan_out(tte2_lat_scanout), |
| 337 | .din0 ({tte1[54:47],partition_id1[2:0],tte1[42:38],1'b1,1'b0,tte1[34:7],tte1[5:0]}), |
| 338 | .din1 ({tld_tag_pid[2:0],tld_tag_real,12'b0,1'b0,1'b1,7'b0,tgd_tag_c1[12:0],tgd_tag_c0[12:0],1'b0}), |
| 339 | .sel0 (tlc_write_next), |
| 340 | .dout (tte2_lat_out[51:0]), |
| 341 | .clk(clk), |
| 342 | .en(en), |
| 343 | .se(se), |
| 344 | .siclk(siclk), |
| 345 | .soclk(soclk), |
| 346 | .pce_ov(pce_ov), |
| 347 | .stop(stop) |
| 348 | ); |
| 349 | |
| 350 | assign {tte2[54:47],partition_id2[2:0],tte2[42:38],wrdata_sel,wrdata_sel_,tte2[34:7],tte2[5:0]} = tte2_lat_out[51:0]; |
| 351 | assign {access_tag_m[68:56], access_tag_m[12:0]} = tte2_lat_out[26:1]; |
| 352 | assign access_tag_m[55:52] = tte2_lat_out[51:48]; |
| 353 | |
| 354 | assign tld_index_valid = |
| 355 | tte2[54]; |
| 356 | |
| 357 | ///////////////////////////TTE tag/////////////////////////////////////////////// |
| 358 | |
| 359 | assign partition_id1[2:0] = default_tag[55:53]; |
| 360 | |
| 361 | // Now build tag for the two cycles |
| 362 | // Demap with specified context |
| 363 | assign tag_to_demap_d[68:0] = |
| 364 | {tte0 [12:0], // Context |
| 365 | partition_id1 [2:0], // PID |
| 366 | tte1 [34 ], // R |
| 367 | tte0 [47:28], // VA[47:28] |
| 368 | tte0 [27:22], // VA[27:22] |
| 369 | tte0 [21 ], // 27_22_V |
| 370 | tte0 [20 ], // V |
| 371 | tte0 [18:13], // VA[21:16] |
| 372 | tte1 [42 ], // 21_16_V |
| 373 | tte1 [41:39], // VA[15:13] |
| 374 | tte1 [38 ], // 15_13_V |
| 375 | tte0 [12:0]}; // Context[12:00] |
| 376 | |
| 377 | // Write with muxed context |
| 378 | assign tag_to_write[68:0] = |
| 379 | {tte1 [12:0], // Context |
| 380 | partition_id2 [2:0], // PID |
| 381 | tte2 [34 ], // R |
| 382 | tte1 [47:28], // VA[47:28] |
| 383 | tte1 [27:22], // VA[27:22] |
| 384 | tte1 [21 ], // 27_22_V |
| 385 | tte1 [20 ], // V |
| 386 | tte1 [18:13], // VA[21:16] |
| 387 | tte2 [42 ], // 21_16_V |
| 388 | tte2 [41:39], // VA[15:13] |
| 389 | tte2 [38 ], // 15_13_V |
| 390 | tte1 [12:0] // Context[12:00] |
| 391 | }; |
| 392 | |
| 393 | |
| 394 | lsu_tld_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_8 buf_mbi_wdata ( |
| 395 | .din (mbi_wdata[7:0]), |
| 396 | .dout (bist_data_0[7:0]) |
| 397 | ); |
| 398 | |
| 399 | // Page mask and real bits must be zero for bist to avoid masking lower address and context bits. |
| 400 | assign mbist_wdata[69:0] = { bist_data_0[0], // U |
| 401 | bist_data_0[7:0],bist_data_0[7:3], // [68:56] |
| 402 | bist_data_0[4:2], // [55:53] |
| 403 | 1'b0, // [52] |
| 404 | bist_data_0[0],{3{bist_data_0[7:0]}},bist_data_0[7], // [51:26] |
| 405 | 1'b0, // [25] |
| 406 | bist_data_0[6:0], // [24:18] |
| 407 | 1'b0, // [17] |
| 408 | bist_data_0[7:5], // [16:14] |
| 409 | 1'b0, // [13] |
| 410 | bist_data_0[4:0],bist_data_0[7:0]}; // [12:0] |
| 411 | |
| 412 | // Key to CAMBIST match/write data |
| 413 | // [0] = other [4] = Valid |
| 414 | // [1] = PID [5] = Real |
| 415 | // [2] = Context1 [6] = Used |
| 416 | // [3] = Context0 |
| 417 | |
| 418 | lsu_tld_dp_msff_macro__mux_aope__ports_4__stack_70c__width_70 test_data_mux ( |
| 419 | .scan_in(test_data_mux_scanin), |
| 420 | .scan_out(test_data_mux_scanout), |
| 421 | .en (tlc_mbi_run), |
| 422 | .din0 ({13'b0,1'b1,55'b0,1'b1}), |
| 423 | .din1 ({1'b1, |
| 424 | bist_wdata[67:56],1'b0, |
| 425 | bist_wdata[54:26],bist_wdata[23], |
| 426 | 1'b0,1'b1, |
| 427 | bist_wdata[22:18],bist_wdata[16], |
| 428 | 1'b0, |
| 429 | bist_wdata[15:14],bist_wdata[12], |
| 430 | 1'b0, |
| 431 | bist_wdata[11:0],1'b0}), // CAMBIST shift data |
| 432 | .din2 ({bist_data_0[6],{13{bist_data_0[2]}},{3{bist_data_0[1]}},bist_data_0[5], |
| 433 | {26{bist_data_0[0]}},1'b0,bist_data_0[4],{6{bist_data_0[0]}}, |
| 434 | 1'b0,{3{bist_data_0[0]}},1'b0,{13{bist_data_0[3]}}} |
| 435 | ), // CAMBIST match/write data |
| 436 | .din3 (mbist_wdata[69:0]), // MEMBIST data |
| 437 | .sel0 (mbi_init_to_zero), |
| 438 | .sel1 (mbi_cambist_shift), |
| 439 | .sel2 (tld_mbi_cambist_run), |
| 440 | .dout (bist_wdata[69:0]), |
| 441 | .clk(clk), |
| 442 | .se(se), |
| 443 | .siclk(siclk), |
| 444 | .soclk(soclk), |
| 445 | .pce_ov(pce_ov), |
| 446 | .stop(stop) |
| 447 | ); |
| 448 | |
| 449 | // tte_tag pin ordering is, from left of CAM to right of CAM |
| 450 | // Used Valid Context0[12:0] Context1[12:0] Real VA[27:13] VA[47:28] PID[2:0] |
| 451 | |
| 452 | // Valid and context are muxed one way. The context result of this mux will be muxed later |
| 453 | // with the stored context values. This mux sits above the tlb, that mux sits below in |
| 454 | // lsu_tgd_dp. |
| 455 | lsu_tld_dp_mux_macro__mux_aonpe__ports_3__stack_28l__width_28 mx_tag0_d ( |
| 456 | .din0 ({bist_wdata[69], bist_wdata [24],bist_wdata [12:0],bist_wdata [68:56] }), |
| 457 | .din1 ({ 1'b1, tag_to_write [24],tag_to_write [12:0],tag_to_write [68:56] }), |
| 458 | .din2 ({ 1'b1, tag_to_demap_d[24],tag_to_demap_d[12:0],tag_to_demap_d[68:56] }), |
| 459 | .sel0 (tlc_mbi_run ), |
| 460 | .sel1 (tlc_sel_write_tag ), |
| 461 | .sel2 (tlc_sel_dm_tag ), |
| 462 | .dout (tag0[27:0]) |
| 463 | ); |
| 464 | lsu_tld_dp_buff_macro__width_28 tag0_buf ( |
| 465 | .din (tag0[27:0]), |
| 466 | .dout ({tld_ubit, tld_tag_valid,tld_tag_c0 [12:0],tld_tag_c1 [12:0] }) |
| 467 | ); |
| 468 | |
| 469 | // VA/PID/Real bit are muxed differently. I use two levels of muxing to keep |
| 470 | // the delay for the exu address path to a minimum. |
| 471 | lsu_tld_dp_mux_macro__mux_aonpe__ports_3__stack_42l__width_42 mx_tag1_d ( |
| 472 | .din0 ({bist_wdata [52],bist_wdata [31:25],bist_wdata [23:13],bist_wdata [51:32],bist_wdata [55:53] }), |
| 473 | .din1 ({tag_to_write [52],tag_to_write [31:25],tag_to_write [23:13],tag_to_write [51:32],tag_to_write [55:53] }), |
| 474 | .din2 ({tag_to_demap_d[52],tag_to_demap_d[31:25],tag_to_demap_d[23:13],tag_to_demap_d[51:32],tag_to_demap_d[55:53] }), |
| 475 | .sel0 (tlc_mbi_run ), |
| 476 | .sel1 (tlc_sel_write_tag ), |
| 477 | .sel2 (tlc_sel_dm_tag ), |
| 478 | .dout ({tld_tag_0 [52],tld_tag_0 [31:25],tld_tag_0 [23:13],tld_tag_0 [51:32],tld_tag_0 [55:53] }) |
| 479 | ); |
| 480 | |
| 481 | lsu_tld_dp_buff_macro__dbuff_32x__stack_none__width_35 exu_addr_buf ( |
| 482 | .din ({tld_tag_0[51:26],tld_tag_0[23:18],tld_tag_0[16:14]}), |
| 483 | .dout (lsu_exu_address_e[47:13]) |
| 484 | ); |
| 485 | |
| 486 | // R 27_22_V 21_16_V 15_13_V PID |
| 487 | lsu_tld_dp_mux_macro__mux_pgpe__ports_2__stack_42r__width_7 mx_tag2_d ( |
| 488 | .din0 ({tld_tag_0 [52],tld_tag_0 [25],tld_tag_0 [17],tld_tag_0 [13],tld_tag_0 [55:53] }), |
| 489 | .din1 ({default_tag [52],default_tag[25],default_tag[17],default_tag[13],default_tag[55:53] }), |
| 490 | .sel0 (tlc_sel_wr_dm_bist ), |
| 491 | .dout ({tld_tag_real ,tld_tag_mask[2],tld_tag_mask[1],tld_tag_mask[0],tld_tag_pid[2:0] }) |
| 492 | ); |
| 493 | |
| 494 | assign default_unused=default_tag[24]; |
| 495 | |
| 496 | lsu_tld_dp_mux_macro__mux_aope__ports_3__stack_8l__width_7 mx_index ( |
| 497 | .din0 (tld_mbi_addr[6:0] ), |
| 498 | .din1 (tte2[53:47] ), |
| 499 | .din2 (exu_lsu_address_e[9:3] ), |
| 500 | .sel0 (tlc_mbi_run ), |
| 501 | .sel1 (tlc_sel_write_tag ), |
| 502 | .dout (tld_rw_index[6:0] ) |
| 503 | ); |
| 504 | |
| 505 | /////////////////////////////////////////////// |
| 506 | // Parity generation for tte_tag |
| 507 | /////////////////////////////////////////////// |
| 508 | |
| 509 | // Mask the appropriate address/context bits based on page size and RA or VA trans type. |
| 510 | |
| 511 | lsu_tld_dp_inv_macro__width_3 pg_mask_va ( |
| 512 | .din ({tag_to_write[25],tag_to_write[17],tag_to_write[13]}), |
| 513 | .dout ({mask_va_27_22_, mask_va_21_16_, mask_va_15_13_}) |
| 514 | ); |
| 515 | lsu_tld_dp_inv_macro__width_1 pg_mask_ctxt ( |
| 516 | .din (tag_to_write[52]), |
| 517 | .dout (mask_context_) |
| 518 | ); |
| 519 | |
| 520 | lsu_tld_dp_and_macro__ports_2__stack_28l__width_28 mask_tag ( |
| 521 | .din0 ({tag_to_write[31:26], |
| 522 | tag_to_write[23:18], |
| 523 | tag_to_write[16:14], |
| 524 | tag_to_write[12:0]}), |
| 525 | .din1 ({{6{mask_va_27_22_}}, |
| 526 | {6{mask_va_21_16_}}, |
| 527 | {3{mask_va_15_13_}}, |
| 528 | {13{mask_context_}}}), |
| 529 | .dout ({masked_va[27:22], |
| 530 | masked_va[21:16], |
| 531 | masked_va[15:13], |
| 532 | masked_ctxt[12:0]}) |
| 533 | ); |
| 534 | |
| 535 | lsu_tld_dp_mux_macro__left_6__mux_aonpe__ports_2__stack_70c__width_52 parity_mux ( |
| 536 | .din0 ({tag_to_write[55:53], |
| 537 | tag_to_write[52], |
| 538 | tag_to_write[51:32], |
| 539 | masked_va [27:22], |
| 540 | masked_va [21:16], |
| 541 | masked_va [15:13], |
| 542 | masked_ctxt [12:0]}), |
| 543 | .din1 ({access_tag_m[55:53], |
| 544 | access_tag_m[52], |
| 545 | va_m [47:22], |
| 546 | va_m [21:16], |
| 547 | va_m [15:13], |
| 548 | 13'b0}), |
| 549 | .sel0 (wrdata_sel ), |
| 550 | .sel1 (wrdata_sel_ ), |
| 551 | .dout ({tag_for_parity[51:0]}) |
| 552 | ); |
| 553 | |
| 554 | lsu_tld_dp_prty_macro__width_32 tag_pgen0 ( |
| 555 | .din ({tlc_tag_error_inj,1'b0,tag_for_parity[51:28],6'b0}), |
| 556 | .dout (tag_parity_unmasked) |
| 557 | ); |
| 558 | lsu_tld_dp_prty_macro__width_32 tag_pgen1 ( |
| 559 | .din ({2'b0,tag_for_parity[27:0],2'b0}), |
| 560 | .dout (tag_parity_masked) |
| 561 | ); |
| 562 | lsu_tld_dp_inv_macro__width_2 inv_tag_par ( |
| 563 | .din ({tag_parity_unmasked ,tag_parity_masked}), |
| 564 | .dout ({tag_parity_unmasked_,tag_parity_masked_}) |
| 565 | ); |
| 566 | lsu_tld_dp_xor_macro__ports_2__width_1 pgen_tag ( |
| 567 | .din0 (tag_parity_unmasked_), |
| 568 | .din1 (tag_parity_masked_), |
| 569 | .dout (tag_parity) |
| 570 | ); |
| 571 | |
| 572 | // Additional logic needed to complete parity detection. |
| 573 | // tag_parity_unmasked is valid for all page sizes (it's complete for 256m) |
| 574 | // tag_parity_masked represents the addtional parity for 8k pages |
| 575 | |
| 576 | lsu_tld_dp_inv_macro__width_2 pgen_256m ( |
| 577 | .din ({tag_parity_unmasked_,tag_parity_masked_}), |
| 578 | .dout ({prty_256m, prty_8k_lower}) |
| 579 | ); |
| 580 | |
| 581 | lsu_tld_dp_prty_macro__width_8 pgen_va_27_22 ( |
| 582 | .din ({va_m[27:22],2'b00}), |
| 583 | .dout (prty_va_27_22) |
| 584 | ); |
| 585 | lsu_tld_dp_xor_macro__ports_2__width_1 pgen_4m ( |
| 586 | .din0 (prty_256m), |
| 587 | .din1 (prty_va_27_22), |
| 588 | .dout (prty_4m) |
| 589 | ); |
| 590 | |
| 591 | lsu_tld_dp_prty_macro__width_16 pgen_va_27_16 ( |
| 592 | .din ({va_m[27:22],4'b0000,va_m[21:16]}), |
| 593 | .dout (prty_va_27_16) |
| 594 | ); |
| 595 | lsu_tld_dp_xor_macro__ports_2__width_1 pgen_64k ( |
| 596 | .din0 (prty_256m), |
| 597 | .din1 (prty_va_27_16), |
| 598 | .dout (prty_64k) |
| 599 | ); |
| 600 | |
| 601 | lsu_tld_dp_xor_macro__ports_2__width_1 pgen_8k ( |
| 602 | .din0 (prty_256m), |
| 603 | .din1 (prty_8k_lower), |
| 604 | .dout (prty_8k) |
| 605 | ); |
| 606 | |
| 607 | lsu_tld_dp_prty_macro__width_16 pgen_ctxt0 ( |
| 608 | .din ({access_tag_m[12:0],3'b000}), |
| 609 | .dout (prty_ctxt0) |
| 610 | ); |
| 611 | lsu_tld_dp_prty_macro__width_16 pgen_ctxt1 ( |
| 612 | .din ({3'b000,access_tag_m[68:56]}), |
| 613 | .dout (prty_ctxt1) |
| 614 | ); |
| 615 | |
| 616 | lsu_tld_dp_buff_macro__width_6 prty_buf ( |
| 617 | .din ({ prty_256m, prty_4m, prty_64k, prty_8k, prty_ctxt1, prty_ctxt0}), |
| 618 | .dout ({tld_prty_256m,tld_prty_4m,tld_prty_64k,tld_prty_8k,tld_prty_ctxt1,tld_prty_ctxt0}) |
| 619 | ); |
| 620 | |
| 621 | ///////////////////////////TTE data//////////////////////////////////////////// |
| 622 | |
| 623 | // Data is only needed for write, so only need a mux for bist |
| 624 | |
| 625 | assign wr_data[36:0] = |
| 626 | {data_parity , // Data Parity |
| 627 | tte2 [33:22], // PA[39:28] |
| 628 | tte2 [21:16], // PA[27:22] |
| 629 | tte1 [21 ], // 27_22_V, PS_EQ_256M |
| 630 | tte2 [15:10], // PA[21:16] |
| 631 | tte2 [42 ], // 21_16_V, PS_GT_64K |
| 632 | tte2 [9:7], // PA[15:13] |
| 633 | tte2 [38 ], // 15_13_V, PS_GT_8K |
| 634 | tte2 [5:0] // NFO, IE, CP, E, P, W |
| 635 | }; |
| 636 | |
| 637 | lsu_tld_dp_mux_macro__mux_aope__ports_3__stack_20r__width_19 mx_data_odd ( |
| 638 | .din0 ({16'b0,tld_mbi_addr[5],tld_mbi_addr[3],tld_mbi_addr[1]}), |
| 639 | .din1 ({bist_data_1[5],bist_data_1[3],bist_data_1[1],{4{bist_data_1[7],bist_data_1[5],bist_data_1[3],bist_data_1[1]}}}), |
| 640 | .din2 ({ tag_parity ,wr_data[35],wr_data[33],wr_data[31], |
| 641 | wr_data[29],wr_data[27],wr_data[25],wr_data[23],wr_data[21], |
| 642 | wr_data[19],wr_data[17],wr_data[15],wr_data[13],wr_data[11], |
| 643 | wr_data[9],wr_data[7],wr_data[5],wr_data[3],wr_data[1]}), |
| 644 | .sel0 (tld_mbi_cambist_run), |
| 645 | .sel1 (tlc_mbi_run), |
| 646 | .dout ({ tld_data[37],tld_data[35],tld_data[33],tld_data[31], |
| 647 | tld_data[29],tld_data[27],tld_data[25],tld_data[23],tld_data[21], |
| 648 | tld_data[19],tld_data[17],tld_data[15],tld_data[13],tld_data[11], |
| 649 | tld_data[9],tld_data[7],tld_data[5],tld_data[3],tld_data[1]}) |
| 650 | ); |
| 651 | lsu_tld_dp_mux_macro__mux_aope__ports_3__stack_20r__width_19 mx_data_even ( |
| 652 | .din0 ({15'b0,tld_mbi_addr[6],tld_mbi_addr[4],tld_mbi_addr[2],tld_mbi_addr[0]}), |
| 653 | .din1 ({bist_data_1[4],bist_data_1[2],bist_data_1[0],{4{bist_data_1[6],bist_data_1[4],bist_data_1[2],bist_data_1[0]}}}), |
| 654 | .din2 ({ wr_data[36],wr_data[34],wr_data[32],wr_data[30], |
| 655 | wr_data[28],wr_data[26],wr_data[24],wr_data[22],wr_data[20], |
| 656 | wr_data[18],wr_data[16],wr_data[14],wr_data[12],wr_data[10], |
| 657 | wr_data[8],wr_data[6],wr_data[4],wr_data[2],wr_data[0]}), |
| 658 | .sel0 (tld_mbi_cambist_run), |
| 659 | .sel1 (tlc_mbi_run), |
| 660 | .dout ({ tld_data[36],tld_data[34],tld_data[32],tld_data[30], |
| 661 | tld_data[28],tld_data[26],tld_data[24],tld_data[22],tld_data[20], |
| 662 | tld_data[18],tld_data[16],tld_data[14],tld_data[12],tld_data[10], |
| 663 | tld_data[8],tld_data[6],tld_data[4],tld_data[2],tld_data[0]}) |
| 664 | ); |
| 665 | |
| 666 | lsu_tld_dp_prty_macro__width_16 dprty0 ( |
| 667 | .din ({tlc_data_error_inj,wr_data[10],wr_data[7:6],1'b0,wr_data[35:25]}), |
| 668 | .dout (data_parity_0) |
| 669 | ); |
| 670 | lsu_tld_dp_prty_macro__width_16 dprty1 ( |
| 671 | .din ({wr_data[24],wr_data[17],wr_data[23:18],wr_data[16:11],wr_data[9:8]}), |
| 672 | .dout (data_parity_1) |
| 673 | ); |
| 674 | lsu_tld_dp_prty_macro__width_8 dprty2 ( |
| 675 | .din ({wr_data[5:0],data_parity_0,data_parity_1}), |
| 676 | .dout (data_parity) |
| 677 | ); |
| 678 | |
| 679 | assign tld_demap_control0[2:0] = |
| 680 | tte0[45:43]; |
| 681 | assign tld_demap_control1[3:0] = |
| 682 | tte1[46:43]; |
| 683 | |
| 684 | |
| 685 | |
| 686 | //////////////////////////////////////////////////////////////////// |
| 687 | // VA staging from E to M - it's located here for floorplan reasons |
| 688 | lsu_tld_dp_msff_macro__stack_48c__width_48 va_m_lat ( |
| 689 | .scan_in(va_m_lat_scanin), |
| 690 | .scan_out(va_m_lat_scanout), |
| 691 | .se (tcu_se_scancollar_in), |
| 692 | .din (exu_lsu_address_e[47:0]), |
| 693 | .dout (va_m[47:0]), |
| 694 | .clk(clk), |
| 695 | .en(en), |
| 696 | .siclk(siclk), |
| 697 | .soclk(soclk), |
| 698 | .pce_ov(pce_ov), |
| 699 | .stop(stop) |
| 700 | ); |
| 701 | lsu_tld_dp_zero_macro__width_32 va_m_zdt ( |
| 702 | .din (va_m[47:16]), |
| 703 | .dout (tld_va_m_eq_zero) |
| 704 | ); |
| 705 | |
| 706 | lsu_tld_dp_buff_macro__rep_1__stack_48c__width_48 lsu_va_m_buf ( |
| 707 | .din (va_m[47:0]), |
| 708 | .dout (lsu_va_m[47:0]) |
| 709 | ); |
| 710 | lsu_tld_dp_buff_macro__rep_1__stack_48c__width_48 lsu_mmu_va_m_buf ( |
| 711 | .din (va_m[47:0]), |
| 712 | .dout (lsu_mmu_va_m[47:0]) |
| 713 | ); |
| 714 | |
| 715 | lsu_tld_dp_msff_macro__stack_22r__width_22 bist_lat ( |
| 716 | .scan_in(bist_lat_scanin), |
| 717 | .scan_out(bist_lat_scanout), |
| 718 | .en (tlc_mbi_run), |
| 719 | .din ({bist_data_0[7:0], mbi_addr[6:0], mbi_dtb_write_en, mbi_cambist_run, |
| 720 | mbi_repl_write, mbi_dis_clr_ubit, |
| 721 | mbi_dtb_demap_en, mbi_demap_type[1:0]}), |
| 722 | .dout ({bist_data_1[7:0], tld_mbi_addr[6:0], tld_mbi_dtb_write_en, tld_mbi_cambist_run, |
| 723 | tld_mbi_repl_write, tld_mbi_dis_clr_ubit, |
| 724 | tld_mbi_dtb_demap_en,tld_mbi_demap_type[1:0]}), |
| 725 | .clk(clk), |
| 726 | .se(se), |
| 727 | .siclk(siclk), |
| 728 | .soclk(soclk), |
| 729 | .pce_ov(pce_ov), |
| 730 | .stop(stop) |
| 731 | ); |
| 732 | |
| 733 | // fixscan start: |
| 734 | assign tte0_lat_scanin = scan_in ; |
| 735 | assign tte1_lat_scanin = tte0_lat_scanout ; |
| 736 | assign tte2_lat_scanin = tte1_lat_scanout ; |
| 737 | assign test_data_mux_scanin = tte2_lat_scanout ; |
| 738 | assign va_m_lat_scanin = test_data_mux_scanout ; |
| 739 | assign bist_lat_scanin = va_m_lat_scanout ; |
| 740 | assign scan_out = bist_lat_scanout ; |
| 741 | // fixscan end: |
| 742 | endmodule |
| 743 | |
| 744 | |
| 745 | // |
| 746 | // buff macro |
| 747 | // |
| 748 | // |
| 749 | |
| 750 | |
| 751 | |
| 752 | |
| 753 | |
| 754 | module lsu_tld_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 ( |
| 755 | din, |
| 756 | dout); |
| 757 | input [3:0] din; |
| 758 | output [3:0] dout; |
| 759 | |
| 760 | |
| 761 | |
| 762 | |
| 763 | |
| 764 | |
| 765 | buff #(4) d0_0 ( |
| 766 | .in(din[3:0]), |
| 767 | .out(dout[3:0]) |
| 768 | ); |
| 769 | |
| 770 | |
| 771 | |
| 772 | |
| 773 | |
| 774 | |
| 775 | |
| 776 | |
| 777 | endmodule |
| 778 | |
| 779 | |
| 780 | |
| 781 | |
| 782 | |
| 783 | |
| 784 | |
| 785 | |
| 786 | |
| 787 | // any PARAMS parms go into naming of macro |
| 788 | |
| 789 | module lsu_tld_dp_msff_macro__stack_70c__width_55 ( |
| 790 | din, |
| 791 | clk, |
| 792 | en, |
| 793 | se, |
| 794 | scan_in, |
| 795 | siclk, |
| 796 | soclk, |
| 797 | pce_ov, |
| 798 | stop, |
| 799 | dout, |
| 800 | scan_out); |
| 801 | wire l1clk; |
| 802 | wire siclk_out; |
| 803 | wire soclk_out; |
| 804 | wire [53:0] so; |
| 805 | |
| 806 | input [54:0] din; |
| 807 | |
| 808 | |
| 809 | input clk; |
| 810 | input en; |
| 811 | input se; |
| 812 | input scan_in; |
| 813 | input siclk; |
| 814 | input soclk; |
| 815 | input pce_ov; |
| 816 | input stop; |
| 817 | |
| 818 | |
| 819 | |
| 820 | output [54:0] dout; |
| 821 | |
| 822 | |
| 823 | output scan_out; |
| 824 | |
| 825 | |
| 826 | |
| 827 | |
| 828 | cl_dp1_l1hdr_8x c0_0 ( |
| 829 | .l2clk(clk), |
| 830 | .pce(en), |
| 831 | .aclk(siclk), |
| 832 | .bclk(soclk), |
| 833 | .l1clk(l1clk), |
| 834 | .se(se), |
| 835 | .pce_ov(pce_ov), |
| 836 | .stop(stop), |
| 837 | .siclk_out(siclk_out), |
| 838 | .soclk_out(soclk_out) |
| 839 | ); |
| 840 | dff #(55) d0_0 ( |
| 841 | .l1clk(l1clk), |
| 842 | .siclk(siclk_out), |
| 843 | .soclk(soclk_out), |
| 844 | .d(din[54:0]), |
| 845 | .si({scan_in,so[53:0]}), |
| 846 | .so({so[53:0],scan_out}), |
| 847 | .q(dout[54:0]) |
| 848 | ); |
| 849 | |
| 850 | |
| 851 | |
| 852 | |
| 853 | |
| 854 | |
| 855 | |
| 856 | |
| 857 | |
| 858 | |
| 859 | |
| 860 | |
| 861 | |
| 862 | |
| 863 | |
| 864 | |
| 865 | |
| 866 | |
| 867 | |
| 868 | |
| 869 | endmodule |
| 870 | |
| 871 | |
| 872 | |
| 873 | |
| 874 | |
| 875 | |
| 876 | |
| 877 | |
| 878 | |
| 879 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 880 | // also for pass-gate with decoder |
| 881 | |
| 882 | |
| 883 | |
| 884 | |
| 885 | |
| 886 | // any PARAMS parms go into naming of macro |
| 887 | |
| 888 | module lsu_tld_dp_mux_macro__mux_aope__ports_2__stack_70c__width_13 ( |
| 889 | din0, |
| 890 | din1, |
| 891 | sel0, |
| 892 | dout); |
| 893 | wire psel0; |
| 894 | wire psel1; |
| 895 | |
| 896 | input [12:0] din0; |
| 897 | input [12:0] din1; |
| 898 | input sel0; |
| 899 | output [12:0] dout; |
| 900 | |
| 901 | |
| 902 | |
| 903 | |
| 904 | |
| 905 | cl_dp1_penc2_8x c0_0 ( |
| 906 | .sel0(sel0), |
| 907 | .psel0(psel0), |
| 908 | .psel1(psel1) |
| 909 | ); |
| 910 | |
| 911 | mux2s #(13) d0_0 ( |
| 912 | .sel0(psel0), |
| 913 | .sel1(psel1), |
| 914 | .in0(din0[12:0]), |
| 915 | .in1(din1[12:0]), |
| 916 | .dout(dout[12:0]) |
| 917 | ); |
| 918 | |
| 919 | |
| 920 | |
| 921 | |
| 922 | |
| 923 | |
| 924 | |
| 925 | |
| 926 | |
| 927 | |
| 928 | |
| 929 | |
| 930 | |
| 931 | endmodule |
| 932 | |
| 933 | |
| 934 | |
| 935 | |
| 936 | |
| 937 | |
| 938 | // any PARAMS parms go into naming of macro |
| 939 | |
| 940 | module lsu_tld_dp_msff_macro__mux_aope__ports_2__stack_70c__width_52 ( |
| 941 | din0, |
| 942 | din1, |
| 943 | sel0, |
| 944 | clk, |
| 945 | en, |
| 946 | se, |
| 947 | scan_in, |
| 948 | siclk, |
| 949 | soclk, |
| 950 | pce_ov, |
| 951 | stop, |
| 952 | dout, |
| 953 | scan_out); |
| 954 | wire psel0; |
| 955 | wire psel1; |
| 956 | wire [51:0] muxout; |
| 957 | wire l1clk; |
| 958 | wire siclk_out; |
| 959 | wire soclk_out; |
| 960 | wire [50:0] so; |
| 961 | |
| 962 | input [51:0] din0; |
| 963 | input [51:0] din1; |
| 964 | input sel0; |
| 965 | |
| 966 | |
| 967 | input clk; |
| 968 | input en; |
| 969 | input se; |
| 970 | input scan_in; |
| 971 | input siclk; |
| 972 | input soclk; |
| 973 | input pce_ov; |
| 974 | input stop; |
| 975 | |
| 976 | |
| 977 | |
| 978 | output [51:0] dout; |
| 979 | |
| 980 | |
| 981 | output scan_out; |
| 982 | |
| 983 | |
| 984 | |
| 985 | |
| 986 | cl_dp1_penc2_8x c1_0 ( |
| 987 | .sel0(sel0), |
| 988 | .psel0(psel0), |
| 989 | .psel1(psel1) |
| 990 | ); |
| 991 | |
| 992 | mux2s #(52) d1_0 ( |
| 993 | .sel0(psel0), |
| 994 | .sel1(psel1), |
| 995 | .in0(din0[51:0]), |
| 996 | .in1(din1[51:0]), |
| 997 | .dout(muxout[51:0]) |
| 998 | ); |
| 999 | cl_dp1_l1hdr_8x c0_0 ( |
| 1000 | .l2clk(clk), |
| 1001 | .pce(en), |
| 1002 | .aclk(siclk), |
| 1003 | .bclk(soclk), |
| 1004 | .l1clk(l1clk), |
| 1005 | .se(se), |
| 1006 | .pce_ov(pce_ov), |
| 1007 | .stop(stop), |
| 1008 | .siclk_out(siclk_out), |
| 1009 | .soclk_out(soclk_out) |
| 1010 | ); |
| 1011 | dff #(52) d0_0 ( |
| 1012 | .l1clk(l1clk), |
| 1013 | .siclk(siclk_out), |
| 1014 | .soclk(soclk_out), |
| 1015 | .d(muxout[51:0]), |
| 1016 | .si({scan_in,so[50:0]}), |
| 1017 | .so({so[50:0],scan_out}), |
| 1018 | .q(dout[51:0]) |
| 1019 | ); |
| 1020 | |
| 1021 | |
| 1022 | |
| 1023 | |
| 1024 | |
| 1025 | |
| 1026 | |
| 1027 | |
| 1028 | |
| 1029 | |
| 1030 | |
| 1031 | |
| 1032 | |
| 1033 | |
| 1034 | |
| 1035 | |
| 1036 | |
| 1037 | |
| 1038 | |
| 1039 | |
| 1040 | endmodule |
| 1041 | |
| 1042 | |
| 1043 | |
| 1044 | |
| 1045 | |
| 1046 | |
| 1047 | |
| 1048 | |
| 1049 | |
| 1050 | // |
| 1051 | // buff macro |
| 1052 | // |
| 1053 | // |
| 1054 | |
| 1055 | |
| 1056 | |
| 1057 | |
| 1058 | |
| 1059 | module lsu_tld_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_8 ( |
| 1060 | din, |
| 1061 | dout); |
| 1062 | input [7:0] din; |
| 1063 | output [7:0] dout; |
| 1064 | |
| 1065 | |
| 1066 | |
| 1067 | |
| 1068 | |
| 1069 | |
| 1070 | buff #(8) d0_0 ( |
| 1071 | .in(din[7:0]), |
| 1072 | .out(dout[7:0]) |
| 1073 | ); |
| 1074 | |
| 1075 | |
| 1076 | |
| 1077 | |
| 1078 | |
| 1079 | |
| 1080 | |
| 1081 | |
| 1082 | endmodule |
| 1083 | |
| 1084 | |
| 1085 | |
| 1086 | |
| 1087 | |
| 1088 | |
| 1089 | |
| 1090 | |
| 1091 | |
| 1092 | // any PARAMS parms go into naming of macro |
| 1093 | |
| 1094 | module lsu_tld_dp_msff_macro__mux_aope__ports_4__stack_70c__width_70 ( |
| 1095 | din0, |
| 1096 | din1, |
| 1097 | din2, |
| 1098 | din3, |
| 1099 | sel0, |
| 1100 | sel1, |
| 1101 | sel2, |
| 1102 | clk, |
| 1103 | en, |
| 1104 | se, |
| 1105 | scan_in, |
| 1106 | siclk, |
| 1107 | soclk, |
| 1108 | pce_ov, |
| 1109 | stop, |
| 1110 | dout, |
| 1111 | scan_out); |
| 1112 | wire psel0; |
| 1113 | wire psel1; |
| 1114 | wire psel2; |
| 1115 | wire psel3; |
| 1116 | wire [69:0] muxout; |
| 1117 | wire l1clk; |
| 1118 | wire siclk_out; |
| 1119 | wire soclk_out; |
| 1120 | wire [68:0] so; |
| 1121 | |
| 1122 | input [69:0] din0; |
| 1123 | input [69:0] din1; |
| 1124 | input [69:0] din2; |
| 1125 | input [69:0] din3; |
| 1126 | input sel0; |
| 1127 | input sel1; |
| 1128 | input sel2; |
| 1129 | |
| 1130 | |
| 1131 | input clk; |
| 1132 | input en; |
| 1133 | input se; |
| 1134 | input scan_in; |
| 1135 | input siclk; |
| 1136 | input soclk; |
| 1137 | input pce_ov; |
| 1138 | input stop; |
| 1139 | |
| 1140 | |
| 1141 | |
| 1142 | output [69:0] dout; |
| 1143 | |
| 1144 | |
| 1145 | output scan_out; |
| 1146 | |
| 1147 | |
| 1148 | |
| 1149 | |
| 1150 | cl_dp1_penc4_8x c1_0 ( |
| 1151 | .test(1'b1), |
| 1152 | .sel0(sel0), |
| 1153 | .sel1(sel1), |
| 1154 | .sel2(sel2), |
| 1155 | .psel0(psel0), |
| 1156 | .psel1(psel1), |
| 1157 | .psel2(psel2), |
| 1158 | .psel3(psel3) |
| 1159 | ); |
| 1160 | |
| 1161 | mux4s #(70) d1_0 ( |
| 1162 | .sel0(psel0), |
| 1163 | .sel1(psel1), |
| 1164 | .sel2(psel2), |
| 1165 | .sel3(psel3), |
| 1166 | .in0(din0[69:0]), |
| 1167 | .in1(din1[69:0]), |
| 1168 | .in2(din2[69:0]), |
| 1169 | .in3(din3[69:0]), |
| 1170 | .dout(muxout[69:0]) |
| 1171 | ); |
| 1172 | cl_dp1_l1hdr_8x c0_0 ( |
| 1173 | .l2clk(clk), |
| 1174 | .pce(en), |
| 1175 | .aclk(siclk), |
| 1176 | .bclk(soclk), |
| 1177 | .l1clk(l1clk), |
| 1178 | .se(se), |
| 1179 | .pce_ov(pce_ov), |
| 1180 | .stop(stop), |
| 1181 | .siclk_out(siclk_out), |
| 1182 | .soclk_out(soclk_out) |
| 1183 | ); |
| 1184 | dff #(70) d0_0 ( |
| 1185 | .l1clk(l1clk), |
| 1186 | .siclk(siclk_out), |
| 1187 | .soclk(soclk_out), |
| 1188 | .d(muxout[69:0]), |
| 1189 | .si({scan_in,so[68:0]}), |
| 1190 | .so({so[68:0],scan_out}), |
| 1191 | .q(dout[69:0]) |
| 1192 | ); |
| 1193 | |
| 1194 | |
| 1195 | |
| 1196 | |
| 1197 | |
| 1198 | |
| 1199 | |
| 1200 | |
| 1201 | |
| 1202 | |
| 1203 | |
| 1204 | |
| 1205 | |
| 1206 | |
| 1207 | |
| 1208 | |
| 1209 | |
| 1210 | |
| 1211 | |
| 1212 | |
| 1213 | endmodule |
| 1214 | |
| 1215 | |
| 1216 | |
| 1217 | |
| 1218 | |
| 1219 | |
| 1220 | |
| 1221 | |
| 1222 | |
| 1223 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1224 | // also for pass-gate with decoder |
| 1225 | |
| 1226 | |
| 1227 | |
| 1228 | |
| 1229 | |
| 1230 | // any PARAMS parms go into naming of macro |
| 1231 | |
| 1232 | module lsu_tld_dp_mux_macro__mux_aonpe__ports_3__stack_28l__width_28 ( |
| 1233 | din0, |
| 1234 | sel0, |
| 1235 | din1, |
| 1236 | sel1, |
| 1237 | din2, |
| 1238 | sel2, |
| 1239 | dout); |
| 1240 | wire buffout0; |
| 1241 | wire buffout1; |
| 1242 | wire buffout2; |
| 1243 | |
| 1244 | input [27:0] din0; |
| 1245 | input sel0; |
| 1246 | input [27:0] din1; |
| 1247 | input sel1; |
| 1248 | input [27:0] din2; |
| 1249 | input sel2; |
| 1250 | output [27:0] dout; |
| 1251 | |
| 1252 | |
| 1253 | |
| 1254 | |
| 1255 | |
| 1256 | cl_dp1_muxbuff3_8x c0_0 ( |
| 1257 | .in0(sel0), |
| 1258 | .in1(sel1), |
| 1259 | .in2(sel2), |
| 1260 | .out0(buffout0), |
| 1261 | .out1(buffout1), |
| 1262 | .out2(buffout2) |
| 1263 | ); |
| 1264 | mux3s #(28) d0_0 ( |
| 1265 | .sel0(buffout0), |
| 1266 | .sel1(buffout1), |
| 1267 | .sel2(buffout2), |
| 1268 | .in0(din0[27:0]), |
| 1269 | .in1(din1[27:0]), |
| 1270 | .in2(din2[27:0]), |
| 1271 | .dout(dout[27:0]) |
| 1272 | ); |
| 1273 | |
| 1274 | |
| 1275 | |
| 1276 | |
| 1277 | |
| 1278 | |
| 1279 | |
| 1280 | |
| 1281 | |
| 1282 | |
| 1283 | |
| 1284 | |
| 1285 | |
| 1286 | endmodule |
| 1287 | |
| 1288 | |
| 1289 | // |
| 1290 | // buff macro |
| 1291 | // |
| 1292 | // |
| 1293 | |
| 1294 | |
| 1295 | |
| 1296 | |
| 1297 | |
| 1298 | module lsu_tld_dp_buff_macro__width_28 ( |
| 1299 | din, |
| 1300 | dout); |
| 1301 | input [27:0] din; |
| 1302 | output [27:0] dout; |
| 1303 | |
| 1304 | |
| 1305 | |
| 1306 | |
| 1307 | |
| 1308 | |
| 1309 | buff #(28) d0_0 ( |
| 1310 | .in(din[27:0]), |
| 1311 | .out(dout[27:0]) |
| 1312 | ); |
| 1313 | |
| 1314 | |
| 1315 | |
| 1316 | |
| 1317 | |
| 1318 | |
| 1319 | |
| 1320 | |
| 1321 | endmodule |
| 1322 | |
| 1323 | |
| 1324 | |
| 1325 | |
| 1326 | |
| 1327 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1328 | // also for pass-gate with decoder |
| 1329 | |
| 1330 | |
| 1331 | |
| 1332 | |
| 1333 | |
| 1334 | // any PARAMS parms go into naming of macro |
| 1335 | |
| 1336 | module lsu_tld_dp_mux_macro__mux_aonpe__ports_3__stack_42l__width_42 ( |
| 1337 | din0, |
| 1338 | sel0, |
| 1339 | din1, |
| 1340 | sel1, |
| 1341 | din2, |
| 1342 | sel2, |
| 1343 | dout); |
| 1344 | wire buffout0; |
| 1345 | wire buffout1; |
| 1346 | wire buffout2; |
| 1347 | |
| 1348 | input [41:0] din0; |
| 1349 | input sel0; |
| 1350 | input [41:0] din1; |
| 1351 | input sel1; |
| 1352 | input [41:0] din2; |
| 1353 | input sel2; |
| 1354 | output [41:0] dout; |
| 1355 | |
| 1356 | |
| 1357 | |
| 1358 | |
| 1359 | |
| 1360 | cl_dp1_muxbuff3_8x c0_0 ( |
| 1361 | .in0(sel0), |
| 1362 | .in1(sel1), |
| 1363 | .in2(sel2), |
| 1364 | .out0(buffout0), |
| 1365 | .out1(buffout1), |
| 1366 | .out2(buffout2) |
| 1367 | ); |
| 1368 | mux3s #(42) d0_0 ( |
| 1369 | .sel0(buffout0), |
| 1370 | .sel1(buffout1), |
| 1371 | .sel2(buffout2), |
| 1372 | .in0(din0[41:0]), |
| 1373 | .in1(din1[41:0]), |
| 1374 | .in2(din2[41:0]), |
| 1375 | .dout(dout[41:0]) |
| 1376 | ); |
| 1377 | |
| 1378 | |
| 1379 | |
| 1380 | |
| 1381 | |
| 1382 | |
| 1383 | |
| 1384 | |
| 1385 | |
| 1386 | |
| 1387 | |
| 1388 | |
| 1389 | |
| 1390 | endmodule |
| 1391 | |
| 1392 | |
| 1393 | // |
| 1394 | // buff macro |
| 1395 | // |
| 1396 | // |
| 1397 | |
| 1398 | |
| 1399 | |
| 1400 | |
| 1401 | |
| 1402 | module lsu_tld_dp_buff_macro__dbuff_32x__stack_none__width_35 ( |
| 1403 | din, |
| 1404 | dout); |
| 1405 | input [34:0] din; |
| 1406 | output [34:0] dout; |
| 1407 | |
| 1408 | |
| 1409 | |
| 1410 | |
| 1411 | |
| 1412 | |
| 1413 | buff #(35) d0_0 ( |
| 1414 | .in(din[34:0]), |
| 1415 | .out(dout[34:0]) |
| 1416 | ); |
| 1417 | |
| 1418 | |
| 1419 | |
| 1420 | |
| 1421 | |
| 1422 | |
| 1423 | |
| 1424 | |
| 1425 | endmodule |
| 1426 | |
| 1427 | |
| 1428 | |
| 1429 | |
| 1430 | |
| 1431 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1432 | // also for pass-gate with decoder |
| 1433 | |
| 1434 | |
| 1435 | |
| 1436 | |
| 1437 | |
| 1438 | // any PARAMS parms go into naming of macro |
| 1439 | |
| 1440 | module lsu_tld_dp_mux_macro__mux_pgpe__ports_2__stack_42r__width_7 ( |
| 1441 | din0, |
| 1442 | din1, |
| 1443 | sel0, |
| 1444 | dout); |
| 1445 | wire psel0_unused; |
| 1446 | wire psel1; |
| 1447 | |
| 1448 | input [6:0] din0; |
| 1449 | input [6:0] din1; |
| 1450 | input sel0; |
| 1451 | output [6:0] dout; |
| 1452 | |
| 1453 | |
| 1454 | |
| 1455 | |
| 1456 | |
| 1457 | cl_dp1_penc2_8x c0_0 ( |
| 1458 | .sel0(sel0), |
| 1459 | .psel0(psel0_unused), |
| 1460 | .psel1(psel1) |
| 1461 | ); |
| 1462 | |
| 1463 | mux2e #(7) d0_0 ( |
| 1464 | .sel(psel1), |
| 1465 | .in0(din0[6:0]), |
| 1466 | .in1(din1[6:0]), |
| 1467 | .dout(dout[6:0]) |
| 1468 | ); |
| 1469 | |
| 1470 | |
| 1471 | |
| 1472 | |
| 1473 | |
| 1474 | |
| 1475 | |
| 1476 | |
| 1477 | |
| 1478 | |
| 1479 | |
| 1480 | |
| 1481 | |
| 1482 | endmodule |
| 1483 | |
| 1484 | |
| 1485 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1486 | // also for pass-gate with decoder |
| 1487 | |
| 1488 | |
| 1489 | |
| 1490 | |
| 1491 | |
| 1492 | // any PARAMS parms go into naming of macro |
| 1493 | |
| 1494 | module lsu_tld_dp_mux_macro__mux_aope__ports_3__stack_8l__width_7 ( |
| 1495 | din0, |
| 1496 | din1, |
| 1497 | din2, |
| 1498 | sel0, |
| 1499 | sel1, |
| 1500 | dout); |
| 1501 | wire psel0; |
| 1502 | wire psel1; |
| 1503 | wire psel2; |
| 1504 | |
| 1505 | input [6:0] din0; |
| 1506 | input [6:0] din1; |
| 1507 | input [6:0] din2; |
| 1508 | input sel0; |
| 1509 | input sel1; |
| 1510 | output [6:0] dout; |
| 1511 | |
| 1512 | |
| 1513 | |
| 1514 | |
| 1515 | |
| 1516 | cl_dp1_penc3_8x c0_0 ( |
| 1517 | .test(1'b1), |
| 1518 | .sel0(sel0), |
| 1519 | .sel1(sel1), |
| 1520 | .psel0(psel0), |
| 1521 | .psel1(psel1), |
| 1522 | .psel2(psel2) |
| 1523 | ); |
| 1524 | |
| 1525 | mux3s #(7) d0_0 ( |
| 1526 | .sel0(psel0), |
| 1527 | .sel1(psel1), |
| 1528 | .sel2(psel2), |
| 1529 | .in0(din0[6:0]), |
| 1530 | .in1(din1[6:0]), |
| 1531 | .in2(din2[6:0]), |
| 1532 | .dout(dout[6:0]) |
| 1533 | ); |
| 1534 | |
| 1535 | |
| 1536 | |
| 1537 | |
| 1538 | |
| 1539 | |
| 1540 | |
| 1541 | |
| 1542 | |
| 1543 | |
| 1544 | |
| 1545 | |
| 1546 | |
| 1547 | endmodule |
| 1548 | |
| 1549 | |
| 1550 | // |
| 1551 | // invert macro |
| 1552 | // |
| 1553 | // |
| 1554 | |
| 1555 | |
| 1556 | |
| 1557 | |
| 1558 | |
| 1559 | module lsu_tld_dp_inv_macro__width_3 ( |
| 1560 | din, |
| 1561 | dout); |
| 1562 | input [2:0] din; |
| 1563 | output [2:0] dout; |
| 1564 | |
| 1565 | |
| 1566 | |
| 1567 | |
| 1568 | |
| 1569 | |
| 1570 | inv #(3) d0_0 ( |
| 1571 | .in(din[2:0]), |
| 1572 | .out(dout[2:0]) |
| 1573 | ); |
| 1574 | |
| 1575 | |
| 1576 | |
| 1577 | |
| 1578 | |
| 1579 | |
| 1580 | |
| 1581 | |
| 1582 | |
| 1583 | endmodule |
| 1584 | |
| 1585 | |
| 1586 | |
| 1587 | |
| 1588 | |
| 1589 | // |
| 1590 | // invert macro |
| 1591 | // |
| 1592 | // |
| 1593 | |
| 1594 | |
| 1595 | |
| 1596 | |
| 1597 | |
| 1598 | module lsu_tld_dp_inv_macro__width_1 ( |
| 1599 | din, |
| 1600 | dout); |
| 1601 | input [0:0] din; |
| 1602 | output [0:0] dout; |
| 1603 | |
| 1604 | |
| 1605 | |
| 1606 | |
| 1607 | |
| 1608 | |
| 1609 | inv #(1) d0_0 ( |
| 1610 | .in(din[0:0]), |
| 1611 | .out(dout[0:0]) |
| 1612 | ); |
| 1613 | |
| 1614 | |
| 1615 | |
| 1616 | |
| 1617 | |
| 1618 | |
| 1619 | |
| 1620 | |
| 1621 | |
| 1622 | endmodule |
| 1623 | |
| 1624 | |
| 1625 | |
| 1626 | |
| 1627 | |
| 1628 | // |
| 1629 | // and macro for ports = 2,3,4 |
| 1630 | // |
| 1631 | // |
| 1632 | |
| 1633 | |
| 1634 | |
| 1635 | |
| 1636 | |
| 1637 | module lsu_tld_dp_and_macro__ports_2__stack_28l__width_28 ( |
| 1638 | din0, |
| 1639 | din1, |
| 1640 | dout); |
| 1641 | input [27:0] din0; |
| 1642 | input [27:0] din1; |
| 1643 | output [27:0] dout; |
| 1644 | |
| 1645 | |
| 1646 | |
| 1647 | |
| 1648 | |
| 1649 | |
| 1650 | and2 #(28) d0_0 ( |
| 1651 | .in0(din0[27:0]), |
| 1652 | .in1(din1[27:0]), |
| 1653 | .out(dout[27:0]) |
| 1654 | ); |
| 1655 | |
| 1656 | |
| 1657 | |
| 1658 | |
| 1659 | |
| 1660 | |
| 1661 | |
| 1662 | |
| 1663 | |
| 1664 | endmodule |
| 1665 | |
| 1666 | |
| 1667 | |
| 1668 | |
| 1669 | |
| 1670 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1671 | // also for pass-gate with decoder |
| 1672 | |
| 1673 | |
| 1674 | |
| 1675 | |
| 1676 | |
| 1677 | // any PARAMS parms go into naming of macro |
| 1678 | |
| 1679 | module lsu_tld_dp_mux_macro__left_6__mux_aonpe__ports_2__stack_70c__width_52 ( |
| 1680 | din0, |
| 1681 | sel0, |
| 1682 | din1, |
| 1683 | sel1, |
| 1684 | dout); |
| 1685 | wire buffout0; |
| 1686 | wire buffout1; |
| 1687 | |
| 1688 | input [51:0] din0; |
| 1689 | input sel0; |
| 1690 | input [51:0] din1; |
| 1691 | input sel1; |
| 1692 | output [51:0] dout; |
| 1693 | |
| 1694 | |
| 1695 | |
| 1696 | |
| 1697 | |
| 1698 | cl_dp1_muxbuff2_8x c0_0 ( |
| 1699 | .in0(sel0), |
| 1700 | .in1(sel1), |
| 1701 | .out0(buffout0), |
| 1702 | .out1(buffout1) |
| 1703 | ); |
| 1704 | mux2s #(52) d0_0 ( |
| 1705 | .sel0(buffout0), |
| 1706 | .sel1(buffout1), |
| 1707 | .in0(din0[51:0]), |
| 1708 | .in1(din1[51:0]), |
| 1709 | .dout(dout[51:0]) |
| 1710 | ); |
| 1711 | |
| 1712 | |
| 1713 | |
| 1714 | |
| 1715 | |
| 1716 | |
| 1717 | |
| 1718 | |
| 1719 | |
| 1720 | |
| 1721 | |
| 1722 | |
| 1723 | |
| 1724 | endmodule |
| 1725 | |
| 1726 | |
| 1727 | // |
| 1728 | // parity macro (even parity) |
| 1729 | // |
| 1730 | // |
| 1731 | |
| 1732 | |
| 1733 | |
| 1734 | |
| 1735 | |
| 1736 | module lsu_tld_dp_prty_macro__width_32 ( |
| 1737 | din, |
| 1738 | dout); |
| 1739 | input [31:0] din; |
| 1740 | output dout; |
| 1741 | |
| 1742 | |
| 1743 | |
| 1744 | |
| 1745 | |
| 1746 | |
| 1747 | |
| 1748 | prty #(32) m0_0 ( |
| 1749 | .in(din[31:0]), |
| 1750 | .out(dout) |
| 1751 | ); |
| 1752 | |
| 1753 | |
| 1754 | |
| 1755 | |
| 1756 | |
| 1757 | |
| 1758 | |
| 1759 | |
| 1760 | |
| 1761 | |
| 1762 | endmodule |
| 1763 | |
| 1764 | |
| 1765 | |
| 1766 | |
| 1767 | |
| 1768 | // |
| 1769 | // invert macro |
| 1770 | // |
| 1771 | // |
| 1772 | |
| 1773 | |
| 1774 | |
| 1775 | |
| 1776 | |
| 1777 | module lsu_tld_dp_inv_macro__width_2 ( |
| 1778 | din, |
| 1779 | dout); |
| 1780 | input [1:0] din; |
| 1781 | output [1:0] dout; |
| 1782 | |
| 1783 | |
| 1784 | |
| 1785 | |
| 1786 | |
| 1787 | |
| 1788 | inv #(2) d0_0 ( |
| 1789 | .in(din[1:0]), |
| 1790 | .out(dout[1:0]) |
| 1791 | ); |
| 1792 | |
| 1793 | |
| 1794 | |
| 1795 | |
| 1796 | |
| 1797 | |
| 1798 | |
| 1799 | |
| 1800 | |
| 1801 | endmodule |
| 1802 | |
| 1803 | |
| 1804 | |
| 1805 | |
| 1806 | |
| 1807 | // |
| 1808 | // xor macro for ports = 2,3 |
| 1809 | // |
| 1810 | // |
| 1811 | |
| 1812 | |
| 1813 | |
| 1814 | |
| 1815 | |
| 1816 | module lsu_tld_dp_xor_macro__ports_2__width_1 ( |
| 1817 | din0, |
| 1818 | din1, |
| 1819 | dout); |
| 1820 | input [0:0] din0; |
| 1821 | input [0:0] din1; |
| 1822 | output [0:0] dout; |
| 1823 | |
| 1824 | |
| 1825 | |
| 1826 | |
| 1827 | |
| 1828 | xor2 #(1) d0_0 ( |
| 1829 | .in0(din0[0:0]), |
| 1830 | .in1(din1[0:0]), |
| 1831 | .out(dout[0:0]) |
| 1832 | ); |
| 1833 | |
| 1834 | |
| 1835 | |
| 1836 | |
| 1837 | |
| 1838 | |
| 1839 | |
| 1840 | |
| 1841 | endmodule |
| 1842 | |
| 1843 | |
| 1844 | |
| 1845 | |
| 1846 | |
| 1847 | // |
| 1848 | // parity macro (even parity) |
| 1849 | // |
| 1850 | // |
| 1851 | |
| 1852 | |
| 1853 | |
| 1854 | |
| 1855 | |
| 1856 | module lsu_tld_dp_prty_macro__width_8 ( |
| 1857 | din, |
| 1858 | dout); |
| 1859 | input [7:0] din; |
| 1860 | output dout; |
| 1861 | |
| 1862 | |
| 1863 | |
| 1864 | |
| 1865 | |
| 1866 | |
| 1867 | |
| 1868 | prty #(8) m0_0 ( |
| 1869 | .in(din[7:0]), |
| 1870 | .out(dout) |
| 1871 | ); |
| 1872 | |
| 1873 | |
| 1874 | |
| 1875 | |
| 1876 | |
| 1877 | |
| 1878 | |
| 1879 | |
| 1880 | |
| 1881 | |
| 1882 | endmodule |
| 1883 | |
| 1884 | |
| 1885 | |
| 1886 | |
| 1887 | |
| 1888 | // |
| 1889 | // parity macro (even parity) |
| 1890 | // |
| 1891 | // |
| 1892 | |
| 1893 | |
| 1894 | |
| 1895 | |
| 1896 | |
| 1897 | module lsu_tld_dp_prty_macro__width_16 ( |
| 1898 | din, |
| 1899 | dout); |
| 1900 | input [15:0] din; |
| 1901 | output dout; |
| 1902 | |
| 1903 | |
| 1904 | |
| 1905 | |
| 1906 | |
| 1907 | |
| 1908 | |
| 1909 | prty #(16) m0_0 ( |
| 1910 | .in(din[15:0]), |
| 1911 | .out(dout) |
| 1912 | ); |
| 1913 | |
| 1914 | |
| 1915 | |
| 1916 | |
| 1917 | |
| 1918 | |
| 1919 | |
| 1920 | |
| 1921 | |
| 1922 | |
| 1923 | endmodule |
| 1924 | |
| 1925 | |
| 1926 | |
| 1927 | |
| 1928 | |
| 1929 | // |
| 1930 | // buff macro |
| 1931 | // |
| 1932 | // |
| 1933 | |
| 1934 | |
| 1935 | |
| 1936 | |
| 1937 | |
| 1938 | module lsu_tld_dp_buff_macro__width_6 ( |
| 1939 | din, |
| 1940 | dout); |
| 1941 | input [5:0] din; |
| 1942 | output [5:0] dout; |
| 1943 | |
| 1944 | |
| 1945 | |
| 1946 | |
| 1947 | |
| 1948 | |
| 1949 | buff #(6) d0_0 ( |
| 1950 | .in(din[5:0]), |
| 1951 | .out(dout[5:0]) |
| 1952 | ); |
| 1953 | |
| 1954 | |
| 1955 | |
| 1956 | |
| 1957 | |
| 1958 | |
| 1959 | |
| 1960 | |
| 1961 | endmodule |
| 1962 | |
| 1963 | |
| 1964 | |
| 1965 | |
| 1966 | |
| 1967 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1968 | // also for pass-gate with decoder |
| 1969 | |
| 1970 | |
| 1971 | |
| 1972 | |
| 1973 | |
| 1974 | // any PARAMS parms go into naming of macro |
| 1975 | |
| 1976 | module lsu_tld_dp_mux_macro__mux_aope__ports_3__stack_20r__width_19 ( |
| 1977 | din0, |
| 1978 | din1, |
| 1979 | din2, |
| 1980 | sel0, |
| 1981 | sel1, |
| 1982 | dout); |
| 1983 | wire psel0; |
| 1984 | wire psel1; |
| 1985 | wire psel2; |
| 1986 | |
| 1987 | input [18:0] din0; |
| 1988 | input [18:0] din1; |
| 1989 | input [18:0] din2; |
| 1990 | input sel0; |
| 1991 | input sel1; |
| 1992 | output [18:0] dout; |
| 1993 | |
| 1994 | |
| 1995 | |
| 1996 | |
| 1997 | |
| 1998 | cl_dp1_penc3_8x c0_0 ( |
| 1999 | .test(1'b1), |
| 2000 | .sel0(sel0), |
| 2001 | .sel1(sel1), |
| 2002 | .psel0(psel0), |
| 2003 | .psel1(psel1), |
| 2004 | .psel2(psel2) |
| 2005 | ); |
| 2006 | |
| 2007 | mux3s #(19) d0_0 ( |
| 2008 | .sel0(psel0), |
| 2009 | .sel1(psel1), |
| 2010 | .sel2(psel2), |
| 2011 | .in0(din0[18:0]), |
| 2012 | .in1(din1[18:0]), |
| 2013 | .in2(din2[18:0]), |
| 2014 | .dout(dout[18:0]) |
| 2015 | ); |
| 2016 | |
| 2017 | |
| 2018 | |
| 2019 | |
| 2020 | |
| 2021 | |
| 2022 | |
| 2023 | |
| 2024 | |
| 2025 | |
| 2026 | |
| 2027 | |
| 2028 | |
| 2029 | endmodule |
| 2030 | |
| 2031 | |
| 2032 | |
| 2033 | |
| 2034 | |
| 2035 | |
| 2036 | // any PARAMS parms go into naming of macro |
| 2037 | |
| 2038 | module lsu_tld_dp_msff_macro__stack_48c__width_48 ( |
| 2039 | din, |
| 2040 | clk, |
| 2041 | en, |
| 2042 | se, |
| 2043 | scan_in, |
| 2044 | siclk, |
| 2045 | soclk, |
| 2046 | pce_ov, |
| 2047 | stop, |
| 2048 | dout, |
| 2049 | scan_out); |
| 2050 | wire l1clk; |
| 2051 | wire siclk_out; |
| 2052 | wire soclk_out; |
| 2053 | wire [46:0] so; |
| 2054 | |
| 2055 | input [47:0] din; |
| 2056 | |
| 2057 | |
| 2058 | input clk; |
| 2059 | input en; |
| 2060 | input se; |
| 2061 | input scan_in; |
| 2062 | input siclk; |
| 2063 | input soclk; |
| 2064 | input pce_ov; |
| 2065 | input stop; |
| 2066 | |
| 2067 | |
| 2068 | |
| 2069 | output [47:0] dout; |
| 2070 | |
| 2071 | |
| 2072 | output scan_out; |
| 2073 | |
| 2074 | |
| 2075 | |
| 2076 | |
| 2077 | cl_dp1_l1hdr_8x c0_0 ( |
| 2078 | .l2clk(clk), |
| 2079 | .pce(en), |
| 2080 | .aclk(siclk), |
| 2081 | .bclk(soclk), |
| 2082 | .l1clk(l1clk), |
| 2083 | .se(se), |
| 2084 | .pce_ov(pce_ov), |
| 2085 | .stop(stop), |
| 2086 | .siclk_out(siclk_out), |
| 2087 | .soclk_out(soclk_out) |
| 2088 | ); |
| 2089 | dff #(48) d0_0 ( |
| 2090 | .l1clk(l1clk), |
| 2091 | .siclk(siclk_out), |
| 2092 | .soclk(soclk_out), |
| 2093 | .d(din[47:0]), |
| 2094 | .si({scan_in,so[46:0]}), |
| 2095 | .so({so[46:0],scan_out}), |
| 2096 | .q(dout[47:0]) |
| 2097 | ); |
| 2098 | |
| 2099 | |
| 2100 | |
| 2101 | |
| 2102 | |
| 2103 | |
| 2104 | |
| 2105 | |
| 2106 | |
| 2107 | |
| 2108 | |
| 2109 | |
| 2110 | |
| 2111 | |
| 2112 | |
| 2113 | |
| 2114 | |
| 2115 | |
| 2116 | |
| 2117 | |
| 2118 | endmodule |
| 2119 | |
| 2120 | |
| 2121 | |
| 2122 | |
| 2123 | |
| 2124 | |
| 2125 | |
| 2126 | |
| 2127 | |
| 2128 | // |
| 2129 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) |
| 2130 | // |
| 2131 | // |
| 2132 | |
| 2133 | |
| 2134 | |
| 2135 | |
| 2136 | |
| 2137 | module lsu_tld_dp_zero_macro__width_32 ( |
| 2138 | din, |
| 2139 | dout); |
| 2140 | input [31:0] din; |
| 2141 | output dout; |
| 2142 | |
| 2143 | |
| 2144 | |
| 2145 | |
| 2146 | |
| 2147 | |
| 2148 | zero #(32) m0_0 ( |
| 2149 | .in(din[31:0]), |
| 2150 | .out(dout) |
| 2151 | ); |
| 2152 | |
| 2153 | |
| 2154 | |
| 2155 | |
| 2156 | |
| 2157 | |
| 2158 | |
| 2159 | |
| 2160 | |
| 2161 | |
| 2162 | endmodule |
| 2163 | |
| 2164 | |
| 2165 | |
| 2166 | |
| 2167 | |
| 2168 | // |
| 2169 | // buff macro |
| 2170 | // |
| 2171 | // |
| 2172 | |
| 2173 | |
| 2174 | |
| 2175 | |
| 2176 | |
| 2177 | module lsu_tld_dp_buff_macro__rep_1__stack_48c__width_48 ( |
| 2178 | din, |
| 2179 | dout); |
| 2180 | input [47:0] din; |
| 2181 | output [47:0] dout; |
| 2182 | |
| 2183 | |
| 2184 | |
| 2185 | |
| 2186 | |
| 2187 | |
| 2188 | buff #(48) d0_0 ( |
| 2189 | .in(din[47:0]), |
| 2190 | .out(dout[47:0]) |
| 2191 | ); |
| 2192 | |
| 2193 | |
| 2194 | |
| 2195 | |
| 2196 | |
| 2197 | |
| 2198 | |
| 2199 | |
| 2200 | endmodule |
| 2201 | |
| 2202 | |
| 2203 | |
| 2204 | |
| 2205 | |
| 2206 | |
| 2207 | |
| 2208 | |
| 2209 | |
| 2210 | // any PARAMS parms go into naming of macro |
| 2211 | |
| 2212 | module lsu_tld_dp_msff_macro__stack_22r__width_22 ( |
| 2213 | din, |
| 2214 | clk, |
| 2215 | en, |
| 2216 | se, |
| 2217 | scan_in, |
| 2218 | siclk, |
| 2219 | soclk, |
| 2220 | pce_ov, |
| 2221 | stop, |
| 2222 | dout, |
| 2223 | scan_out); |
| 2224 | wire l1clk; |
| 2225 | wire siclk_out; |
| 2226 | wire soclk_out; |
| 2227 | wire [20:0] so; |
| 2228 | |
| 2229 | input [21:0] din; |
| 2230 | |
| 2231 | |
| 2232 | input clk; |
| 2233 | input en; |
| 2234 | input se; |
| 2235 | input scan_in; |
| 2236 | input siclk; |
| 2237 | input soclk; |
| 2238 | input pce_ov; |
| 2239 | input stop; |
| 2240 | |
| 2241 | |
| 2242 | |
| 2243 | output [21:0] dout; |
| 2244 | |
| 2245 | |
| 2246 | output scan_out; |
| 2247 | |
| 2248 | |
| 2249 | |
| 2250 | |
| 2251 | cl_dp1_l1hdr_8x c0_0 ( |
| 2252 | .l2clk(clk), |
| 2253 | .pce(en), |
| 2254 | .aclk(siclk), |
| 2255 | .bclk(soclk), |
| 2256 | .l1clk(l1clk), |
| 2257 | .se(se), |
| 2258 | .pce_ov(pce_ov), |
| 2259 | .stop(stop), |
| 2260 | .siclk_out(siclk_out), |
| 2261 | .soclk_out(soclk_out) |
| 2262 | ); |
| 2263 | dff #(22) d0_0 ( |
| 2264 | .l1clk(l1clk), |
| 2265 | .siclk(siclk_out), |
| 2266 | .soclk(soclk_out), |
| 2267 | .d(din[21:0]), |
| 2268 | .si({scan_in,so[20:0]}), |
| 2269 | .so({so[20:0],scan_out}), |
| 2270 | .q(dout[21:0]) |
| 2271 | ); |
| 2272 | |
| 2273 | |
| 2274 | |
| 2275 | |
| 2276 | |
| 2277 | |
| 2278 | |
| 2279 | |
| 2280 | |
| 2281 | |
| 2282 | |
| 2283 | |
| 2284 | |
| 2285 | |
| 2286 | |
| 2287 | |
| 2288 | |
| 2289 | |
| 2290 | |
| 2291 | |
| 2292 | endmodule |
| 2293 | |
| 2294 | |
| 2295 | |
| 2296 | |
| 2297 | |
| 2298 | |
| 2299 | |
| 2300 | |