| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: mmu_asd_dp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module mmu_asd_dp ( |
| 36 | l2clk, |
| 37 | scan_in, |
| 38 | tcu_pce_ov, |
| 39 | spc_aclk, |
| 40 | spc_bclk, |
| 41 | tcu_scan_en, |
| 42 | tcu_scan_en_wmr, |
| 43 | spc_aclk_wmr, |
| 44 | wmr_scan_in, |
| 45 | thread_group, |
| 46 | ase_lsu_va_w, |
| 47 | ase_lsu_context_w, |
| 48 | asi_mra_rd_en_last, |
| 49 | asi_rd_immu_tag_target, |
| 50 | asi_rd_immu_tag_access, |
| 51 | asi_rd_dmmu_tag_target, |
| 52 | asi_rd_dmmu_tag_access, |
| 53 | asi_rd_i_access_target, |
| 54 | asi_rd_d_access_target, |
| 55 | asi_rd_access_target, |
| 56 | asi_rd_itte_tag, |
| 57 | asi_rd_itte_data, |
| 58 | asi_rd_dtte, |
| 59 | asi_wr_data, |
| 60 | asi_wr_immu_tag_access, |
| 61 | asi_i_tag_access_en, |
| 62 | asi_wr_itlb_data_in, |
| 63 | asi_wr_itlb_data_access, |
| 64 | asi_wr_immu_demap, |
| 65 | asi_wr_immu_demap_p, |
| 66 | asi_wr_immu_demap_n, |
| 67 | asi_i_data_in_en, |
| 68 | asi_wr_dmmu_tag_access, |
| 69 | asi_d_tag_access_en, |
| 70 | asi_wr_dtlb_data_in, |
| 71 | asi_wr_dtlb_data_access, |
| 72 | asi_wr_dmmu_demap, |
| 73 | asi_wr_dmmu_demap_p, |
| 74 | asi_wr_dmmu_demap_s_n, |
| 75 | asi_d_data_in_en, |
| 76 | asi_dmmu_demap_s, |
| 77 | asi_wr_p_context_0, |
| 78 | asi_p_context_0_en, |
| 79 | asi_data_in_real, |
| 80 | asi_tag_access_sel, |
| 81 | asi_mra_wr_data, |
| 82 | asi_demap_r_bit, |
| 83 | asi_mra_rd_addr_bit_1, |
| 84 | asi_rd_tsb_ptr_, |
| 85 | mra_data, |
| 86 | tlu_pc_w, |
| 87 | tlu_load_i_tag_access_p, |
| 88 | tlu_load_i_tag_access_n, |
| 89 | tlu_load_d_tag_access, |
| 90 | tlu_load_d_tag_access_r, |
| 91 | htd_tagaccess_din, |
| 92 | htd_tlbdatain_din, |
| 93 | htc_wr_itlb_data_in, |
| 94 | htc_wr_dtlb_data_in, |
| 95 | mmu_use_context_0, |
| 96 | mmu_use_context_1, |
| 97 | mmu_sec_context, |
| 98 | scan_out, |
| 99 | wmr_scan_out, |
| 100 | asd_rd_data, |
| 101 | asd_asi_rd_data, |
| 102 | asd_dtte_tag, |
| 103 | asd_dtte_data, |
| 104 | asd_itte_tag_data_, |
| 105 | asd_itte_index, |
| 106 | asd_iht_p_ctx_0_0, |
| 107 | asd_iht_p_ctx_0_1, |
| 108 | asd_iht_p_ctx_0_2, |
| 109 | asd_iht_p_ctx_0_3, |
| 110 | asd_tag_access, |
| 111 | asd_zero_context, |
| 112 | asd_asi_zero_context, |
| 113 | asd_mra_rd_addr_bit_1, |
| 114 | asd_pc_w); |
| 115 | wire [3:0] htc_wr_itlb_tag_access; |
| 116 | wire [3:0] htc_wr_dtlb_tag_access; |
| 117 | wire [60:48] wr_data_unused; |
| 118 | wire [12:0] mra_wr_data_unused; |
| 119 | wire clk; |
| 120 | wire stop; |
| 121 | wire pce_ov; |
| 122 | wire se; |
| 123 | wire siclk; |
| 124 | wire soclk; |
| 125 | wire mra_read_1_lat_scanin; |
| 126 | wire mra_read_1_lat_scanout; |
| 127 | wire [81:0] mra_rd_data; |
| 128 | wire mra_read_0_lat_scanin; |
| 129 | wire mra_read_0_lat_scanout; |
| 130 | wire p_context_lat_wmr_scanin; |
| 131 | wire p_context_lat_wmr_scanout; |
| 132 | wire [12:0] p_context_0_3; |
| 133 | wire [12:0] p_context_0_2; |
| 134 | wire [12:0] p_context_0_1; |
| 135 | wire [12:0] p_context_0_0; |
| 136 | wire immu_tag_access_3_lat_wmr_scanin; |
| 137 | wire immu_tag_access_3_lat_wmr_scanout; |
| 138 | wire [47:0] immu_tag_access_3; |
| 139 | wire immu_tag_access_2_lat_wmr_scanin; |
| 140 | wire immu_tag_access_2_lat_wmr_scanout; |
| 141 | wire [47:0] immu_tag_access_2; |
| 142 | wire immu_tag_access_1_lat_wmr_scanin; |
| 143 | wire immu_tag_access_1_lat_wmr_scanout; |
| 144 | wire [47:0] immu_tag_access_1; |
| 145 | wire immu_tag_access_0_lat_wmr_scanin; |
| 146 | wire immu_tag_access_0_lat_wmr_scanout; |
| 147 | wire [47:0] immu_tag_access_0; |
| 148 | wire [61:0] immu_access_target; |
| 149 | wire dmmu_tag_access_3_lat_wmr_scanin; |
| 150 | wire dmmu_tag_access_3_lat_wmr_scanout; |
| 151 | wire [47:0] dmmu_tag_access_3; |
| 152 | wire dmmu_tag_access_2_lat_wmr_scanin; |
| 153 | wire dmmu_tag_access_2_lat_wmr_scanout; |
| 154 | wire [47:0] dmmu_tag_access_2; |
| 155 | wire dmmu_tag_access_1_lat_wmr_scanin; |
| 156 | wire dmmu_tag_access_1_lat_wmr_scanout; |
| 157 | wire [47:0] dmmu_tag_access_1; |
| 158 | wire dmmu_tag_access_0_lat_wmr_scanin; |
| 159 | wire dmmu_tag_access_0_lat_wmr_scanout; |
| 160 | wire [47:0] dmmu_tag_access_0; |
| 161 | wire [61:0] dmmu_access_target; |
| 162 | wire [47:0] tag_access; |
| 163 | wire [2:0] tag_access_sel; |
| 164 | wire zero_context; |
| 165 | wire bit1; |
| 166 | wire asi_rd_mux_scanin; |
| 167 | wire asi_rd_mux_scanout; |
| 168 | wire [48:0] itlb_data_in_0; |
| 169 | wire [48:0] itlb_data_in_1; |
| 170 | wire [48:0] itlb_data_in_2; |
| 171 | wire [48:0] itlb_data_in_3; |
| 172 | wire [50:0] dtlb_data_in_0; |
| 173 | wire [50:0] dtlb_data_in_1; |
| 174 | wire [50:0] dtlb_data_in_2; |
| 175 | wire [50:0] dtlb_data_in_3; |
| 176 | wire itlb_ps_eq_256m_0; |
| 177 | wire itlb_ps_eq_256m_1; |
| 178 | wire itlb_ps_eq_256m_2; |
| 179 | wire itlb_ps_eq_256m_3; |
| 180 | wire dtlb_ps_eq_256m_0; |
| 181 | wire dtlb_ps_eq_256m_1; |
| 182 | wire dtlb_ps_eq_256m_2; |
| 183 | wire dtlb_ps_eq_256m_3; |
| 184 | wire itlb_ps_gt_64k_0; |
| 185 | wire itlb_ps_gt_64k_1; |
| 186 | wire itlb_ps_gt_64k_2; |
| 187 | wire itlb_ps_gt_64k_3; |
| 188 | wire dtlb_ps_gt_64k_0; |
| 189 | wire dtlb_ps_gt_64k_1; |
| 190 | wire dtlb_ps_gt_64k_2; |
| 191 | wire dtlb_ps_gt_64k_3; |
| 192 | wire itlb_ps_gt_8k_0; |
| 193 | wire itlb_ps_gt_8k_1; |
| 194 | wire itlb_ps_gt_8k_2; |
| 195 | wire itlb_ps_gt_8k_3; |
| 196 | wire dtlb_ps_gt_8k_0; |
| 197 | wire dtlb_ps_gt_8k_1; |
| 198 | wire dtlb_ps_gt_8k_2; |
| 199 | wire dtlb_ps_gt_8k_3; |
| 200 | wire [47:0] itte_tag; |
| 201 | wire [47:0] dtte_tag; |
| 202 | wire [38:0] data_in; |
| 203 | wire itlb_data_in_3_lat_scanin; |
| 204 | wire itlb_data_in_3_lat_scanout; |
| 205 | wire itlb_data_in_2_lat_scanin; |
| 206 | wire itlb_data_in_2_lat_scanout; |
| 207 | wire itlb_data_in_1_lat_scanin; |
| 208 | wire itlb_data_in_1_lat_scanout; |
| 209 | wire itlb_data_in_0_lat_scanin; |
| 210 | wire itlb_data_in_0_lat_scanout; |
| 211 | wire dtlb_data_in_3_lat_scanin; |
| 212 | wire dtlb_data_in_3_lat_scanout; |
| 213 | wire dtlb_data_in_2_lat_scanin; |
| 214 | wire dtlb_data_in_2_lat_scanout; |
| 215 | wire dtlb_data_in_1_lat_scanin; |
| 216 | wire dtlb_data_in_1_lat_scanout; |
| 217 | wire dtlb_data_in_0_lat_scanin; |
| 218 | wire dtlb_data_in_0_lat_scanout; |
| 219 | wire [45:0] itte_data; |
| 220 | wire [54:0] dtte_data; |
| 221 | |
| 222 | |
| 223 | |
| 224 | input l2clk; |
| 225 | input scan_in; |
| 226 | input tcu_pce_ov; |
| 227 | input spc_aclk; |
| 228 | input spc_bclk; |
| 229 | input tcu_scan_en; |
| 230 | |
| 231 | input tcu_scan_en_wmr; |
| 232 | input spc_aclk_wmr; // Warm reset (non)scan |
| 233 | input wmr_scan_in; |
| 234 | |
| 235 | input thread_group; |
| 236 | |
| 237 | input [47:13] ase_lsu_va_w; |
| 238 | input [12:0] ase_lsu_context_w; |
| 239 | |
| 240 | input asi_mra_rd_en_last; |
| 241 | |
| 242 | input [3:0] asi_rd_immu_tag_target; |
| 243 | input [3:0] asi_rd_immu_tag_access; |
| 244 | input [3:0] asi_rd_dmmu_tag_target; |
| 245 | input [3:0] asi_rd_dmmu_tag_access; |
| 246 | input asi_rd_i_access_target; |
| 247 | input asi_rd_d_access_target; |
| 248 | input asi_rd_access_target; |
| 249 | input [3:0] asi_rd_itte_tag; |
| 250 | input [3:0] asi_rd_itte_data; |
| 251 | input [2:0] asi_rd_dtte; |
| 252 | |
| 253 | input [63:0] asi_wr_data; |
| 254 | input [3:0] asi_wr_immu_tag_access; |
| 255 | input [3:0] asi_i_tag_access_en; |
| 256 | input [3:0] asi_wr_itlb_data_in; |
| 257 | input [3:0] asi_wr_itlb_data_access; |
| 258 | input [3:0] asi_wr_immu_demap; |
| 259 | input [3:0] asi_wr_immu_demap_p; |
| 260 | input [3:0] asi_wr_immu_demap_n; |
| 261 | input [3:0] asi_i_data_in_en; |
| 262 | input [3:0] asi_wr_dmmu_tag_access; |
| 263 | input [3:0] asi_d_tag_access_en; |
| 264 | input [3:0] asi_wr_dtlb_data_in; |
| 265 | input [3:0] asi_wr_dtlb_data_access; |
| 266 | input [3:0] asi_wr_dmmu_demap; |
| 267 | input [3:0] asi_wr_dmmu_demap_p; |
| 268 | input [3:0] asi_wr_dmmu_demap_s_n; |
| 269 | input [3:0] asi_d_data_in_en; |
| 270 | input asi_dmmu_demap_s; |
| 271 | input [3:0] asi_wr_p_context_0; |
| 272 | input asi_p_context_0_en; |
| 273 | input asi_data_in_real; |
| 274 | input [2:0] asi_tag_access_sel; |
| 275 | |
| 276 | input [39:0] asi_mra_wr_data; |
| 277 | input asi_demap_r_bit; |
| 278 | |
| 279 | input asi_mra_rd_addr_bit_1; |
| 280 | input asi_rd_tsb_ptr_; |
| 281 | |
| 282 | input [81:0] mra_data; |
| 283 | |
| 284 | input [47:13] tlu_pc_w; |
| 285 | input [3:0] tlu_load_i_tag_access_p; |
| 286 | input [3:0] tlu_load_i_tag_access_n; |
| 287 | input [3:0] tlu_load_d_tag_access; |
| 288 | input [3:0] tlu_load_d_tag_access_r; |
| 289 | |
| 290 | input [47:0] htd_tagaccess_din; |
| 291 | input [38:0] htd_tlbdatain_din; |
| 292 | input [3:0] htc_wr_itlb_data_in; |
| 293 | input [3:0] htc_wr_dtlb_data_in; |
| 294 | |
| 295 | input mmu_use_context_0; // HW TW: Replace TTE ctxt with ctxt 0 |
| 296 | input mmu_use_context_1; // HW TW: Replace TTE ctxt with ctxt 1 |
| 297 | input mmu_sec_context; // HW TW: Replace TTE ctxt with secon. |
| 298 | |
| 299 | output scan_out; |
| 300 | |
| 301 | output wmr_scan_out; // Warm reset (non)scan |
| 302 | |
| 303 | output [81:0] asd_rd_data; |
| 304 | |
| 305 | output [63:0] asd_asi_rd_data; |
| 306 | |
| 307 | output [47:0] asd_dtte_tag; |
| 308 | output [54:0] asd_dtte_data; |
| 309 | output [47:0] asd_itte_tag_data_; |
| 310 | output [6:0] asd_itte_index; |
| 311 | |
| 312 | output [12:0] asd_iht_p_ctx_0_0; |
| 313 | output [12:0] asd_iht_p_ctx_0_1; |
| 314 | output [12:0] asd_iht_p_ctx_0_2; |
| 315 | output [12:0] asd_iht_p_ctx_0_3; |
| 316 | |
| 317 | output [47:0] asd_tag_access; |
| 318 | output asd_zero_context; |
| 319 | output asd_asi_zero_context; |
| 320 | |
| 321 | output asd_mra_rd_addr_bit_1; |
| 322 | |
| 323 | output [47:13] asd_pc_w; // Needs to feed mmu_htd_dp |
| 324 | |
| 325 | |
| 326 | |
| 327 | |
| 328 | ////////////////////////////////////////////////////////////////////////////// |
| 329 | assign htc_wr_itlb_tag_access[3:0] = |
| 330 | htc_wr_itlb_data_in[3:0]; |
| 331 | |
| 332 | assign htc_wr_dtlb_tag_access[3:0] = |
| 333 | htc_wr_dtlb_data_in[3:0]; |
| 334 | |
| 335 | assign wr_data_unused[60:48] = |
| 336 | asi_wr_data[60:48]; |
| 337 | |
| 338 | assign mra_wr_data_unused[12:10] = |
| 339 | asi_mra_wr_data[12:10]; |
| 340 | |
| 341 | assign mra_wr_data_unused[2:0] = |
| 342 | asi_mra_wr_data[2:0]; |
| 343 | |
| 344 | |
| 345 | |
| 346 | ////////////////////////////////////////////////////////////////////// |
| 347 | |
| 348 | assign clk = l2clk; |
| 349 | assign stop = 1'b0; |
| 350 | |
| 351 | mmu_asd_dp_buff_macro__width_4 clk_control_buf ( |
| 352 | .din ({tcu_pce_ov , |
| 353 | tcu_scan_en , |
| 354 | spc_aclk , |
| 355 | spc_bclk }), |
| 356 | .dout ({pce_ov , |
| 357 | se , |
| 358 | siclk , |
| 359 | soclk }) |
| 360 | ); |
| 361 | |
| 362 | |
| 363 | |
| 364 | ////////////////////////////////////////////////////////////////////// |
| 365 | // |
| 366 | // Capture read data from mra |
| 367 | // |
| 368 | |
| 369 | mmu_asd_dp_msff_macro__minbuff_1__stack_58c__width_24 mra_read_1_lat ( |
| 370 | .scan_in(mra_read_1_lat_scanin), |
| 371 | .scan_out(mra_read_1_lat_scanout), |
| 372 | .en (asi_mra_rd_en_last ), |
| 373 | .din (mra_data [81:58]), |
| 374 | .dout (mra_rd_data [81:58]), |
| 375 | .clk(clk), |
| 376 | .se(se), |
| 377 | .siclk(siclk), |
| 378 | .soclk(soclk), |
| 379 | .pce_ov(pce_ov), |
| 380 | .stop(stop) |
| 381 | ); |
| 382 | |
| 383 | mmu_asd_dp_msff_macro__minbuff_1__stack_58c__width_58 mra_read_0_lat ( |
| 384 | .scan_in(mra_read_0_lat_scanin), |
| 385 | .scan_out(mra_read_0_lat_scanout), |
| 386 | .en (asi_mra_rd_en_last ), |
| 387 | .din (mra_data [57:0] ), |
| 388 | .dout (mra_rd_data [57:0] ), |
| 389 | .clk(clk), |
| 390 | .se(se), |
| 391 | .siclk(siclk), |
| 392 | .soclk(soclk), |
| 393 | .pce_ov(pce_ov), |
| 394 | .stop(stop) |
| 395 | ); |
| 396 | |
| 397 | assign asd_rd_data[81:0] = |
| 398 | mra_rd_data[81:0]; |
| 399 | |
| 400 | |
| 401 | |
| 402 | ////////////////////////////////////////////////////////////////////// |
| 403 | // |
| 404 | // Individual registers |
| 405 | // |
| 406 | |
| 407 | // Shadow copy of p_context_0 for tag_access regs |
| 408 | mmu_asd_dp_msff_macro__mux_aonpe__ports_4__stack_58c__width_52 p_context_lat ( |
| 409 | .scan_in(p_context_lat_wmr_scanin), |
| 410 | .scan_out(p_context_lat_wmr_scanout), |
| 411 | .siclk(spc_aclk_wmr), |
| 412 | .se (tcu_scan_en_wmr ), |
| 413 | .din0 ({p_context_0_3 [12:0], |
| 414 | p_context_0_2 [12:0], |
| 415 | p_context_0_1 [12:0], |
| 416 | asi_wr_data [12:0]}), |
| 417 | .din1 ({p_context_0_3 [12:0], |
| 418 | p_context_0_2 [12:0], |
| 419 | asi_wr_data [12:0], |
| 420 | p_context_0_0 [12:0]}), |
| 421 | .din2 ({p_context_0_3 [12:0], |
| 422 | asi_wr_data [12:0], |
| 423 | p_context_0_1 [12:0], |
| 424 | p_context_0_0 [12:0]}), |
| 425 | .din3 ({asi_wr_data [12:0], |
| 426 | p_context_0_2 [12:0], |
| 427 | p_context_0_1 [12:0], |
| 428 | p_context_0_0 [12:0]}), |
| 429 | .sel0 (asi_wr_p_context_0 [0 ] ), |
| 430 | .sel1 (asi_wr_p_context_0 [1 ] ), |
| 431 | .sel2 (asi_wr_p_context_0 [2 ] ), |
| 432 | .sel3 (asi_wr_p_context_0 [3 ] ), |
| 433 | .en (asi_p_context_0_en ), |
| 434 | .dout ({p_context_0_3 [12:0], |
| 435 | p_context_0_2 [12:0], |
| 436 | p_context_0_1 [12:0], |
| 437 | p_context_0_0 [12:0]}), |
| 438 | .clk(clk), |
| 439 | .soclk(soclk), |
| 440 | .pce_ov(pce_ov), |
| 441 | .stop(stop) |
| 442 | ); |
| 443 | |
| 444 | mmu_asd_dp_buff_macro__left_13__stack_58c__width_35 pc_w_buf ( |
| 445 | .din (tlu_pc_w [47:13] ), |
| 446 | .dout (asd_pc_w [47:13] ) |
| 447 | ); |
| 448 | |
| 449 | mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 immu_tag_access_3_lat ( |
| 450 | .scan_in(immu_tag_access_3_lat_wmr_scanin), |
| 451 | .scan_out(immu_tag_access_3_lat_wmr_scanout), |
| 452 | .siclk(spc_aclk_wmr), |
| 453 | .se (tcu_scan_en_wmr ), |
| 454 | .din0 ({asd_pc_w [47:13], |
| 455 | p_context_0_3 [12:0]}), |
| 456 | .din1 ({asd_pc_w [47:13], |
| 457 | {13 {1'b0}} }), |
| 458 | .din2 (asi_wr_data [47:0] ), |
| 459 | .din3 ({asi_wr_data [47:40], // Demap VA[47:40] in data |
| 460 | asi_mra_wr_data [39:13], |
| 461 | p_context_0_3 [12:0]}), |
| 462 | .din4 ({asi_wr_data [47:40], // Demap VA[47:40] in data |
| 463 | asi_mra_wr_data [39:13], |
| 464 | {13 {1'b0}} }), |
| 465 | .din5 (htd_tagaccess_din [47:0] ), |
| 466 | .din6 (immu_tag_access_3 [47:0] ), |
| 467 | .sel0 (tlu_load_i_tag_access_p[3 ] ), |
| 468 | .sel1 (tlu_load_i_tag_access_n[3 ] ), |
| 469 | .sel2 (asi_wr_immu_tag_access [3 ] ), |
| 470 | .sel3 (asi_wr_immu_demap_p [3 ] ), |
| 471 | .sel4 (asi_wr_immu_demap_n [3 ] ), |
| 472 | .sel5 (htc_wr_itlb_tag_access [3 ] ), // HWTW Write ITLB Tag Access |
| 473 | .en (asi_i_tag_access_en [3 ] ), |
| 474 | .dout (immu_tag_access_3 [47:0] ), |
| 475 | .clk(clk), |
| 476 | .soclk(soclk), |
| 477 | .pce_ov(pce_ov), |
| 478 | .stop(stop) |
| 479 | ); |
| 480 | |
| 481 | mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 immu_tag_access_2_lat ( |
| 482 | .scan_in(immu_tag_access_2_lat_wmr_scanin), |
| 483 | .scan_out(immu_tag_access_2_lat_wmr_scanout), |
| 484 | .siclk(spc_aclk_wmr), |
| 485 | .se (tcu_scan_en_wmr ), |
| 486 | .din0 ({asd_pc_w [47:13], |
| 487 | p_context_0_2 [12:0]}), |
| 488 | .din1 ({asd_pc_w [47:13], |
| 489 | {13 {1'b0}} }), |
| 490 | .din2 (asi_wr_data [47:0] ), |
| 491 | .din3 ({asi_wr_data [47:40], // Demap VA[47:40] in data |
| 492 | asi_mra_wr_data [39:13], |
| 493 | p_context_0_2 [12:0]}), |
| 494 | .din4 ({asi_wr_data [47:40], // Demap VA[47:40] in data |
| 495 | asi_mra_wr_data [39:13], |
| 496 | {13 {1'b0}} }), |
| 497 | .din5 (htd_tagaccess_din [47:0] ), |
| 498 | .din6 (immu_tag_access_2 [47:0] ), |
| 499 | .sel0 (tlu_load_i_tag_access_p[2 ] ), |
| 500 | .sel1 (tlu_load_i_tag_access_n[2 ] ), |
| 501 | .sel2 (asi_wr_immu_tag_access [2 ] ), |
| 502 | .sel3 (asi_wr_immu_demap_p [2 ] ), |
| 503 | .sel4 (asi_wr_immu_demap_n [2 ] ), |
| 504 | .sel5 (htc_wr_itlb_tag_access [2 ] ), // HWTW Write ITLB Tag Access |
| 505 | .en (asi_i_tag_access_en [2 ] ), |
| 506 | .dout (immu_tag_access_2 [47:0] ), |
| 507 | .clk(clk), |
| 508 | .soclk(soclk), |
| 509 | .pce_ov(pce_ov), |
| 510 | .stop(stop) |
| 511 | ); |
| 512 | |
| 513 | mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 immu_tag_access_1_lat ( |
| 514 | .scan_in(immu_tag_access_1_lat_wmr_scanin), |
| 515 | .scan_out(immu_tag_access_1_lat_wmr_scanout), |
| 516 | .siclk(spc_aclk_wmr), |
| 517 | .se (tcu_scan_en_wmr ), |
| 518 | .din0 ({asd_pc_w [47:13], |
| 519 | p_context_0_1 [12:0]}), |
| 520 | .din1 ({asd_pc_w [47:13], |
| 521 | {13 {1'b0}} }), |
| 522 | .din2 (asi_wr_data [47:0] ), |
| 523 | .din3 ({asi_wr_data [47:40], // Demap VA[47:40] in data |
| 524 | asi_mra_wr_data [39:13], |
| 525 | p_context_0_1 [12:0]}), |
| 526 | .din4 ({asi_wr_data [47:40], // Demap VA[47:40] in data |
| 527 | asi_mra_wr_data [39:13], |
| 528 | {13 {1'b0}} }), |
| 529 | .din5 (htd_tagaccess_din [47:0] ), |
| 530 | .din6 (immu_tag_access_1 [47:0] ), |
| 531 | .sel0 (tlu_load_i_tag_access_p[1 ] ), |
| 532 | .sel1 (tlu_load_i_tag_access_n[1 ] ), |
| 533 | .sel2 (asi_wr_immu_tag_access [1 ] ), |
| 534 | .sel3 (asi_wr_immu_demap_p [1 ] ), |
| 535 | .sel4 (asi_wr_immu_demap_n [1 ] ), |
| 536 | .sel5 (htc_wr_itlb_tag_access [1 ] ), // HWTW Write ITLB Tag Access |
| 537 | .en (asi_i_tag_access_en [1 ] ), |
| 538 | .dout (immu_tag_access_1 [47:0] ), |
| 539 | .clk(clk), |
| 540 | .soclk(soclk), |
| 541 | .pce_ov(pce_ov), |
| 542 | .stop(stop) |
| 543 | ); |
| 544 | |
| 545 | mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 immu_tag_access_0_lat ( |
| 546 | .scan_in(immu_tag_access_0_lat_wmr_scanin), |
| 547 | .scan_out(immu_tag_access_0_lat_wmr_scanout), |
| 548 | .siclk(spc_aclk_wmr), |
| 549 | .se (tcu_scan_en_wmr ), |
| 550 | .din0 ({asd_pc_w [47:13], |
| 551 | p_context_0_0 [12:0]}), |
| 552 | .din1 ({asd_pc_w [47:13], |
| 553 | {13 {1'b0}} }), |
| 554 | .din2 (asi_wr_data [47:0] ), |
| 555 | .din3 ({asi_wr_data [47:40], // Demap VA[47:40] in data |
| 556 | asi_mra_wr_data [39:13], |
| 557 | p_context_0_0 [12:0]}), |
| 558 | .din4 ({asi_wr_data [47:40], // Demap VA[47:40] in data |
| 559 | asi_mra_wr_data [39:13], |
| 560 | {13 {1'b0}} }), |
| 561 | .din5 (htd_tagaccess_din [47:0] ), |
| 562 | .din6 (immu_tag_access_0 [47:0] ), |
| 563 | .sel0 (tlu_load_i_tag_access_p[0 ] ), |
| 564 | .sel1 (tlu_load_i_tag_access_n[0 ] ), |
| 565 | .sel2 (asi_wr_immu_tag_access [0 ] ), |
| 566 | .sel3 (asi_wr_immu_demap_p [0 ] ), |
| 567 | .sel4 (asi_wr_immu_demap_n [0 ] ), |
| 568 | .sel5 (htc_wr_itlb_tag_access [0 ] ), // HWTW Write ITLB Tag Access |
| 569 | .en (asi_i_tag_access_en [0 ] ), |
| 570 | .dout (immu_tag_access_0 [47:0] ), |
| 571 | .clk(clk), |
| 572 | .soclk(soclk), |
| 573 | .pce_ov(pce_ov), |
| 574 | .stop(stop) |
| 575 | ); |
| 576 | |
| 577 | mmu_asd_dp_mux_macro__mux_aonpe__ports_8__width_62 immu_access_target_mux ( |
| 578 | .din0 ({{14 {immu_tag_access_0[47 ]}}, |
| 579 | immu_tag_access_0 [47:0]}), |
| 580 | .din1 ({{14 {immu_tag_access_1[47 ]}}, |
| 581 | immu_tag_access_1 [47:0]}), |
| 582 | .din2 ({{14 {immu_tag_access_2[47 ]}}, |
| 583 | immu_tag_access_2 [47:0]}), |
| 584 | .din3 ({{14 {immu_tag_access_3[47 ]}}, |
| 585 | immu_tag_access_3 [47:0]}), |
| 586 | .din4 ({1'b0 , |
| 587 | immu_tag_access_0 [12:0], |
| 588 | {6 {1'b0}} , |
| 589 | {16 {immu_tag_access_0[47 ]}}, |
| 590 | immu_tag_access_0 [47:22]}), // tag target |
| 591 | .din5 ({1'b0 , |
| 592 | immu_tag_access_1 [12:0], |
| 593 | {6 {1'b0}} , |
| 594 | {16 {immu_tag_access_1[47 ]}}, |
| 595 | immu_tag_access_1 [47:22]}), // tag target |
| 596 | .din6 ({1'b0 , |
| 597 | immu_tag_access_2 [12:0], |
| 598 | {6 {1'b0}} , |
| 599 | {16 {immu_tag_access_2[47 ]}}, |
| 600 | immu_tag_access_2 [47:22]}), // tag target |
| 601 | .din7 ({1'b0 , |
| 602 | immu_tag_access_3 [12:0], |
| 603 | {6 {1'b0}} , |
| 604 | {16 {immu_tag_access_3[47 ]}}, |
| 605 | immu_tag_access_3 [47:22]}), // tag target |
| 606 | .sel0 (asi_rd_immu_tag_access [0 ] ), |
| 607 | .sel1 (asi_rd_immu_tag_access [1 ] ), |
| 608 | .sel2 (asi_rd_immu_tag_access [2 ] ), |
| 609 | .sel3 (asi_rd_immu_tag_access [3 ] ), |
| 610 | .sel4 (asi_rd_immu_tag_target [0 ] ), |
| 611 | .sel5 (asi_rd_immu_tag_target [1 ] ), |
| 612 | .sel6 (asi_rd_immu_tag_target [2 ] ), |
| 613 | .sel7 (asi_rd_immu_tag_target [3 ] ), |
| 614 | .dout (immu_access_target [61:0] ) |
| 615 | ); |
| 616 | |
| 617 | mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 dmmu_tag_access_3_lat ( |
| 618 | .scan_in(dmmu_tag_access_3_lat_wmr_scanin), |
| 619 | .scan_out(dmmu_tag_access_3_lat_wmr_scanout), |
| 620 | .siclk(spc_aclk_wmr), |
| 621 | .se (tcu_scan_en_wmr ), |
| 622 | .din0 ({ase_lsu_va_w [47:13], |
| 623 | ase_lsu_context_w [12:0]}), |
| 624 | .din1 ({ase_lsu_va_w [47:13], |
| 625 | {13 {1'b0}} }), |
| 626 | .din2 (asi_wr_data [47:0] ), |
| 627 | .din3 ({asi_wr_data [47:40], // Demap VA[47:40] in data |
| 628 | asi_mra_wr_data [39:13], |
| 629 | p_context_0_3 [12:0]}), |
| 630 | .din4 ({asi_wr_data [47:40], // Demap VA[47:40] in data |
| 631 | asi_mra_wr_data [39:13], |
| 632 | {13 {1'b0}} }), |
| 633 | .din5 (htd_tagaccess_din [47:0] ), |
| 634 | .din6 (dmmu_tag_access_3 [47:0] ), |
| 635 | .sel0 (tlu_load_d_tag_access [3 ] ), |
| 636 | .sel1 (tlu_load_d_tag_access_r[3 ] ), |
| 637 | .sel2 (asi_wr_dmmu_tag_access [3 ] ), |
| 638 | .sel3 (asi_wr_dmmu_demap_p [3 ] ), |
| 639 | .sel4 (asi_wr_dmmu_demap_s_n [3 ] ), |
| 640 | .sel5 (htc_wr_dtlb_tag_access [3 ] ), //HWTW Write DTLB Tag Access |
| 641 | .en (asi_d_tag_access_en [3 ] ), |
| 642 | .dout (dmmu_tag_access_3 [47:0] ), |
| 643 | .clk(clk), |
| 644 | .soclk(soclk), |
| 645 | .pce_ov(pce_ov), |
| 646 | .stop(stop) |
| 647 | ); |
| 648 | |
| 649 | mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 dmmu_tag_access_2_lat ( |
| 650 | .scan_in(dmmu_tag_access_2_lat_wmr_scanin), |
| 651 | .scan_out(dmmu_tag_access_2_lat_wmr_scanout), |
| 652 | .siclk(spc_aclk_wmr), |
| 653 | .se (tcu_scan_en_wmr ), |
| 654 | .din0 ({ase_lsu_va_w [47:13], |
| 655 | ase_lsu_context_w [12:0]}), |
| 656 | .din1 ({ase_lsu_va_w [47:13], |
| 657 | {13 {1'b0}} }), |
| 658 | .din2 (asi_wr_data [47:0] ), |
| 659 | .din3 ({asi_wr_data [47:40], // Demap VA[47:40] in data |
| 660 | asi_mra_wr_data [39:13], |
| 661 | p_context_0_2 [12:0]}), |
| 662 | .din4 ({asi_wr_data [47:40], // Demap VA[47:40] in data |
| 663 | asi_mra_wr_data [39:13], |
| 664 | {13 {1'b0}} }), |
| 665 | .din5 (htd_tagaccess_din [47:0] ), |
| 666 | .din6 (dmmu_tag_access_2 [47:0] ), |
| 667 | .sel0 (tlu_load_d_tag_access [2 ] ), |
| 668 | .sel1 (tlu_load_d_tag_access_r[2 ] ), |
| 669 | .sel2 (asi_wr_dmmu_tag_access [2 ] ), |
| 670 | .sel3 (asi_wr_dmmu_demap_p [2 ] ), |
| 671 | .sel4 (asi_wr_dmmu_demap_s_n [2 ] ), |
| 672 | .sel5 (htc_wr_dtlb_tag_access [2 ] ), //HWTW Write DTLB Tag Access |
| 673 | .en (asi_d_tag_access_en [2 ] ), |
| 674 | .dout (dmmu_tag_access_2 [47:0] ), |
| 675 | .clk(clk), |
| 676 | .soclk(soclk), |
| 677 | .pce_ov(pce_ov), |
| 678 | .stop(stop) |
| 679 | ); |
| 680 | |
| 681 | mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 dmmu_tag_access_1_lat ( |
| 682 | .scan_in(dmmu_tag_access_1_lat_wmr_scanin), |
| 683 | .scan_out(dmmu_tag_access_1_lat_wmr_scanout), |
| 684 | .siclk(spc_aclk_wmr), |
| 685 | .se (tcu_scan_en_wmr ), |
| 686 | .din0 ({ase_lsu_va_w [47:13], |
| 687 | ase_lsu_context_w [12:0]}), |
| 688 | .din1 ({ase_lsu_va_w [47:13], |
| 689 | {13 {1'b0}} }), |
| 690 | .din2 (asi_wr_data [47:0] ), |
| 691 | .din3 ({asi_wr_data [47:40], // Demap VA[47:40] in data |
| 692 | asi_mra_wr_data [39:13], |
| 693 | p_context_0_1 [12:0]}), |
| 694 | .din4 ({asi_wr_data [47:40], // Demap VA[47:40] in data |
| 695 | asi_mra_wr_data [39:13], |
| 696 | {13 {1'b0}} }), |
| 697 | .din5 (htd_tagaccess_din [47:0] ), |
| 698 | .din6 (dmmu_tag_access_1 [47:0] ), |
| 699 | .sel0 (tlu_load_d_tag_access [1 ] ), |
| 700 | .sel1 (tlu_load_d_tag_access_r[1 ] ), |
| 701 | .sel2 (asi_wr_dmmu_tag_access [1 ] ), |
| 702 | .sel3 (asi_wr_dmmu_demap_p [1 ] ), |
| 703 | .sel4 (asi_wr_dmmu_demap_s_n [1 ] ), |
| 704 | .sel5 (htc_wr_dtlb_tag_access [1 ] ), //HWTW Write DTLB Tag Access |
| 705 | .en (asi_d_tag_access_en [1 ] ), |
| 706 | .dout (dmmu_tag_access_1 [47:0] ), |
| 707 | .clk(clk), |
| 708 | .soclk(soclk), |
| 709 | .pce_ov(pce_ov), |
| 710 | .stop(stop) |
| 711 | ); |
| 712 | |
| 713 | mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 dmmu_tag_access_0_lat ( |
| 714 | .scan_in(dmmu_tag_access_0_lat_wmr_scanin), |
| 715 | .scan_out(dmmu_tag_access_0_lat_wmr_scanout), |
| 716 | .siclk(spc_aclk_wmr), |
| 717 | .se (tcu_scan_en_wmr ), |
| 718 | .din0 ({ase_lsu_va_w [47:13], |
| 719 | ase_lsu_context_w [12:0]}), |
| 720 | .din1 ({ase_lsu_va_w [47:13], |
| 721 | {13 {1'b0}} }), |
| 722 | .din2 (asi_wr_data [47:0] ), |
| 723 | .din3 ({asi_wr_data [47:40], // Demap VA[47:40] in data |
| 724 | asi_mra_wr_data [39:13], |
| 725 | p_context_0_0 [12:0]}), |
| 726 | .din4 ({asi_wr_data [47:40], // Demap VA[47:40] in data |
| 727 | asi_mra_wr_data [39:13], |
| 728 | {13 {1'b0}} }), |
| 729 | .din5 (htd_tagaccess_din [47:0] ), |
| 730 | .din6 (dmmu_tag_access_0 [47:0] ), |
| 731 | .sel0 (tlu_load_d_tag_access [0 ] ), |
| 732 | .sel1 (tlu_load_d_tag_access_r[0 ] ), |
| 733 | .sel2 (asi_wr_dmmu_tag_access [0 ] ), |
| 734 | .sel3 (asi_wr_dmmu_demap_p [0 ] ), |
| 735 | .sel4 (asi_wr_dmmu_demap_s_n [0 ] ), |
| 736 | .sel5 (htc_wr_dtlb_tag_access [0 ] ), //HWTW Write DTLB Tag Access |
| 737 | .en (asi_d_tag_access_en [0 ] ), |
| 738 | .dout (dmmu_tag_access_0 [47:0] ), |
| 739 | .clk(clk), |
| 740 | .soclk(soclk), |
| 741 | .pce_ov(pce_ov), |
| 742 | .stop(stop) |
| 743 | ); |
| 744 | |
| 745 | mmu_asd_dp_mux_macro__mux_aonpe__ports_8__width_62 dmmu_access_target_mux ( |
| 746 | .din0 ({{14 {dmmu_tag_access_0[47 ]}}, |
| 747 | dmmu_tag_access_0 [47:0]}), |
| 748 | .din1 ({{14 {dmmu_tag_access_1[47 ]}}, |
| 749 | dmmu_tag_access_1 [47:0]}), |
| 750 | .din2 ({{14 {dmmu_tag_access_2[47 ]}}, |
| 751 | dmmu_tag_access_2 [47:0]}), |
| 752 | .din3 ({{14 {dmmu_tag_access_3[47 ]}}, |
| 753 | dmmu_tag_access_3 [47:0]}), |
| 754 | .din4 ({1'b0 , |
| 755 | dmmu_tag_access_0 [12:0], |
| 756 | {6 {1'b0}} , |
| 757 | {16 {dmmu_tag_access_0[47 ]}}, |
| 758 | dmmu_tag_access_0 [47:22]}), // tag target |
| 759 | .din5 ({1'b0 , |
| 760 | dmmu_tag_access_1 [12:0], |
| 761 | {6 {1'b0}} , |
| 762 | {16 {dmmu_tag_access_1[47 ]}}, |
| 763 | dmmu_tag_access_1 [47:22]}), // tag target |
| 764 | .din6 ({1'b0 , |
| 765 | dmmu_tag_access_2 [12:0], |
| 766 | {6 {1'b0}} , |
| 767 | {16 {dmmu_tag_access_2[47 ]}}, |
| 768 | dmmu_tag_access_2 [47:22]}), // tag target |
| 769 | .din7 ({1'b0 , |
| 770 | dmmu_tag_access_3 [12:0], |
| 771 | {6 {1'b0}} , |
| 772 | {16 {dmmu_tag_access_3[47 ]}}, |
| 773 | dmmu_tag_access_3 [47:22]}), // tag target |
| 774 | .sel0 (asi_rd_dmmu_tag_access [0 ] ), |
| 775 | .sel1 (asi_rd_dmmu_tag_access [1 ] ), |
| 776 | .sel2 (asi_rd_dmmu_tag_access [2 ] ), |
| 777 | .sel3 (asi_rd_dmmu_tag_access [3 ] ), |
| 778 | .sel4 (asi_rd_dmmu_tag_target [0 ] ), |
| 779 | .sel5 (asi_rd_dmmu_tag_target [1 ] ), |
| 780 | .sel6 (asi_rd_dmmu_tag_target [2 ] ), |
| 781 | .sel7 (asi_rd_dmmu_tag_target [3 ] ), |
| 782 | .dout (dmmu_access_target [61:0] ) |
| 783 | ); |
| 784 | |
| 785 | mmu_asd_dp_mux_macro__mux_aodec__ports_8__stack_58c__width_13 tag_access_crit_mux ( |
| 786 | .din0 (immu_tag_access_0 [12:0] ), |
| 787 | .din1 (immu_tag_access_1 [12:0] ), |
| 788 | .din2 (immu_tag_access_2 [12:0] ), |
| 789 | .din3 (immu_tag_access_3 [12:0] ), |
| 790 | .din4 (dmmu_tag_access_0 [12:0] ), |
| 791 | .din5 (dmmu_tag_access_1 [12:0] ), |
| 792 | .din6 (dmmu_tag_access_2 [12:0] ), |
| 793 | .din7 (dmmu_tag_access_3 [12:0] ), |
| 794 | .sel (asi_tag_access_sel [2:0] ), |
| 795 | .dout (tag_access [12:0] ) |
| 796 | ); |
| 797 | |
| 798 | mmu_asd_dp_buff_macro__stack_58c__width_3 tag_access_sel_buf ( |
| 799 | .din (asi_tag_access_sel [2:0] ), |
| 800 | .dout (tag_access_sel [2:0] ) |
| 801 | ); |
| 802 | mmu_asd_dp_mux_macro__left_13__mux_aodec__ports_8__stack_58c__width_35 tag_access_mux ( |
| 803 | .din0 (immu_tag_access_0 [47:13] ), |
| 804 | .din1 (immu_tag_access_1 [47:13] ), |
| 805 | .din2 (immu_tag_access_2 [47:13] ), |
| 806 | .din3 (immu_tag_access_3 [47:13] ), |
| 807 | .din4 (dmmu_tag_access_0 [47:13] ), |
| 808 | .din5 (dmmu_tag_access_1 [47:13] ), |
| 809 | .din6 (dmmu_tag_access_2 [47:13] ), |
| 810 | .din7 (dmmu_tag_access_3 [47:13] ), |
| 811 | .sel (tag_access_sel [2:0] ), |
| 812 | .dout (tag_access [47:13] ) |
| 813 | ); |
| 814 | |
| 815 | mmu_asd_dp_buff_macro__rep_1__stack_58c__width_48 tag_access_buf ( |
| 816 | .din (tag_access [47:0] ), |
| 817 | .dout (asd_tag_access [47:0] ) |
| 818 | ); |
| 819 | |
| 820 | mmu_asd_dp_zero_macro__width_16 zero_context_cmp ( |
| 821 | .din ({{3 {1'b0}}, |
| 822 | tag_access [12:0]}), |
| 823 | .dout (zero_context ) |
| 824 | ); |
| 825 | |
| 826 | mmu_asd_dp_nor_macro__ports_2__width_1 bit1_nor ( |
| 827 | .din0 (zero_context ), |
| 828 | .din1 (asi_rd_tsb_ptr_ ), |
| 829 | .dout (bit1 ) |
| 830 | ); |
| 831 | |
| 832 | mmu_asd_dp_or_macro__ports_2__width_1 bit1_or ( |
| 833 | .din0 (bit1 ), |
| 834 | .din1 (asi_mra_rd_addr_bit_1 ), |
| 835 | .dout (asd_mra_rd_addr_bit_1 ) |
| 836 | ); |
| 837 | |
| 838 | mmu_asd_dp_buff_macro__rep_1__width_2 zero_context_buf ( |
| 839 | .din ({2 {zero_context }}), |
| 840 | .dout ({asd_zero_context , |
| 841 | asd_asi_zero_context }) |
| 842 | ); |
| 843 | |
| 844 | mmu_asd_dp_msff_macro__mux_aonpe__ports_2__width_62 asi_rd_mux ( |
| 845 | .scan_in(asi_rd_mux_scanin), |
| 846 | .scan_out(asi_rd_mux_scanout), |
| 847 | .din0 (immu_access_target [61:0] ), |
| 848 | .din1 (dmmu_access_target [61:0] ), |
| 849 | .sel0 (asi_rd_i_access_target ), |
| 850 | .sel1 (asi_rd_d_access_target ), |
| 851 | .en (asi_rd_access_target ), |
| 852 | .dout (asd_asi_rd_data [61:0] ), |
| 853 | .clk(clk), |
| 854 | .se(se), |
| 855 | .siclk(siclk), |
| 856 | .soclk(soclk), |
| 857 | .pce_ov(pce_ov), |
| 858 | .stop(stop) |
| 859 | ); |
| 860 | |
| 861 | assign asd_asi_rd_data[63:62] = |
| 862 | {2 {asd_asi_rd_data[61]}}; |
| 863 | |
| 864 | mmu_asd_dp_and_macro__ports_2__stack_58c__width_8 ps_eq_256m_and ( |
| 865 | .din0 ({itlb_data_in_0 [2 ], |
| 866 | itlb_data_in_1 [2 ], |
| 867 | itlb_data_in_2 [2 ], |
| 868 | itlb_data_in_3 [2 ], |
| 869 | dtlb_data_in_0 [2 ], |
| 870 | dtlb_data_in_1 [2 ], |
| 871 | dtlb_data_in_2 [2 ], |
| 872 | dtlb_data_in_3 [2 ]}), |
| 873 | .din1 ({itlb_data_in_0 [0 ], |
| 874 | itlb_data_in_1 [0 ], |
| 875 | itlb_data_in_2 [0 ], |
| 876 | itlb_data_in_3 [0 ], |
| 877 | dtlb_data_in_0 [0 ], |
| 878 | dtlb_data_in_1 [0 ], |
| 879 | dtlb_data_in_2 [0 ], |
| 880 | dtlb_data_in_3 [0 ]}), |
| 881 | .dout ({itlb_ps_eq_256m_0 , |
| 882 | itlb_ps_eq_256m_1 , |
| 883 | itlb_ps_eq_256m_2 , |
| 884 | itlb_ps_eq_256m_3 , |
| 885 | dtlb_ps_eq_256m_0 , |
| 886 | dtlb_ps_eq_256m_1 , |
| 887 | dtlb_ps_eq_256m_2 , |
| 888 | dtlb_ps_eq_256m_3 }) |
| 889 | ); |
| 890 | |
| 891 | mmu_asd_dp_or_macro__ports_2__stack_58c__width_8 ps_gt_64k_or ( |
| 892 | .din0 ({itlb_data_in_0 [2 ], |
| 893 | itlb_data_in_1 [2 ], |
| 894 | itlb_data_in_2 [2 ], |
| 895 | itlb_data_in_3 [2 ], |
| 896 | dtlb_data_in_0 [2 ], |
| 897 | dtlb_data_in_1 [2 ], |
| 898 | dtlb_data_in_2 [2 ], |
| 899 | dtlb_data_in_3 [2 ]}), |
| 900 | .din1 ({itlb_data_in_0 [1 ], |
| 901 | itlb_data_in_1 [1 ], |
| 902 | itlb_data_in_2 [1 ], |
| 903 | itlb_data_in_3 [1 ], |
| 904 | dtlb_data_in_0 [1 ], |
| 905 | dtlb_data_in_1 [1 ], |
| 906 | dtlb_data_in_2 [1 ], |
| 907 | dtlb_data_in_3 [1 ]}), |
| 908 | .dout ({itlb_ps_gt_64k_0 , |
| 909 | itlb_ps_gt_64k_1 , |
| 910 | itlb_ps_gt_64k_2 , |
| 911 | itlb_ps_gt_64k_3 , |
| 912 | dtlb_ps_gt_64k_0 , |
| 913 | dtlb_ps_gt_64k_1 , |
| 914 | dtlb_ps_gt_64k_2 , |
| 915 | dtlb_ps_gt_64k_3 }) |
| 916 | ); |
| 917 | |
| 918 | mmu_asd_dp_or_macro__ports_3__stack_58c__width_8 ps_gt_8k_or ( |
| 919 | .din0 ({itlb_data_in_0 [2 ], |
| 920 | itlb_data_in_1 [2 ], |
| 921 | itlb_data_in_2 [2 ], |
| 922 | itlb_data_in_3 [2 ], |
| 923 | dtlb_data_in_0 [2 ], |
| 924 | dtlb_data_in_1 [2 ], |
| 925 | dtlb_data_in_2 [2 ], |
| 926 | dtlb_data_in_3 [2 ]}), |
| 927 | .din1 ({itlb_data_in_0 [1 ], |
| 928 | itlb_data_in_1 [1 ], |
| 929 | itlb_data_in_2 [1 ], |
| 930 | itlb_data_in_3 [1 ], |
| 931 | dtlb_data_in_0 [1 ], |
| 932 | dtlb_data_in_1 [1 ], |
| 933 | dtlb_data_in_2 [1 ], |
| 934 | dtlb_data_in_3 [1 ]}), |
| 935 | .din2 ({itlb_data_in_0 [0 ], |
| 936 | itlb_data_in_1 [0 ], |
| 937 | itlb_data_in_2 [0 ], |
| 938 | itlb_data_in_3 [0 ], |
| 939 | dtlb_data_in_0 [0 ], |
| 940 | dtlb_data_in_1 [0 ], |
| 941 | dtlb_data_in_2 [0 ], |
| 942 | dtlb_data_in_3 [0 ]}), |
| 943 | .dout ({itlb_ps_gt_8k_0 , |
| 944 | itlb_ps_gt_8k_1 , |
| 945 | itlb_ps_gt_8k_2 , |
| 946 | itlb_ps_gt_8k_3 , |
| 947 | dtlb_ps_gt_8k_0 , |
| 948 | dtlb_ps_gt_8k_1 , |
| 949 | dtlb_ps_gt_8k_2 , |
| 950 | dtlb_ps_gt_8k_3 }) |
| 951 | ); |
| 952 | |
| 953 | |
| 954 | mmu_asd_dp_mux_macro__mux_aonpe__ports_4__stack_58c__width_48 itte_tag_mux ( |
| 955 | .din0 ({immu_tag_access_0 [47:28], // VA[47:28] |
| 956 | immu_tag_access_0 [27:22], // VA[27:22] |
| 957 | itlb_ps_eq_256m_0 , |
| 958 | itlb_data_in_0 [38 ], // Valid |
| 959 | itlb_data_in_0 [35 ], // Locked |
| 960 | immu_tag_access_0 [21:16], // VA[21:16] |
| 961 | immu_tag_access_0 [12:0]}), // Context |
| 962 | .din1 ({immu_tag_access_1 [47:28], // VA[47:28] |
| 963 | immu_tag_access_1 [27:22], // VA[27:22] |
| 964 | itlb_ps_eq_256m_1 , |
| 965 | itlb_data_in_1 [38 ], // Valid |
| 966 | itlb_data_in_1 [35 ], // Locked |
| 967 | immu_tag_access_1 [21:16], // VA[21:16] |
| 968 | immu_tag_access_1 [12:0]}), // Context |
| 969 | .din2 ({immu_tag_access_2 [47:28], // VA[47:28] |
| 970 | immu_tag_access_2 [27:22], // VA[27:22] |
| 971 | itlb_ps_eq_256m_2 , |
| 972 | itlb_data_in_2 [38 ], // Valid |
| 973 | itlb_data_in_2 [35 ], // Locked |
| 974 | immu_tag_access_2 [21:16], // VA[21:16] |
| 975 | immu_tag_access_2 [12:0]}), // Context |
| 976 | .din3 ({immu_tag_access_3 [47:28], // VA[47:28] |
| 977 | immu_tag_access_3 [27:22], // VA[27:22] |
| 978 | itlb_ps_eq_256m_3 , |
| 979 | itlb_data_in_3 [38 ], // Valid |
| 980 | itlb_data_in_3 [35 ], // Locked |
| 981 | immu_tag_access_3 [21:16], // VA[21:16] |
| 982 | immu_tag_access_3 [12:0]}), // Context |
| 983 | .sel0 (asi_rd_itte_tag [0 ] ), |
| 984 | .sel1 (asi_rd_itte_tag [1 ] ), |
| 985 | .sel2 (asi_rd_itte_tag [2 ] ), |
| 986 | .sel3 (asi_rd_itte_tag [3 ] ), |
| 987 | .dout (itte_tag [47:0] ) |
| 988 | ); |
| 989 | |
| 990 | mmu_asd_dp_mux_macro__dmux_8x__mux_aope__ports_4__stack_58c__width_48 dtte_tag_mux ( |
| 991 | .din0 ({dmmu_tag_access_0 [47:28], // VA[47:28] |
| 992 | dmmu_tag_access_0 [27:22], // VA[27:22] |
| 993 | dtlb_ps_eq_256m_0 , |
| 994 | dtlb_data_in_0 [38 ], // Valid |
| 995 | dtlb_data_in_0 [35 ], // Locked |
| 996 | dmmu_tag_access_0 [21:16], // VA[21:16] |
| 997 | dmmu_tag_access_0 [12:0]}), // Context |
| 998 | .din1 ({dmmu_tag_access_1 [47:28], // VA[47:28] |
| 999 | dmmu_tag_access_1 [27:22], // VA[27:22] |
| 1000 | dtlb_ps_eq_256m_1 , |
| 1001 | dtlb_data_in_1 [38 ], // Valid |
| 1002 | dtlb_data_in_1 [35 ], // Locked |
| 1003 | dmmu_tag_access_1 [21:16], // VA[21:16] |
| 1004 | dmmu_tag_access_1 [12:0]}), // Context |
| 1005 | .din2 ({dmmu_tag_access_2 [47:28], // VA[47:28] |
| 1006 | dmmu_tag_access_2 [27:22], // VA[27:22] |
| 1007 | dtlb_ps_eq_256m_2 , |
| 1008 | dtlb_data_in_2 [38 ], // Valid |
| 1009 | dtlb_data_in_2 [35 ], // Locked |
| 1010 | dmmu_tag_access_2 [21:16], // VA[21:16] |
| 1011 | dmmu_tag_access_2 [12:0]}), // Context |
| 1012 | .din3 ({dmmu_tag_access_3 [47:28], // VA[47:28] |
| 1013 | dmmu_tag_access_3 [27:22], // VA[27:22] |
| 1014 | dtlb_ps_eq_256m_3 , |
| 1015 | dtlb_data_in_3 [38 ], // Valid |
| 1016 | dtlb_data_in_3 [35 ], // Locked |
| 1017 | dmmu_tag_access_3 [21:16], // VA[21:16] |
| 1018 | dmmu_tag_access_3 [12:0]}), // Context |
| 1019 | .sel0 (asi_rd_dtte [0 ] ), |
| 1020 | .sel1 (asi_rd_dtte [1 ] ), |
| 1021 | .sel2 (asi_rd_dtte [2 ] ), |
| 1022 | .dout (dtte_tag [47:0] ) |
| 1023 | ); |
| 1024 | |
| 1025 | mmu_asd_dp_buff_macro__rep_1__stack_58c__width_48 dtte_tag_buf ( |
| 1026 | .din (dtte_tag [47:0] ), |
| 1027 | .dout (asd_dtte_tag [47:0] ) |
| 1028 | ); |
| 1029 | |
| 1030 | |
| 1031 | assign data_in[38:0] = |
| 1032 | {asi_wr_data [63 ], // V |
| 1033 | asi_wr_data [62 ], // NFO |
| 1034 | asi_data_in_real , // Real |
| 1035 | asi_wr_data [61 ], // Locked |
| 1036 | asi_wr_data [39:13], // PA[39:13] |
| 1037 | asi_wr_data [12 ], // IE |
| 1038 | asi_wr_data [11 ], // Side effect |
| 1039 | asi_wr_data [10 ], // CP |
| 1040 | asi_wr_data [8 ], // P |
| 1041 | asi_wr_data [6 ], // W |
| 1042 | asi_wr_data [2:0]}; // Size |
| 1043 | |
| 1044 | mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_49 itlb_data_in_3_lat ( |
| 1045 | .scan_in(itlb_data_in_3_lat_scanin), |
| 1046 | .scan_out(itlb_data_in_3_lat_scanout), |
| 1047 | .din0 ({{7 {1'b0}} , // Index valid & index |
| 1048 | {3 {1'b0}} , // Demap valid & type |
| 1049 | data_in [38:0]}), |
| 1050 | .din1 ({1'b1 , // Index valid |
| 1051 | asi_mra_wr_data [8:3], // Index to write |
| 1052 | {3 {1'b0}} , // Demap valid & type |
| 1053 | data_in [38:0]}), |
| 1054 | .din2 ({{7 {1'b0}} , // Index valid & index |
| 1055 | 1'b1 , // Demap |
| 1056 | asi_mra_wr_data [7:6], // Demap type field |
| 1057 | itlb_data_in_3 [38:37], |
| 1058 | asi_demap_r_bit , // Demap R bit |
| 1059 | itlb_data_in_3 [35:0]}), |
| 1060 | .din3 ({{7 {1'b0}} , // Index valid & index |
| 1061 | 1'b0 , // Demap valid |
| 1062 | mmu_use_context_1 , // Context type |
| 1063 | mmu_use_context_0 , // Context type |
| 1064 | htd_tlbdatain_din [38:0]}), |
| 1065 | .din4 (itlb_data_in_3 [48:0] ), |
| 1066 | .sel0 (asi_wr_itlb_data_in [3 ] ), // ASI Write |
| 1067 | .sel1 (asi_wr_itlb_data_access[3 ] ), // ASI Write |
| 1068 | .sel2 (asi_wr_immu_demap [3 ] ), |
| 1069 | .sel3 (htc_wr_itlb_data_in [3 ] ), // HWTW Write ITLB Data-In |
| 1070 | .en (asi_i_data_in_en [3 ] ), |
| 1071 | .dout (itlb_data_in_3 [48:0] ), |
| 1072 | .clk(clk), |
| 1073 | .se(se), |
| 1074 | .siclk(siclk), |
| 1075 | .soclk(soclk), |
| 1076 | .pce_ov(pce_ov), |
| 1077 | .stop(stop) |
| 1078 | ); |
| 1079 | |
| 1080 | mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_49 itlb_data_in_2_lat ( |
| 1081 | .scan_in(itlb_data_in_2_lat_scanin), |
| 1082 | .scan_out(itlb_data_in_2_lat_scanout), |
| 1083 | .din0 ({{7 {1'b0}} , // Index valid & index |
| 1084 | {3 {1'b0}} , // Demap valid & type |
| 1085 | data_in [38:0]}), |
| 1086 | .din1 ({1'b1 , // Index valid |
| 1087 | asi_mra_wr_data [8:3], // Index to write |
| 1088 | {3 {1'b0}} , // Demap valid & type |
| 1089 | data_in [38:0]}), |
| 1090 | .din2 ({{7 {1'b0}} , // Index valid & index |
| 1091 | 1'b1 , // Demap |
| 1092 | asi_mra_wr_data [7:6], // Demap type field |
| 1093 | itlb_data_in_2 [38:37], |
| 1094 | asi_demap_r_bit , // Demap R bit |
| 1095 | itlb_data_in_2 [35:0]}), |
| 1096 | .din3 ({{7 {1'b0}} , // Index valid & index |
| 1097 | 1'b0 , // Demap valid |
| 1098 | mmu_use_context_1 , // Context type |
| 1099 | mmu_use_context_0 , // Context type |
| 1100 | htd_tlbdatain_din [38:0]}), |
| 1101 | .din4 (itlb_data_in_2 [48:0] ), |
| 1102 | .sel0 (asi_wr_itlb_data_in [2 ] ), // ASI Write |
| 1103 | .sel1 (asi_wr_itlb_data_access[2 ] ), // ASI Write |
| 1104 | .sel2 (asi_wr_immu_demap [2 ] ), |
| 1105 | .sel3 (htc_wr_itlb_data_in [2 ] ), // HWTW Write ITLB Data-In |
| 1106 | .en (asi_i_data_in_en [2 ] ), |
| 1107 | .dout (itlb_data_in_2 [48:0] ), |
| 1108 | .clk(clk), |
| 1109 | .se(se), |
| 1110 | .siclk(siclk), |
| 1111 | .soclk(soclk), |
| 1112 | .pce_ov(pce_ov), |
| 1113 | .stop(stop) |
| 1114 | ); |
| 1115 | |
| 1116 | mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_49 itlb_data_in_1_lat ( |
| 1117 | .scan_in(itlb_data_in_1_lat_scanin), |
| 1118 | .scan_out(itlb_data_in_1_lat_scanout), |
| 1119 | .din0 ({{7 {1'b0}} , // Index valid & index |
| 1120 | {3 {1'b0}} , // Demap valid & type |
| 1121 | data_in [38:0]}), |
| 1122 | .din1 ({1'b1 , // Index valid |
| 1123 | asi_mra_wr_data [8:3], // Index to write |
| 1124 | {3 {1'b0}} , // Demap valid & type |
| 1125 | data_in [38:0]}), |
| 1126 | .din2 ({{7 {1'b0}} , // Index valid & index |
| 1127 | 1'b1 , // Demap |
| 1128 | asi_mra_wr_data [7:6], // Demap type field |
| 1129 | itlb_data_in_1 [38:37], |
| 1130 | asi_demap_r_bit , // Demap R bit |
| 1131 | itlb_data_in_1 [35:0]}), |
| 1132 | .din3 ({{7 {1'b0}} , // Index valid & index |
| 1133 | 1'b0 , // Demap valid |
| 1134 | mmu_use_context_1 , // Context type |
| 1135 | mmu_use_context_0 , // Context type |
| 1136 | htd_tlbdatain_din [38:0]}), |
| 1137 | .din4 (itlb_data_in_1 [48:0] ), |
| 1138 | .sel0 (asi_wr_itlb_data_in [1 ] ), // ASI Write |
| 1139 | .sel1 (asi_wr_itlb_data_access[1 ] ), // ASI Write |
| 1140 | .sel2 (asi_wr_immu_demap [1 ] ), |
| 1141 | .sel3 (htc_wr_itlb_data_in [1 ] ), // HWTW Write ITLB Data-In |
| 1142 | .en (asi_i_data_in_en [1 ] ), |
| 1143 | .dout (itlb_data_in_1 [48:0] ), |
| 1144 | .clk(clk), |
| 1145 | .se(se), |
| 1146 | .siclk(siclk), |
| 1147 | .soclk(soclk), |
| 1148 | .pce_ov(pce_ov), |
| 1149 | .stop(stop) |
| 1150 | ); |
| 1151 | |
| 1152 | mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_49 itlb_data_in_0_lat ( |
| 1153 | .scan_in(itlb_data_in_0_lat_scanin), |
| 1154 | .scan_out(itlb_data_in_0_lat_scanout), |
| 1155 | .din0 ({{7 {1'b0}} , // Index valid & index |
| 1156 | {3 {1'b0}} , // Demap valid & type |
| 1157 | data_in [38:0]}), |
| 1158 | .din1 ({1'b1 , // Index valid |
| 1159 | asi_mra_wr_data [8:3], // Index to write |
| 1160 | {3 {1'b0}} , // Demap valid & type |
| 1161 | data_in [38:0]}), |
| 1162 | .din2 ({{7 {1'b0}} , // Index valid & index |
| 1163 | 1'b1 , // Demap |
| 1164 | asi_mra_wr_data [7:6], // Demap type field |
| 1165 | itlb_data_in_0 [38:37], |
| 1166 | asi_demap_r_bit , // Demap R bit |
| 1167 | itlb_data_in_0 [35:0]}), |
| 1168 | .din3 ({{7 {1'b0}} , // Index valid & index |
| 1169 | 1'b0 , // Demap valid |
| 1170 | mmu_use_context_1 , // Context type |
| 1171 | mmu_use_context_0 , // Context type |
| 1172 | htd_tlbdatain_din [38:0]}), |
| 1173 | .din4 (itlb_data_in_0 [48:0] ), |
| 1174 | .sel0 (asi_wr_itlb_data_in [0 ] ), // ASI Write |
| 1175 | .sel1 (asi_wr_itlb_data_access[0 ] ), // ASI Write |
| 1176 | .sel2 (asi_wr_immu_demap [0 ] ), |
| 1177 | .sel3 (htc_wr_itlb_data_in [0 ] ), // HWTW Write ITLB Data-In |
| 1178 | .en (asi_i_data_in_en [0 ] ), |
| 1179 | .dout (itlb_data_in_0 [48:0] ), |
| 1180 | .clk(clk), |
| 1181 | .se(se), |
| 1182 | .siclk(siclk), |
| 1183 | .soclk(soclk), |
| 1184 | .pce_ov(pce_ov), |
| 1185 | .stop(stop) |
| 1186 | ); |
| 1187 | |
| 1188 | mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_51 dtlb_data_in_3_lat ( |
| 1189 | .scan_in(dtlb_data_in_3_lat_scanin), |
| 1190 | .scan_out(dtlb_data_in_3_lat_scanout), |
| 1191 | .din0 ({{8 {1'b0}} , // Index valid & index |
| 1192 | {4 {1'b0}} , // Demap valids & type |
| 1193 | data_in [38:0]}), |
| 1194 | .din1 ({1'b1 , // Index valid |
| 1195 | asi_mra_wr_data [9:3], // Index to write |
| 1196 | {4 {1'b0}} , // Demap valids & type |
| 1197 | data_in [38:0]}), |
| 1198 | .din2 ({{8 {1'b0}} , // Index valid & index |
| 1199 | asi_dmmu_demap_s , // Demap secondary context |
| 1200 | 1'b1 , // Demap |
| 1201 | asi_mra_wr_data [7:6], // Demap type field |
| 1202 | dtlb_data_in_3 [38:37], |
| 1203 | asi_demap_r_bit , // Demap R bit |
| 1204 | dtlb_data_in_3 [35:0]}), |
| 1205 | .din3 ({{8 {1'b0}} , // Index valid & index |
| 1206 | mmu_sec_context , // Replace with secondary cxt |
| 1207 | 1'b0 , // Demap valid |
| 1208 | mmu_use_context_1 , // Context type |
| 1209 | mmu_use_context_0 , // Context type |
| 1210 | htd_tlbdatain_din [38:0]}), |
| 1211 | .din4 (dtlb_data_in_3 [50:0] ), |
| 1212 | .sel0 (asi_wr_dtlb_data_in [3 ] ), // ASI Write |
| 1213 | .sel1 (asi_wr_dtlb_data_access[3 ] ), // ASI Write |
| 1214 | .sel2 (asi_wr_dmmu_demap [3 ] ), |
| 1215 | .sel3 (htc_wr_dtlb_data_in [3 ] ), // HWTW Write DTLB Data-In |
| 1216 | .en (asi_d_data_in_en [3 ] ), |
| 1217 | .dout (dtlb_data_in_3 [50:0] ), |
| 1218 | .clk(clk), |
| 1219 | .se(se), |
| 1220 | .siclk(siclk), |
| 1221 | .soclk(soclk), |
| 1222 | .pce_ov(pce_ov), |
| 1223 | .stop(stop) |
| 1224 | ); |
| 1225 | |
| 1226 | mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_51 dtlb_data_in_2_lat ( |
| 1227 | .scan_in(dtlb_data_in_2_lat_scanin), |
| 1228 | .scan_out(dtlb_data_in_2_lat_scanout), |
| 1229 | .din0 ({{8 {1'b0}} , // Index valid & index |
| 1230 | {4 {1'b0}} , // Demap valids & type |
| 1231 | data_in [38:0]}), |
| 1232 | .din1 ({1'b1 , // Index valid |
| 1233 | asi_mra_wr_data [9:3], // Index to write |
| 1234 | {4 {1'b0}} , // Demap valids & type |
| 1235 | data_in [38:0]}), |
| 1236 | .din2 ({{8 {1'b0}} , // Index valid & index |
| 1237 | asi_dmmu_demap_s , // Demap secondary context |
| 1238 | 1'b1 , // Demap |
| 1239 | asi_mra_wr_data [7:6], // Demap type field |
| 1240 | dtlb_data_in_2 [38:37], |
| 1241 | asi_demap_r_bit , // Demap R bit |
| 1242 | dtlb_data_in_2 [35:0]}), |
| 1243 | .din3 ({{8 {1'b0}} , // Index valid & index |
| 1244 | mmu_sec_context , // Replace with secondary cxt |
| 1245 | 1'b0 , // Demap valid |
| 1246 | mmu_use_context_1 , // Context type |
| 1247 | mmu_use_context_0 , // Context type |
| 1248 | htd_tlbdatain_din [38:0]}), |
| 1249 | .din4 (dtlb_data_in_2 [50:0] ), |
| 1250 | .sel0 (asi_wr_dtlb_data_in [2 ] ), // ASI Write |
| 1251 | .sel1 (asi_wr_dtlb_data_access[2 ] ), // ASI Write |
| 1252 | .sel2 (asi_wr_dmmu_demap [2 ] ), |
| 1253 | .sel3 (htc_wr_dtlb_data_in [2 ] ), // HWTW Write DTLB Data-In |
| 1254 | .en (asi_d_data_in_en [2 ] ), |
| 1255 | .dout (dtlb_data_in_2 [50:0] ), |
| 1256 | .clk(clk), |
| 1257 | .se(se), |
| 1258 | .siclk(siclk), |
| 1259 | .soclk(soclk), |
| 1260 | .pce_ov(pce_ov), |
| 1261 | .stop(stop) |
| 1262 | ); |
| 1263 | |
| 1264 | mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_51 dtlb_data_in_1_lat ( |
| 1265 | .scan_in(dtlb_data_in_1_lat_scanin), |
| 1266 | .scan_out(dtlb_data_in_1_lat_scanout), |
| 1267 | .din0 ({{8 {1'b0}} , // Index valid & index |
| 1268 | {4 {1'b0}} , // Demap valids & type |
| 1269 | data_in [38:0]}), |
| 1270 | .din1 ({1'b1 , // Index valid |
| 1271 | asi_mra_wr_data [9:3], // Index to write |
| 1272 | {4 {1'b0}} , // Demap valids & type |
| 1273 | data_in [38:0]}), |
| 1274 | .din2 ({{8 {1'b0}} , // Index valid & index |
| 1275 | asi_dmmu_demap_s , // Demap secondary context |
| 1276 | 1'b1 , // Demap |
| 1277 | asi_mra_wr_data [7:6], // Demap type field |
| 1278 | dtlb_data_in_1 [38:37], |
| 1279 | asi_demap_r_bit , // Demap R bit |
| 1280 | dtlb_data_in_1 [35:0]}), |
| 1281 | .din3 ({{8 {1'b0}} , // Index valid & index |
| 1282 | mmu_sec_context , // Replace with secondary cxt |
| 1283 | 1'b0 , // Demap valid |
| 1284 | mmu_use_context_1 , // Context type |
| 1285 | mmu_use_context_0 , // Context type |
| 1286 | htd_tlbdatain_din [38:0]}), |
| 1287 | .din4 (dtlb_data_in_1 [50:0] ), |
| 1288 | .sel0 (asi_wr_dtlb_data_in [1 ] ), // ASI Write |
| 1289 | .sel1 (asi_wr_dtlb_data_access[1 ] ), // ASI Write |
| 1290 | .sel2 (asi_wr_dmmu_demap [1 ] ), |
| 1291 | .sel3 (htc_wr_dtlb_data_in [1 ] ), // HWTW Write DTLB Data-In |
| 1292 | .en (asi_d_data_in_en [1 ] ), |
| 1293 | .dout (dtlb_data_in_1 [50:0] ), |
| 1294 | .clk(clk), |
| 1295 | .se(se), |
| 1296 | .siclk(siclk), |
| 1297 | .soclk(soclk), |
| 1298 | .pce_ov(pce_ov), |
| 1299 | .stop(stop) |
| 1300 | ); |
| 1301 | |
| 1302 | mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_51 dtlb_data_in_0_lat ( |
| 1303 | .scan_in(dtlb_data_in_0_lat_scanin), |
| 1304 | .scan_out(dtlb_data_in_0_lat_scanout), |
| 1305 | .din0 ({{8 {1'b0}} , // Index valid & index |
| 1306 | {4 {1'b0}} , // Demap valids & type |
| 1307 | data_in [38:0]}), |
| 1308 | .din1 ({1'b1 , // Index valid |
| 1309 | asi_mra_wr_data [9:3], // Index to write |
| 1310 | {4 {1'b0}} , // Demap valids & type |
| 1311 | data_in [38:0]}), |
| 1312 | .din2 ({{8 {1'b0}} , // Index valid & index |
| 1313 | asi_dmmu_demap_s , // Demap secondary context |
| 1314 | 1'b1 , // Demap |
| 1315 | asi_mra_wr_data [7:6], // Demap type field |
| 1316 | dtlb_data_in_0 [38:37], |
| 1317 | asi_demap_r_bit , // Demap R bit |
| 1318 | dtlb_data_in_0 [35:0]}), |
| 1319 | .din3 ({{8 {1'b0}} , // Index valid & index |
| 1320 | mmu_sec_context , // Replace with secondary cxt |
| 1321 | 1'b0 , // Demap valid |
| 1322 | mmu_use_context_1 , // Context type |
| 1323 | mmu_use_context_0 , // Context type |
| 1324 | htd_tlbdatain_din [38:0]}), |
| 1325 | .din4 (dtlb_data_in_0 [50:0] ), |
| 1326 | .sel0 (asi_wr_dtlb_data_in [0 ] ), // ASI Write |
| 1327 | .sel1 (asi_wr_dtlb_data_access[0 ] ), |
| 1328 | .sel2 (asi_wr_dmmu_demap [0 ] ), |
| 1329 | .sel3 (htc_wr_dtlb_data_in [0 ] ), // HWTW Write DTLB Data-In |
| 1330 | .en (asi_d_data_in_en [0 ] ), |
| 1331 | .dout (dtlb_data_in_0 [50:0] ), |
| 1332 | .clk(clk), |
| 1333 | .se(se), |
| 1334 | .siclk(siclk), |
| 1335 | .soclk(soclk), |
| 1336 | .pce_ov(pce_ov), |
| 1337 | .stop(stop) |
| 1338 | ); |
| 1339 | |
| 1340 | |
| 1341 | mmu_asd_dp_mux_macro__dmux_8x__mux_aonpe__ports_4__stack_58c__width_53 itte_data_mux ( |
| 1342 | .din0 ({itlb_data_in_0 [48:39], // Demap info, etc. |
| 1343 | itlb_ps_gt_64k_0 , |
| 1344 | immu_tag_access_0 [15:13], // VA[15:13] |
| 1345 | itlb_ps_gt_8k_0 , |
| 1346 | thread_group , // TID[02] |
| 1347 | 2'b00 , // TID[01:00] |
| 1348 | itlb_data_in_0 [36 ], // Real bit |
| 1349 | itlb_data_in_0 [34:23], // PA[39:28] |
| 1350 | itlb_data_in_0 [22:17], // PA[27:22] |
| 1351 | itlb_data_in_0 [16:11], // PA[21:16] |
| 1352 | itlb_data_in_0 [10:8], // PA[15:13] |
| 1353 | itlb_data_in_0 [38 ], // Valid |
| 1354 | itlb_data_in_0 [37 ], // NFO |
| 1355 | itlb_data_in_0 [7 ], // IE |
| 1356 | itlb_data_in_0 [5 ], // CP |
| 1357 | itlb_data_in_0 [6 ], // E |
| 1358 | itlb_data_in_0 [4 ], // P |
| 1359 | itlb_data_in_0 [3 ]}), // W |
| 1360 | .din1 ({itlb_data_in_1 [48:39], // Demap info, etc. |
| 1361 | itlb_ps_gt_64k_1 , |
| 1362 | immu_tag_access_1 [15:13], // VA[15:13] |
| 1363 | itlb_ps_gt_8k_1 , |
| 1364 | thread_group , // TID[02] |
| 1365 | 2'b01 , // TID[01:00] |
| 1366 | itlb_data_in_1 [36 ], // Real bit |
| 1367 | itlb_data_in_1 [34:23], // PA[39:28] |
| 1368 | itlb_data_in_1 [22:17], // PA[27:22] |
| 1369 | itlb_data_in_1 [16:11], // PA[21:16] |
| 1370 | itlb_data_in_1 [10:8], // PA[15:13] |
| 1371 | itlb_data_in_1 [38 ], // Valid |
| 1372 | itlb_data_in_1 [37 ], // NFO |
| 1373 | itlb_data_in_1 [7 ], // IE |
| 1374 | itlb_data_in_1 [5 ], // CP |
| 1375 | itlb_data_in_1 [6 ], // E |
| 1376 | itlb_data_in_1 [4 ], // P |
| 1377 | itlb_data_in_1 [3 ]}), // W |
| 1378 | .din2 ({itlb_data_in_2 [48:39], // Demap info, etc. |
| 1379 | itlb_ps_gt_64k_2 , |
| 1380 | immu_tag_access_2 [15:13], // VA[15:13] |
| 1381 | itlb_ps_gt_8k_2 , |
| 1382 | thread_group , // TID[02] |
| 1383 | 2'b10 , // TID[01:00] |
| 1384 | itlb_data_in_2 [36 ], // Real bit |
| 1385 | itlb_data_in_2 [34:23], // PA[39:28] |
| 1386 | itlb_data_in_2 [22:17], // PA[27:22] |
| 1387 | itlb_data_in_2 [16:11], // PA[21:16] |
| 1388 | itlb_data_in_2 [10:8], // PA[15:13] |
| 1389 | itlb_data_in_2 [38 ], // Valid |
| 1390 | itlb_data_in_2 [37 ], // NFO |
| 1391 | itlb_data_in_2 [7 ], // IE |
| 1392 | itlb_data_in_2 [5 ], // CP |
| 1393 | itlb_data_in_2 [6 ], // E |
| 1394 | itlb_data_in_2 [4 ], // P |
| 1395 | itlb_data_in_2 [3 ]}), // W |
| 1396 | .din3 ({itlb_data_in_3 [48:39], // Demap info, etc. |
| 1397 | itlb_ps_gt_64k_3 , |
| 1398 | immu_tag_access_3 [15:13], // VA[15:13] |
| 1399 | itlb_ps_gt_8k_3 , |
| 1400 | thread_group , // TID[02] |
| 1401 | 2'b11 , // TID[01:00] |
| 1402 | itlb_data_in_3 [36 ], // Real bit |
| 1403 | itlb_data_in_3 [34:23], // PA[39:28] |
| 1404 | itlb_data_in_3 [22:17], // PA[27:22] |
| 1405 | itlb_data_in_3 [16:11], // PA[21:16] |
| 1406 | itlb_data_in_3 [10:8], // PA[15:13] |
| 1407 | itlb_data_in_3 [38 ], // Valid |
| 1408 | itlb_data_in_3 [37 ], // NFO |
| 1409 | itlb_data_in_3 [7 ], // IE |
| 1410 | itlb_data_in_3 [5 ], // CP |
| 1411 | itlb_data_in_3 [6 ], // E |
| 1412 | itlb_data_in_3 [4 ], // P |
| 1413 | itlb_data_in_3 [3 ]}), // W |
| 1414 | .sel0 (asi_rd_itte_data [0 ] ), |
| 1415 | .sel1 (asi_rd_itte_data [1 ] ), |
| 1416 | .sel2 (asi_rd_itte_data [2 ] ), |
| 1417 | .sel3 (asi_rd_itte_data [3 ] ), |
| 1418 | .dout ({asd_itte_index [6:0], |
| 1419 | itte_data [45:0]}) |
| 1420 | ); |
| 1421 | |
| 1422 | // Merge ITLB tag and data |
| 1423 | mmu_asd_dp_nor_macro__ports_2__stack_58c__width_48 itte_tag_data_b_nor ( |
| 1424 | .din0 (itte_tag [47:0] ), |
| 1425 | .din1 ({2'b00 , |
| 1426 | itte_data [45:0]}), |
| 1427 | .dout (asd_itte_tag_data_ [47:0] ) |
| 1428 | ); |
| 1429 | |
| 1430 | |
| 1431 | mmu_asd_dp_mux_macro__mux_aope__ports_4__stack_58c__width_55 dtte_data_mux ( |
| 1432 | .din0 ({dtlb_data_in_0 [50:39], // Demap info, etc |
| 1433 | dtlb_ps_gt_64k_0 , |
| 1434 | dmmu_tag_access_0 [15:13], // VA[15:13] |
| 1435 | dtlb_ps_gt_8k_0 , |
| 1436 | thread_group , // TID[02] |
| 1437 | 2'b00 , // TID[01:00] |
| 1438 | dtlb_data_in_0 [36 ], // Real bit |
| 1439 | dtlb_data_in_0 [34:23], // PA[39:28] |
| 1440 | dtlb_data_in_0 [22:17], // PA[27:22] |
| 1441 | dtlb_data_in_0 [16:11], // PA[21:16] |
| 1442 | dtlb_data_in_0 [10:8], // PA[15:13] |
| 1443 | dtlb_data_in_0 [38 ], // Valid |
| 1444 | dtlb_data_in_0 [37 ], // NFO |
| 1445 | dtlb_data_in_0 [7 ], // IE |
| 1446 | dtlb_data_in_0 [5 ], // CP |
| 1447 | dtlb_data_in_0 [6 ], // E (Side effect) |
| 1448 | dtlb_data_in_0 [4 ], // P |
| 1449 | dtlb_data_in_0 [3 ]}), // W |
| 1450 | .din1 ({dtlb_data_in_1 [50:39], // Demap info, etc |
| 1451 | dtlb_ps_gt_64k_1 , |
| 1452 | dmmu_tag_access_1 [15:13], // VA[15:13] |
| 1453 | dtlb_ps_gt_8k_1 , |
| 1454 | thread_group , // TID[02] |
| 1455 | 2'b01 , // TID[01:00] |
| 1456 | dtlb_data_in_1 [36 ], // Real bit |
| 1457 | dtlb_data_in_1 [34:23], // PA[39:28] |
| 1458 | dtlb_data_in_1 [22:17], // PA[27:22] |
| 1459 | dtlb_data_in_1 [16:11], // PA[21:16] |
| 1460 | dtlb_data_in_1 [10:8], // PA[15:13] |
| 1461 | dtlb_data_in_1 [38 ], // Valid |
| 1462 | dtlb_data_in_1 [37 ], // NFO |
| 1463 | dtlb_data_in_1 [7 ], // IE |
| 1464 | dtlb_data_in_1 [5 ], // CP |
| 1465 | dtlb_data_in_1 [6 ], // E (Side effect) |
| 1466 | dtlb_data_in_1 [4 ], // P |
| 1467 | dtlb_data_in_1 [3 ]}), // W |
| 1468 | .din2 ({dtlb_data_in_2 [50:39], // Demap info, etc |
| 1469 | dtlb_ps_gt_64k_2 , |
| 1470 | dmmu_tag_access_2 [15:13], // VA[15:13] |
| 1471 | dtlb_ps_gt_8k_2 , |
| 1472 | thread_group , // TID[02] |
| 1473 | 2'b10 , // TID[01:00] |
| 1474 | dtlb_data_in_2 [36 ], // Real bit |
| 1475 | dtlb_data_in_2 [34:23], // PA[39:28] |
| 1476 | dtlb_data_in_2 [22:17], // PA[27:22] |
| 1477 | dtlb_data_in_2 [16:11], // PA[21:16] |
| 1478 | dtlb_data_in_2 [10:8], // PA[15:13] |
| 1479 | dtlb_data_in_2 [38 ], // Valid |
| 1480 | dtlb_data_in_2 [37 ], // NFO |
| 1481 | dtlb_data_in_2 [7 ], // IE |
| 1482 | dtlb_data_in_2 [5 ], // CP |
| 1483 | dtlb_data_in_2 [6 ], // E (Side effect) |
| 1484 | dtlb_data_in_2 [4 ], // P |
| 1485 | dtlb_data_in_2 [3 ]}), // W |
| 1486 | .din3 ({dtlb_data_in_3 [50:39], // Demap info, etc |
| 1487 | dtlb_ps_gt_64k_3 , |
| 1488 | dmmu_tag_access_3 [15:13], // VA[15:13] |
| 1489 | dtlb_ps_gt_8k_3 , |
| 1490 | thread_group , // TID[02] |
| 1491 | 2'b11 , // TID[01:00] |
| 1492 | dtlb_data_in_3 [36 ], // Real bit |
| 1493 | dtlb_data_in_3 [34:23], // PA[39:28] |
| 1494 | dtlb_data_in_3 [22:17], // PA[27:22] |
| 1495 | dtlb_data_in_3 [16:11], // PA[21:16] |
| 1496 | dtlb_data_in_3 [10:8], // PA[15:13] |
| 1497 | dtlb_data_in_3 [38 ], // Valid |
| 1498 | dtlb_data_in_3 [37 ], // NFO |
| 1499 | dtlb_data_in_3 [7 ], // IE |
| 1500 | dtlb_data_in_3 [5 ], // CP |
| 1501 | dtlb_data_in_3 [6 ], // E (Side effect) |
| 1502 | dtlb_data_in_3 [4 ], // P |
| 1503 | dtlb_data_in_3 [3 ]}), // W |
| 1504 | .sel0 (asi_rd_dtte [0 ] ), |
| 1505 | .sel1 (asi_rd_dtte [1 ] ), |
| 1506 | .sel2 (asi_rd_dtte [2 ] ), |
| 1507 | .dout (dtte_data [54:0] ) |
| 1508 | ); |
| 1509 | |
| 1510 | mmu_asd_dp_buff_macro__rep_1__stack_58c__width_55 dtte_data_buf ( |
| 1511 | .din (dtte_data [54:0] ), |
| 1512 | .dout (asd_dtte_data [54:0] ) |
| 1513 | ); |
| 1514 | |
| 1515 | assign asd_iht_p_ctx_0_0 [12:0] = p_context_0_0 [12:0]; |
| 1516 | assign asd_iht_p_ctx_0_1 [12:0] = p_context_0_1 [12:0]; |
| 1517 | assign asd_iht_p_ctx_0_2 [12:0] = p_context_0_2 [12:0]; |
| 1518 | assign asd_iht_p_ctx_0_3 [12:0] = p_context_0_3 [12:0]; |
| 1519 | |
| 1520 | ////////////////////////////////////////////////////////////////////// |
| 1521 | // |
| 1522 | // Scan patch panel |
| 1523 | // |
| 1524 | // fixscan start: |
| 1525 | assign mra_read_1_lat_scanin = scan_in ; |
| 1526 | assign mra_read_0_lat_scanin = mra_read_1_lat_scanout ; |
| 1527 | assign asi_rd_mux_scanin = mra_read_0_lat_scanout ; |
| 1528 | assign itlb_data_in_3_lat_scanin = asi_rd_mux_scanout ; |
| 1529 | assign itlb_data_in_2_lat_scanin = itlb_data_in_3_lat_scanout; |
| 1530 | assign itlb_data_in_1_lat_scanin = itlb_data_in_2_lat_scanout; |
| 1531 | assign itlb_data_in_0_lat_scanin = itlb_data_in_1_lat_scanout; |
| 1532 | assign dtlb_data_in_3_lat_scanin = itlb_data_in_0_lat_scanout; |
| 1533 | assign dtlb_data_in_2_lat_scanin = dtlb_data_in_3_lat_scanout; |
| 1534 | assign dtlb_data_in_1_lat_scanin = dtlb_data_in_2_lat_scanout; |
| 1535 | assign dtlb_data_in_0_lat_scanin = dtlb_data_in_1_lat_scanout; |
| 1536 | assign scan_out = dtlb_data_in_0_lat_scanout; |
| 1537 | |
| 1538 | assign p_context_lat_wmr_scanin = wmr_scan_in ; |
| 1539 | assign immu_tag_access_3_lat_wmr_scanin = p_context_lat_wmr_scanout; |
| 1540 | assign immu_tag_access_2_lat_wmr_scanin = immu_tag_access_3_lat_wmr_scanout; |
| 1541 | assign immu_tag_access_1_lat_wmr_scanin = immu_tag_access_2_lat_wmr_scanout; |
| 1542 | assign immu_tag_access_0_lat_wmr_scanin = immu_tag_access_1_lat_wmr_scanout; |
| 1543 | assign dmmu_tag_access_3_lat_wmr_scanin = immu_tag_access_0_lat_wmr_scanout; |
| 1544 | assign dmmu_tag_access_2_lat_wmr_scanin = dmmu_tag_access_3_lat_wmr_scanout; |
| 1545 | assign dmmu_tag_access_1_lat_wmr_scanin = dmmu_tag_access_2_lat_wmr_scanout; |
| 1546 | assign dmmu_tag_access_0_lat_wmr_scanin = dmmu_tag_access_1_lat_wmr_scanout; |
| 1547 | assign wmr_scan_out = dmmu_tag_access_0_lat_wmr_scanout; |
| 1548 | // fixscan end: |
| 1549 | endmodule |
| 1550 | |
| 1551 | |
| 1552 | // |
| 1553 | // buff macro |
| 1554 | // |
| 1555 | // |
| 1556 | |
| 1557 | |
| 1558 | |
| 1559 | |
| 1560 | |
| 1561 | module mmu_asd_dp_buff_macro__width_4 ( |
| 1562 | din, |
| 1563 | dout); |
| 1564 | input [3:0] din; |
| 1565 | output [3:0] dout; |
| 1566 | |
| 1567 | |
| 1568 | |
| 1569 | |
| 1570 | |
| 1571 | |
| 1572 | buff #(4) d0_0 ( |
| 1573 | .in(din[3:0]), |
| 1574 | .out(dout[3:0]) |
| 1575 | ); |
| 1576 | |
| 1577 | |
| 1578 | |
| 1579 | |
| 1580 | |
| 1581 | |
| 1582 | |
| 1583 | |
| 1584 | endmodule |
| 1585 | |
| 1586 | |
| 1587 | |
| 1588 | |
| 1589 | |
| 1590 | |
| 1591 | |
| 1592 | |
| 1593 | |
| 1594 | // any PARAMS parms go into naming of macro |
| 1595 | |
| 1596 | module mmu_asd_dp_msff_macro__minbuff_1__stack_58c__width_24 ( |
| 1597 | din, |
| 1598 | clk, |
| 1599 | en, |
| 1600 | se, |
| 1601 | scan_in, |
| 1602 | siclk, |
| 1603 | soclk, |
| 1604 | pce_ov, |
| 1605 | stop, |
| 1606 | dout, |
| 1607 | scan_out); |
| 1608 | wire l1clk; |
| 1609 | wire siclk_out; |
| 1610 | wire soclk_out; |
| 1611 | wire [22:0] so; |
| 1612 | |
| 1613 | input [23:0] din; |
| 1614 | |
| 1615 | |
| 1616 | input clk; |
| 1617 | input en; |
| 1618 | input se; |
| 1619 | input scan_in; |
| 1620 | input siclk; |
| 1621 | input soclk; |
| 1622 | input pce_ov; |
| 1623 | input stop; |
| 1624 | |
| 1625 | |
| 1626 | |
| 1627 | output [23:0] dout; |
| 1628 | |
| 1629 | |
| 1630 | output scan_out; |
| 1631 | |
| 1632 | |
| 1633 | |
| 1634 | |
| 1635 | cl_dp1_l1hdr_8x c0_0 ( |
| 1636 | .l2clk(clk), |
| 1637 | .pce(en), |
| 1638 | .aclk(siclk), |
| 1639 | .bclk(soclk), |
| 1640 | .l1clk(l1clk), |
| 1641 | .se(se), |
| 1642 | .pce_ov(pce_ov), |
| 1643 | .stop(stop), |
| 1644 | .siclk_out(siclk_out), |
| 1645 | .soclk_out(soclk_out) |
| 1646 | ); |
| 1647 | dff #(24) d0_0 ( |
| 1648 | .l1clk(l1clk), |
| 1649 | .siclk(siclk_out), |
| 1650 | .soclk(soclk_out), |
| 1651 | .d(din[23:0]), |
| 1652 | .si({scan_in,so[22:0]}), |
| 1653 | .so({so[22:0],scan_out}), |
| 1654 | .q(dout[23:0]) |
| 1655 | ); |
| 1656 | |
| 1657 | |
| 1658 | |
| 1659 | |
| 1660 | |
| 1661 | |
| 1662 | |
| 1663 | |
| 1664 | |
| 1665 | |
| 1666 | |
| 1667 | |
| 1668 | |
| 1669 | |
| 1670 | |
| 1671 | |
| 1672 | |
| 1673 | |
| 1674 | |
| 1675 | |
| 1676 | endmodule |
| 1677 | |
| 1678 | |
| 1679 | |
| 1680 | |
| 1681 | |
| 1682 | |
| 1683 | |
| 1684 | |
| 1685 | |
| 1686 | |
| 1687 | |
| 1688 | |
| 1689 | |
| 1690 | // any PARAMS parms go into naming of macro |
| 1691 | |
| 1692 | module mmu_asd_dp_msff_macro__minbuff_1__stack_58c__width_58 ( |
| 1693 | din, |
| 1694 | clk, |
| 1695 | en, |
| 1696 | se, |
| 1697 | scan_in, |
| 1698 | siclk, |
| 1699 | soclk, |
| 1700 | pce_ov, |
| 1701 | stop, |
| 1702 | dout, |
| 1703 | scan_out); |
| 1704 | wire l1clk; |
| 1705 | wire siclk_out; |
| 1706 | wire soclk_out; |
| 1707 | wire [56:0] so; |
| 1708 | |
| 1709 | input [57:0] din; |
| 1710 | |
| 1711 | |
| 1712 | input clk; |
| 1713 | input en; |
| 1714 | input se; |
| 1715 | input scan_in; |
| 1716 | input siclk; |
| 1717 | input soclk; |
| 1718 | input pce_ov; |
| 1719 | input stop; |
| 1720 | |
| 1721 | |
| 1722 | |
| 1723 | output [57:0] dout; |
| 1724 | |
| 1725 | |
| 1726 | output scan_out; |
| 1727 | |
| 1728 | |
| 1729 | |
| 1730 | |
| 1731 | cl_dp1_l1hdr_8x c0_0 ( |
| 1732 | .l2clk(clk), |
| 1733 | .pce(en), |
| 1734 | .aclk(siclk), |
| 1735 | .bclk(soclk), |
| 1736 | .l1clk(l1clk), |
| 1737 | .se(se), |
| 1738 | .pce_ov(pce_ov), |
| 1739 | .stop(stop), |
| 1740 | .siclk_out(siclk_out), |
| 1741 | .soclk_out(soclk_out) |
| 1742 | ); |
| 1743 | dff #(58) d0_0 ( |
| 1744 | .l1clk(l1clk), |
| 1745 | .siclk(siclk_out), |
| 1746 | .soclk(soclk_out), |
| 1747 | .d(din[57:0]), |
| 1748 | .si({scan_in,so[56:0]}), |
| 1749 | .so({so[56:0],scan_out}), |
| 1750 | .q(dout[57:0]) |
| 1751 | ); |
| 1752 | |
| 1753 | |
| 1754 | |
| 1755 | |
| 1756 | |
| 1757 | |
| 1758 | |
| 1759 | |
| 1760 | |
| 1761 | |
| 1762 | |
| 1763 | |
| 1764 | |
| 1765 | |
| 1766 | |
| 1767 | |
| 1768 | |
| 1769 | |
| 1770 | |
| 1771 | |
| 1772 | endmodule |
| 1773 | |
| 1774 | |
| 1775 | |
| 1776 | |
| 1777 | |
| 1778 | |
| 1779 | |
| 1780 | |
| 1781 | |
| 1782 | |
| 1783 | |
| 1784 | |
| 1785 | |
| 1786 | // any PARAMS parms go into naming of macro |
| 1787 | |
| 1788 | module mmu_asd_dp_msff_macro__mux_aonpe__ports_4__stack_58c__width_52 ( |
| 1789 | din0, |
| 1790 | sel0, |
| 1791 | din1, |
| 1792 | sel1, |
| 1793 | din2, |
| 1794 | sel2, |
| 1795 | din3, |
| 1796 | sel3, |
| 1797 | clk, |
| 1798 | en, |
| 1799 | se, |
| 1800 | scan_in, |
| 1801 | siclk, |
| 1802 | soclk, |
| 1803 | pce_ov, |
| 1804 | stop, |
| 1805 | dout, |
| 1806 | scan_out); |
| 1807 | wire buffout0; |
| 1808 | wire buffout1; |
| 1809 | wire buffout2; |
| 1810 | wire buffout3; |
| 1811 | wire [51:0] muxout; |
| 1812 | wire l1clk; |
| 1813 | wire siclk_out; |
| 1814 | wire soclk_out; |
| 1815 | wire [50:0] so; |
| 1816 | |
| 1817 | input [51:0] din0; |
| 1818 | input sel0; |
| 1819 | input [51:0] din1; |
| 1820 | input sel1; |
| 1821 | input [51:0] din2; |
| 1822 | input sel2; |
| 1823 | input [51:0] din3; |
| 1824 | input sel3; |
| 1825 | |
| 1826 | |
| 1827 | input clk; |
| 1828 | input en; |
| 1829 | input se; |
| 1830 | input scan_in; |
| 1831 | input siclk; |
| 1832 | input soclk; |
| 1833 | input pce_ov; |
| 1834 | input stop; |
| 1835 | |
| 1836 | |
| 1837 | |
| 1838 | output [51:0] dout; |
| 1839 | |
| 1840 | |
| 1841 | output scan_out; |
| 1842 | |
| 1843 | |
| 1844 | |
| 1845 | |
| 1846 | cl_dp1_muxbuff4_8x c1_0 ( |
| 1847 | .in0(sel0), |
| 1848 | .in1(sel1), |
| 1849 | .in2(sel2), |
| 1850 | .in3(sel3), |
| 1851 | .out0(buffout0), |
| 1852 | .out1(buffout1), |
| 1853 | .out2(buffout2), |
| 1854 | .out3(buffout3) |
| 1855 | ); |
| 1856 | mux4s #(52) d1_0 ( |
| 1857 | .sel0(buffout0), |
| 1858 | .sel1(buffout1), |
| 1859 | .sel2(buffout2), |
| 1860 | .sel3(buffout3), |
| 1861 | .in0(din0[51:0]), |
| 1862 | .in1(din1[51:0]), |
| 1863 | .in2(din2[51:0]), |
| 1864 | .in3(din3[51:0]), |
| 1865 | .dout(muxout[51:0]) |
| 1866 | ); |
| 1867 | cl_dp1_l1hdr_8x c0_0 ( |
| 1868 | .l2clk(clk), |
| 1869 | .pce(en), |
| 1870 | .aclk(siclk), |
| 1871 | .bclk(soclk), |
| 1872 | .l1clk(l1clk), |
| 1873 | .se(se), |
| 1874 | .pce_ov(pce_ov), |
| 1875 | .stop(stop), |
| 1876 | .siclk_out(siclk_out), |
| 1877 | .soclk_out(soclk_out) |
| 1878 | ); |
| 1879 | dff #(52) d0_0 ( |
| 1880 | .l1clk(l1clk), |
| 1881 | .siclk(siclk_out), |
| 1882 | .soclk(soclk_out), |
| 1883 | .d(muxout[51:0]), |
| 1884 | .si({scan_in,so[50:0]}), |
| 1885 | .so({so[50:0],scan_out}), |
| 1886 | .q(dout[51:0]) |
| 1887 | ); |
| 1888 | |
| 1889 | |
| 1890 | |
| 1891 | |
| 1892 | |
| 1893 | |
| 1894 | |
| 1895 | |
| 1896 | |
| 1897 | |
| 1898 | |
| 1899 | |
| 1900 | |
| 1901 | |
| 1902 | |
| 1903 | |
| 1904 | |
| 1905 | |
| 1906 | |
| 1907 | |
| 1908 | endmodule |
| 1909 | |
| 1910 | |
| 1911 | |
| 1912 | |
| 1913 | |
| 1914 | |
| 1915 | |
| 1916 | |
| 1917 | |
| 1918 | // |
| 1919 | // buff macro |
| 1920 | // |
| 1921 | // |
| 1922 | |
| 1923 | |
| 1924 | |
| 1925 | |
| 1926 | |
| 1927 | module mmu_asd_dp_buff_macro__left_13__stack_58c__width_35 ( |
| 1928 | din, |
| 1929 | dout); |
| 1930 | input [34:0] din; |
| 1931 | output [34:0] dout; |
| 1932 | |
| 1933 | |
| 1934 | |
| 1935 | |
| 1936 | |
| 1937 | |
| 1938 | buff #(35) d0_0 ( |
| 1939 | .in(din[34:0]), |
| 1940 | .out(dout[34:0]) |
| 1941 | ); |
| 1942 | |
| 1943 | |
| 1944 | |
| 1945 | |
| 1946 | |
| 1947 | |
| 1948 | |
| 1949 | |
| 1950 | endmodule |
| 1951 | |
| 1952 | |
| 1953 | |
| 1954 | |
| 1955 | |
| 1956 | |
| 1957 | |
| 1958 | |
| 1959 | |
| 1960 | // any PARAMS parms go into naming of macro |
| 1961 | |
| 1962 | module mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 ( |
| 1963 | din0, |
| 1964 | din1, |
| 1965 | din2, |
| 1966 | din3, |
| 1967 | din4, |
| 1968 | din5, |
| 1969 | din6, |
| 1970 | sel0, |
| 1971 | sel1, |
| 1972 | sel2, |
| 1973 | sel3, |
| 1974 | sel4, |
| 1975 | sel5, |
| 1976 | clk, |
| 1977 | en, |
| 1978 | se, |
| 1979 | scan_in, |
| 1980 | siclk, |
| 1981 | soclk, |
| 1982 | pce_ov, |
| 1983 | stop, |
| 1984 | dout, |
| 1985 | scan_out); |
| 1986 | wire psel0; |
| 1987 | wire psel1; |
| 1988 | wire psel2; |
| 1989 | wire psel3; |
| 1990 | wire psel4; |
| 1991 | wire psel5; |
| 1992 | wire psel6; |
| 1993 | wire [47:0] muxout; |
| 1994 | wire l1clk; |
| 1995 | wire siclk_out; |
| 1996 | wire soclk_out; |
| 1997 | wire [46:0] so; |
| 1998 | |
| 1999 | input [47:0] din0; |
| 2000 | input [47:0] din1; |
| 2001 | input [47:0] din2; |
| 2002 | input [47:0] din3; |
| 2003 | input [47:0] din4; |
| 2004 | input [47:0] din5; |
| 2005 | input [47:0] din6; |
| 2006 | input sel0; |
| 2007 | input sel1; |
| 2008 | input sel2; |
| 2009 | input sel3; |
| 2010 | input sel4; |
| 2011 | input sel5; |
| 2012 | |
| 2013 | |
| 2014 | input clk; |
| 2015 | input en; |
| 2016 | input se; |
| 2017 | input scan_in; |
| 2018 | input siclk; |
| 2019 | input soclk; |
| 2020 | input pce_ov; |
| 2021 | input stop; |
| 2022 | |
| 2023 | |
| 2024 | |
| 2025 | output [47:0] dout; |
| 2026 | |
| 2027 | |
| 2028 | output scan_out; |
| 2029 | |
| 2030 | |
| 2031 | |
| 2032 | |
| 2033 | cl_dp1_penc7_8x c1_0 ( |
| 2034 | .test(1'b1), |
| 2035 | .sel0(sel0), |
| 2036 | .sel1(sel1), |
| 2037 | .sel2(sel2), |
| 2038 | .sel3(sel3), |
| 2039 | .sel4(sel4), |
| 2040 | .sel5(sel5), |
| 2041 | .psel0(psel0), |
| 2042 | .psel1(psel1), |
| 2043 | .psel2(psel2), |
| 2044 | .psel3(psel3), |
| 2045 | .psel4(psel4), |
| 2046 | .psel5(psel5), |
| 2047 | .psel6(psel6) |
| 2048 | ); |
| 2049 | |
| 2050 | mux7s #(48) d1_0 ( |
| 2051 | .sel0(psel0), |
| 2052 | .sel1(psel1), |
| 2053 | .sel2(psel2), |
| 2054 | .sel3(psel3), |
| 2055 | .sel4(psel4), |
| 2056 | .sel5(psel5), |
| 2057 | .sel6(psel6), |
| 2058 | .in0(din0[47:0]), |
| 2059 | .in1(din1[47:0]), |
| 2060 | .in2(din2[47:0]), |
| 2061 | .in3(din3[47:0]), |
| 2062 | .in4(din4[47:0]), |
| 2063 | .in5(din5[47:0]), |
| 2064 | .in6(din6[47:0]), |
| 2065 | .dout(muxout[47:0]) |
| 2066 | ); |
| 2067 | cl_dp1_l1hdr_8x c0_0 ( |
| 2068 | .l2clk(clk), |
| 2069 | .pce(en), |
| 2070 | .aclk(siclk), |
| 2071 | .bclk(soclk), |
| 2072 | .l1clk(l1clk), |
| 2073 | .se(se), |
| 2074 | .pce_ov(pce_ov), |
| 2075 | .stop(stop), |
| 2076 | .siclk_out(siclk_out), |
| 2077 | .soclk_out(soclk_out) |
| 2078 | ); |
| 2079 | dff #(48) d0_0 ( |
| 2080 | .l1clk(l1clk), |
| 2081 | .siclk(siclk_out), |
| 2082 | .soclk(soclk_out), |
| 2083 | .d(muxout[47:0]), |
| 2084 | .si({scan_in,so[46:0]}), |
| 2085 | .so({so[46:0],scan_out}), |
| 2086 | .q(dout[47:0]) |
| 2087 | ); |
| 2088 | |
| 2089 | |
| 2090 | |
| 2091 | |
| 2092 | |
| 2093 | |
| 2094 | |
| 2095 | |
| 2096 | |
| 2097 | |
| 2098 | |
| 2099 | |
| 2100 | |
| 2101 | |
| 2102 | |
| 2103 | |
| 2104 | |
| 2105 | |
| 2106 | |
| 2107 | |
| 2108 | endmodule |
| 2109 | |
| 2110 | |
| 2111 | |
| 2112 | |
| 2113 | |
| 2114 | |
| 2115 | |
| 2116 | |
| 2117 | |
| 2118 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2119 | // also for pass-gate with decoder |
| 2120 | |
| 2121 | |
| 2122 | |
| 2123 | |
| 2124 | |
| 2125 | // any PARAMS parms go into naming of macro |
| 2126 | |
| 2127 | module mmu_asd_dp_mux_macro__mux_aonpe__ports_8__width_62 ( |
| 2128 | din0, |
| 2129 | sel0, |
| 2130 | din1, |
| 2131 | sel1, |
| 2132 | din2, |
| 2133 | sel2, |
| 2134 | din3, |
| 2135 | sel3, |
| 2136 | din4, |
| 2137 | sel4, |
| 2138 | din5, |
| 2139 | sel5, |
| 2140 | din6, |
| 2141 | sel6, |
| 2142 | din7, |
| 2143 | sel7, |
| 2144 | dout); |
| 2145 | wire buffout0; |
| 2146 | wire buffout1; |
| 2147 | wire buffout2; |
| 2148 | wire buffout3; |
| 2149 | wire buffout4; |
| 2150 | wire buffout5; |
| 2151 | wire buffout6; |
| 2152 | wire buffout7; |
| 2153 | |
| 2154 | input [61:0] din0; |
| 2155 | input sel0; |
| 2156 | input [61:0] din1; |
| 2157 | input sel1; |
| 2158 | input [61:0] din2; |
| 2159 | input sel2; |
| 2160 | input [61:0] din3; |
| 2161 | input sel3; |
| 2162 | input [61:0] din4; |
| 2163 | input sel4; |
| 2164 | input [61:0] din5; |
| 2165 | input sel5; |
| 2166 | input [61:0] din6; |
| 2167 | input sel6; |
| 2168 | input [61:0] din7; |
| 2169 | input sel7; |
| 2170 | output [61:0] dout; |
| 2171 | |
| 2172 | |
| 2173 | |
| 2174 | |
| 2175 | |
| 2176 | cl_dp1_muxbuff8_8x c0_0 ( |
| 2177 | .in0(sel0), |
| 2178 | .in1(sel1), |
| 2179 | .in2(sel2), |
| 2180 | .in3(sel3), |
| 2181 | .in4(sel4), |
| 2182 | .in5(sel5), |
| 2183 | .in6(sel6), |
| 2184 | .in7(sel7), |
| 2185 | .out0(buffout0), |
| 2186 | .out1(buffout1), |
| 2187 | .out2(buffout2), |
| 2188 | .out3(buffout3), |
| 2189 | .out4(buffout4), |
| 2190 | .out5(buffout5), |
| 2191 | .out6(buffout6), |
| 2192 | .out7(buffout7) |
| 2193 | ); |
| 2194 | mux8s #(62) d0_0 ( |
| 2195 | .sel0(buffout0), |
| 2196 | .sel1(buffout1), |
| 2197 | .sel2(buffout2), |
| 2198 | .sel3(buffout3), |
| 2199 | .sel4(buffout4), |
| 2200 | .sel5(buffout5), |
| 2201 | .sel6(buffout6), |
| 2202 | .sel7(buffout7), |
| 2203 | .in0(din0[61:0]), |
| 2204 | .in1(din1[61:0]), |
| 2205 | .in2(din2[61:0]), |
| 2206 | .in3(din3[61:0]), |
| 2207 | .in4(din4[61:0]), |
| 2208 | .in5(din5[61:0]), |
| 2209 | .in6(din6[61:0]), |
| 2210 | .in7(din7[61:0]), |
| 2211 | .dout(dout[61:0]) |
| 2212 | ); |
| 2213 | |
| 2214 | |
| 2215 | |
| 2216 | |
| 2217 | |
| 2218 | |
| 2219 | |
| 2220 | |
| 2221 | |
| 2222 | |
| 2223 | |
| 2224 | |
| 2225 | |
| 2226 | endmodule |
| 2227 | |
| 2228 | |
| 2229 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2230 | // also for pass-gate with decoder |
| 2231 | |
| 2232 | |
| 2233 | |
| 2234 | |
| 2235 | |
| 2236 | // any PARAMS parms go into naming of macro |
| 2237 | |
| 2238 | module mmu_asd_dp_mux_macro__mux_aodec__ports_8__stack_58c__width_13 ( |
| 2239 | din0, |
| 2240 | din1, |
| 2241 | din2, |
| 2242 | din3, |
| 2243 | din4, |
| 2244 | din5, |
| 2245 | din6, |
| 2246 | din7, |
| 2247 | sel, |
| 2248 | dout); |
| 2249 | wire psel0; |
| 2250 | wire psel1; |
| 2251 | wire psel2; |
| 2252 | wire psel3; |
| 2253 | wire psel4; |
| 2254 | wire psel5; |
| 2255 | wire psel6; |
| 2256 | wire psel7; |
| 2257 | |
| 2258 | input [12:0] din0; |
| 2259 | input [12:0] din1; |
| 2260 | input [12:0] din2; |
| 2261 | input [12:0] din3; |
| 2262 | input [12:0] din4; |
| 2263 | input [12:0] din5; |
| 2264 | input [12:0] din6; |
| 2265 | input [12:0] din7; |
| 2266 | input [2:0] sel; |
| 2267 | output [12:0] dout; |
| 2268 | |
| 2269 | |
| 2270 | |
| 2271 | |
| 2272 | |
| 2273 | cl_dp1_pdec8_8x c0_0 ( |
| 2274 | .test(1'b1), |
| 2275 | .sel0(sel[0]), |
| 2276 | .sel1(sel[1]), |
| 2277 | .sel2(sel[2]), |
| 2278 | .psel0(psel0), |
| 2279 | .psel1(psel1), |
| 2280 | .psel2(psel2), |
| 2281 | .psel3(psel3), |
| 2282 | .psel4(psel4), |
| 2283 | .psel5(psel5), |
| 2284 | .psel6(psel6), |
| 2285 | .psel7(psel7) |
| 2286 | ); |
| 2287 | |
| 2288 | mux8s #(13) d0_0 ( |
| 2289 | .sel0(psel0), |
| 2290 | .sel1(psel1), |
| 2291 | .sel2(psel2), |
| 2292 | .sel3(psel3), |
| 2293 | .sel4(psel4), |
| 2294 | .sel5(psel5), |
| 2295 | .sel6(psel6), |
| 2296 | .sel7(psel7), |
| 2297 | .in0(din0[12:0]), |
| 2298 | .in1(din1[12:0]), |
| 2299 | .in2(din2[12:0]), |
| 2300 | .in3(din3[12:0]), |
| 2301 | .in4(din4[12:0]), |
| 2302 | .in5(din5[12:0]), |
| 2303 | .in6(din6[12:0]), |
| 2304 | .in7(din7[12:0]), |
| 2305 | .dout(dout[12:0]) |
| 2306 | ); |
| 2307 | |
| 2308 | |
| 2309 | |
| 2310 | |
| 2311 | |
| 2312 | |
| 2313 | |
| 2314 | |
| 2315 | |
| 2316 | |
| 2317 | |
| 2318 | |
| 2319 | |
| 2320 | endmodule |
| 2321 | |
| 2322 | |
| 2323 | // |
| 2324 | // buff macro |
| 2325 | // |
| 2326 | // |
| 2327 | |
| 2328 | |
| 2329 | |
| 2330 | |
| 2331 | |
| 2332 | module mmu_asd_dp_buff_macro__stack_58c__width_3 ( |
| 2333 | din, |
| 2334 | dout); |
| 2335 | input [2:0] din; |
| 2336 | output [2:0] dout; |
| 2337 | |
| 2338 | |
| 2339 | |
| 2340 | |
| 2341 | |
| 2342 | |
| 2343 | buff #(3) d0_0 ( |
| 2344 | .in(din[2:0]), |
| 2345 | .out(dout[2:0]) |
| 2346 | ); |
| 2347 | |
| 2348 | |
| 2349 | |
| 2350 | |
| 2351 | |
| 2352 | |
| 2353 | |
| 2354 | |
| 2355 | endmodule |
| 2356 | |
| 2357 | |
| 2358 | |
| 2359 | |
| 2360 | |
| 2361 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2362 | // also for pass-gate with decoder |
| 2363 | |
| 2364 | |
| 2365 | |
| 2366 | |
| 2367 | |
| 2368 | // any PARAMS parms go into naming of macro |
| 2369 | |
| 2370 | module mmu_asd_dp_mux_macro__left_13__mux_aodec__ports_8__stack_58c__width_35 ( |
| 2371 | din0, |
| 2372 | din1, |
| 2373 | din2, |
| 2374 | din3, |
| 2375 | din4, |
| 2376 | din5, |
| 2377 | din6, |
| 2378 | din7, |
| 2379 | sel, |
| 2380 | dout); |
| 2381 | wire psel0; |
| 2382 | wire psel1; |
| 2383 | wire psel2; |
| 2384 | wire psel3; |
| 2385 | wire psel4; |
| 2386 | wire psel5; |
| 2387 | wire psel6; |
| 2388 | wire psel7; |
| 2389 | |
| 2390 | input [34:0] din0; |
| 2391 | input [34:0] din1; |
| 2392 | input [34:0] din2; |
| 2393 | input [34:0] din3; |
| 2394 | input [34:0] din4; |
| 2395 | input [34:0] din5; |
| 2396 | input [34:0] din6; |
| 2397 | input [34:0] din7; |
| 2398 | input [2:0] sel; |
| 2399 | output [34:0] dout; |
| 2400 | |
| 2401 | |
| 2402 | |
| 2403 | |
| 2404 | |
| 2405 | cl_dp1_pdec8_8x c0_0 ( |
| 2406 | .test(1'b1), |
| 2407 | .sel0(sel[0]), |
| 2408 | .sel1(sel[1]), |
| 2409 | .sel2(sel[2]), |
| 2410 | .psel0(psel0), |
| 2411 | .psel1(psel1), |
| 2412 | .psel2(psel2), |
| 2413 | .psel3(psel3), |
| 2414 | .psel4(psel4), |
| 2415 | .psel5(psel5), |
| 2416 | .psel6(psel6), |
| 2417 | .psel7(psel7) |
| 2418 | ); |
| 2419 | |
| 2420 | mux8s #(35) d0_0 ( |
| 2421 | .sel0(psel0), |
| 2422 | .sel1(psel1), |
| 2423 | .sel2(psel2), |
| 2424 | .sel3(psel3), |
| 2425 | .sel4(psel4), |
| 2426 | .sel5(psel5), |
| 2427 | .sel6(psel6), |
| 2428 | .sel7(psel7), |
| 2429 | .in0(din0[34:0]), |
| 2430 | .in1(din1[34:0]), |
| 2431 | .in2(din2[34:0]), |
| 2432 | .in3(din3[34:0]), |
| 2433 | .in4(din4[34:0]), |
| 2434 | .in5(din5[34:0]), |
| 2435 | .in6(din6[34:0]), |
| 2436 | .in7(din7[34:0]), |
| 2437 | .dout(dout[34:0]) |
| 2438 | ); |
| 2439 | |
| 2440 | |
| 2441 | |
| 2442 | |
| 2443 | |
| 2444 | |
| 2445 | |
| 2446 | |
| 2447 | |
| 2448 | |
| 2449 | |
| 2450 | |
| 2451 | |
| 2452 | endmodule |
| 2453 | |
| 2454 | |
| 2455 | // |
| 2456 | // buff macro |
| 2457 | // |
| 2458 | // |
| 2459 | |
| 2460 | |
| 2461 | |
| 2462 | |
| 2463 | |
| 2464 | module mmu_asd_dp_buff_macro__rep_1__stack_58c__width_48 ( |
| 2465 | din, |
| 2466 | dout); |
| 2467 | input [47:0] din; |
| 2468 | output [47:0] dout; |
| 2469 | |
| 2470 | |
| 2471 | |
| 2472 | |
| 2473 | |
| 2474 | |
| 2475 | buff #(48) d0_0 ( |
| 2476 | .in(din[47:0]), |
| 2477 | .out(dout[47:0]) |
| 2478 | ); |
| 2479 | |
| 2480 | |
| 2481 | |
| 2482 | |
| 2483 | |
| 2484 | |
| 2485 | |
| 2486 | |
| 2487 | endmodule |
| 2488 | |
| 2489 | |
| 2490 | |
| 2491 | |
| 2492 | |
| 2493 | // |
| 2494 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) |
| 2495 | // |
| 2496 | // |
| 2497 | |
| 2498 | |
| 2499 | |
| 2500 | |
| 2501 | |
| 2502 | module mmu_asd_dp_zero_macro__width_16 ( |
| 2503 | din, |
| 2504 | dout); |
| 2505 | input [15:0] din; |
| 2506 | output dout; |
| 2507 | |
| 2508 | |
| 2509 | |
| 2510 | |
| 2511 | |
| 2512 | |
| 2513 | zero #(16) m0_0 ( |
| 2514 | .in(din[15:0]), |
| 2515 | .out(dout) |
| 2516 | ); |
| 2517 | |
| 2518 | |
| 2519 | |
| 2520 | |
| 2521 | |
| 2522 | |
| 2523 | |
| 2524 | |
| 2525 | |
| 2526 | |
| 2527 | endmodule |
| 2528 | |
| 2529 | |
| 2530 | |
| 2531 | |
| 2532 | |
| 2533 | // |
| 2534 | // nor macro for ports = 2,3 |
| 2535 | // |
| 2536 | // |
| 2537 | |
| 2538 | |
| 2539 | |
| 2540 | |
| 2541 | |
| 2542 | module mmu_asd_dp_nor_macro__ports_2__width_1 ( |
| 2543 | din0, |
| 2544 | din1, |
| 2545 | dout); |
| 2546 | input [0:0] din0; |
| 2547 | input [0:0] din1; |
| 2548 | output [0:0] dout; |
| 2549 | |
| 2550 | |
| 2551 | |
| 2552 | |
| 2553 | |
| 2554 | |
| 2555 | nor2 #(1) d0_0 ( |
| 2556 | .in0(din0[0:0]), |
| 2557 | .in1(din1[0:0]), |
| 2558 | .out(dout[0:0]) |
| 2559 | ); |
| 2560 | |
| 2561 | |
| 2562 | |
| 2563 | |
| 2564 | |
| 2565 | |
| 2566 | |
| 2567 | endmodule |
| 2568 | |
| 2569 | |
| 2570 | |
| 2571 | |
| 2572 | |
| 2573 | // |
| 2574 | // or macro for ports = 2,3 |
| 2575 | // |
| 2576 | // |
| 2577 | |
| 2578 | |
| 2579 | |
| 2580 | |
| 2581 | |
| 2582 | module mmu_asd_dp_or_macro__ports_2__width_1 ( |
| 2583 | din0, |
| 2584 | din1, |
| 2585 | dout); |
| 2586 | input [0:0] din0; |
| 2587 | input [0:0] din1; |
| 2588 | output [0:0] dout; |
| 2589 | |
| 2590 | |
| 2591 | |
| 2592 | |
| 2593 | |
| 2594 | |
| 2595 | or2 #(1) d0_0 ( |
| 2596 | .in0(din0[0:0]), |
| 2597 | .in1(din1[0:0]), |
| 2598 | .out(dout[0:0]) |
| 2599 | ); |
| 2600 | |
| 2601 | |
| 2602 | |
| 2603 | |
| 2604 | |
| 2605 | |
| 2606 | |
| 2607 | |
| 2608 | |
| 2609 | endmodule |
| 2610 | |
| 2611 | |
| 2612 | |
| 2613 | |
| 2614 | |
| 2615 | // |
| 2616 | // buff macro |
| 2617 | // |
| 2618 | // |
| 2619 | |
| 2620 | |
| 2621 | |
| 2622 | |
| 2623 | |
| 2624 | module mmu_asd_dp_buff_macro__rep_1__width_2 ( |
| 2625 | din, |
| 2626 | dout); |
| 2627 | input [1:0] din; |
| 2628 | output [1:0] dout; |
| 2629 | |
| 2630 | |
| 2631 | |
| 2632 | |
| 2633 | |
| 2634 | |
| 2635 | buff #(2) d0_0 ( |
| 2636 | .in(din[1:0]), |
| 2637 | .out(dout[1:0]) |
| 2638 | ); |
| 2639 | |
| 2640 | |
| 2641 | |
| 2642 | |
| 2643 | |
| 2644 | |
| 2645 | |
| 2646 | |
| 2647 | endmodule |
| 2648 | |
| 2649 | |
| 2650 | |
| 2651 | |
| 2652 | |
| 2653 | |
| 2654 | |
| 2655 | |
| 2656 | |
| 2657 | // any PARAMS parms go into naming of macro |
| 2658 | |
| 2659 | module mmu_asd_dp_msff_macro__mux_aonpe__ports_2__width_62 ( |
| 2660 | din0, |
| 2661 | sel0, |
| 2662 | din1, |
| 2663 | sel1, |
| 2664 | clk, |
| 2665 | en, |
| 2666 | se, |
| 2667 | scan_in, |
| 2668 | siclk, |
| 2669 | soclk, |
| 2670 | pce_ov, |
| 2671 | stop, |
| 2672 | dout, |
| 2673 | scan_out); |
| 2674 | wire buffout0; |
| 2675 | wire buffout1; |
| 2676 | wire [61:0] muxout; |
| 2677 | wire l1clk; |
| 2678 | wire siclk_out; |
| 2679 | wire soclk_out; |
| 2680 | wire [60:0] so; |
| 2681 | |
| 2682 | input [61:0] din0; |
| 2683 | input sel0; |
| 2684 | input [61:0] din1; |
| 2685 | input sel1; |
| 2686 | |
| 2687 | |
| 2688 | input clk; |
| 2689 | input en; |
| 2690 | input se; |
| 2691 | input scan_in; |
| 2692 | input siclk; |
| 2693 | input soclk; |
| 2694 | input pce_ov; |
| 2695 | input stop; |
| 2696 | |
| 2697 | |
| 2698 | |
| 2699 | output [61:0] dout; |
| 2700 | |
| 2701 | |
| 2702 | output scan_out; |
| 2703 | |
| 2704 | |
| 2705 | |
| 2706 | |
| 2707 | cl_dp1_muxbuff2_8x c1_0 ( |
| 2708 | .in0(sel0), |
| 2709 | .in1(sel1), |
| 2710 | .out0(buffout0), |
| 2711 | .out1(buffout1) |
| 2712 | ); |
| 2713 | mux2s #(62) d1_0 ( |
| 2714 | .sel0(buffout0), |
| 2715 | .sel1(buffout1), |
| 2716 | .in0(din0[61:0]), |
| 2717 | .in1(din1[61:0]), |
| 2718 | .dout(muxout[61:0]) |
| 2719 | ); |
| 2720 | cl_dp1_l1hdr_8x c0_0 ( |
| 2721 | .l2clk(clk), |
| 2722 | .pce(en), |
| 2723 | .aclk(siclk), |
| 2724 | .bclk(soclk), |
| 2725 | .l1clk(l1clk), |
| 2726 | .se(se), |
| 2727 | .pce_ov(pce_ov), |
| 2728 | .stop(stop), |
| 2729 | .siclk_out(siclk_out), |
| 2730 | .soclk_out(soclk_out) |
| 2731 | ); |
| 2732 | dff #(62) d0_0 ( |
| 2733 | .l1clk(l1clk), |
| 2734 | .siclk(siclk_out), |
| 2735 | .soclk(soclk_out), |
| 2736 | .d(muxout[61:0]), |
| 2737 | .si({scan_in,so[60:0]}), |
| 2738 | .so({so[60:0],scan_out}), |
| 2739 | .q(dout[61:0]) |
| 2740 | ); |
| 2741 | |
| 2742 | |
| 2743 | |
| 2744 | |
| 2745 | |
| 2746 | |
| 2747 | |
| 2748 | |
| 2749 | |
| 2750 | |
| 2751 | |
| 2752 | |
| 2753 | |
| 2754 | |
| 2755 | |
| 2756 | |
| 2757 | |
| 2758 | |
| 2759 | |
| 2760 | |
| 2761 | endmodule |
| 2762 | |
| 2763 | |
| 2764 | |
| 2765 | |
| 2766 | |
| 2767 | |
| 2768 | |
| 2769 | |
| 2770 | |
| 2771 | // |
| 2772 | // and macro for ports = 2,3,4 |
| 2773 | // |
| 2774 | // |
| 2775 | |
| 2776 | |
| 2777 | |
| 2778 | |
| 2779 | |
| 2780 | module mmu_asd_dp_and_macro__ports_2__stack_58c__width_8 ( |
| 2781 | din0, |
| 2782 | din1, |
| 2783 | dout); |
| 2784 | input [7:0] din0; |
| 2785 | input [7:0] din1; |
| 2786 | output [7:0] dout; |
| 2787 | |
| 2788 | |
| 2789 | |
| 2790 | |
| 2791 | |
| 2792 | |
| 2793 | and2 #(8) d0_0 ( |
| 2794 | .in0(din0[7:0]), |
| 2795 | .in1(din1[7:0]), |
| 2796 | .out(dout[7:0]) |
| 2797 | ); |
| 2798 | |
| 2799 | |
| 2800 | |
| 2801 | |
| 2802 | |
| 2803 | |
| 2804 | |
| 2805 | |
| 2806 | |
| 2807 | endmodule |
| 2808 | |
| 2809 | |
| 2810 | |
| 2811 | |
| 2812 | |
| 2813 | // |
| 2814 | // or macro for ports = 2,3 |
| 2815 | // |
| 2816 | // |
| 2817 | |
| 2818 | |
| 2819 | |
| 2820 | |
| 2821 | |
| 2822 | module mmu_asd_dp_or_macro__ports_2__stack_58c__width_8 ( |
| 2823 | din0, |
| 2824 | din1, |
| 2825 | dout); |
| 2826 | input [7:0] din0; |
| 2827 | input [7:0] din1; |
| 2828 | output [7:0] dout; |
| 2829 | |
| 2830 | |
| 2831 | |
| 2832 | |
| 2833 | |
| 2834 | |
| 2835 | or2 #(8) d0_0 ( |
| 2836 | .in0(din0[7:0]), |
| 2837 | .in1(din1[7:0]), |
| 2838 | .out(dout[7:0]) |
| 2839 | ); |
| 2840 | |
| 2841 | |
| 2842 | |
| 2843 | |
| 2844 | |
| 2845 | |
| 2846 | |
| 2847 | |
| 2848 | |
| 2849 | endmodule |
| 2850 | |
| 2851 | |
| 2852 | |
| 2853 | |
| 2854 | |
| 2855 | // |
| 2856 | // or macro for ports = 2,3 |
| 2857 | // |
| 2858 | // |
| 2859 | |
| 2860 | |
| 2861 | |
| 2862 | |
| 2863 | |
| 2864 | module mmu_asd_dp_or_macro__ports_3__stack_58c__width_8 ( |
| 2865 | din0, |
| 2866 | din1, |
| 2867 | din2, |
| 2868 | dout); |
| 2869 | input [7:0] din0; |
| 2870 | input [7:0] din1; |
| 2871 | input [7:0] din2; |
| 2872 | output [7:0] dout; |
| 2873 | |
| 2874 | |
| 2875 | |
| 2876 | |
| 2877 | |
| 2878 | |
| 2879 | or3 #(8) d0_0 ( |
| 2880 | .in0(din0[7:0]), |
| 2881 | .in1(din1[7:0]), |
| 2882 | .in2(din2[7:0]), |
| 2883 | .out(dout[7:0]) |
| 2884 | ); |
| 2885 | |
| 2886 | |
| 2887 | |
| 2888 | |
| 2889 | |
| 2890 | |
| 2891 | |
| 2892 | |
| 2893 | |
| 2894 | endmodule |
| 2895 | |
| 2896 | |
| 2897 | |
| 2898 | |
| 2899 | |
| 2900 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2901 | // also for pass-gate with decoder |
| 2902 | |
| 2903 | |
| 2904 | |
| 2905 | |
| 2906 | |
| 2907 | // any PARAMS parms go into naming of macro |
| 2908 | |
| 2909 | module mmu_asd_dp_mux_macro__mux_aonpe__ports_4__stack_58c__width_48 ( |
| 2910 | din0, |
| 2911 | sel0, |
| 2912 | din1, |
| 2913 | sel1, |
| 2914 | din2, |
| 2915 | sel2, |
| 2916 | din3, |
| 2917 | sel3, |
| 2918 | dout); |
| 2919 | wire buffout0; |
| 2920 | wire buffout1; |
| 2921 | wire buffout2; |
| 2922 | wire buffout3; |
| 2923 | |
| 2924 | input [47:0] din0; |
| 2925 | input sel0; |
| 2926 | input [47:0] din1; |
| 2927 | input sel1; |
| 2928 | input [47:0] din2; |
| 2929 | input sel2; |
| 2930 | input [47:0] din3; |
| 2931 | input sel3; |
| 2932 | output [47:0] dout; |
| 2933 | |
| 2934 | |
| 2935 | |
| 2936 | |
| 2937 | |
| 2938 | cl_dp1_muxbuff4_8x c0_0 ( |
| 2939 | .in0(sel0), |
| 2940 | .in1(sel1), |
| 2941 | .in2(sel2), |
| 2942 | .in3(sel3), |
| 2943 | .out0(buffout0), |
| 2944 | .out1(buffout1), |
| 2945 | .out2(buffout2), |
| 2946 | .out3(buffout3) |
| 2947 | ); |
| 2948 | mux4s #(48) d0_0 ( |
| 2949 | .sel0(buffout0), |
| 2950 | .sel1(buffout1), |
| 2951 | .sel2(buffout2), |
| 2952 | .sel3(buffout3), |
| 2953 | .in0(din0[47:0]), |
| 2954 | .in1(din1[47:0]), |
| 2955 | .in2(din2[47:0]), |
| 2956 | .in3(din3[47:0]), |
| 2957 | .dout(dout[47:0]) |
| 2958 | ); |
| 2959 | |
| 2960 | |
| 2961 | |
| 2962 | |
| 2963 | |
| 2964 | |
| 2965 | |
| 2966 | |
| 2967 | |
| 2968 | |
| 2969 | |
| 2970 | |
| 2971 | |
| 2972 | endmodule |
| 2973 | |
| 2974 | |
| 2975 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 2976 | // also for pass-gate with decoder |
| 2977 | |
| 2978 | |
| 2979 | |
| 2980 | |
| 2981 | |
| 2982 | // any PARAMS parms go into naming of macro |
| 2983 | |
| 2984 | module mmu_asd_dp_mux_macro__dmux_8x__mux_aope__ports_4__stack_58c__width_48 ( |
| 2985 | din0, |
| 2986 | din1, |
| 2987 | din2, |
| 2988 | din3, |
| 2989 | sel0, |
| 2990 | sel1, |
| 2991 | sel2, |
| 2992 | dout); |
| 2993 | wire psel0; |
| 2994 | wire psel1; |
| 2995 | wire psel2; |
| 2996 | wire psel3; |
| 2997 | |
| 2998 | input [47:0] din0; |
| 2999 | input [47:0] din1; |
| 3000 | input [47:0] din2; |
| 3001 | input [47:0] din3; |
| 3002 | input sel0; |
| 3003 | input sel1; |
| 3004 | input sel2; |
| 3005 | output [47:0] dout; |
| 3006 | |
| 3007 | |
| 3008 | |
| 3009 | |
| 3010 | |
| 3011 | cl_dp1_penc4_8x c0_0 ( |
| 3012 | .test(1'b1), |
| 3013 | .sel0(sel0), |
| 3014 | .sel1(sel1), |
| 3015 | .sel2(sel2), |
| 3016 | .psel0(psel0), |
| 3017 | .psel1(psel1), |
| 3018 | .psel2(psel2), |
| 3019 | .psel3(psel3) |
| 3020 | ); |
| 3021 | |
| 3022 | mux4s #(48) d0_0 ( |
| 3023 | .sel0(psel0), |
| 3024 | .sel1(psel1), |
| 3025 | .sel2(psel2), |
| 3026 | .sel3(psel3), |
| 3027 | .in0(din0[47:0]), |
| 3028 | .in1(din1[47:0]), |
| 3029 | .in2(din2[47:0]), |
| 3030 | .in3(din3[47:0]), |
| 3031 | .dout(dout[47:0]) |
| 3032 | ); |
| 3033 | |
| 3034 | |
| 3035 | |
| 3036 | |
| 3037 | |
| 3038 | |
| 3039 | |
| 3040 | |
| 3041 | |
| 3042 | |
| 3043 | |
| 3044 | |
| 3045 | |
| 3046 | endmodule |
| 3047 | |
| 3048 | |
| 3049 | |
| 3050 | |
| 3051 | |
| 3052 | |
| 3053 | // any PARAMS parms go into naming of macro |
| 3054 | |
| 3055 | module mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_49 ( |
| 3056 | din0, |
| 3057 | din1, |
| 3058 | din2, |
| 3059 | din3, |
| 3060 | din4, |
| 3061 | sel0, |
| 3062 | sel1, |
| 3063 | sel2, |
| 3064 | sel3, |
| 3065 | clk, |
| 3066 | en, |
| 3067 | se, |
| 3068 | scan_in, |
| 3069 | siclk, |
| 3070 | soclk, |
| 3071 | pce_ov, |
| 3072 | stop, |
| 3073 | dout, |
| 3074 | scan_out); |
| 3075 | wire psel0; |
| 3076 | wire psel1; |
| 3077 | wire psel2; |
| 3078 | wire psel3; |
| 3079 | wire psel4; |
| 3080 | wire [48:0] muxout; |
| 3081 | wire l1clk; |
| 3082 | wire siclk_out; |
| 3083 | wire soclk_out; |
| 3084 | wire [47:0] so; |
| 3085 | |
| 3086 | input [48:0] din0; |
| 3087 | input [48:0] din1; |
| 3088 | input [48:0] din2; |
| 3089 | input [48:0] din3; |
| 3090 | input [48:0] din4; |
| 3091 | input sel0; |
| 3092 | input sel1; |
| 3093 | input sel2; |
| 3094 | input sel3; |
| 3095 | |
| 3096 | |
| 3097 | input clk; |
| 3098 | input en; |
| 3099 | input se; |
| 3100 | input scan_in; |
| 3101 | input siclk; |
| 3102 | input soclk; |
| 3103 | input pce_ov; |
| 3104 | input stop; |
| 3105 | |
| 3106 | |
| 3107 | |
| 3108 | output [48:0] dout; |
| 3109 | |
| 3110 | |
| 3111 | output scan_out; |
| 3112 | |
| 3113 | |
| 3114 | |
| 3115 | |
| 3116 | cl_dp1_penc5_8x c1_0 ( |
| 3117 | .test(1'b1), |
| 3118 | .sel0(sel0), |
| 3119 | .sel1(sel1), |
| 3120 | .sel2(sel2), |
| 3121 | .sel3(sel3), |
| 3122 | .psel0(psel0), |
| 3123 | .psel1(psel1), |
| 3124 | .psel2(psel2), |
| 3125 | .psel3(psel3), |
| 3126 | .psel4(psel4) |
| 3127 | ); |
| 3128 | |
| 3129 | mux5s #(49) d1_0 ( |
| 3130 | .sel0(psel0), |
| 3131 | .sel1(psel1), |
| 3132 | .sel2(psel2), |
| 3133 | .sel3(psel3), |
| 3134 | .sel4(psel4), |
| 3135 | .in0(din0[48:0]), |
| 3136 | .in1(din1[48:0]), |
| 3137 | .in2(din2[48:0]), |
| 3138 | .in3(din3[48:0]), |
| 3139 | .in4(din4[48:0]), |
| 3140 | .dout(muxout[48:0]) |
| 3141 | ); |
| 3142 | cl_dp1_l1hdr_8x c0_0 ( |
| 3143 | .l2clk(clk), |
| 3144 | .pce(en), |
| 3145 | .aclk(siclk), |
| 3146 | .bclk(soclk), |
| 3147 | .l1clk(l1clk), |
| 3148 | .se(se), |
| 3149 | .pce_ov(pce_ov), |
| 3150 | .stop(stop), |
| 3151 | .siclk_out(siclk_out), |
| 3152 | .soclk_out(soclk_out) |
| 3153 | ); |
| 3154 | dff #(49) d0_0 ( |
| 3155 | .l1clk(l1clk), |
| 3156 | .siclk(siclk_out), |
| 3157 | .soclk(soclk_out), |
| 3158 | .d(muxout[48:0]), |
| 3159 | .si({scan_in,so[47:0]}), |
| 3160 | .so({so[47:0],scan_out}), |
| 3161 | .q(dout[48:0]) |
| 3162 | ); |
| 3163 | |
| 3164 | |
| 3165 | |
| 3166 | |
| 3167 | |
| 3168 | |
| 3169 | |
| 3170 | |
| 3171 | |
| 3172 | |
| 3173 | |
| 3174 | |
| 3175 | |
| 3176 | |
| 3177 | |
| 3178 | |
| 3179 | |
| 3180 | |
| 3181 | |
| 3182 | |
| 3183 | endmodule |
| 3184 | |
| 3185 | |
| 3186 | |
| 3187 | |
| 3188 | |
| 3189 | |
| 3190 | |
| 3191 | |
| 3192 | |
| 3193 | |
| 3194 | |
| 3195 | |
| 3196 | |
| 3197 | // any PARAMS parms go into naming of macro |
| 3198 | |
| 3199 | module mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_51 ( |
| 3200 | din0, |
| 3201 | din1, |
| 3202 | din2, |
| 3203 | din3, |
| 3204 | din4, |
| 3205 | sel0, |
| 3206 | sel1, |
| 3207 | sel2, |
| 3208 | sel3, |
| 3209 | clk, |
| 3210 | en, |
| 3211 | se, |
| 3212 | scan_in, |
| 3213 | siclk, |
| 3214 | soclk, |
| 3215 | pce_ov, |
| 3216 | stop, |
| 3217 | dout, |
| 3218 | scan_out); |
| 3219 | wire psel0; |
| 3220 | wire psel1; |
| 3221 | wire psel2; |
| 3222 | wire psel3; |
| 3223 | wire psel4; |
| 3224 | wire [50:0] muxout; |
| 3225 | wire l1clk; |
| 3226 | wire siclk_out; |
| 3227 | wire soclk_out; |
| 3228 | wire [49:0] so; |
| 3229 | |
| 3230 | input [50:0] din0; |
| 3231 | input [50:0] din1; |
| 3232 | input [50:0] din2; |
| 3233 | input [50:0] din3; |
| 3234 | input [50:0] din4; |
| 3235 | input sel0; |
| 3236 | input sel1; |
| 3237 | input sel2; |
| 3238 | input sel3; |
| 3239 | |
| 3240 | |
| 3241 | input clk; |
| 3242 | input en; |
| 3243 | input se; |
| 3244 | input scan_in; |
| 3245 | input siclk; |
| 3246 | input soclk; |
| 3247 | input pce_ov; |
| 3248 | input stop; |
| 3249 | |
| 3250 | |
| 3251 | |
| 3252 | output [50:0] dout; |
| 3253 | |
| 3254 | |
| 3255 | output scan_out; |
| 3256 | |
| 3257 | |
| 3258 | |
| 3259 | |
| 3260 | cl_dp1_penc5_8x c1_0 ( |
| 3261 | .test(1'b1), |
| 3262 | .sel0(sel0), |
| 3263 | .sel1(sel1), |
| 3264 | .sel2(sel2), |
| 3265 | .sel3(sel3), |
| 3266 | .psel0(psel0), |
| 3267 | .psel1(psel1), |
| 3268 | .psel2(psel2), |
| 3269 | .psel3(psel3), |
| 3270 | .psel4(psel4) |
| 3271 | ); |
| 3272 | |
| 3273 | mux5s #(51) d1_0 ( |
| 3274 | .sel0(psel0), |
| 3275 | .sel1(psel1), |
| 3276 | .sel2(psel2), |
| 3277 | .sel3(psel3), |
| 3278 | .sel4(psel4), |
| 3279 | .in0(din0[50:0]), |
| 3280 | .in1(din1[50:0]), |
| 3281 | .in2(din2[50:0]), |
| 3282 | .in3(din3[50:0]), |
| 3283 | .in4(din4[50:0]), |
| 3284 | .dout(muxout[50:0]) |
| 3285 | ); |
| 3286 | cl_dp1_l1hdr_8x c0_0 ( |
| 3287 | .l2clk(clk), |
| 3288 | .pce(en), |
| 3289 | .aclk(siclk), |
| 3290 | .bclk(soclk), |
| 3291 | .l1clk(l1clk), |
| 3292 | .se(se), |
| 3293 | .pce_ov(pce_ov), |
| 3294 | .stop(stop), |
| 3295 | .siclk_out(siclk_out), |
| 3296 | .soclk_out(soclk_out) |
| 3297 | ); |
| 3298 | dff #(51) d0_0 ( |
| 3299 | .l1clk(l1clk), |
| 3300 | .siclk(siclk_out), |
| 3301 | .soclk(soclk_out), |
| 3302 | .d(muxout[50:0]), |
| 3303 | .si({scan_in,so[49:0]}), |
| 3304 | .so({so[49:0],scan_out}), |
| 3305 | .q(dout[50:0]) |
| 3306 | ); |
| 3307 | |
| 3308 | |
| 3309 | |
| 3310 | |
| 3311 | |
| 3312 | |
| 3313 | |
| 3314 | |
| 3315 | |
| 3316 | |
| 3317 | |
| 3318 | |
| 3319 | |
| 3320 | |
| 3321 | |
| 3322 | |
| 3323 | |
| 3324 | |
| 3325 | |
| 3326 | |
| 3327 | endmodule |
| 3328 | |
| 3329 | |
| 3330 | |
| 3331 | |
| 3332 | |
| 3333 | |
| 3334 | |
| 3335 | |
| 3336 | |
| 3337 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 3338 | // also for pass-gate with decoder |
| 3339 | |
| 3340 | |
| 3341 | |
| 3342 | |
| 3343 | |
| 3344 | // any PARAMS parms go into naming of macro |
| 3345 | |
| 3346 | module mmu_asd_dp_mux_macro__dmux_8x__mux_aonpe__ports_4__stack_58c__width_53 ( |
| 3347 | din0, |
| 3348 | sel0, |
| 3349 | din1, |
| 3350 | sel1, |
| 3351 | din2, |
| 3352 | sel2, |
| 3353 | din3, |
| 3354 | sel3, |
| 3355 | dout); |
| 3356 | wire buffout0; |
| 3357 | wire buffout1; |
| 3358 | wire buffout2; |
| 3359 | wire buffout3; |
| 3360 | |
| 3361 | input [52:0] din0; |
| 3362 | input sel0; |
| 3363 | input [52:0] din1; |
| 3364 | input sel1; |
| 3365 | input [52:0] din2; |
| 3366 | input sel2; |
| 3367 | input [52:0] din3; |
| 3368 | input sel3; |
| 3369 | output [52:0] dout; |
| 3370 | |
| 3371 | |
| 3372 | |
| 3373 | |
| 3374 | |
| 3375 | cl_dp1_muxbuff4_8x c0_0 ( |
| 3376 | .in0(sel0), |
| 3377 | .in1(sel1), |
| 3378 | .in2(sel2), |
| 3379 | .in3(sel3), |
| 3380 | .out0(buffout0), |
| 3381 | .out1(buffout1), |
| 3382 | .out2(buffout2), |
| 3383 | .out3(buffout3) |
| 3384 | ); |
| 3385 | mux4s #(53) d0_0 ( |
| 3386 | .sel0(buffout0), |
| 3387 | .sel1(buffout1), |
| 3388 | .sel2(buffout2), |
| 3389 | .sel3(buffout3), |
| 3390 | .in0(din0[52:0]), |
| 3391 | .in1(din1[52:0]), |
| 3392 | .in2(din2[52:0]), |
| 3393 | .in3(din3[52:0]), |
| 3394 | .dout(dout[52:0]) |
| 3395 | ); |
| 3396 | |
| 3397 | |
| 3398 | |
| 3399 | |
| 3400 | |
| 3401 | |
| 3402 | |
| 3403 | |
| 3404 | |
| 3405 | |
| 3406 | |
| 3407 | |
| 3408 | |
| 3409 | endmodule |
| 3410 | |
| 3411 | |
| 3412 | // |
| 3413 | // nor macro for ports = 2,3 |
| 3414 | // |
| 3415 | // |
| 3416 | |
| 3417 | |
| 3418 | |
| 3419 | |
| 3420 | |
| 3421 | module mmu_asd_dp_nor_macro__ports_2__stack_58c__width_48 ( |
| 3422 | din0, |
| 3423 | din1, |
| 3424 | dout); |
| 3425 | input [47:0] din0; |
| 3426 | input [47:0] din1; |
| 3427 | output [47:0] dout; |
| 3428 | |
| 3429 | |
| 3430 | |
| 3431 | |
| 3432 | |
| 3433 | |
| 3434 | nor2 #(48) d0_0 ( |
| 3435 | .in0(din0[47:0]), |
| 3436 | .in1(din1[47:0]), |
| 3437 | .out(dout[47:0]) |
| 3438 | ); |
| 3439 | |
| 3440 | |
| 3441 | |
| 3442 | |
| 3443 | |
| 3444 | |
| 3445 | |
| 3446 | endmodule |
| 3447 | |
| 3448 | |
| 3449 | |
| 3450 | |
| 3451 | |
| 3452 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 3453 | // also for pass-gate with decoder |
| 3454 | |
| 3455 | |
| 3456 | |
| 3457 | |
| 3458 | |
| 3459 | // any PARAMS parms go into naming of macro |
| 3460 | |
| 3461 | module mmu_asd_dp_mux_macro__mux_aope__ports_4__stack_58c__width_55 ( |
| 3462 | din0, |
| 3463 | din1, |
| 3464 | din2, |
| 3465 | din3, |
| 3466 | sel0, |
| 3467 | sel1, |
| 3468 | sel2, |
| 3469 | dout); |
| 3470 | wire psel0; |
| 3471 | wire psel1; |
| 3472 | wire psel2; |
| 3473 | wire psel3; |
| 3474 | |
| 3475 | input [54:0] din0; |
| 3476 | input [54:0] din1; |
| 3477 | input [54:0] din2; |
| 3478 | input [54:0] din3; |
| 3479 | input sel0; |
| 3480 | input sel1; |
| 3481 | input sel2; |
| 3482 | output [54:0] dout; |
| 3483 | |
| 3484 | |
| 3485 | |
| 3486 | |
| 3487 | |
| 3488 | cl_dp1_penc4_8x c0_0 ( |
| 3489 | .test(1'b1), |
| 3490 | .sel0(sel0), |
| 3491 | .sel1(sel1), |
| 3492 | .sel2(sel2), |
| 3493 | .psel0(psel0), |
| 3494 | .psel1(psel1), |
| 3495 | .psel2(psel2), |
| 3496 | .psel3(psel3) |
| 3497 | ); |
| 3498 | |
| 3499 | mux4s #(55) d0_0 ( |
| 3500 | .sel0(psel0), |
| 3501 | .sel1(psel1), |
| 3502 | .sel2(psel2), |
| 3503 | .sel3(psel3), |
| 3504 | .in0(din0[54:0]), |
| 3505 | .in1(din1[54:0]), |
| 3506 | .in2(din2[54:0]), |
| 3507 | .in3(din3[54:0]), |
| 3508 | .dout(dout[54:0]) |
| 3509 | ); |
| 3510 | |
| 3511 | |
| 3512 | |
| 3513 | |
| 3514 | |
| 3515 | |
| 3516 | |
| 3517 | |
| 3518 | |
| 3519 | |
| 3520 | |
| 3521 | |
| 3522 | |
| 3523 | endmodule |
| 3524 | |
| 3525 | |
| 3526 | // |
| 3527 | // buff macro |
| 3528 | // |
| 3529 | // |
| 3530 | |
| 3531 | |
| 3532 | |
| 3533 | |
| 3534 | |
| 3535 | module mmu_asd_dp_buff_macro__rep_1__stack_58c__width_55 ( |
| 3536 | din, |
| 3537 | dout); |
| 3538 | input [54:0] din; |
| 3539 | output [54:0] dout; |
| 3540 | |
| 3541 | |
| 3542 | |
| 3543 | |
| 3544 | |
| 3545 | |
| 3546 | buff #(55) d0_0 ( |
| 3547 | .in(din[54:0]), |
| 3548 | .out(dout[54:0]) |
| 3549 | ); |
| 3550 | |
| 3551 | |
| 3552 | |
| 3553 | |
| 3554 | |
| 3555 | |
| 3556 | |
| 3557 | |
| 3558 | endmodule |
| 3559 | |
| 3560 | |
| 3561 | |
| 3562 | |