| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: spu.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module spu ( |
| 36 | scan_in, |
| 37 | scan_out, |
| 38 | l2clk, |
| 39 | in_rngl_cdbus, |
| 40 | |
| 41 | spu_mbi_mam_fail_, |
| 42 | spu_mbi_mam_fail2_, |
| 43 | spu_mbi_arf_fail_, |
| 44 | spu_mbi_rrf_fail_, |
| 45 | spu_rngl_cdbus, |
| 46 | spu_l15_valid, |
| 47 | spu_l15_addr, |
| 48 | spu_l15_cpkt, |
| 49 | spu_l15_data, |
| 50 | spu_mult_request, |
| 51 | spu_fgu_rs1_e, |
| 52 | spu_fgu_rs2_e, |
| 53 | spu_fgu_fpy_ctl_d, |
| 54 | spu_pmu_cwq_busy, |
| 55 | spu_pmu_cwq_tid, |
| 56 | spu_pmu_ma_busy, |
| 57 | spu_tlu_cwq_busy, |
| 58 | spu_tlu_cwq_int_req, |
| 59 | spu_tlu_ma_int_req, |
| 60 | spu_tlu_mamu_err_req, |
| 61 | spu_tlu_l2_error); |
| 62 | |
| 63 | input scan_in; |
| 64 | output scan_out; |
| 65 | input l2clk; |
| 66 | |
| 67 | input [64:0] in_rngl_cdbus; // ASI Ring |
| 68 | // 64:0, 65 bit control/data bus coming from the ring |
| 69 | // 64 - ctl/data |
| 70 | // 63 - valid/hole |
| 71 | // 62 - ack |
| 72 | // 61:60 - 00-ASI, 01-ASR, 10-PR, 11-HPR |
| 73 | // 59 - rd/wrx |
| 74 | // 58:56 - Thread ID |
| 75 | // 55:48 - ASI field |
| 76 | // 47:0 - Virtual Address |
| 77 | |
| 78 | output spu_mbi_mam_fail_; // MBIST MAM comparator output bits 63:0 |
| 79 | output spu_mbi_mam_fail2_; // MBIST MAM comparator output bits 71:64 |
| 80 | output spu_mbi_arf_fail_; // MBIST ARF comparator |
| 81 | output spu_mbi_rrf_fail_; // MBIST RRF comparator |
| 82 | |
| 83 | output [64:0] spu_rngl_cdbus; // ASI Ring |
| 84 | |
| 85 | output spu_l15_valid; // To L1.5 : Valid Control/Data |
| 86 | output [38:3] spu_l15_addr; // To L1.5 : Address |
| 87 | output [12:0] spu_l15_cpkt; // To L1.5 : Control portion of PCX packet |
| 88 | output [63:0] spu_l15_data; // To L1.5 : Store data |
| 89 | |
| 90 | output spu_mult_request; // To FGU : Multiply Request |
| 91 | output [63:0] spu_fgu_rs1_e; // To FGU : Multiply RS1 |
| 92 | output [63:0] spu_fgu_rs2_e; // To FGU : Multiply RS2 |
| 93 | output [6:0] spu_fgu_fpy_ctl_d; // To FGU : SPU control bus for crypto multiply ops |
| 94 | |
| 95 | output [4:0] spu_pmu_cwq_busy; // To PMU : CWQ busy {rc4,hash,des,crc,aes} |
| 96 | output [2:0] spu_pmu_cwq_tid; // To PMU : CWQ tid |
| 97 | output [3:0] spu_pmu_ma_busy; // To PMU : Ma busy |
| 98 | |
| 99 | output spu_tlu_cwq_busy; // To TLU : Prevents core from parking |
| 100 | output [3:0] spu_tlu_cwq_int_req; // To TLU : [3] == valid; [2:0] == TID; |
| 101 | output [4:0] spu_tlu_ma_int_req; // To TLU : Int req when MA op completes {4 - error; 3 - req valid; 2:0 - TID} |
| 102 | output [10:0] spu_tlu_mamu_err_req; // was: 14 - valid; 13:11 - TID; 10 - ma port; 9:8 - syndrome; 7:0 - MA index |
| 103 | // now: share 14..11 with tlu_ma_int_req; bits 10:0 stay the same |
| 104 | output [5:0] spu_tlu_l2_error; // To TLU : L2 Error reporting : {MAL2C,MAL2U,MAL2ND,CWQL2C,CWQL2U,CWQL2ND} |
| 105 | |
| 106 | |
| 107 | //----- this module is blackboxed. |
| 108 | |
| 109 | assign scan_out = scan_in; // SCAN |
| 110 | |
| 111 | assign spu_mbi_arf_fail_=1'b1; // MBIST |
| 112 | assign spu_mbi_mam_fail2_=1'b1; // MBIST |
| 113 | assign spu_mbi_mam_fail_=1'b1; // MBIST |
| 114 | assign spu_mbi_rrf_fail_=1'b1; // MBIST |
| 115 | |
| 116 | reg [64:0] in_rngl_cdbus_d1; // ASI ring |
| 117 | reg [64:0] in_rngl_cdbus_d2; // ASI ring |
| 118 | |
| 119 | //nasim |
| 120 | `ifdef OPENSPARC_CMP |
| 121 | reg l2clk_nba; |
| 122 | always @(l2clk) l2clk_nba <= l2clk; |
| 123 | always @(l2clk_nba) |
| 124 | `else |
| 125 | always @(l2clk) |
| 126 | `endif |
| 127 | begin |
| 128 | in_rngl_cdbus_d1=in_rngl_cdbus; |
| 129 | in_rngl_cdbus_d2=in_rngl_cdbus_d1; |
| 130 | end |
| 131 | |
| 132 | assign spu_rngl_cdbus=in_rngl_cdbus_d2; // ASI ring |
| 133 | |
| 134 | assign spu_mult_request=1'b0; // To FGU : Multiply Request |
| 135 | assign spu_fgu_rs1_e=64'b0; // To FGU : Multiply RS1 |
| 136 | assign spu_fgu_rs2_e=64'b0; // To FGU : Multiply RS2 |
| 137 | assign spu_fgu_fpy_ctl_d=7'b0; // To FGU : SPU control bus for crypto multiply ops |
| 138 | |
| 139 | assign spu_l15_valid=1'b0; // To L1.5 : Valid Control/Data |
| 140 | assign spu_l15_addr[38:3] =36'b0; // To L1.5 : Address |
| 141 | assign spu_l15_data=64'b0; // To L1.5 : Store data |
| 142 | assign spu_l15_cpkt=13'b0; // To L1.5 : Control portion of PCX packet |
| 143 | |
| 144 | assign spu_pmu_cwq_tid=3'b0; // To PMU : CWQ tid |
| 145 | assign spu_pmu_ma_busy=4'b0; // To PMU : Ma busy |
| 146 | assign spu_pmu_cwq_busy=5'b0; // To PMU : CWQ busy {rc4,hash,des,crc,aes} |
| 147 | |
| 148 | assign spu_tlu_cwq_busy=1'b0; // To TLU : Prevents core from parking |
| 149 | assign spu_tlu_mamu_err_req=11'b0; // was: 14 - valid; 13:11 - TID; 10 - ma port; 9:8 - syndrome; 7:0 - MA index |
| 150 | assign spu_tlu_cwq_int_req=4'b0; // To TLU : [3] == valid; [2:0] == TID; |
| 151 | assign spu_tlu_ma_int_req=5'b0; // To TLU : Int req when MA op completes {4 - error; 3 - req valid; 2:0 - TID} |
| 152 | assign spu_tlu_l2_error=6'b0; // To TLU : L2 Error reporting : {MAL2C,MAL2U,MAL2ND,CWQL2C,CWQL2U,CWQL2ND} |
| 153 | |
| 154 | endmodule |
| 155 | |