| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: cl_mc1.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module cl_mc1_adrff2b_8x ( latout, latout_l, q, q_l, so, d, l1clk, si, siclk, soclk ); |
| 36 | |
| 37 | output latout; |
| 38 | output latout_l; |
| 39 | output so; |
| 40 | output q; |
| 41 | output q_l; |
| 42 | input d; |
| 43 | input l1clk; |
| 44 | input si; |
| 45 | input siclk; |
| 46 | input soclk; |
| 47 | |
| 48 | wire latout, latout_l, so; |
| 49 | reg m, s; |
| 50 | |
| 51 | `ifdef SCAN_MODE |
| 52 | `ifdef FAST_FLUSH |
| 53 | always @(l1clk or siclk or d) begin //vcs optimized code |
| 54 | |
| 55 | if (!l1clk && !siclk) m <= d; // Load master with data |
| 56 | else if ( l1clk && !siclk) s <= m; // Load slave with master data |
| 57 | else if ( l1clk && siclk) begin |
| 58 | m <= 1'b0; // flush reset |
| 59 | s <= 1'b0; |
| 60 | end |
| 61 | end |
| 62 | `else |
| 63 | |
| 64 | always @(l1clk or siclk or soclk or d or si) begin |
| 65 | |
| 66 | if (!l1clk && !siclk) m <= d; // Load master with data |
| 67 | else if ( l1clk && siclk) m <= si; // Load master with scan or flush |
| 68 | else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan |
| 69 | |
| 70 | if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data |
| 71 | else if (l1clk && siclk && !soclk) s <= si; // Flush |
| 72 | end |
| 73 | `endif |
| 74 | |
| 75 | `else |
| 76 | wire si_unused = si; |
| 77 | `ifdef INITLATZERO |
| 78 | initial m = 1'b0; |
| 79 | initial s = 1'b0; |
| 80 | `endif |
| 81 | |
| 82 | always @(l1clk or d or si or siclk) begin |
| 83 | if(siclk==0 && l1clk==0) m <= d; |
| 84 | else if(siclk && !l1clk) m <= 1'bx; |
| 85 | else if(siclk && l1clk) m <= si; |
| 86 | if(l1clk && !soclk) s<= m; |
| 87 | end |
| 88 | |
| 89 | `endif |
| 90 | assign latout = m & l1clk; |
| 91 | assign latout_l = ~m & l1clk; |
| 92 | assign so = s; |
| 93 | assign q = s; |
| 94 | assign q_l = ~s; |
| 95 | |
| 96 | |
| 97 | endmodule |
| 98 | |
| 99 | module cl_mc1_bistl1hdr_12x ( |
| 100 | l2clk, |
| 101 | se, |
| 102 | clksel, |
| 103 | bistclk, |
| 104 | lce, |
| 105 | l1clk |
| 106 | ); |
| 107 | |
| 108 | |
| 109 | input l2clk; // level 2 clock, from clock grid |
| 110 | input se; // Scan Enable |
| 111 | input clksel; |
| 112 | input bistclk; |
| 113 | input lce; |
| 114 | output l1clk; |
| 115 | |
| 116 | assign l1clk = ((((l2clk & ~clksel)|(bistclk & clksel)) & ~lce) | se) ; |
| 117 | |
| 118 | endmodule |
| 119 | |
| 120 | |
| 121 | module cl_mc1_bistl1hdr_16x ( |
| 122 | l2clk, |
| 123 | se, |
| 124 | clksel, |
| 125 | bistclk, |
| 126 | lce, |
| 127 | l1clk |
| 128 | ); |
| 129 | |
| 130 | |
| 131 | input l2clk; // level 2 clock, from clock grid |
| 132 | input se; // Scan Enable |
| 133 | input clksel; |
| 134 | input bistclk; |
| 135 | input lce; |
| 136 | output l1clk; |
| 137 | |
| 138 | assign l1clk = ((((l2clk & ~clksel)|(bistclk & clksel)) & ~lce) | se) ; |
| 139 | |
| 140 | endmodule |
| 141 | |
| 142 | |
| 143 | module cl_mc1_bistl1hdr_8x ( |
| 144 | l2clk, |
| 145 | se, |
| 146 | clksel, |
| 147 | bistclk, |
| 148 | lce, |
| 149 | l1clk |
| 150 | ); |
| 151 | |
| 152 | |
| 153 | input l2clk; // level 2 clock, from clock grid |
| 154 | input se; // Scan Enable |
| 155 | input clksel; |
| 156 | input bistclk; |
| 157 | input lce; |
| 158 | output l1clk; |
| 159 | |
| 160 | assign l1clk = ((((l2clk & ~clksel)|(bistclk & clksel)) & ~lce) | se) ; |
| 161 | |
| 162 | endmodule |
| 163 | |
| 164 | |
| 165 | module cl_mc1_bistlatch_10x ( |
| 166 | l2clk, |
| 167 | pce, |
| 168 | pce_ov, |
| 169 | lce); |
| 170 | input l2clk; |
| 171 | input pce; |
| 172 | input pce_ov; |
| 173 | output lce; |
| 174 | |
| 175 | `ifdef FORMAL_TOOL |
| 176 | assign lce = ~(pce | pce_ov); |
| 177 | `else |
| 178 | |
| 179 | `ifdef LIB |
| 180 | reg lce; |
| 181 | |
| 182 | always @ (negedge l2clk) |
| 183 | begin |
| 184 | lce <= ~(pce | pce_ov); |
| 185 | end |
| 186 | `endif |
| 187 | `endif |
| 188 | endmodule |
| 189 | |
| 190 | module cl_mc1_bistlatch_20x ( |
| 191 | l2clk, |
| 192 | pce, |
| 193 | pce_ov, |
| 194 | lce); |
| 195 | input l2clk; |
| 196 | input pce; |
| 197 | input pce_ov; |
| 198 | output lce; |
| 199 | |
| 200 | `ifdef FORMAL_TOOL |
| 201 | assign lce = ~(pce | pce_ov); |
| 202 | `else |
| 203 | |
| 204 | `ifdef LIB |
| 205 | reg lce; |
| 206 | |
| 207 | always @ (negedge l2clk) |
| 208 | begin |
| 209 | lce <= ~(pce | pce_ov); |
| 210 | end |
| 211 | `endif |
| 212 | `endif |
| 213 | endmodule |
| 214 | |
| 215 | module cl_mc1_bistlatch_4x ( |
| 216 | l2clk, |
| 217 | pce, |
| 218 | pce_ov, |
| 219 | lce); |
| 220 | input l2clk; |
| 221 | input pce; |
| 222 | input pce_ov; |
| 223 | output lce; |
| 224 | |
| 225 | `ifdef FORMAL_TOOL |
| 226 | assign lce = ~(pce | pce_ov); |
| 227 | `else |
| 228 | |
| 229 | `ifdef LIB |
| 230 | reg lce; |
| 231 | |
| 232 | always @ (negedge l2clk) |
| 233 | begin |
| 234 | lce <= ~(pce | pce_ov); |
| 235 | end |
| 236 | `endif |
| 237 | `endif |
| 238 | endmodule |
| 239 | module cl_mc1_cm_com_adff_l ( master, so, d, l1clk, si, siclk, soclk ); |
| 240 | |
| 241 | output master; |
| 242 | output so; |
| 243 | |
| 244 | input d; |
| 245 | input l1clk; |
| 246 | input si; |
| 247 | input siclk; |
| 248 | input soclk; |
| 249 | |
| 250 | wire master; |
| 251 | wire so; |
| 252 | |
| 253 | reg m, s; |
| 254 | |
| 255 | `ifdef SCAN_MODE |
| 256 | |
| 257 | always @(l1clk or siclk or soclk or d or si) |
| 258 | begin |
| 259 | if (!l1clk && !siclk) m <= d; // Load master with data |
| 260 | else if ( l1clk && siclk) m <= si; // Load master with scan or flush |
| 261 | else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan |
| 262 | |
| 263 | if ( l1clk && !siclk && !soclk) s <= m; // Load slave with master data |
| 264 | else if ( l1clk && siclk && !soclk) s <= si; // Flush |
| 265 | end |
| 266 | `else |
| 267 | wire si_unused = si; |
| 268 | `ifdef INITLATZERO |
| 269 | initial m = 1'b0; |
| 270 | initial s = 1'b0; |
| 271 | `endif |
| 272 | |
| 273 | always @(l1clk or d or si or siclk) begin |
| 274 | if(siclk==0 && l1clk==0) m <= d; |
| 275 | if(siclk && !l1clk) m <= 1'bx; |
| 276 | else if(siclk && l1clk) m <= si; |
| 277 | end |
| 278 | |
| 279 | `endif |
| 280 | |
| 281 | assign master = m; |
| 282 | assign so = s; |
| 283 | |
| 284 | endmodule |
| 285 | |
| 286 | module cl_mc1_cm_com_adff_r ( master, so, d, l1clk, si, siclk, soclk ); |
| 287 | |
| 288 | output master; |
| 289 | output so; |
| 290 | |
| 291 | input d; |
| 292 | input l1clk; |
| 293 | input si; |
| 294 | input siclk; |
| 295 | input soclk; |
| 296 | |
| 297 | wire master; |
| 298 | wire so; |
| 299 | |
| 300 | reg m, s; |
| 301 | |
| 302 | `ifdef SCAN_MODE |
| 303 | |
| 304 | always @(l1clk or siclk or soclk or d or si) |
| 305 | begin |
| 306 | if (!l1clk && !siclk) m <= d; // Load master with data |
| 307 | else if ( l1clk && siclk) m <= si; // Load master with scan or flush |
| 308 | else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan |
| 309 | |
| 310 | if ( l1clk && !siclk && !soclk) s <= m; // Load slave with master data |
| 311 | else if ( l1clk && siclk && !soclk) s <= si; // Flush |
| 312 | end |
| 313 | `else |
| 314 | wire si_unused = si; |
| 315 | `ifdef INITLATZERO |
| 316 | initial m = 1'b0; |
| 317 | initial s = 1'b0; |
| 318 | `endif |
| 319 | |
| 320 | always @(l1clk or d or si or siclk) begin |
| 321 | if(siclk==0 && l1clk==0) m <= d; |
| 322 | if(siclk && !l1clk) m <= 1'bx; |
| 323 | else if(siclk && l1clk) m <= si; |
| 324 | end |
| 325 | |
| 326 | `endif |
| 327 | |
| 328 | assign master = m; |
| 329 | assign so = s; |
| 330 | |
| 331 | endmodule |
| 332 | |
| 333 | module cl_mc1_cm_com_dff ( master, master_l, so, d, l1clk, si, siclk, soclk ); |
| 334 | |
| 335 | output master; |
| 336 | output master_l; |
| 337 | output so; |
| 338 | |
| 339 | input d; |
| 340 | input l1clk; |
| 341 | input si; |
| 342 | input siclk; |
| 343 | input soclk; |
| 344 | |
| 345 | wire master; |
| 346 | wire master_l; |
| 347 | wire so; |
| 348 | |
| 349 | reg m, s; |
| 350 | |
| 351 | `ifdef SCAN_MODE |
| 352 | |
| 353 | always @(l1clk or siclk or soclk or d or si) |
| 354 | begin |
| 355 | if (!l1clk && !siclk) m <= d; // Load master with data |
| 356 | else if ( l1clk && siclk) m <= si; // Load master with scan or flush |
| 357 | else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan |
| 358 | |
| 359 | if ( l1clk && !siclk && !soclk) s <= m; // Load slave with master data |
| 360 | else if ( l1clk && siclk && !soclk) s <= si; // Flush |
| 361 | end |
| 362 | `else |
| 363 | wire si_unused = si; |
| 364 | `ifdef INITLATZERO |
| 365 | initial m = 1'b0; |
| 366 | initial s = 1'b0; |
| 367 | `endif |
| 368 | |
| 369 | always @(l1clk or d or si or siclk) begin |
| 370 | if(siclk==0 && l1clk==0) m <= d; |
| 371 | if(siclk && !l1clk) m <= 1'bx; |
| 372 | else if(siclk && l1clk) m <= si; |
| 373 | end |
| 374 | |
| 375 | `endif |
| 376 | |
| 377 | assign master = m; |
| 378 | assign master_l = ~m; |
| 379 | assign so = s; |
| 380 | |
| 381 | endmodule |
| 382 | |
| 383 | module cl_mc1_cm_nor_msff ( q, so, din, clear, l1clk, si, siclk, soclk ); |
| 384 | // Level sensitive in SCAN_MODE |
| 385 | // Edge triggered when not in SCAN_MODE |
| 386 | |
| 387 | output q; |
| 388 | output so; |
| 389 | |
| 390 | input din, clear; |
| 391 | input l1clk; |
| 392 | input si; |
| 393 | input siclk; |
| 394 | input soclk; |
| 395 | |
| 396 | reg q; |
| 397 | wire so; |
| 398 | wire l1clk, siclk, soclk; |
| 399 | |
| 400 | `ifdef SCAN_MODE |
| 401 | |
| 402 | reg m; |
| 403 | |
| 404 | always @(l1clk or siclk or soclk or din or clear or si) |
| 405 | begin |
| 406 | if (!l1clk && !siclk) m <= ~(din | clear); // Load master with data |
| 407 | else if ( l1clk && siclk) m <= si; // Load master with scan or flush |
| 408 | else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan |
| 409 | |
| 410 | else if ( l1clk && !siclk && !soclk) q <= m; // Load slave with master data |
| 411 | if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 412 | end |
| 413 | |
| 414 | `else |
| 415 | wire si_unused = si; |
| 416 | |
| 417 | `ifdef INITLATZERO |
| 418 | initial q = 1'b0; |
| 419 | `endif |
| 420 | |
| 421 | always @(posedge l1clk) |
| 422 | begin |
| 423 | if (!siclk && !soclk) q <= ~(din | clear); |
| 424 | else q <= 1'bx; |
| 425 | end |
| 426 | `endif |
| 427 | |
| 428 | assign so = q; |
| 429 | |
| 430 | endmodule |
| 431 | // created June 6, 2005, ln |
| 432 | |
| 433 | module cl_mc1_gate_antenna_50k ( in ); |
| 434 | |
| 435 | input in; |
| 436 | |
| 437 | endmodule |
| 438 | // created June 6, 2005, ln |
| 439 | |
| 440 | module cl_mc1_gate_antenna_5k ( in ); |
| 441 | |
| 442 | input in; |
| 443 | |
| 444 | endmodule |
| 445 | |
| 446 | module cl_mc1_irf_lat_rsto ( |
| 447 | l1clk, |
| 448 | d, |
| 449 | mq); |
| 450 | input l1clk; |
| 451 | input d; |
| 452 | output mq; |
| 453 | |
| 454 | reg m; |
| 455 | wire mq; |
| 456 | |
| 457 | always @ (l1clk or d) |
| 458 | if (l1clk == 1'b0) m <= d; |
| 459 | |
| 460 | `ifdef INITLATZERO |
| 461 | initial m = 1'b0; |
| 462 | `endif |
| 463 | |
| 464 | assign mq = m && l1clk; |
| 465 | |
| 466 | endmodule |
| 467 | |
| 468 | |
| 469 | module cl_mc1_irf_lat_swl ( |
| 470 | l1clk, |
| 471 | d, |
| 472 | mq); |
| 473 | input l1clk; |
| 474 | input d; |
| 475 | output mq; |
| 476 | |
| 477 | reg m; |
| 478 | wire mq; |
| 479 | |
| 480 | always @ (l1clk or d) |
| 481 | if (l1clk == 1'b0) m <= d; |
| 482 | |
| 483 | `ifdef INITLATZERO |
| 484 | initial m = 1'b0; |
| 485 | `endif |
| 486 | |
| 487 | assign mq = m && l1clk; |
| 488 | |
| 489 | endmodule |
| 490 | |
| 491 | |
| 492 | module cl_mc1_irf_msff_4x ( q, so, d, l1clk, si, siclk, soclk ); |
| 493 | |
| 494 | output q; |
| 495 | output so; |
| 496 | |
| 497 | input d; |
| 498 | input l1clk; |
| 499 | input si; |
| 500 | input siclk; |
| 501 | input soclk; |
| 502 | |
| 503 | wire q, so; |
| 504 | reg m, s; |
| 505 | |
| 506 | `ifdef SCAN_MODE |
| 507 | |
| 508 | always @(l1clk or siclk or soclk or d or si) begin |
| 509 | |
| 510 | if (!l1clk && !siclk) m <= d; // Load master with data |
| 511 | else if ( l1clk && siclk) m <= si; // Load master with scan or flush |
| 512 | else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan |
| 513 | |
| 514 | if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data |
| 515 | else if (l1clk && siclk && !soclk) s <= si; // Flush |
| 516 | end |
| 517 | |
| 518 | `else |
| 519 | wire si_unused = si; |
| 520 | `ifdef INITLATZERO |
| 521 | initial m = 1'b0; |
| 522 | initial s = 1'b0; |
| 523 | `endif |
| 524 | |
| 525 | always @(l1clk or d or si or siclk) begin |
| 526 | if(siclk==0 && l1clk==0) m <= d; |
| 527 | if(siclk && !l1clk) m <= 1'bx; |
| 528 | else if(siclk && l1clk) m <= si; |
| 529 | end |
| 530 | |
| 531 | `endif |
| 532 | |
| 533 | assign q = s; |
| 534 | assign so = s; |
| 535 | |
| 536 | endmodule |
| 537 | |
| 538 | // Driver |
| 539 | module cl_mc1_l1driver_12x ( |
| 540 | l2clk, |
| 541 | se, |
| 542 | l1en, |
| 543 | l1clk |
| 544 | ); |
| 545 | |
| 546 | input l2clk; // level 2 clock, from clock grid |
| 547 | input se; // Scan Enable |
| 548 | input l1en; // Clock enable for local power savings |
| 549 | output l1clk; |
| 550 | |
| 551 | wire l1clk; |
| 552 | |
| 553 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 554 | endmodule |
| 555 | |
| 556 | // Driver |
| 557 | module cl_mc1_l1driver_16x ( |
| 558 | l2clk, |
| 559 | se, |
| 560 | l1en, |
| 561 | l1clk |
| 562 | ); |
| 563 | |
| 564 | input l2clk; // level 2 clock, from clock grid |
| 565 | input se; // Scan Enable |
| 566 | input l1en; // Clock enable for local power savings |
| 567 | output l1clk; |
| 568 | |
| 569 | wire l1clk; |
| 570 | |
| 571 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 572 | endmodule |
| 573 | |
| 574 | // Driver |
| 575 | module cl_mc1_l1driver_24x ( |
| 576 | l2clk, |
| 577 | se, |
| 578 | l1en, |
| 579 | l1clk |
| 580 | ); |
| 581 | |
| 582 | input l2clk; // level 2 clock, from clock grid |
| 583 | input se; // Scan Enable |
| 584 | input l1en; // Clock enable for local power savings |
| 585 | output l1clk; |
| 586 | |
| 587 | wire l1clk; |
| 588 | |
| 589 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 590 | endmodule |
| 591 | |
| 592 | // Driver |
| 593 | module cl_mc1_l1driver_32x ( |
| 594 | l2clk, |
| 595 | se, |
| 596 | l1en, |
| 597 | l1clk |
| 598 | ); |
| 599 | |
| 600 | input l2clk; // level 2 clock, from clock grid |
| 601 | input se; // Scan Enable |
| 602 | input l1en; // Clock enable for local power savings |
| 603 | output l1clk; |
| 604 | |
| 605 | wire l1clk; |
| 606 | |
| 607 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 608 | endmodule |
| 609 | |
| 610 | module cl_mc1_l1driver_48x ( |
| 611 | l2clk, |
| 612 | se, |
| 613 | l1en, |
| 614 | l1clk |
| 615 | ); |
| 616 | |
| 617 | input l2clk; // level 2 clock, from clock grid |
| 618 | input se; // Scan Enable |
| 619 | input l1en; // Clock enable for local power savings |
| 620 | output l1clk; |
| 621 | |
| 622 | wire l1clk; |
| 623 | |
| 624 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 625 | endmodule |
| 626 | |
| 627 | // Driver |
| 628 | module cl_mc1_l1driver_4x ( |
| 629 | l2clk, |
| 630 | se, |
| 631 | l1en, |
| 632 | l1clk |
| 633 | ); |
| 634 | |
| 635 | input l2clk; // level 2 clock, from clock grid |
| 636 | input se; // Scan Enable |
| 637 | input l1en; // Clock enable for local power savings |
| 638 | output l1clk; |
| 639 | |
| 640 | wire l1clk; |
| 641 | |
| 642 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 643 | |
| 644 | endmodule |
| 645 | |
| 646 | |
| 647 | // Driver |
| 648 | module cl_mc1_l1driver_64x ( |
| 649 | l2clk, |
| 650 | se, |
| 651 | l1en, |
| 652 | l1clk |
| 653 | ); |
| 654 | |
| 655 | input l2clk; // level 2 clock, from clock grid |
| 656 | input se; // Scan Enable |
| 657 | input l1en; // Clock enable for local power savings |
| 658 | output l1clk; |
| 659 | |
| 660 | wire l1clk; |
| 661 | |
| 662 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 663 | endmodule |
| 664 | |
| 665 | // Driver |
| 666 | module cl_mc1_l1driver_8x ( |
| 667 | l2clk, |
| 668 | se, |
| 669 | l1en, |
| 670 | l1clk |
| 671 | ); |
| 672 | |
| 673 | input l2clk; // level 2 clock, from clock grid |
| 674 | input se; // Scan Enable |
| 675 | input l1en; // Clock enable for local power savings |
| 676 | output l1clk; |
| 677 | |
| 678 | wire l1clk; |
| 679 | |
| 680 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 681 | |
| 682 | endmodule |
| 683 | |
| 684 | |
| 685 | // Driver double wide |
| 686 | module cl_mc1_l1driver_by2_24x ( |
| 687 | l2clk, |
| 688 | se, |
| 689 | l1en, |
| 690 | l1clk |
| 691 | ); |
| 692 | |
| 693 | input l2clk; // level 2 clock, from clock grid |
| 694 | input se; // Scan Enable |
| 695 | input l1en; // Clock enable for local power savings |
| 696 | output l1clk; |
| 697 | |
| 698 | wire l1clk; |
| 699 | |
| 700 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 701 | endmodule |
| 702 | |
| 703 | // Driver double wide |
| 704 | module cl_mc1_l1driver_by2_32x ( |
| 705 | l2clk, |
| 706 | se, |
| 707 | l1en, |
| 708 | l1clk |
| 709 | ); |
| 710 | |
| 711 | input l2clk; // level 2 clock, from clock grid |
| 712 | input se; // Scan Enable |
| 713 | input l1en; // Clock enable for local power savings |
| 714 | output l1clk; |
| 715 | |
| 716 | wire l1clk; |
| 717 | |
| 718 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 719 | endmodule |
| 720 | |
| 721 | module cl_mc1_l1driver_by2_48x ( |
| 722 | l2clk, |
| 723 | se, |
| 724 | l1en, |
| 725 | l1clk |
| 726 | ); |
| 727 | |
| 728 | input l2clk; // level 2 clock, from clock grid |
| 729 | input se; // Scan Enable |
| 730 | input l1en; // Clock enable for local power savings |
| 731 | output l1clk; |
| 732 | |
| 733 | wire l1clk; |
| 734 | |
| 735 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 736 | endmodule |
| 737 | |
| 738 | module cl_mc1_l1driver_by2_64x ( |
| 739 | l2clk, |
| 740 | se, |
| 741 | l1en, |
| 742 | l1clk |
| 743 | ); |
| 744 | |
| 745 | input l2clk; // level 2 clock, from clock grid |
| 746 | input se; // Scan Enable |
| 747 | input l1en; // Clock enable for local power savings |
| 748 | output l1clk; |
| 749 | |
| 750 | wire l1clk; |
| 751 | |
| 752 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 753 | endmodule |
| 754 | |
| 755 | // Edge modeled Enable latch |
| 756 | module cl_mc1_l1enable_12x ( |
| 757 | l2clk, |
| 758 | pce, |
| 759 | pce_ov, |
| 760 | l1en); |
| 761 | input l2clk; |
| 762 | input pce; |
| 763 | input pce_ov; |
| 764 | output l1en; |
| 765 | |
| 766 | reg l1en; |
| 767 | |
| 768 | always @ (negedge l2clk ) |
| 769 | begin |
| 770 | l1en <= (pce | pce_ov); |
| 771 | end |
| 772 | |
| 773 | // logically correct model |
| 774 | // always @ (l2clk or pce or pce_ov) |
| 775 | // if (l2clk == 1'b0) l1en <= (pce | pce_ov); |
| 776 | endmodule |
| 777 | |
| 778 | // Edge modeled Enable latch |
| 779 | module cl_mc1_l1enable_16x ( |
| 780 | l2clk, |
| 781 | pce, |
| 782 | pce_ov, |
| 783 | l1en); |
| 784 | input l2clk; |
| 785 | input pce; |
| 786 | input pce_ov; |
| 787 | output l1en; |
| 788 | |
| 789 | reg l1en; |
| 790 | |
| 791 | always @ (negedge l2clk ) |
| 792 | begin |
| 793 | l1en <= (pce | pce_ov); |
| 794 | end |
| 795 | |
| 796 | // logically correct model |
| 797 | // always @ (l2clk or pce or pce_ov) |
| 798 | // if (l2clk == 1'b0) l1en <= (pce | pce_ov); |
| 799 | endmodule |
| 800 | |
| 801 | // Edge modeled Enable latch |
| 802 | module cl_mc1_l1enable_24x ( |
| 803 | l2clk, |
| 804 | pce, |
| 805 | pce_ov, |
| 806 | l1en); |
| 807 | input l2clk; |
| 808 | input pce; |
| 809 | input pce_ov; |
| 810 | output l1en; |
| 811 | |
| 812 | reg l1en; |
| 813 | |
| 814 | always @ (negedge l2clk ) |
| 815 | begin |
| 816 | l1en <= (pce | pce_ov); |
| 817 | end |
| 818 | |
| 819 | // logically correct model |
| 820 | // always @ (l2clk or pce or pce_ov) |
| 821 | // if (l2clk == 1'b0) l1en <= (pce | pce_ov); |
| 822 | endmodule |
| 823 | |
| 824 | // Edge modeled Enable latch |
| 825 | module cl_mc1_l1enable_32x ( |
| 826 | l2clk, |
| 827 | pce, |
| 828 | pce_ov, |
| 829 | l1en); |
| 830 | input l2clk; |
| 831 | input pce; |
| 832 | input pce_ov; |
| 833 | output l1en; |
| 834 | |
| 835 | reg l1en; |
| 836 | |
| 837 | always @ (negedge l2clk ) |
| 838 | begin |
| 839 | l1en <= (pce | pce_ov); |
| 840 | end |
| 841 | |
| 842 | // logically correct model |
| 843 | // always @ (l2clk or pce or pce_ov) |
| 844 | // if (l2clk == 1'b0) l1en <= (pce | pce_ov); |
| 845 | endmodule |
| 846 | |
| 847 | // Edge modeled Enable latch |
| 848 | module cl_mc1_l1enable_48x ( |
| 849 | l2clk, |
| 850 | pce, |
| 851 | pce_ov, |
| 852 | l1en); |
| 853 | input l2clk; |
| 854 | input pce; |
| 855 | input pce_ov; |
| 856 | output l1en; |
| 857 | |
| 858 | reg l1en; |
| 859 | |
| 860 | always @ (negedge l2clk ) |
| 861 | begin |
| 862 | l1en <= (pce | pce_ov); |
| 863 | end |
| 864 | |
| 865 | // logically correct model |
| 866 | // always @ (l2clk or pce or pce_ov) |
| 867 | // if (l2clk == 1'b0) l1en <= (pce | pce_ov); |
| 868 | endmodule |
| 869 | |
| 870 | // Edge modeled Enable latch |
| 871 | module cl_mc1_l1enable_4x ( |
| 872 | l2clk, |
| 873 | pce, |
| 874 | pce_ov, |
| 875 | l1en); |
| 876 | input l2clk; |
| 877 | input pce; |
| 878 | input pce_ov; |
| 879 | output l1en; |
| 880 | |
| 881 | reg l1en; |
| 882 | |
| 883 | always @ (negedge l2clk ) |
| 884 | begin |
| 885 | l1en <= (pce | pce_ov); |
| 886 | end |
| 887 | |
| 888 | // logically correct model |
| 889 | // always @ (l2clk or pce or pce_ov) |
| 890 | // if (l2clk == 1'b0) l1en <= (pce | pce_ov); |
| 891 | endmodule |
| 892 | |
| 893 | // Edge modeled Enable latch |
| 894 | module cl_mc1_l1enable_64x ( |
| 895 | l2clk, |
| 896 | pce, |
| 897 | pce_ov, |
| 898 | l1en); |
| 899 | input l2clk; |
| 900 | input pce; |
| 901 | input pce_ov; |
| 902 | output l1en; |
| 903 | |
| 904 | reg l1en; |
| 905 | |
| 906 | always @ (negedge l2clk ) |
| 907 | begin |
| 908 | l1en <= (pce | pce_ov); |
| 909 | end |
| 910 | |
| 911 | // logically correct model |
| 912 | // always @ (l2clk or pce or pce_ov) |
| 913 | // if (l2clk == 1'b0) l1en <= (pce | pce_ov); |
| 914 | endmodule |
| 915 | |
| 916 | // Edge modeled Enable latch |
| 917 | module cl_mc1_l1enable_8x ( |
| 918 | l2clk, |
| 919 | pce, |
| 920 | pce_ov, |
| 921 | l1en); |
| 922 | input l2clk; |
| 923 | input pce; |
| 924 | input pce_ov; |
| 925 | output l1en; |
| 926 | |
| 927 | reg l1en; |
| 928 | |
| 929 | always @ (negedge l2clk ) |
| 930 | begin |
| 931 | l1en <= (pce | pce_ov); |
| 932 | end |
| 933 | |
| 934 | // logically correct model |
| 935 | // always @ (l2clk or pce or pce_ov) |
| 936 | // if (l2clk == 1'b0) l1en <= (pce | pce_ov); |
| 937 | endmodule |
| 938 | module cl_mc1_l1hdr_16x ( |
| 939 | l2clk, |
| 940 | se, |
| 941 | pce, |
| 942 | pce_ov, |
| 943 | stop, |
| 944 | l1clk |
| 945 | ); |
| 946 | |
| 947 | input l2clk; // level 2 clock, from clock grid |
| 948 | input se; // Scan Enable |
| 949 | input pce; // Clock enable for local power savings |
| 950 | input pce_ov; // TCU sourced clock enable override for testing |
| 951 | input stop; // TCU/CCU sourced clock stop for debug |
| 952 | output l1clk; |
| 953 | |
| 954 | reg l1en; |
| 955 | `ifdef INITLATZERO |
| 956 | initial begin |
| 957 | l1en = 1'b0; |
| 958 | end |
| 959 | `endif |
| 960 | `ifdef SCAN_MODE |
| 961 | always @ (l2clk or stop or pce or pce_ov) |
| 962 | begin |
| 963 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); |
| 964 | end |
| 965 | `else |
| 966 | always @ (negedge l2clk ) |
| 967 | begin |
| 968 | l1en <= (~stop & ( pce | pce_ov )); |
| 969 | end |
| 970 | `endif |
| 971 | |
| 972 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 973 | |
| 974 | endmodule |
| 975 | |
| 976 | module cl_mc1_l1hdr_24x ( |
| 977 | l2clk, |
| 978 | se, |
| 979 | pce, |
| 980 | pce_ov, |
| 981 | stop, |
| 982 | l1clk |
| 983 | ); |
| 984 | |
| 985 | input l2clk; // level 2 clock, from clock grid |
| 986 | input se; // Scan Enable |
| 987 | input pce; // Clock enable for local power savings |
| 988 | input pce_ov; // TCU sourced clock enable override for testing |
| 989 | input stop; // TCU/CCU sourced clock stop for debug |
| 990 | output l1clk; |
| 991 | |
| 992 | reg l1en; |
| 993 | `ifdef INITLATZERO |
| 994 | initial begin |
| 995 | l1en = 1'b0; |
| 996 | end |
| 997 | `endif |
| 998 | `ifdef SCAN_MODE |
| 999 | always @ (l2clk or stop or pce or pce_ov) |
| 1000 | begin |
| 1001 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); |
| 1002 | end |
| 1003 | `else |
| 1004 | always @ (negedge l2clk ) |
| 1005 | begin |
| 1006 | l1en <= (~stop & ( pce | pce_ov )); |
| 1007 | end |
| 1008 | `endif |
| 1009 | |
| 1010 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 1011 | |
| 1012 | endmodule |
| 1013 | |
| 1014 | module cl_mc1_l1hdr_32x ( |
| 1015 | l2clk, |
| 1016 | se, |
| 1017 | pce, |
| 1018 | pce_ov, |
| 1019 | stop, |
| 1020 | l1clk |
| 1021 | ); |
| 1022 | |
| 1023 | input l2clk; // level 2 clock, from clock grid |
| 1024 | input se; // Scan Enable |
| 1025 | input pce; // Clock enable for local power savings |
| 1026 | input pce_ov; // TCU sourced clock enable override for testing |
| 1027 | input stop; // TCU/CCU sourced clock stop for debug |
| 1028 | output l1clk; |
| 1029 | |
| 1030 | reg l1en; |
| 1031 | `ifdef INITLATZERO |
| 1032 | initial begin |
| 1033 | l1en = 1'b0; |
| 1034 | end |
| 1035 | `endif |
| 1036 | `ifdef SCAN_MODE |
| 1037 | always @ (l2clk or stop or pce or pce_ov) |
| 1038 | begin |
| 1039 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); |
| 1040 | end |
| 1041 | `else |
| 1042 | always @ (negedge l2clk ) |
| 1043 | begin |
| 1044 | l1en <= (~stop & ( pce | pce_ov )); |
| 1045 | end |
| 1046 | `endif |
| 1047 | |
| 1048 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 1049 | |
| 1050 | endmodule |
| 1051 | |
| 1052 | module cl_mc1_l1hdr_48x ( |
| 1053 | l2clk, |
| 1054 | se, |
| 1055 | pce, |
| 1056 | pce_ov, |
| 1057 | stop, |
| 1058 | l1clk |
| 1059 | ); |
| 1060 | |
| 1061 | input l2clk; // level 2 clock, from clock grid |
| 1062 | input se; // Scan Enable |
| 1063 | input pce; // Clock enable for local power savings |
| 1064 | input pce_ov; // TCU sourced clock enable override for testing |
| 1065 | input stop; // TCU/CCU sourced clock stop for debug |
| 1066 | output l1clk; |
| 1067 | |
| 1068 | reg l1en; |
| 1069 | `ifdef INITLATZERO |
| 1070 | initial begin |
| 1071 | l1en = 1'b0; |
| 1072 | end |
| 1073 | `endif |
| 1074 | `ifdef SCAN_MODE |
| 1075 | always @ (l2clk or stop or pce or pce_ov) |
| 1076 | begin |
| 1077 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); |
| 1078 | end |
| 1079 | `else |
| 1080 | always @ (negedge l2clk ) |
| 1081 | begin |
| 1082 | l1en <= (~stop & ( pce | pce_ov )); |
| 1083 | end |
| 1084 | `endif |
| 1085 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 1086 | |
| 1087 | endmodule |
| 1088 | |
| 1089 | module cl_mc1_l1hdr_64x ( |
| 1090 | l2clk, |
| 1091 | se, |
| 1092 | pce, |
| 1093 | pce_ov, |
| 1094 | stop, |
| 1095 | l1clk |
| 1096 | ); |
| 1097 | |
| 1098 | input l2clk; // level 2 clock, from clock grid |
| 1099 | input se; // Scan Enable |
| 1100 | input pce; // Clock enable for local power savings |
| 1101 | input pce_ov; // TCU sourced clock enable override for testing |
| 1102 | input stop; // TCU/CCU sourced clock stop for debug |
| 1103 | output l1clk; |
| 1104 | |
| 1105 | reg l1en; |
| 1106 | `ifdef INITLATZERO |
| 1107 | initial begin |
| 1108 | l1en = 1'b0; |
| 1109 | end |
| 1110 | `endif |
| 1111 | `ifdef SCAN_MODE |
| 1112 | always @ (l2clk or stop or pce or pce_ov) |
| 1113 | begin |
| 1114 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); |
| 1115 | end |
| 1116 | `else |
| 1117 | always @ (negedge l2clk ) |
| 1118 | begin |
| 1119 | l1en <= (~stop & ( pce | pce_ov )); |
| 1120 | end |
| 1121 | `endif |
| 1122 | |
| 1123 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 1124 | |
| 1125 | endmodule |
| 1126 | |
| 1127 | module cl_mc1_l1hdr_by4_64x ( |
| 1128 | l2clk, |
| 1129 | se, |
| 1130 | pce, |
| 1131 | pce_ov, |
| 1132 | stop, |
| 1133 | l1clk |
| 1134 | ); |
| 1135 | |
| 1136 | input l2clk; // level 2 clock, from clock grid |
| 1137 | input se; // Scan Enable |
| 1138 | input pce; // Clock enable for local power savings |
| 1139 | input pce_ov; // TCU sourced clock enable override for testing |
| 1140 | input stop; // TCU/CCU sourced clock stop for debug |
| 1141 | output l1clk; |
| 1142 | reg l1en; |
| 1143 | `ifdef INITLATZERO |
| 1144 | initial begin |
| 1145 | l1en = 1'b0; |
| 1146 | end |
| 1147 | `endif |
| 1148 | `ifdef SCAN_MODE |
| 1149 | always @ (l2clk or stop or pce or pce_ov) |
| 1150 | begin |
| 1151 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); |
| 1152 | end |
| 1153 | `else |
| 1154 | always @ (negedge l2clk ) |
| 1155 | begin |
| 1156 | l1en <= (~stop & ( pce | pce_ov )); |
| 1157 | end |
| 1158 | `endif |
| 1159 | |
| 1160 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority |
| 1161 | |
| 1162 | endmodule |
| 1163 | |
| 1164 | |
| 1165 | module cl_mc1_rep_m6_32x ( |
| 1166 | in, |
| 1167 | out |
| 1168 | ); |
| 1169 | input in; |
| 1170 | output out; |
| 1171 | |
| 1172 | assign out = in; |
| 1173 | |
| 1174 | endmodule |
| 1175 | |
| 1176 | module cl_mc1_rrf_msff_8x ( q, so, d, l1clk, si, siclk, soclk ); |
| 1177 | |
| 1178 | output q; |
| 1179 | output so; |
| 1180 | |
| 1181 | input d; |
| 1182 | input l1clk; |
| 1183 | input si; |
| 1184 | input siclk; |
| 1185 | input soclk; |
| 1186 | |
| 1187 | wire q, so; |
| 1188 | reg m, s; |
| 1189 | |
| 1190 | `ifdef SCAN_MODE |
| 1191 | |
| 1192 | always @(l1clk or siclk or soclk or d or si) begin |
| 1193 | |
| 1194 | if (!l1clk && !siclk) m <= d; // Load master with data |
| 1195 | else if ( l1clk && siclk) m <= si; // Load master with scan or flush |
| 1196 | else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan |
| 1197 | |
| 1198 | if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data |
| 1199 | else if (l1clk && siclk && !soclk) s <= si; // Flush |
| 1200 | end |
| 1201 | |
| 1202 | `else |
| 1203 | wire si_unused = si; |
| 1204 | `ifdef INITLATZERO |
| 1205 | initial m = 1'b0; |
| 1206 | initial s = 1'b0; |
| 1207 | `endif |
| 1208 | |
| 1209 | always @(l1clk or d or si or siclk) begin |
| 1210 | if(siclk==0 && l1clk==0) m <= d; |
| 1211 | if(siclk && !l1clk) m <= 1'bx; |
| 1212 | else if(siclk && l1clk) m <= si; |
| 1213 | end |
| 1214 | |
| 1215 | `endif |
| 1216 | |
| 1217 | assign q = s; |
| 1218 | assign so = s; |
| 1219 | |
| 1220 | endmodule |
| 1221 | |
| 1222 | module cl_mc1_rrf_msff_mo_8x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk ); |
| 1223 | |
| 1224 | output mq; |
| 1225 | output mq_l; |
| 1226 | output so; |
| 1227 | output q; |
| 1228 | output q_l; |
| 1229 | input d; |
| 1230 | input l1clk; |
| 1231 | input and_clk; |
| 1232 | input si; |
| 1233 | input siclk; |
| 1234 | input soclk; |
| 1235 | |
| 1236 | wire mq, mq_l, q, q_l, so; |
| 1237 | reg m, s; |
| 1238 | |
| 1239 | `ifdef SCAN_MODE |
| 1240 | always @(l1clk or siclk or soclk or d or si) begin |
| 1241 | |
| 1242 | if (!l1clk && !siclk) m <= d; //Load master with data |
| 1243 | else if ( l1clk && siclk) m <= si; //Load master with scan or flush |
| 1244 | else if (!l1clk && siclk) m <= 1'bx; //Conflict between data and scan |
| 1245 | |
| 1246 | if (l1clk && !soclk && !siclk) s <= m; // Load slave with master data |
| 1247 | else if (l1clk && !soclk && siclk) s <= si; // Flush |
| 1248 | end |
| 1249 | |
| 1250 | `else |
| 1251 | // wire si_unused = si; |
| 1252 | |
| 1253 | `ifdef INITLATZERO |
| 1254 | initial m = 1'b0; |
| 1255 | initial s = 1'b0; |
| 1256 | `endif |
| 1257 | |
| 1258 | always @(l1clk or d or si or siclk) begin |
| 1259 | if (!siclk && !l1clk) m <= d; |
| 1260 | else if ( siclk && !l1clk) m <= 1'bx; |
| 1261 | else if ( siclk && l1clk) m <= si; |
| 1262 | if ( l1clk && !soclk) s <= m; |
| 1263 | end |
| 1264 | |
| 1265 | `endif |
| 1266 | |
| 1267 | `ifdef MODEL_AND |
| 1268 | assign mq = m & (and_clk & l1clk); |
| 1269 | assign mq_l = ~m & (and_clk & l1clk); |
| 1270 | `else |
| 1271 | wire and_clk_unused = and_clk; |
| 1272 | assign mq = m; |
| 1273 | assign mq_l = ~m; |
| 1274 | `endif |
| 1275 | assign so = s; |
| 1276 | assign q = s; |
| 1277 | assign q_l = ~s; |
| 1278 | |
| 1279 | endmodule |
| 1280 | |
| 1281 | module cl_mc1_scm_msff_flop_4x ( q, q_l, so, d, l1clk, si, siclk, soclk); |
| 1282 | |
| 1283 | |
| 1284 | output so; |
| 1285 | output q; |
| 1286 | output q_l; |
| 1287 | input d; |
| 1288 | input l1clk; |
| 1289 | input si; |
| 1290 | input siclk; |
| 1291 | input soclk; |
| 1292 | |
| 1293 | |
| 1294 | wire so; |
| 1295 | reg m, s; |
| 1296 | |
| 1297 | `ifdef SCAN_MODE |
| 1298 | |
| 1299 | always @(l1clk or siclk or soclk or d or si) begin |
| 1300 | |
| 1301 | if (!l1clk && !siclk) m <= d; // Load master with data |
| 1302 | else if ( l1clk && siclk) m <= si; // Load master with scan or flush |
| 1303 | else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan |
| 1304 | |
| 1305 | if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data |
| 1306 | else if (l1clk && siclk && !soclk) s <= si; // Flush |
| 1307 | end |
| 1308 | |
| 1309 | `else |
| 1310 | wire si_unused = si; |
| 1311 | `ifdef INITLATZERO |
| 1312 | initial m = 1'b0; |
| 1313 | initial s = 1'b0; |
| 1314 | `endif |
| 1315 | |
| 1316 | always @(l1clk or d or si or siclk) begin |
| 1317 | if(siclk==0 && l1clk==0) m = d; |
| 1318 | else if(siclk && !l1clk) m = 1'bx; |
| 1319 | if(siclk && l1clk) m = si; |
| 1320 | if(l1clk && !soclk) s = m; |
| 1321 | end |
| 1322 | |
| 1323 | `endif |
| 1324 | |
| 1325 | assign so = s; |
| 1326 | assign q = s; |
| 1327 | assign q_l = ~s; |
| 1328 | |
| 1329 | |
| 1330 | endmodule |
| 1331 | |
| 1332 | module cl_mc1_scm_msff_lat_4x ( latout, q, q_l, so, d, l1clk, si, siclk, soclk); |
| 1333 | |
| 1334 | output latout; |
| 1335 | output so; |
| 1336 | output q; |
| 1337 | output q_l; |
| 1338 | input d; |
| 1339 | input l1clk; |
| 1340 | input si; |
| 1341 | input siclk; |
| 1342 | input soclk; |
| 1343 | |
| 1344 | wire so; |
| 1345 | reg m, s; |
| 1346 | |
| 1347 | `ifdef SCAN_MODE |
| 1348 | `ifdef FAST_FLUSH |
| 1349 | always @(l1clk or siclk or d) begin //vcs optimized code |
| 1350 | |
| 1351 | if (!l1clk && !siclk) m <= d; // Load master with data |
| 1352 | else if ( l1clk && !siclk) s <= m; // Load slave with master data |
| 1353 | else if ( l1clk && siclk) begin |
| 1354 | m <= 1'b0; // flush reset |
| 1355 | s <= 1'b0; |
| 1356 | end |
| 1357 | end |
| 1358 | `else |
| 1359 | |
| 1360 | always @(l1clk or siclk or soclk or d or si) begin |
| 1361 | |
| 1362 | if (!l1clk && !siclk) m <= d; // Load master with data |
| 1363 | else if ( l1clk && siclk) m <= si; // Load master with scan or flush |
| 1364 | else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan |
| 1365 | |
| 1366 | if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data |
| 1367 | else if (l1clk && siclk && !soclk) s <= si; // Flush |
| 1368 | end |
| 1369 | `endif |
| 1370 | |
| 1371 | `else |
| 1372 | wire si_unused = si; |
| 1373 | `ifdef INITLATZERO |
| 1374 | initial m = 1'b0; |
| 1375 | initial s = 1'b0; |
| 1376 | `endif |
| 1377 | |
| 1378 | always @(l1clk or d or si or siclk) begin |
| 1379 | if(siclk==0 && l1clk==0) m = d; |
| 1380 | else if(siclk && !l1clk) m = 1'bx; |
| 1381 | if(siclk && l1clk) m = si; |
| 1382 | if(l1clk && !soclk) s = m; |
| 1383 | end |
| 1384 | |
| 1385 | `endif |
| 1386 | assign latout = m; |
| 1387 | assign so = s; |
| 1388 | assign q = s; |
| 1389 | assign q_l = ~s; |
| 1390 | |
| 1391 | endmodule |
| 1392 | |
| 1393 | module cl_mc1_sram_msff_mo_16x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk ); |
| 1394 | |
| 1395 | output mq; |
| 1396 | output mq_l; |
| 1397 | output so; |
| 1398 | output q; |
| 1399 | output q_l; |
| 1400 | input d; |
| 1401 | input l1clk; |
| 1402 | input and_clk; |
| 1403 | input si; |
| 1404 | input siclk; |
| 1405 | input soclk; |
| 1406 | |
| 1407 | wire mq, mq_l, q, q_l, so; |
| 1408 | reg m, s; |
| 1409 | |
| 1410 | `ifdef SCAN_MODE |
| 1411 | `ifdef FAST_FLUSH |
| 1412 | always @(l1clk or siclk or d) begin //vcs optimized code |
| 1413 | |
| 1414 | if (!l1clk && !siclk) m <= d; // Load master with data |
| 1415 | else if ( l1clk && !siclk) s <= m; // Load slave with master data |
| 1416 | else if ( l1clk && siclk) begin |
| 1417 | m <= 1'b0; // flush reset |
| 1418 | s <= 1'b0; |
| 1419 | end |
| 1420 | end |
| 1421 | `else |
| 1422 | |
| 1423 | always @(l1clk or siclk or soclk or d or si) begin |
| 1424 | |
| 1425 | if (!l1clk && !siclk) m <= d; //Load master with data |
| 1426 | else if ( l1clk && siclk) m <= si; //Load master with scan or flush |
| 1427 | else if (!l1clk && siclk) m <= 1'bx; //Conflict between data and scan |
| 1428 | |
| 1429 | if (l1clk && !soclk && !siclk) s <= m; // Load slave with master data |
| 1430 | else if (l1clk && !soclk && siclk) s <= si; // Flush |
| 1431 | end |
| 1432 | `endif |
| 1433 | |
| 1434 | `else |
| 1435 | // wire si_unused = si; |
| 1436 | |
| 1437 | `ifdef INITLATZERO |
| 1438 | initial m = 1'b0; |
| 1439 | initial s = 1'b0; |
| 1440 | `endif |
| 1441 | |
| 1442 | always @(l1clk or d or si or siclk) begin |
| 1443 | if (!siclk && !l1clk) m <= d; |
| 1444 | else if ( siclk && !l1clk) m <= 1'bx; |
| 1445 | else if ( siclk && l1clk) m <= si; |
| 1446 | if ( l1clk && !soclk) s <= m; |
| 1447 | end |
| 1448 | |
| 1449 | `endif |
| 1450 | |
| 1451 | `ifdef MODEL_AND |
| 1452 | assign mq = m & (and_clk & l1clk); |
| 1453 | assign mq_l = ~m & (and_clk & l1clk); |
| 1454 | `else |
| 1455 | wire and_clk_unused = and_clk; |
| 1456 | assign mq = m; |
| 1457 | assign mq_l = ~m; |
| 1458 | `endif |
| 1459 | assign so = s; |
| 1460 | assign q = s; |
| 1461 | assign q_l = ~s; |
| 1462 | |
| 1463 | endmodule |
| 1464 | |
| 1465 | module cl_mc1_sram_msff_mo_32x ( mq, mq_l, q, so, d, l1clk, si, siclk, soclk, and_clk ); |
| 1466 | |
| 1467 | output mq; |
| 1468 | output mq_l; |
| 1469 | output so; |
| 1470 | output q; |
| 1471 | input d; |
| 1472 | input l1clk; |
| 1473 | input and_clk; |
| 1474 | input si; |
| 1475 | input siclk; |
| 1476 | input soclk; |
| 1477 | |
| 1478 | wire mq, mq_l, q, so; |
| 1479 | reg m, s; |
| 1480 | |
| 1481 | `ifdef SCAN_MODE |
| 1482 | `ifdef FAST_FLUSH |
| 1483 | always @(l1clk or siclk or d) begin //vcs optimized code |
| 1484 | |
| 1485 | if (!l1clk && !siclk) m <= d; // Load master with data |
| 1486 | else if ( l1clk && !siclk) s <= m; // Load slave with master data |
| 1487 | else if ( l1clk && siclk) begin |
| 1488 | m <= 1'b0; // flush reset |
| 1489 | s <= 1'b0; |
| 1490 | end |
| 1491 | end |
| 1492 | `else |
| 1493 | |
| 1494 | always @(l1clk or siclk or soclk or d or si) begin |
| 1495 | |
| 1496 | if (!l1clk && !siclk) m <= d; //Load master with data |
| 1497 | else if ( l1clk && siclk) m <= si; //Load master with scan or flush |
| 1498 | else if (!l1clk && siclk) m <= 1'bx; //Conflict between data and scan |
| 1499 | |
| 1500 | if (l1clk && !soclk && !siclk) s <= m; // Load slave with master data |
| 1501 | else if (l1clk && !soclk && siclk) s <= si; // Flush |
| 1502 | end |
| 1503 | `endif |
| 1504 | |
| 1505 | `else |
| 1506 | // wire si_unused = si; |
| 1507 | |
| 1508 | `ifdef INITLATZERO |
| 1509 | initial m = 1'b0; |
| 1510 | initial s = 1'b0; |
| 1511 | `endif |
| 1512 | |
| 1513 | always @(l1clk or d or si or siclk) begin |
| 1514 | if (!siclk && !l1clk) m <= d; |
| 1515 | else if ( siclk && !l1clk) m <= 1'bx; |
| 1516 | else if ( siclk && l1clk) m <= si; |
| 1517 | if ( l1clk && !soclk) s <= m; |
| 1518 | end |
| 1519 | |
| 1520 | `endif |
| 1521 | |
| 1522 | `ifdef MODEL_AND |
| 1523 | assign mq = m & (and_clk & l1clk); |
| 1524 | assign mq_l = ~m & (and_clk & l1clk); |
| 1525 | `else |
| 1526 | wire and_clk_unused = and_clk; |
| 1527 | assign mq = m; |
| 1528 | assign mq_l = ~m; |
| 1529 | `endif |
| 1530 | assign so = s; |
| 1531 | assign q = s; |
| 1532 | |
| 1533 | endmodule |
| 1534 | |
| 1535 | module cl_mc1_sram_msff_mo_4x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk ); |
| 1536 | |
| 1537 | output mq; |
| 1538 | output mq_l; |
| 1539 | output so; |
| 1540 | output q; |
| 1541 | output q_l; |
| 1542 | input d; |
| 1543 | input l1clk; |
| 1544 | input and_clk; |
| 1545 | input si; |
| 1546 | input siclk; |
| 1547 | input soclk; |
| 1548 | |
| 1549 | wire mq, mq_l, q, q_l, so; |
| 1550 | reg m, s; |
| 1551 | |
| 1552 | `ifdef SCAN_MODE |
| 1553 | `ifdef FAST_FLUSH |
| 1554 | always @(l1clk or siclk or d) begin //vcs optimized code |
| 1555 | |
| 1556 | if (!l1clk && !siclk) m <= d; // Load master with data |
| 1557 | else if ( l1clk && !siclk) s <= m; // Load slave with master data |
| 1558 | else if ( l1clk && siclk) begin |
| 1559 | m <= 1'b0; // flush reset |
| 1560 | s <= 1'b0; |
| 1561 | end |
| 1562 | end |
| 1563 | `else |
| 1564 | |
| 1565 | always @(l1clk or siclk or soclk or d or si) begin |
| 1566 | |
| 1567 | if (!l1clk && !siclk) m <= d; //Load master with data |
| 1568 | else if ( l1clk && siclk) m <= si; //Load master with scan or flush |
| 1569 | else if (!l1clk && siclk) m <= 1'bx; //Conflict between data and scan |
| 1570 | |
| 1571 | if (l1clk && !soclk && !siclk) s <= m; // Load slave with master data |
| 1572 | else if (l1clk && !soclk && siclk) s <= si; // Flush |
| 1573 | end |
| 1574 | `endif |
| 1575 | |
| 1576 | `else |
| 1577 | // wire si_unused = si; |
| 1578 | |
| 1579 | `ifdef INITLATZERO |
| 1580 | initial m = 1'b0; |
| 1581 | initial s = 1'b0; |
| 1582 | `endif |
| 1583 | |
| 1584 | always @(l1clk or d or si or siclk) begin |
| 1585 | if (!siclk && !l1clk) m <= d; |
| 1586 | else if ( siclk && !l1clk) m <= 1'bx; |
| 1587 | else if ( siclk && l1clk) m <= si; |
| 1588 | if ( l1clk && !soclk) s <= m; |
| 1589 | end |
| 1590 | |
| 1591 | `endif |
| 1592 | |
| 1593 | `ifdef MODEL_AND |
| 1594 | assign mq = m & (and_clk & l1clk); |
| 1595 | assign mq_l = ~m & (and_clk & l1clk); |
| 1596 | `else |
| 1597 | wire and_clk_unused = and_clk; |
| 1598 | assign mq = m; |
| 1599 | assign mq_l = ~m; |
| 1600 | `endif |
| 1601 | assign so = s; |
| 1602 | assign q = s; |
| 1603 | assign q_l = ~s; |
| 1604 | |
| 1605 | endmodule |
| 1606 | |
| 1607 | module cl_mc1_sram_msff_mo_8x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk ); |
| 1608 | |
| 1609 | output mq; |
| 1610 | output mq_l; |
| 1611 | output so; |
| 1612 | output q; |
| 1613 | output q_l; |
| 1614 | input d; |
| 1615 | input l1clk; |
| 1616 | input and_clk; |
| 1617 | input si; |
| 1618 | input siclk; |
| 1619 | input soclk; |
| 1620 | |
| 1621 | wire mq, mq_l, q, q_l, so; |
| 1622 | reg m, s; |
| 1623 | |
| 1624 | `ifdef SCAN_MODE |
| 1625 | `ifdef FAST_FLUSH |
| 1626 | always @(l1clk or siclk or d) begin //vcs optimized code |
| 1627 | |
| 1628 | if (!l1clk && !siclk) m <= d; // Load master with data |
| 1629 | else if ( l1clk && !siclk) s <= m; // Load slave with master data |
| 1630 | else if ( l1clk && siclk) begin |
| 1631 | m <= 1'b0; // flush reset |
| 1632 | s <= 1'b0; |
| 1633 | end |
| 1634 | end |
| 1635 | `else |
| 1636 | |
| 1637 | always @(l1clk or siclk or soclk or d or si) begin |
| 1638 | |
| 1639 | if (!l1clk && !siclk) m <= d; //Load master with data |
| 1640 | else if ( l1clk && siclk) m <= si; //Load master with scan or flush |
| 1641 | else if (!l1clk && siclk) m <= 1'bx; //Conflict between data and scan |
| 1642 | |
| 1643 | if (l1clk && !soclk && !siclk) s <= m; // Load slave with master data |
| 1644 | else if (l1clk && !soclk && siclk) s <= si; // Flush |
| 1645 | end |
| 1646 | `endif |
| 1647 | |
| 1648 | `else |
| 1649 | // wire si_unused = si; |
| 1650 | |
| 1651 | `ifdef INITLATZERO |
| 1652 | initial m = 1'b0; |
| 1653 | initial s = 1'b0; |
| 1654 | `endif |
| 1655 | |
| 1656 | always @(l1clk or d or si or siclk) begin |
| 1657 | if (!siclk && !l1clk) m <= d; |
| 1658 | else if ( siclk && !l1clk) m <= 1'bx; |
| 1659 | else if ( siclk && l1clk) m <= si; |
| 1660 | if ( l1clk && !soclk) s <= m; |
| 1661 | end |
| 1662 | |
| 1663 | `endif |
| 1664 | |
| 1665 | `ifdef MODEL_AND |
| 1666 | assign mq = m & (and_clk & l1clk); |
| 1667 | assign mq_l = ~m & (and_clk & l1clk); |
| 1668 | `else |
| 1669 | wire and_clk_unused = and_clk; |
| 1670 | assign mq = m; |
| 1671 | assign mq_l = ~m; |
| 1672 | `endif |
| 1673 | assign so = s; |
| 1674 | assign q = s; |
| 1675 | assign q_l = ~s; |
| 1676 | |
| 1677 | endmodule |
| 1678 | module cl_mc1_sram_msff_mo_nand2_16x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk ); |
| 1679 | |
| 1680 | output mq; |
| 1681 | output mq_l; |
| 1682 | output q; |
| 1683 | output q_l; |
| 1684 | output so; |
| 1685 | |
| 1686 | input d; |
| 1687 | input l1clk; |
| 1688 | input si; |
| 1689 | input siclk; |
| 1690 | input soclk; |
| 1691 | |
| 1692 | wire mq; |
| 1693 | wire mq_l; |
| 1694 | wire q; |
| 1695 | wire q_l; |
| 1696 | wire so; |
| 1697 | |
| 1698 | reg m, s; |
| 1699 | |
| 1700 | `ifdef SCAN_MODE |
| 1701 | always @(l1clk or siclk or soclk or d or si) |
| 1702 | begin |
| 1703 | if (!l1clk && !siclk) m <= d; // Load master with data |
| 1704 | else if ( l1clk && siclk) m <= si; // Load master with scan or flush |
| 1705 | else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan |
| 1706 | |
| 1707 | if ( l1clk && !siclk && !soclk) s <= m; // Load slave with master data |
| 1708 | else if ( l1clk && siclk && !soclk) s <= si; // Flush |
| 1709 | end |
| 1710 | `else |
| 1711 | // wire si_unused = si; |
| 1712 | |
| 1713 | `ifdef INITLATZERO |
| 1714 | initial m = 1'b0; |
| 1715 | initial s = 1'b0; |
| 1716 | `endif |
| 1717 | |
| 1718 | always @(l1clk or d or si or siclk) begin |
| 1719 | if (!siclk && !l1clk) m <= d; |
| 1720 | else if ( siclk && !l1clk) m <= 1'bx; |
| 1721 | else if ( siclk && l1clk) m <= si; |
| 1722 | if ( l1clk && !soclk) s <= m; |
| 1723 | end |
| 1724 | |
| 1725 | `endif |
| 1726 | |
| 1727 | `ifdef MODEL_AND |
| 1728 | assign mq = m & l1clk; |
| 1729 | assign mq_l = ~m & l1clk; |
| 1730 | `else |
| 1731 | wire si_unused = siclk; |
| 1732 | assign mq = m; |
| 1733 | assign mq_l = ~m; |
| 1734 | `endif |
| 1735 | |
| 1736 | assign so = s; |
| 1737 | assign q = s; |
| 1738 | assign q_l = ~s; |
| 1739 | |
| 1740 | endmodule |
| 1741 | |
| 1742 | module cl_mc1_sram_msff_mo_nand2_8x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk ); |
| 1743 | |
| 1744 | output mq; |
| 1745 | output mq_l; |
| 1746 | output q; |
| 1747 | output q_l; |
| 1748 | output so; |
| 1749 | |
| 1750 | input d; |
| 1751 | input l1clk; |
| 1752 | input si; |
| 1753 | input siclk; |
| 1754 | input soclk; |
| 1755 | |
| 1756 | wire mq; |
| 1757 | wire mq_l; |
| 1758 | wire q; |
| 1759 | wire q_l; |
| 1760 | wire so; |
| 1761 | |
| 1762 | reg m, s; |
| 1763 | |
| 1764 | `ifdef SCAN_MODE |
| 1765 | always @(l1clk or siclk or soclk or d or si) |
| 1766 | begin |
| 1767 | if (!l1clk && !siclk) m <= d; // Load master with data |
| 1768 | else if ( l1clk && siclk) m <= si; // Load master with scan or flush |
| 1769 | else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan |
| 1770 | |
| 1771 | if ( l1clk && !siclk && !soclk) s <= m; // Load slave with master data |
| 1772 | else if ( l1clk && siclk && !soclk) s <= si; // Flush |
| 1773 | end |
| 1774 | `else |
| 1775 | // wire si_unused = si; |
| 1776 | |
| 1777 | `ifdef INITLATZERO |
| 1778 | initial m = 1'b0; |
| 1779 | initial s = 1'b0; |
| 1780 | `endif |
| 1781 | |
| 1782 | always @(l1clk or d or si or siclk) begin |
| 1783 | if (!siclk && !l1clk) m <= d; |
| 1784 | else if ( siclk && !l1clk) m <= 1'bx; |
| 1785 | else if ( siclk && l1clk) m <= si; |
| 1786 | if ( l1clk && !soclk) s <= m; |
| 1787 | end |
| 1788 | |
| 1789 | `endif |
| 1790 | |
| 1791 | `ifdef MODEL_AND |
| 1792 | assign mq = m & l1clk; |
| 1793 | assign mq_l = ~m & l1clk; |
| 1794 | `else |
| 1795 | wire si_unused = siclk; |
| 1796 | assign mq = m; |
| 1797 | assign mq_l = ~m; |
| 1798 | `endif |
| 1799 | |
| 1800 | assign so = s; |
| 1801 | assign q = s; |
| 1802 | assign q_l = ~s; |
| 1803 | |
| 1804 | endmodule |
| 1805 | |
| 1806 | |
| 1807 | module cl_mc1_sram_msff_mo_nand3_16x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk ); |
| 1808 | |
| 1809 | output mq; |
| 1810 | output mq_l; |
| 1811 | output so; |
| 1812 | output q; |
| 1813 | output q_l; |
| 1814 | input d; |
| 1815 | input l1clk; |
| 1816 | input and_clk; |
| 1817 | input si; |
| 1818 | input siclk; |
| 1819 | input soclk; |
| 1820 | |
| 1821 | wire mq, mq_l, q, q_l, so; |
| 1822 | reg m, s; |
| 1823 | |
| 1824 | `ifdef SCAN_MODE |
| 1825 | always @(l1clk or siclk or soclk or d or si) begin |
| 1826 | |
| 1827 | if (!l1clk && !siclk) m <= d; //Load master with data |
| 1828 | else if ( l1clk && siclk) m <= si; //Load master with scan or flush |
| 1829 | else if (!l1clk && siclk) m <= 1'bx; //Conflict between data and scan |
| 1830 | |
| 1831 | if (l1clk && !soclk && !siclk) s <= m; // Load slave with master data |
| 1832 | else if (l1clk && !soclk && siclk) s <= si; // Flush |
| 1833 | end |
| 1834 | |
| 1835 | `else |
| 1836 | // wire si_unused = si; |
| 1837 | |
| 1838 | `ifdef INITLATZERO |
| 1839 | initial m = 1'b0; |
| 1840 | initial s = 1'b0; |
| 1841 | `endif |
| 1842 | |
| 1843 | always @(l1clk or d or si or siclk) begin |
| 1844 | if (!siclk && !l1clk) m <= d; |
| 1845 | else if ( siclk && !l1clk) m <= 1'bx; |
| 1846 | else if ( siclk && l1clk) m <= si; |
| 1847 | if ( l1clk && !soclk) s <= m; |
| 1848 | end |
| 1849 | |
| 1850 | `endif |
| 1851 | |
| 1852 | `ifdef MODEL_AND |
| 1853 | assign mq = m & (and_clk & l1clk); |
| 1854 | assign mq_l = ~m & (and_clk & l1clk); |
| 1855 | `else |
| 1856 | wire and_clk_unused = and_clk; |
| 1857 | assign mq = m; |
| 1858 | assign mq_l = ~m; |
| 1859 | `endif |
| 1860 | assign so = s; |
| 1861 | assign q = s; |
| 1862 | assign q_l = ~s; |
| 1863 | |
| 1864 | endmodule |
| 1865 | |
| 1866 | module cl_mc1_sram_msff_mo_nand3_8x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk ); |
| 1867 | |
| 1868 | output mq; |
| 1869 | output mq_l; |
| 1870 | output so; |
| 1871 | output q; |
| 1872 | output q_l; |
| 1873 | input d; |
| 1874 | input l1clk; |
| 1875 | input and_clk; |
| 1876 | input si; |
| 1877 | input siclk; |
| 1878 | input soclk; |
| 1879 | |
| 1880 | wire mq, mq_l, q, q_l, so; |
| 1881 | reg m, s; |
| 1882 | |
| 1883 | `ifdef SCAN_MODE |
| 1884 | always @(l1clk or siclk or soclk or d or si) begin |
| 1885 | |
| 1886 | if (!l1clk && !siclk) m <= d; //Load master with data |
| 1887 | else if ( l1clk && siclk) m <= si; //Load master with scan or flush |
| 1888 | else if (!l1clk && siclk) m <= 1'bx; //Conflict between data and scan |
| 1889 | |
| 1890 | if (l1clk && !soclk && !siclk) s <= m; // Load slave with master data |
| 1891 | else if (l1clk && !soclk && siclk) s <= si; // Flush |
| 1892 | end |
| 1893 | |
| 1894 | `else |
| 1895 | // wire si_unused = si; |
| 1896 | |
| 1897 | `ifdef INITLATZERO |
| 1898 | initial m = 1'b0; |
| 1899 | initial s = 1'b0; |
| 1900 | `endif |
| 1901 | |
| 1902 | always @(l1clk or d or si or siclk) begin |
| 1903 | if (!siclk && !l1clk) m <= d; |
| 1904 | else if ( siclk && !l1clk) m <= 1'bx; |
| 1905 | else if ( siclk && l1clk) m <= si; |
| 1906 | if ( l1clk && !soclk) s <= m; |
| 1907 | end |
| 1908 | |
| 1909 | `endif |
| 1910 | |
| 1911 | `ifdef MODEL_AND |
| 1912 | assign mq = m & (and_clk & l1clk); |
| 1913 | assign mq_l = ~m & (and_clk & l1clk); |
| 1914 | `else |
| 1915 | wire and_clk_unused = and_clk; |
| 1916 | assign mq = m; |
| 1917 | assign mq_l = ~m; |
| 1918 | `endif |
| 1919 | assign so = s; |
| 1920 | assign q = s; |
| 1921 | assign q_l = ~s; |
| 1922 | |
| 1923 | endmodule |
| 1924 | |
| 1925 | module cl_mc1_sram_msff_mo_opt_16x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk ); |
| 1926 | |
| 1927 | output mq; |
| 1928 | output mq_l; |
| 1929 | output so; |
| 1930 | output q; |
| 1931 | output q_l; |
| 1932 | input d; |
| 1933 | input l1clk; |
| 1934 | input and_clk; |
| 1935 | input si; |
| 1936 | input siclk; |
| 1937 | input soclk; |
| 1938 | |
| 1939 | wire mq, mq_l, q, q_l, so; |
| 1940 | reg m, s; |
| 1941 | |
| 1942 | `ifdef SCAN_MODE |
| 1943 | always @(l1clk or siclk or soclk or d or si) begin |
| 1944 | |
| 1945 | if (!l1clk && !siclk) m <= d; //Load master with data |
| 1946 | else if ( l1clk && siclk) m <= si; //Load master with scan or flush |
| 1947 | else if (!l1clk && siclk) m <= 1'bx; //Conflict between data and scan |
| 1948 | |
| 1949 | if (l1clk && !soclk && !siclk) s <= m; // Load slave with master data |
| 1950 | else if (l1clk && !soclk && siclk) s <= si; // Flush |
| 1951 | end |
| 1952 | |
| 1953 | `else |
| 1954 | // wire si_unused = si; |
| 1955 | |
| 1956 | `ifdef INITLATZERO |
| 1957 | initial m = 1'b0; |
| 1958 | initial s = 1'b0; |
| 1959 | `endif |
| 1960 | |
| 1961 | always @(l1clk or d or si or siclk) begin |
| 1962 | if (!siclk && !l1clk) m <= d; |
| 1963 | else if ( siclk && !l1clk) m <= 1'bx; |
| 1964 | else if ( siclk && l1clk) m <= si; |
| 1965 | if ( l1clk && !soclk) s <= m; |
| 1966 | end |
| 1967 | |
| 1968 | `endif |
| 1969 | |
| 1970 | `ifdef MODEL_AND |
| 1971 | assign mq = m & (and_clk & l1clk); |
| 1972 | assign mq_l = ~m & (and_clk & l1clk); |
| 1973 | `else |
| 1974 | wire and_clk_unused = and_clk; |
| 1975 | assign mq = m; |
| 1976 | assign mq_l = ~m; |
| 1977 | `endif |
| 1978 | assign so = s; |
| 1979 | assign q = s; |
| 1980 | assign q_l = ~s; |
| 1981 | |
| 1982 | endmodule |
| 1983 | |
| 1984 | module cl_mc1_sram_msff_mo_opt_8x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk ); |
| 1985 | |
| 1986 | output mq; |
| 1987 | output mq_l; |
| 1988 | output so; |
| 1989 | output q; |
| 1990 | output q_l; |
| 1991 | input d; |
| 1992 | input l1clk; |
| 1993 | input and_clk; |
| 1994 | input si; |
| 1995 | input siclk; |
| 1996 | input soclk; |
| 1997 | |
| 1998 | wire mq, mq_l, q, q_l, so; |
| 1999 | reg m, s; |
| 2000 | |
| 2001 | `ifdef SCAN_MODE |
| 2002 | always @(l1clk or siclk or soclk or d or si) begin |
| 2003 | |
| 2004 | if (!l1clk && !siclk) m <= d; //Load master with data |
| 2005 | else if ( l1clk && siclk) m <= si; //Load master with scan or flush |
| 2006 | else if (!l1clk && siclk) m <= 1'bx; //Conflict between data and scan |
| 2007 | |
| 2008 | if (l1clk && !soclk && !siclk) s <= m; // Load slave with master data |
| 2009 | else if (l1clk && !soclk && siclk) s <= si; // Flush |
| 2010 | end |
| 2011 | |
| 2012 | `else |
| 2013 | // wire si_unused = si; |
| 2014 | |
| 2015 | `ifdef INITLATZERO |
| 2016 | initial m = 1'b0; |
| 2017 | initial s = 1'b0; |
| 2018 | `endif |
| 2019 | |
| 2020 | always @(l1clk or d or si or siclk) begin |
| 2021 | if (!siclk && !l1clk) m <= d; |
| 2022 | else if ( siclk && !l1clk) m <= 1'bx; |
| 2023 | else if ( siclk && l1clk) m <= si; |
| 2024 | if ( l1clk && !soclk) s <= m; |
| 2025 | end |
| 2026 | |
| 2027 | `endif |
| 2028 | |
| 2029 | `ifdef MODEL_AND |
| 2030 | assign mq = m & (and_clk & l1clk); |
| 2031 | assign mq_l = ~m & (and_clk & l1clk); |
| 2032 | `else |
| 2033 | wire and_clk_unused = and_clk; |
| 2034 | assign mq = m; |
| 2035 | assign mq_l = ~m; |
| 2036 | `endif |
| 2037 | assign so = s; |
| 2038 | assign q = s; |
| 2039 | assign q_l = ~s; |
| 2040 | |
| 2041 | endmodule |
| 2042 | module cl_mc1_sram_msff_mo_phaseb_8x ( phaseb_mq, phaseb_mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk ); |
| 2043 | |
| 2044 | output phaseb_mq; |
| 2045 | output phaseb_mq_l; |
| 2046 | output q; |
| 2047 | output q_l; |
| 2048 | output so; |
| 2049 | |
| 2050 | input d; |
| 2051 | input l1clk; |
| 2052 | input si; |
| 2053 | input siclk; |
| 2054 | input soclk; |
| 2055 | input and_clk; |
| 2056 | |
| 2057 | wire phaseb_mq; |
| 2058 | wire phaseb_mq_l; |
| 2059 | reg q; |
| 2060 | wire q_l; |
| 2061 | wire so; |
| 2062 | |
| 2063 | reg m; |
| 2064 | |
| 2065 | `ifdef SCAN_MODE |
| 2066 | always @(l1clk or siclk or soclk or d or si) |
| 2067 | begin |
| 2068 | if (!l1clk && !siclk) m <= d; // Load master with data |
| 2069 | else if ( l1clk && siclk) m <= si; // Load master with scan or flush |
| 2070 | else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan |
| 2071 | |
| 2072 | if ( l1clk && !siclk && !soclk) q <= m; // Load slave with master data |
| 2073 | else if ( l1clk && siclk && !soclk) q <= si; // Flush |
| 2074 | end |
| 2075 | `else |
| 2076 | // wire si_unused = si; |
| 2077 | |
| 2078 | `ifdef INITLATZERO |
| 2079 | initial q = 1'b0; |
| 2080 | initial m = 1'b0; |
| 2081 | `endif |
| 2082 | |
| 2083 | always @(l1clk or d or si or siclk) begin |
| 2084 | if (!siclk && !l1clk) m <= d; |
| 2085 | else if ( siclk && !l1clk) m <= 1'bx; |
| 2086 | else if ( siclk && l1clk) m <= si; |
| 2087 | if ( l1clk && !soclk) q <= m; |
| 2088 | end |
| 2089 | |
| 2090 | `endif |
| 2091 | |
| 2092 | `ifdef MODEL_AND |
| 2093 | assign phaseb_mq = ~and_clk && q; |
| 2094 | assign phaseb_mq_l = ~and_clk && q_l; |
| 2095 | `else |
| 2096 | wire and_clk_unused = and_clk; |
| 2097 | assign phaseb_mq = q; |
| 2098 | assign phaseb_mq_l = ~q; |
| 2099 | `endif |
| 2100 | assign so = q; |
| 2101 | assign q_l = ~q; |
| 2102 | |
| 2103 | endmodule |
| 2104 | |
| 2105 | |
| 2106 | module cl_mc1_tcam_msff_4x ( q, so, d, l1clk, si, siclk, soclk ); |
| 2107 | |
| 2108 | output q; |
| 2109 | output so; |
| 2110 | |
| 2111 | input d; |
| 2112 | input l1clk; |
| 2113 | input si; |
| 2114 | input siclk; |
| 2115 | input soclk; |
| 2116 | |
| 2117 | wire q, so; |
| 2118 | reg m, s; |
| 2119 | |
| 2120 | `ifdef SCAN_MODE |
| 2121 | |
| 2122 | always @(l1clk or siclk or soclk or d or si) begin |
| 2123 | |
| 2124 | if (!l1clk && !siclk) m <= d; // Load master with data |
| 2125 | else if ( l1clk && siclk) m <= si; // Load master with scan or flush |
| 2126 | else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan |
| 2127 | |
| 2128 | if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data |
| 2129 | else if (l1clk && siclk && !soclk) s <= si; // Flush |
| 2130 | end |
| 2131 | |
| 2132 | `else |
| 2133 | wire si_unused = si; |
| 2134 | `ifdef INITLATZERO |
| 2135 | initial m = 1'b0; |
| 2136 | initial s = 1'b0; |
| 2137 | `endif |
| 2138 | |
| 2139 | always @(l1clk or d or si or siclk) begin |
| 2140 | if(siclk==0 && l1clk==0) m <= d; |
| 2141 | if(siclk && !l1clk) m <= 1'bx; |
| 2142 | else if(siclk && l1clk) m <= si; |
| 2143 | end |
| 2144 | |
| 2145 | `endif |
| 2146 | |
| 2147 | assign q = s; |
| 2148 | assign so = s; |
| 2149 | |
| 2150 | endmodule |
| 2151 | |
| 2152 | module cl_mc1_tisram_bla_4x (q_a, d_b, l1clk); |
| 2153 | output q_a; |
| 2154 | input d_b; |
| 2155 | input l1clk; |
| 2156 | reg q_a; |
| 2157 | |
| 2158 | `ifdef INITLATZERO |
| 2159 | initial q_a = 1'b0; |
| 2160 | `endif |
| 2161 | |
| 2162 | always @(l1clk or d_b) begin |
| 2163 | if(l1clk==1) q_a <= d_b; |
| 2164 | end |
| 2165 | |
| 2166 | endmodule |
| 2167 | |
| 2168 | |
| 2169 | module cl_mc1_tisram_blb_4x (q_b, d_a, l1clk); |
| 2170 | output q_b; |
| 2171 | input d_a; |
| 2172 | input l1clk; |
| 2173 | reg q_b; |
| 2174 | |
| 2175 | `ifdef INITLATZERO |
| 2176 | initial q_b = 1'b0; |
| 2177 | `endif |
| 2178 | |
| 2179 | always @(l1clk or d_a) begin |
| 2180 | if(l1clk==0) q_b <= d_a; |
| 2181 | end |
| 2182 | |
| 2183 | endmodule |
| 2184 | |
| 2185 | |
| 2186 | module cl_mc1_tisram_blbi_8x (q_b_l, d_a, l1clk); |
| 2187 | output q_b_l; |
| 2188 | input d_a; |
| 2189 | input l1clk; |
| 2190 | reg q_b_l; |
| 2191 | |
| 2192 | `ifdef INITLATZERO |
| 2193 | initial q_b_l = 1'b0; |
| 2194 | `endif |
| 2195 | |
| 2196 | always @(l1clk or d_a) begin |
| 2197 | if(l1clk==0) q_b_l <= ~d_a; |
| 2198 | end |
| 2199 | |
| 2200 | endmodule |
| 2201 | |
| 2202 | module cl_mc1_tisram_msff_16x ( latout, latout_l, so, d, l1clk, si, |
| 2203 | siclk, soclk ); |
| 2204 | |
| 2205 | output latout; |
| 2206 | output latout_l; |
| 2207 | output so; |
| 2208 | |
| 2209 | input d; |
| 2210 | input l1clk; |
| 2211 | input si; |
| 2212 | input siclk; |
| 2213 | input soclk; |
| 2214 | |
| 2215 | wire latout, latout_l, so; |
| 2216 | reg m, s; |
| 2217 | |
| 2218 | `ifdef SCAN_MODE |
| 2219 | |
| 2220 | always @(l1clk or siclk or soclk or d or si) begin |
| 2221 | |
| 2222 | if (!l1clk && !siclk) m <= d; // Load master with data |
| 2223 | else if ( l1clk && siclk) m <= si; // Load master with scan or flush |
| 2224 | else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan |
| 2225 | |
| 2226 | if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data |
| 2227 | else if (l1clk && siclk && !soclk) s <= si; // Flush |
| 2228 | end |
| 2229 | |
| 2230 | `else |
| 2231 | wire si_unused = si; |
| 2232 | `ifdef INITLATZERO |
| 2233 | initial m = 1'b0; |
| 2234 | initial s = 1'b0; |
| 2235 | `endif |
| 2236 | |
| 2237 | always @(l1clk or d or si or siclk) begin |
| 2238 | if(siclk==0 && l1clk==0) m <= d; |
| 2239 | if(siclk && !l1clk) m <= 1'bx; |
| 2240 | else if(siclk && l1clk) m <= si; |
| 2241 | end |
| 2242 | |
| 2243 | `endif |
| 2244 | |
| 2245 | assign latout = m; |
| 2246 | assign latout_l = ~m; |
| 2247 | assign so = s; |
| 2248 | |
| 2249 | endmodule |
| 2250 | |
| 2251 | module cl_mc1_tisram_msff_8x ( latout, latout_l, so, d, l1clk, si, |
| 2252 | siclk, soclk ); |
| 2253 | |
| 2254 | output latout; |
| 2255 | output latout_l; |
| 2256 | output so; |
| 2257 | |
| 2258 | input d; |
| 2259 | input l1clk; |
| 2260 | input si; |
| 2261 | input siclk; |
| 2262 | input soclk; |
| 2263 | |
| 2264 | wire latout, latout_l, so; |
| 2265 | reg m, s; |
| 2266 | |
| 2267 | `ifdef SCAN_MODE |
| 2268 | |
| 2269 | always @(l1clk or siclk or soclk or d or si) begin |
| 2270 | |
| 2271 | if (!l1clk && !siclk) m <= d; // Load master with data |
| 2272 | else if ( l1clk && siclk) m <= si; // Load master with scan or flush |
| 2273 | else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan |
| 2274 | |
| 2275 | if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data |
| 2276 | else if (l1clk && siclk && !soclk) s <= si; // Flush |
| 2277 | end |
| 2278 | |
| 2279 | `else |
| 2280 | wire si_unused = si; |
| 2281 | `ifdef INITLATZERO |
| 2282 | initial m = 1'b0; |
| 2283 | initial s = 1'b0; |
| 2284 | `endif |
| 2285 | |
| 2286 | always @(l1clk or d or si or siclk) begin |
| 2287 | if(siclk==0 && l1clk==0) m <= d; |
| 2288 | if(siclk && !l1clk) m <= 1'bx; |
| 2289 | else if(siclk && l1clk) m <= si; |
| 2290 | end |
| 2291 | |
| 2292 | `endif |
| 2293 | |
| 2294 | assign latout = m; |
| 2295 | assign latout_l = ~m; |
| 2296 | assign so = s; |
| 2297 | |
| 2298 | endmodule |