| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: cl_u1.behV |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module cl_u1_aoi12_12x ( |
| 36 | out, |
| 37 | in10, |
| 38 | in00, |
| 39 | in01 ); |
| 40 | |
| 41 | output out; |
| 42 | input in10; |
| 43 | input in00; |
| 44 | input in01; |
| 45 | |
| 46 | `ifdef LIB |
| 47 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 48 | `endif |
| 49 | |
| 50 | endmodule |
| 51 | // -------------------------------------------------- |
| 52 | // File: cl_u1_aoi12_16x.behV |
| 53 | // Auto generated verilog module by HnBCellAuto |
| 54 | // |
| 55 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST |
| 56 | // By: balmiki |
| 57 | // -------------------------------------------------- |
| 58 | // |
| 59 | module cl_u1_aoi12_16x ( |
| 60 | out, |
| 61 | in10, |
| 62 | in00, |
| 63 | in01 ); |
| 64 | |
| 65 | output out; |
| 66 | input in10; |
| 67 | input in00; |
| 68 | input in01; |
| 69 | |
| 70 | `ifdef LIB |
| 71 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 72 | `endif |
| 73 | |
| 74 | endmodule |
| 75 | // -------------------------------------------------- |
| 76 | // File: cl_u1_aoi12_1x.behV |
| 77 | // Auto generated verilog module by HnBCellAuto |
| 78 | // |
| 79 | // Created: Thursday Dec 6,2001 at 02:09:00 PM PST |
| 80 | // By: balmiki |
| 81 | // -------------------------------------------------- |
| 82 | // |
| 83 | module cl_u1_aoi12_1x ( |
| 84 | out, |
| 85 | in10, |
| 86 | in00, |
| 87 | in01 ); |
| 88 | |
| 89 | output out; |
| 90 | input in10; |
| 91 | input in00; |
| 92 | input in01; |
| 93 | |
| 94 | `ifdef LIB |
| 95 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 96 | `endif |
| 97 | |
| 98 | endmodule |
| 99 | // -------------------------------------------------- |
| 100 | // File: cl_u1_aoi12_2x.behV |
| 101 | // Auto generated verilog module by HnBCellAuto |
| 102 | // |
| 103 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST |
| 104 | // By: balmiki |
| 105 | // -------------------------------------------------- |
| 106 | // |
| 107 | module cl_u1_aoi12_2x ( |
| 108 | out, |
| 109 | in10, |
| 110 | in00, |
| 111 | in01 ); |
| 112 | |
| 113 | output out; |
| 114 | input in10; |
| 115 | input in00; |
| 116 | input in01; |
| 117 | |
| 118 | `ifdef LIB |
| 119 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 120 | `endif |
| 121 | |
| 122 | endmodule |
| 123 | // -------------------------------------------------- |
| 124 | // File: cl_u1_aoi12_4x.behV |
| 125 | // Auto generated verilog module by HnBCellAuto |
| 126 | // |
| 127 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST |
| 128 | // By: balmiki |
| 129 | // -------------------------------------------------- |
| 130 | // |
| 131 | module cl_u1_aoi12_4x ( |
| 132 | out, |
| 133 | in10, |
| 134 | in00, |
| 135 | in01 ); |
| 136 | |
| 137 | output out; |
| 138 | input in10; |
| 139 | input in00; |
| 140 | input in01; |
| 141 | |
| 142 | `ifdef LIB |
| 143 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 144 | `endif |
| 145 | |
| 146 | endmodule |
| 147 | // -------------------------------------------------- |
| 148 | // File: cl_u1_aoi12_8x.behV |
| 149 | // Auto generated verilog module by HnBCellAuto |
| 150 | // |
| 151 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST |
| 152 | // By: balmiki |
| 153 | // -------------------------------------------------- |
| 154 | // |
| 155 | module cl_u1_aoi12_8x ( |
| 156 | out, |
| 157 | in10, |
| 158 | in00, |
| 159 | in01 ); |
| 160 | |
| 161 | output out; |
| 162 | input in10; |
| 163 | input in00; |
| 164 | input in01; |
| 165 | |
| 166 | `ifdef LIB |
| 167 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 168 | `endif |
| 169 | |
| 170 | endmodule |
| 171 | // -------------------------------------------------- |
| 172 | // File: cl_u1_aoi21_12x.behV |
| 173 | // Auto generated verilog module by HnBCellAuto |
| 174 | // |
| 175 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 176 | // By: balmiki |
| 177 | // -------------------------------------------------- |
| 178 | // |
| 179 | module cl_u1_aoi21_12x ( |
| 180 | out, |
| 181 | in10, |
| 182 | in11, |
| 183 | in00 ); |
| 184 | |
| 185 | output out; |
| 186 | input in10; |
| 187 | input in11; |
| 188 | input in00; |
| 189 | |
| 190 | `ifdef LIB |
| 191 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 192 | `endif |
| 193 | |
| 194 | endmodule |
| 195 | // -------------------------------------------------- |
| 196 | // File: cl_u1_aoi21_16x.behV |
| 197 | // Auto generated verilog module by HnBCellAuto |
| 198 | // |
| 199 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 200 | // By: balmiki |
| 201 | // -------------------------------------------------- |
| 202 | // |
| 203 | module cl_u1_aoi21_16x ( |
| 204 | out, |
| 205 | in10, |
| 206 | in11, |
| 207 | in00 ); |
| 208 | |
| 209 | output out; |
| 210 | input in10; |
| 211 | input in11; |
| 212 | input in00; |
| 213 | |
| 214 | `ifdef LIB |
| 215 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 216 | `endif |
| 217 | |
| 218 | endmodule |
| 219 | // -------------------------------------------------- |
| 220 | // File: cl_u1_aoi21_1x.behV |
| 221 | // Auto generated verilog module by HnBCellAuto |
| 222 | // |
| 223 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 224 | // By: balmiki |
| 225 | // -------------------------------------------------- |
| 226 | // |
| 227 | module cl_u1_aoi21_1x ( |
| 228 | out, |
| 229 | in10, |
| 230 | in11, |
| 231 | in00 ); |
| 232 | |
| 233 | output out; |
| 234 | input in10; |
| 235 | input in11; |
| 236 | input in00; |
| 237 | |
| 238 | `ifdef LIB |
| 239 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 240 | `endif |
| 241 | |
| 242 | endmodule |
| 243 | // -------------------------------------------------- |
| 244 | // File: cl_u1_aoi21_2x.behV |
| 245 | // Auto generated verilog module by HnBCellAuto |
| 246 | // |
| 247 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 248 | // By: balmiki |
| 249 | // -------------------------------------------------- |
| 250 | // |
| 251 | module cl_u1_aoi21_2x ( |
| 252 | out, |
| 253 | in10, |
| 254 | in11, |
| 255 | in00 ); |
| 256 | |
| 257 | output out; |
| 258 | input in10; |
| 259 | input in11; |
| 260 | input in00; |
| 261 | |
| 262 | `ifdef LIB |
| 263 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 264 | `endif |
| 265 | |
| 266 | endmodule |
| 267 | // -------------------------------------------------- |
| 268 | // File: cl_u1_aoi21_4x.behV |
| 269 | // Auto generated verilog module by HnBCellAuto |
| 270 | // |
| 271 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 272 | // By: balmiki |
| 273 | // -------------------------------------------------- |
| 274 | // |
| 275 | module cl_u1_aoi21_4x ( |
| 276 | out, |
| 277 | in10, |
| 278 | in11, |
| 279 | in00 ); |
| 280 | |
| 281 | output out; |
| 282 | input in10; |
| 283 | input in11; |
| 284 | input in00; |
| 285 | |
| 286 | `ifdef LIB |
| 287 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 288 | `endif |
| 289 | |
| 290 | endmodule |
| 291 | // -------------------------------------------------- |
| 292 | // File: cl_u1_aoi21_8x.behV |
| 293 | // Auto generated verilog module by HnBCellAuto |
| 294 | // |
| 295 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 296 | // By: balmiki |
| 297 | // -------------------------------------------------- |
| 298 | // |
| 299 | module cl_u1_aoi21_8x ( |
| 300 | out, |
| 301 | in10, |
| 302 | in11, |
| 303 | in00 ); |
| 304 | |
| 305 | output out; |
| 306 | input in10; |
| 307 | input in11; |
| 308 | input in00; |
| 309 | |
| 310 | `ifdef LIB |
| 311 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 312 | `endif |
| 313 | |
| 314 | endmodule |
| 315 | // -------------------------------------------------- |
| 316 | // File: cl_u1_aoi22_12x.behV |
| 317 | // Auto generated verilog module by HnBCellAuto |
| 318 | // |
| 319 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT |
| 320 | // By: balmiki |
| 321 | // -------------------------------------------------- |
| 322 | // |
| 323 | module cl_u1_aoi22_12x ( |
| 324 | out, |
| 325 | in10, |
| 326 | in11, |
| 327 | in00, |
| 328 | in01 ); |
| 329 | |
| 330 | output out; |
| 331 | input in10; |
| 332 | input in11; |
| 333 | input in00; |
| 334 | input in01; |
| 335 | |
| 336 | `ifdef LIB |
| 337 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); |
| 338 | `endif |
| 339 | |
| 340 | endmodule |
| 341 | |
| 342 | // -------------------------------------------------- |
| 343 | // File: cl_u1_aoi22_1x.behV |
| 344 | // Auto generated verilog module by HnBCellAuto |
| 345 | // |
| 346 | // Created: Wednesday May 29,2002 at 04:04:32 PM PDT |
| 347 | // By: balmiki |
| 348 | // -------------------------------------------------- |
| 349 | // |
| 350 | module cl_u1_aoi22_1x ( |
| 351 | out, |
| 352 | in10, |
| 353 | in11, |
| 354 | in00, |
| 355 | in01 ); |
| 356 | |
| 357 | output out; |
| 358 | input in10; |
| 359 | input in11; |
| 360 | input in00; |
| 361 | input in01; |
| 362 | |
| 363 | `ifdef LIB |
| 364 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); |
| 365 | `endif |
| 366 | |
| 367 | endmodule |
| 368 | // -------------------------------------------------- |
| 369 | // File: cl_u1_aoi22_2x.behV |
| 370 | // Auto generated verilog module by HnBCellAuto |
| 371 | // |
| 372 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT |
| 373 | // By: balmiki |
| 374 | // -------------------------------------------------- |
| 375 | // |
| 376 | module cl_u1_aoi22_2x ( |
| 377 | out, |
| 378 | in10, |
| 379 | in11, |
| 380 | in00, |
| 381 | in01 ); |
| 382 | |
| 383 | output out; |
| 384 | input in10; |
| 385 | input in11; |
| 386 | input in00; |
| 387 | input in01; |
| 388 | |
| 389 | `ifdef LIB |
| 390 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); |
| 391 | `endif |
| 392 | |
| 393 | endmodule |
| 394 | // -------------------------------------------------- |
| 395 | // File: cl_u1_aoi22_4x.behV |
| 396 | // Auto generated verilog module by HnBCellAuto |
| 397 | // |
| 398 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT |
| 399 | // By: balmiki |
| 400 | // -------------------------------------------------- |
| 401 | // |
| 402 | module cl_u1_aoi22_4x ( |
| 403 | out, |
| 404 | in10, |
| 405 | in11, |
| 406 | in00, |
| 407 | in01 ); |
| 408 | |
| 409 | output out; |
| 410 | input in10; |
| 411 | input in11; |
| 412 | input in00; |
| 413 | input in01; |
| 414 | |
| 415 | `ifdef LIB |
| 416 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); |
| 417 | `endif |
| 418 | |
| 419 | endmodule |
| 420 | // -------------------------------------------------- |
| 421 | // File: cl_u1_aoi22_8x.behV |
| 422 | // Auto generated verilog module by HnBCellAuto |
| 423 | // |
| 424 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT |
| 425 | // By: balmiki |
| 426 | // -------------------------------------------------- |
| 427 | // |
| 428 | module cl_u1_aoi22_8x ( |
| 429 | out, |
| 430 | in10, |
| 431 | in11, |
| 432 | in00, |
| 433 | in01 ); |
| 434 | |
| 435 | output out; |
| 436 | input in10; |
| 437 | input in11; |
| 438 | input in00; |
| 439 | input in01; |
| 440 | |
| 441 | `ifdef LIB |
| 442 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); |
| 443 | `endif |
| 444 | |
| 445 | endmodule |
| 446 | |
| 447 | |
| 448 | // -------------------------------------------------- |
| 449 | // File: cl_u1_aoi33_1x.behV |
| 450 | // Auto generated verilog module by HnBCellAuto |
| 451 | // |
| 452 | // Created: Thursday Dec 6,2001 at 02:09:02 PM PST |
| 453 | // By: balmiki |
| 454 | // -------------------------------------------------- |
| 455 | // |
| 456 | module cl_u1_aoi33_1x ( |
| 457 | out, |
| 458 | in10, |
| 459 | in11, |
| 460 | in12, |
| 461 | in00, |
| 462 | in01, |
| 463 | in02 ); |
| 464 | |
| 465 | output out; |
| 466 | input in10; |
| 467 | input in11; |
| 468 | input in12; |
| 469 | input in00; |
| 470 | input in01; |
| 471 | input in02; |
| 472 | |
| 473 | `ifdef LIB |
| 474 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); |
| 475 | `endif |
| 476 | |
| 477 | endmodule |
| 478 | // -------------------------------------------------- |
| 479 | // File: cl_u1_aoi33_2x.behV |
| 480 | // Auto generated verilog module by HnBCellAuto |
| 481 | // |
| 482 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT |
| 483 | // By: balmiki |
| 484 | // -------------------------------------------------- |
| 485 | // |
| 486 | module cl_u1_aoi33_2x ( |
| 487 | out, |
| 488 | in10, |
| 489 | in11, |
| 490 | in12, |
| 491 | in00, |
| 492 | in01, |
| 493 | in02 ); |
| 494 | |
| 495 | output out; |
| 496 | input in10; |
| 497 | input in11; |
| 498 | input in12; |
| 499 | input in00; |
| 500 | input in01; |
| 501 | input in02; |
| 502 | |
| 503 | `ifdef LIB |
| 504 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); |
| 505 | `endif |
| 506 | |
| 507 | endmodule |
| 508 | // -------------------------------------------------- |
| 509 | // File: cl_u1_aoi33_4x.behV |
| 510 | // Auto generated verilog module by HnBCellAuto |
| 511 | // |
| 512 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT |
| 513 | // By: balmiki |
| 514 | // -------------------------------------------------- |
| 515 | // |
| 516 | module cl_u1_aoi33_4x ( |
| 517 | out, |
| 518 | in10, |
| 519 | in11, |
| 520 | in12, |
| 521 | in00, |
| 522 | in01, |
| 523 | in02 ); |
| 524 | |
| 525 | output out; |
| 526 | input in10; |
| 527 | input in11; |
| 528 | input in12; |
| 529 | input in00; |
| 530 | input in01; |
| 531 | input in02; |
| 532 | |
| 533 | `ifdef LIB |
| 534 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); |
| 535 | `endif |
| 536 | |
| 537 | endmodule |
| 538 | // -------------------------------------------------- |
| 539 | // File: cl_u1_aoi33_8x.behV |
| 540 | // Auto generated verilog module by HnBCellAuto |
| 541 | // |
| 542 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT |
| 543 | // By: balmiki |
| 544 | // -------------------------------------------------- |
| 545 | // |
| 546 | module cl_u1_aoi33_8x ( |
| 547 | out, |
| 548 | in10, |
| 549 | in11, |
| 550 | in12, |
| 551 | in00, |
| 552 | in01, |
| 553 | in02 ); |
| 554 | |
| 555 | output out; |
| 556 | input in10; |
| 557 | input in11; |
| 558 | input in12; |
| 559 | input in00; |
| 560 | input in01; |
| 561 | input in02; |
| 562 | |
| 563 | `ifdef LIB |
| 564 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); |
| 565 | `endif |
| 566 | |
| 567 | endmodule |
| 568 | module cl_u1_rep_lvt_32x ( |
| 569 | in, |
| 570 | out |
| 571 | ); |
| 572 | input in; |
| 573 | output out; |
| 574 | |
| 575 | `ifdef LIB |
| 576 | assign out = in; |
| 577 | `endif |
| 578 | |
| 579 | endmodule |
| 580 | module cl_u1_rep_lvt_48x ( |
| 581 | in, |
| 582 | out |
| 583 | ); |
| 584 | input in; |
| 585 | output out; |
| 586 | |
| 587 | `ifdef LIB |
| 588 | assign out = in; |
| 589 | `endif |
| 590 | |
| 591 | endmodule |
| 592 | module cl_u1_rep_32x ( |
| 593 | in, |
| 594 | out |
| 595 | ); |
| 596 | input in; |
| 597 | output out; |
| 598 | |
| 599 | `ifdef LIB |
| 600 | assign out = in; |
| 601 | `endif |
| 602 | |
| 603 | endmodule |
| 604 | module cl_u1_rep_40x ( |
| 605 | in, |
| 606 | out |
| 607 | ); |
| 608 | input in; |
| 609 | output out; |
| 610 | |
| 611 | `ifdef LIB |
| 612 | assign out = in; |
| 613 | `endif |
| 614 | |
| 615 | endmodule |
| 616 | module cl_u1_rep_24x ( |
| 617 | in, |
| 618 | out |
| 619 | ); |
| 620 | input in; |
| 621 | output out; |
| 622 | |
| 623 | `ifdef LIB |
| 624 | assign out = in; |
| 625 | `endif |
| 626 | |
| 627 | endmodule |
| 628 | module cl_u1_rep_16x ( |
| 629 | in, |
| 630 | out |
| 631 | ); |
| 632 | input in; |
| 633 | output out; |
| 634 | |
| 635 | `ifdef LIB |
| 636 | assign out = in; |
| 637 | `endif |
| 638 | |
| 639 | endmodule |
| 640 | module cl_u1_rep_8x ( |
| 641 | in, |
| 642 | out |
| 643 | ); |
| 644 | input in; |
| 645 | output out; |
| 646 | |
| 647 | `ifdef LIB |
| 648 | assign out = in; |
| 649 | `endif |
| 650 | |
| 651 | endmodule |
| 652 | module cl_u1_rep_48x ( |
| 653 | in, |
| 654 | out |
| 655 | ); |
| 656 | input in; |
| 657 | output out; |
| 658 | |
| 659 | `ifdef LIB |
| 660 | assign out = in; |
| 661 | `endif |
| 662 | |
| 663 | endmodule |
| 664 | module cl_u1_rep_dcp2x_32x ( |
| 665 | in, |
| 666 | out |
| 667 | ); |
| 668 | input in; |
| 669 | output out; |
| 670 | |
| 671 | `ifdef LIB |
| 672 | assign out = in; |
| 673 | `endif |
| 674 | |
| 675 | endmodule |
| 676 | |
| 677 | module cl_u1_rep_dcp2x_16x ( |
| 678 | in, |
| 679 | out |
| 680 | ); |
| 681 | input in; |
| 682 | output out; |
| 683 | |
| 684 | `ifdef LIB |
| 685 | assign out = in; |
| 686 | `endif |
| 687 | |
| 688 | endmodule |
| 689 | module cl_u1_rep_dcp2x_24x ( |
| 690 | in, |
| 691 | out |
| 692 | ); |
| 693 | input in; |
| 694 | output out; |
| 695 | |
| 696 | `ifdef LIB |
| 697 | assign out = in; |
| 698 | `endif |
| 699 | |
| 700 | endmodule |
| 701 | module cl_u1_rep_dcp2x_40x ( |
| 702 | in, |
| 703 | out |
| 704 | ); |
| 705 | input in; |
| 706 | output out; |
| 707 | |
| 708 | `ifdef LIB |
| 709 | assign out = in; |
| 710 | `endif |
| 711 | |
| 712 | endmodule |
| 713 | module cl_u1_rep_dcp2x_48x ( |
| 714 | in, |
| 715 | out |
| 716 | ); |
| 717 | input in; |
| 718 | output out; |
| 719 | |
| 720 | `ifdef LIB |
| 721 | assign out = in; |
| 722 | `endif |
| 723 | |
| 724 | endmodule |
| 725 | module cl_u1_rep_dcp_32x ( |
| 726 | in, |
| 727 | out |
| 728 | ); |
| 729 | input in; |
| 730 | output out; |
| 731 | |
| 732 | `ifdef LIB |
| 733 | assign out = in; |
| 734 | `endif |
| 735 | |
| 736 | endmodule |
| 737 | |
| 738 | module cl_u1_rep_dcp_16x ( |
| 739 | in, |
| 740 | out |
| 741 | ); |
| 742 | input in; |
| 743 | output out; |
| 744 | |
| 745 | `ifdef LIB |
| 746 | assign out = in; |
| 747 | `endif |
| 748 | |
| 749 | endmodule |
| 750 | module cl_u1_rep_dcp_24x ( |
| 751 | in, |
| 752 | out |
| 753 | ); |
| 754 | input in; |
| 755 | output out; |
| 756 | |
| 757 | `ifdef LIB |
| 758 | assign out = in; |
| 759 | `endif |
| 760 | |
| 761 | endmodule |
| 762 | module cl_u1_rep_dcp_40x ( |
| 763 | in, |
| 764 | out |
| 765 | ); |
| 766 | input in; |
| 767 | output out; |
| 768 | |
| 769 | `ifdef LIB |
| 770 | assign out = in; |
| 771 | `endif |
| 772 | |
| 773 | endmodule |
| 774 | module cl_u1_rep_dcp_48x ( |
| 775 | in, |
| 776 | out |
| 777 | ); |
| 778 | input in; |
| 779 | output out; |
| 780 | |
| 781 | `ifdef LIB |
| 782 | assign out = in; |
| 783 | `endif |
| 784 | |
| 785 | endmodule |
| 786 | module cl_u1_rep_dcp50k_48x ( |
| 787 | in, |
| 788 | out |
| 789 | ); |
| 790 | input in; |
| 791 | output out; |
| 792 | |
| 793 | `ifdef LIB |
| 794 | assign out = in; |
| 795 | `endif |
| 796 | |
| 797 | endmodule |
| 798 | module cl_u1_rep_dcp50k_32x ( |
| 799 | in, |
| 800 | out |
| 801 | ); |
| 802 | input in; |
| 803 | output out; |
| 804 | |
| 805 | `ifdef LIB |
| 806 | assign out = in; |
| 807 | `endif |
| 808 | |
| 809 | endmodule |
| 810 | module cl_u1_rep_dcp50k_40x ( |
| 811 | in, |
| 812 | out |
| 813 | ); |
| 814 | input in; |
| 815 | output out; |
| 816 | |
| 817 | `ifdef LIB |
| 818 | assign out = in; |
| 819 | `endif |
| 820 | |
| 821 | endmodule |
| 822 | |
| 823 | module cl_u1_buf_12x ( |
| 824 | in, |
| 825 | out |
| 826 | ); |
| 827 | input in; |
| 828 | output out; |
| 829 | |
| 830 | `ifdef LIB |
| 831 | assign out = in; |
| 832 | `endif |
| 833 | |
| 834 | endmodule |
| 835 | module cl_u1_buf_16x ( |
| 836 | in, |
| 837 | out |
| 838 | ); |
| 839 | input in; |
| 840 | output out; |
| 841 | |
| 842 | `ifdef LIB |
| 843 | assign out = in; |
| 844 | `endif |
| 845 | |
| 846 | endmodule |
| 847 | module cl_u1_buf_1x ( |
| 848 | in, |
| 849 | out |
| 850 | ); |
| 851 | input in; |
| 852 | output out; |
| 853 | |
| 854 | `ifdef LIB |
| 855 | assign out = in; |
| 856 | `endif |
| 857 | |
| 858 | endmodule |
| 859 | module cl_u1_buf_20x ( |
| 860 | in, |
| 861 | out |
| 862 | ); |
| 863 | input in; |
| 864 | output out; |
| 865 | |
| 866 | `ifdef LIB |
| 867 | assign out = in; |
| 868 | `endif |
| 869 | |
| 870 | endmodule |
| 871 | module cl_u1_buf_24x ( |
| 872 | in, |
| 873 | out |
| 874 | ); |
| 875 | input in; |
| 876 | output out; |
| 877 | |
| 878 | `ifdef LIB |
| 879 | assign out = in; |
| 880 | `endif |
| 881 | |
| 882 | endmodule |
| 883 | module cl_u1_buf_28x ( |
| 884 | in, |
| 885 | out |
| 886 | ); |
| 887 | input in; |
| 888 | output out; |
| 889 | |
| 890 | `ifdef LIB |
| 891 | assign out = in; |
| 892 | `endif |
| 893 | |
| 894 | endmodule |
| 895 | module cl_u1_buf_2x ( |
| 896 | in, |
| 897 | out |
| 898 | ); |
| 899 | input in; |
| 900 | output out; |
| 901 | |
| 902 | `ifdef LIB |
| 903 | assign out = in; |
| 904 | `endif |
| 905 | |
| 906 | endmodule |
| 907 | module cl_u1_buf_32x ( |
| 908 | in, |
| 909 | out |
| 910 | ); |
| 911 | input in; |
| 912 | output out; |
| 913 | |
| 914 | `ifdef LIB |
| 915 | assign out = in; |
| 916 | `endif |
| 917 | |
| 918 | endmodule |
| 919 | module cl_u1_buf_36x ( |
| 920 | in, |
| 921 | out |
| 922 | ); |
| 923 | input in; |
| 924 | output out; |
| 925 | |
| 926 | `ifdef LIB |
| 927 | assign out = in; |
| 928 | `endif |
| 929 | |
| 930 | endmodule |
| 931 | module cl_u1_buf_40x ( |
| 932 | in, |
| 933 | out |
| 934 | ); |
| 935 | input in; |
| 936 | output out; |
| 937 | |
| 938 | `ifdef LIB |
| 939 | assign out = in; |
| 940 | `endif |
| 941 | |
| 942 | endmodule |
| 943 | module cl_u1_buf_44x ( |
| 944 | in, |
| 945 | out |
| 946 | ); |
| 947 | input in; |
| 948 | output out; |
| 949 | |
| 950 | `ifdef LIB |
| 951 | assign out = in; |
| 952 | `endif |
| 953 | |
| 954 | endmodule |
| 955 | module cl_u1_buf_48x ( |
| 956 | in, |
| 957 | out |
| 958 | ); |
| 959 | input in; |
| 960 | output out; |
| 961 | |
| 962 | `ifdef LIB |
| 963 | assign out = in; |
| 964 | `endif |
| 965 | |
| 966 | endmodule |
| 967 | module cl_u1_buf_4x ( |
| 968 | in, |
| 969 | out |
| 970 | ); |
| 971 | input in; |
| 972 | output out; |
| 973 | |
| 974 | `ifdef LIB |
| 975 | assign out = in; |
| 976 | `endif |
| 977 | |
| 978 | endmodule |
| 979 | module cl_u1_buf_56x ( |
| 980 | in, |
| 981 | out |
| 982 | ); |
| 983 | input in; |
| 984 | output out; |
| 985 | |
| 986 | `ifdef LIB |
| 987 | assign out = in; |
| 988 | `endif |
| 989 | |
| 990 | endmodule |
| 991 | module cl_u1_buf_64x ( |
| 992 | in, |
| 993 | out |
| 994 | ); |
| 995 | input in; |
| 996 | output out; |
| 997 | |
| 998 | `ifdef LIB |
| 999 | assign out = in; |
| 1000 | `endif |
| 1001 | |
| 1002 | endmodule |
| 1003 | module cl_u1_buf_6x ( |
| 1004 | in, |
| 1005 | out |
| 1006 | ); |
| 1007 | input in; |
| 1008 | output out; |
| 1009 | |
| 1010 | `ifdef LIB |
| 1011 | assign out = in; |
| 1012 | `endif |
| 1013 | |
| 1014 | endmodule |
| 1015 | module cl_u1_buf_8x ( |
| 1016 | in, |
| 1017 | out |
| 1018 | ); |
| 1019 | input in; |
| 1020 | output out; |
| 1021 | |
| 1022 | `ifdef LIB |
| 1023 | assign out = in; |
| 1024 | `endif |
| 1025 | |
| 1026 | endmodule |
| 1027 | module cl_u1_bufmin_15ps_30x ( |
| 1028 | in, |
| 1029 | out |
| 1030 | ); |
| 1031 | input in; |
| 1032 | output out; |
| 1033 | |
| 1034 | `ifdef LIB |
| 1035 | assign out = in; |
| 1036 | `endif |
| 1037 | |
| 1038 | endmodule |
| 1039 | module cl_u1_bufmin_1x ( |
| 1040 | in, |
| 1041 | out |
| 1042 | ); |
| 1043 | input in; |
| 1044 | output out; |
| 1045 | |
| 1046 | `ifdef LIB |
| 1047 | assign out = in; |
| 1048 | `endif |
| 1049 | |
| 1050 | endmodule |
| 1051 | module cl_u1_bufmin_4x ( |
| 1052 | in, |
| 1053 | out |
| 1054 | ); |
| 1055 | input in; |
| 1056 | output out; |
| 1057 | |
| 1058 | `ifdef LIB |
| 1059 | assign out = in; |
| 1060 | `endif |
| 1061 | |
| 1062 | endmodule |
| 1063 | module cl_u1_bufmin_8x ( |
| 1064 | in, |
| 1065 | out |
| 1066 | ); |
| 1067 | input in; |
| 1068 | output out; |
| 1069 | |
| 1070 | `ifdef LIB |
| 1071 | assign out = in; |
| 1072 | `endif |
| 1073 | |
| 1074 | endmodule |
| 1075 | module cl_u1_bufmin_16x ( |
| 1076 | in, |
| 1077 | out |
| 1078 | ); |
| 1079 | input in; |
| 1080 | output out; |
| 1081 | |
| 1082 | `ifdef LIB |
| 1083 | assign out = in; |
| 1084 | `endif |
| 1085 | |
| 1086 | endmodule |
| 1087 | module cl_u1_bufmin_32x ( |
| 1088 | in, |
| 1089 | out |
| 1090 | ); |
| 1091 | input in; |
| 1092 | output out; |
| 1093 | |
| 1094 | `ifdef LIB |
| 1095 | assign out = in; |
| 1096 | `endif |
| 1097 | |
| 1098 | endmodule |
| 1099 | module cl_u1_csa32_16x ( |
| 1100 | in0, |
| 1101 | in1, |
| 1102 | in2, |
| 1103 | carry, |
| 1104 | sum |
| 1105 | ); |
| 1106 | input in0; |
| 1107 | input in1; |
| 1108 | input in2; |
| 1109 | output carry; |
| 1110 | output sum; |
| 1111 | |
| 1112 | `ifdef LIB |
| 1113 | assign carry = (in0 & in1) | (in0 & in2) | (in1 & in2); |
| 1114 | assign sum = (in0 ^ in1 ^ in2); |
| 1115 | `endif |
| 1116 | |
| 1117 | endmodule |
| 1118 | module cl_u1_csa32_4x ( |
| 1119 | in0, |
| 1120 | in1, |
| 1121 | in2, |
| 1122 | carry, |
| 1123 | sum |
| 1124 | ); |
| 1125 | input in0; |
| 1126 | input in1; |
| 1127 | input in2; |
| 1128 | output carry; |
| 1129 | output sum; |
| 1130 | |
| 1131 | `ifdef LIB |
| 1132 | assign carry = (in0 & in1) | (in0 & in2) | (in1 & in2); |
| 1133 | assign sum = (in0 ^ in1 ^ in2); |
| 1134 | `endif |
| 1135 | |
| 1136 | endmodule |
| 1137 | module cl_u1_csa32_8x ( |
| 1138 | in0, |
| 1139 | in1, |
| 1140 | in2, |
| 1141 | carry, |
| 1142 | sum |
| 1143 | ); |
| 1144 | input in0; |
| 1145 | input in1; |
| 1146 | input in2; |
| 1147 | output carry; |
| 1148 | output sum; |
| 1149 | |
| 1150 | `ifdef LIB |
| 1151 | assign carry = (in0 & in1) | (in0 & in2) | (in1 & in2); |
| 1152 | assign sum = (in0 ^ in1 ^ in2); |
| 1153 | `endif |
| 1154 | |
| 1155 | endmodule |
| 1156 | module cl_u1_csa42_16x ( |
| 1157 | in0, |
| 1158 | in1, |
| 1159 | in2, |
| 1160 | in3, |
| 1161 | cin, |
| 1162 | cout, |
| 1163 | carry, |
| 1164 | sum |
| 1165 | ); |
| 1166 | input in0; |
| 1167 | input in1; |
| 1168 | input in2; |
| 1169 | input in3; |
| 1170 | input cin; |
| 1171 | output cout; |
| 1172 | output carry; |
| 1173 | output sum; |
| 1174 | |
| 1175 | `ifdef LIB |
| 1176 | assign cout = (in1 & in2) | (in0 & in2) | (in0 & in1); |
| 1177 | |
| 1178 | assign sum = (~in0 & ~in1 & ~in2 & ~in3 & cin) | |
| 1179 | (~in0 & ~in1 & ~in2 & in3 & ~cin) | |
| 1180 | (~in0 & ~in1 & in2 & ~in3 & ~cin) | |
| 1181 | (~in0 & ~in1 & in2 & in3 & cin) | |
| 1182 | |
| 1183 | (~in0 & in1 & ~in2 & ~in3 & ~cin) | |
| 1184 | (~in0 & in1 & ~in2 & in3 & cin) | |
| 1185 | (~in0 & in1 & in2 & ~in3 & cin) | |
| 1186 | (~in0 & in1 & in2 & in3 & ~cin) | |
| 1187 | |
| 1188 | ( in0 & ~in1 & ~in2 & ~in3 & ~cin) | |
| 1189 | ( in0 & ~in1 & ~in2 & in3 & cin) | |
| 1190 | ( in0 & ~in1 & in2 & ~in3 & cin) | |
| 1191 | ( in0 & ~in1 & in2 & in3 & ~cin) | |
| 1192 | |
| 1193 | ( in0 & in1 & ~in2 & ~in3 & cin) | |
| 1194 | ( in0 & in1 & ~in2 & in3 & ~cin) | |
| 1195 | ( in0 & in1 & in2 & ~in3 & ~cin) | |
| 1196 | ( in0 & in1 & in2 & in3 & cin); |
| 1197 | |
| 1198 | assign carry = (~in0 & ~in1 & ~in2 & ~in3 & 1'b0) | |
| 1199 | (~in0 & ~in1 & ~in2 & in3 & cin) | |
| 1200 | (~in0 & ~in1 & in2 & ~in3 & cin) | |
| 1201 | (~in0 & ~in1 & in2 & in3 & 1'b1) | |
| 1202 | |
| 1203 | (~in0 & in1 & ~in2 & ~in3 & cin) | |
| 1204 | (~in0 & in1 & ~in2 & in3 & 1'b1) | |
| 1205 | (~in0 & in1 & in2 & ~in3 & 1'b0) | |
| 1206 | (~in0 & in1 & in2 & in3 & cin) | |
| 1207 | |
| 1208 | ( in0 & ~in1 & ~in2 & ~in3 & cin) | |
| 1209 | ( in0 & ~in1 & ~in2 & in3 & 1'b1) | |
| 1210 | ( in0 & ~in1 & in2 & ~in3 & 1'b0) | |
| 1211 | ( in0 & ~in1 & in2 & in3 & cin) | |
| 1212 | |
| 1213 | ( in0 & in1 & ~in2 & ~in3 & 1'b0) | |
| 1214 | ( in0 & in1 & ~in2 & in3 & cin) | |
| 1215 | ( in0 & in1 & in2 & ~in3 & cin) | |
| 1216 | ( in0 & in1 & in2 & in3 & 1'b1); |
| 1217 | |
| 1218 | |
| 1219 | |
| 1220 | `endif |
| 1221 | |
| 1222 | endmodule |
| 1223 | module cl_u1_csa42_4x ( |
| 1224 | in0, |
| 1225 | in1, |
| 1226 | in2, |
| 1227 | in3, |
| 1228 | cin, |
| 1229 | cout, |
| 1230 | carry, |
| 1231 | sum |
| 1232 | ); |
| 1233 | input in0; |
| 1234 | input in1; |
| 1235 | input in2; |
| 1236 | input in3; |
| 1237 | input cin; |
| 1238 | output cout; |
| 1239 | output carry; |
| 1240 | output sum; |
| 1241 | |
| 1242 | `ifdef LIB |
| 1243 | assign cout = (in1 & in2) | (in0 & in2) | (in0 & in1); |
| 1244 | |
| 1245 | assign sum = (~in0 & ~in1 & ~in2 & ~in3 & cin) | |
| 1246 | (~in0 & ~in1 & ~in2 & in3 & ~cin) | |
| 1247 | (~in0 & ~in1 & in2 & ~in3 & ~cin) | |
| 1248 | (~in0 & ~in1 & in2 & in3 & cin) | |
| 1249 | |
| 1250 | (~in0 & in1 & ~in2 & ~in3 & ~cin) | |
| 1251 | (~in0 & in1 & ~in2 & in3 & cin) | |
| 1252 | (~in0 & in1 & in2 & ~in3 & cin) | |
| 1253 | (~in0 & in1 & in2 & in3 & ~cin) | |
| 1254 | |
| 1255 | ( in0 & ~in1 & ~in2 & ~in3 & ~cin) | |
| 1256 | ( in0 & ~in1 & ~in2 & in3 & cin) | |
| 1257 | ( in0 & ~in1 & in2 & ~in3 & cin) | |
| 1258 | ( in0 & ~in1 & in2 & in3 & ~cin) | |
| 1259 | |
| 1260 | ( in0 & in1 & ~in2 & ~in3 & cin) | |
| 1261 | ( in0 & in1 & ~in2 & in3 & ~cin) | |
| 1262 | ( in0 & in1 & in2 & ~in3 & ~cin) | |
| 1263 | ( in0 & in1 & in2 & in3 & cin); |
| 1264 | |
| 1265 | assign carry = (~in0 & ~in1 & ~in2 & ~in3 & 1'b0) | |
| 1266 | (~in0 & ~in1 & ~in2 & in3 & cin) | |
| 1267 | (~in0 & ~in1 & in2 & ~in3 & cin) | |
| 1268 | (~in0 & ~in1 & in2 & in3 & 1'b1) | |
| 1269 | |
| 1270 | (~in0 & in1 & ~in2 & ~in3 & cin) | |
| 1271 | (~in0 & in1 & ~in2 & in3 & 1'b1) | |
| 1272 | (~in0 & in1 & in2 & ~in3 & 1'b0) | |
| 1273 | (~in0 & in1 & in2 & in3 & cin) | |
| 1274 | |
| 1275 | ( in0 & ~in1 & ~in2 & ~in3 & cin) | |
| 1276 | ( in0 & ~in1 & ~in2 & in3 & 1'b1) | |
| 1277 | ( in0 & ~in1 & in2 & ~in3 & 1'b0) | |
| 1278 | ( in0 & ~in1 & in2 & in3 & cin) | |
| 1279 | |
| 1280 | ( in0 & in1 & ~in2 & ~in3 & 1'b0) | |
| 1281 | ( in0 & in1 & ~in2 & in3 & cin) | |
| 1282 | ( in0 & in1 & in2 & ~in3 & cin) | |
| 1283 | ( in0 & in1 & in2 & in3 & 1'b1); |
| 1284 | |
| 1285 | |
| 1286 | |
| 1287 | `endif |
| 1288 | |
| 1289 | endmodule |
| 1290 | module cl_u1_csa42_8x ( |
| 1291 | in0, |
| 1292 | in1, |
| 1293 | in2, |
| 1294 | in3, |
| 1295 | cin, |
| 1296 | cout, |
| 1297 | carry, |
| 1298 | sum |
| 1299 | ); |
| 1300 | input in0; |
| 1301 | input in1; |
| 1302 | input in2; |
| 1303 | input in3; |
| 1304 | input cin; |
| 1305 | output cout; |
| 1306 | output carry; |
| 1307 | output sum; |
| 1308 | |
| 1309 | `ifdef LIB |
| 1310 | assign cout = (in1 & in2) | (in0 & in2) | (in0 & in1); |
| 1311 | |
| 1312 | assign sum = (~in0 & ~in1 & ~in2 & ~in3 & cin) | |
| 1313 | (~in0 & ~in1 & ~in2 & in3 & ~cin) | |
| 1314 | (~in0 & ~in1 & in2 & ~in3 & ~cin) | |
| 1315 | (~in0 & ~in1 & in2 & in3 & cin) | |
| 1316 | |
| 1317 | (~in0 & in1 & ~in2 & ~in3 & ~cin) | |
| 1318 | (~in0 & in1 & ~in2 & in3 & cin) | |
| 1319 | (~in0 & in1 & in2 & ~in3 & cin) | |
| 1320 | (~in0 & in1 & in2 & in3 & ~cin) | |
| 1321 | |
| 1322 | ( in0 & ~in1 & ~in2 & ~in3 & ~cin) | |
| 1323 | ( in0 & ~in1 & ~in2 & in3 & cin) | |
| 1324 | ( in0 & ~in1 & in2 & ~in3 & cin) | |
| 1325 | ( in0 & ~in1 & in2 & in3 & ~cin) | |
| 1326 | |
| 1327 | ( in0 & in1 & ~in2 & ~in3 & cin) | |
| 1328 | ( in0 & in1 & ~in2 & in3 & ~cin) | |
| 1329 | ( in0 & in1 & in2 & ~in3 & ~cin) | |
| 1330 | ( in0 & in1 & in2 & in3 & cin); |
| 1331 | |
| 1332 | assign carry = (~in0 & ~in1 & ~in2 & ~in3 & 1'b0) | |
| 1333 | (~in0 & ~in1 & ~in2 & in3 & cin) | |
| 1334 | (~in0 & ~in1 & in2 & ~in3 & cin) | |
| 1335 | (~in0 & ~in1 & in2 & in3 & 1'b1) | |
| 1336 | |
| 1337 | (~in0 & in1 & ~in2 & ~in3 & cin) | |
| 1338 | (~in0 & in1 & ~in2 & in3 & 1'b1) | |
| 1339 | (~in0 & in1 & in2 & ~in3 & 1'b0) | |
| 1340 | (~in0 & in1 & in2 & in3 & cin) | |
| 1341 | |
| 1342 | ( in0 & ~in1 & ~in2 & ~in3 & cin) | |
| 1343 | ( in0 & ~in1 & ~in2 & in3 & 1'b1) | |
| 1344 | ( in0 & ~in1 & in2 & ~in3 & 1'b0) | |
| 1345 | ( in0 & ~in1 & in2 & in3 & cin) | |
| 1346 | |
| 1347 | ( in0 & in1 & ~in2 & ~in3 & 1'b0) | |
| 1348 | ( in0 & in1 & ~in2 & in3 & cin) | |
| 1349 | ( in0 & in1 & in2 & ~in3 & cin) | |
| 1350 | ( in0 & in1 & in2 & in3 & 1'b1); |
| 1351 | |
| 1352 | |
| 1353 | |
| 1354 | `endif |
| 1355 | |
| 1356 | endmodule |
| 1357 | module cl_u1_inv_12x ( |
| 1358 | in, |
| 1359 | out |
| 1360 | ); |
| 1361 | input in; |
| 1362 | output out; |
| 1363 | |
| 1364 | `ifdef LIB |
| 1365 | assign out = ~in; |
| 1366 | `endif |
| 1367 | |
| 1368 | endmodule |
| 1369 | module cl_u1_inv_16x ( |
| 1370 | in, |
| 1371 | out |
| 1372 | ); |
| 1373 | input in; |
| 1374 | output out; |
| 1375 | |
| 1376 | `ifdef LIB |
| 1377 | assign out = ~in; |
| 1378 | `endif |
| 1379 | |
| 1380 | endmodule |
| 1381 | module cl_u1_inv_1x ( |
| 1382 | in, |
| 1383 | out |
| 1384 | ); |
| 1385 | input in; |
| 1386 | output out; |
| 1387 | |
| 1388 | `ifdef LIB |
| 1389 | assign out = ~in; |
| 1390 | `endif |
| 1391 | |
| 1392 | endmodule |
| 1393 | module cl_u1_inv_20x ( |
| 1394 | in, |
| 1395 | out |
| 1396 | ); |
| 1397 | input in; |
| 1398 | output out; |
| 1399 | |
| 1400 | `ifdef LIB |
| 1401 | assign out = ~in; |
| 1402 | `endif |
| 1403 | |
| 1404 | endmodule |
| 1405 | module cl_u1_inv_24x ( |
| 1406 | in, |
| 1407 | out |
| 1408 | ); |
| 1409 | input in; |
| 1410 | output out; |
| 1411 | |
| 1412 | `ifdef LIB |
| 1413 | assign out = ~in; |
| 1414 | `endif |
| 1415 | |
| 1416 | endmodule |
| 1417 | module cl_u1_inv_28x ( |
| 1418 | in, |
| 1419 | out |
| 1420 | ); |
| 1421 | input in; |
| 1422 | output out; |
| 1423 | |
| 1424 | `ifdef LIB |
| 1425 | assign out = ~in; |
| 1426 | `endif |
| 1427 | |
| 1428 | endmodule |
| 1429 | module cl_u1_inv_2x ( |
| 1430 | in, |
| 1431 | out |
| 1432 | ); |
| 1433 | input in; |
| 1434 | output out; |
| 1435 | |
| 1436 | `ifdef LIB |
| 1437 | assign out = ~in; |
| 1438 | `endif |
| 1439 | |
| 1440 | endmodule |
| 1441 | module cl_u1_inv_32x ( |
| 1442 | in, |
| 1443 | out |
| 1444 | ); |
| 1445 | input in; |
| 1446 | output out; |
| 1447 | |
| 1448 | `ifdef LIB |
| 1449 | assign out = ~in; |
| 1450 | `endif |
| 1451 | |
| 1452 | endmodule |
| 1453 | module cl_u1_inv_36x ( |
| 1454 | in, |
| 1455 | out |
| 1456 | ); |
| 1457 | input in; |
| 1458 | output out; |
| 1459 | |
| 1460 | `ifdef LIB |
| 1461 | assign out = ~in; |
| 1462 | `endif |
| 1463 | |
| 1464 | endmodule |
| 1465 | module cl_u1_inv_40x ( |
| 1466 | in, |
| 1467 | out |
| 1468 | ); |
| 1469 | input in; |
| 1470 | output out; |
| 1471 | |
| 1472 | `ifdef LIB |
| 1473 | assign out = ~in; |
| 1474 | `endif |
| 1475 | |
| 1476 | endmodule |
| 1477 | module cl_u1_inv_44x ( |
| 1478 | in, |
| 1479 | out |
| 1480 | ); |
| 1481 | input in; |
| 1482 | output out; |
| 1483 | |
| 1484 | `ifdef LIB |
| 1485 | assign out = ~in; |
| 1486 | `endif |
| 1487 | |
| 1488 | endmodule |
| 1489 | module cl_u1_inv_48x ( |
| 1490 | in, |
| 1491 | out |
| 1492 | ); |
| 1493 | input in; |
| 1494 | output out; |
| 1495 | |
| 1496 | `ifdef LIB |
| 1497 | assign out = ~in; |
| 1498 | `endif |
| 1499 | |
| 1500 | endmodule |
| 1501 | module cl_u1_inv_4x ( |
| 1502 | in, |
| 1503 | out |
| 1504 | ); |
| 1505 | input in; |
| 1506 | output out; |
| 1507 | |
| 1508 | `ifdef LIB |
| 1509 | assign out = ~in; |
| 1510 | `endif |
| 1511 | |
| 1512 | endmodule |
| 1513 | module cl_u1_inv_56x ( |
| 1514 | in, |
| 1515 | out |
| 1516 | ); |
| 1517 | input in; |
| 1518 | output out; |
| 1519 | |
| 1520 | `ifdef LIB |
| 1521 | assign out = ~in; |
| 1522 | `endif |
| 1523 | |
| 1524 | endmodule |
| 1525 | module cl_u1_inv_64x ( |
| 1526 | in, |
| 1527 | out |
| 1528 | ); |
| 1529 | input in; |
| 1530 | output out; |
| 1531 | |
| 1532 | `ifdef LIB |
| 1533 | assign out = ~in; |
| 1534 | `endif |
| 1535 | |
| 1536 | endmodule |
| 1537 | module cl_u1_inv_6x ( |
| 1538 | in, |
| 1539 | out |
| 1540 | ); |
| 1541 | input in; |
| 1542 | output out; |
| 1543 | |
| 1544 | `ifdef LIB |
| 1545 | assign out = ~in; |
| 1546 | `endif |
| 1547 | |
| 1548 | endmodule |
| 1549 | module cl_u1_inv_8x ( |
| 1550 | in, |
| 1551 | out |
| 1552 | ); |
| 1553 | input in; |
| 1554 | output out; |
| 1555 | |
| 1556 | `ifdef LIB |
| 1557 | assign out = ~in; |
| 1558 | `endif |
| 1559 | |
| 1560 | endmodule |
| 1561 | module cl_u1_nand2_12x ( |
| 1562 | in0, |
| 1563 | in1, |
| 1564 | out |
| 1565 | ); |
| 1566 | input in0; |
| 1567 | input in1; |
| 1568 | output out; |
| 1569 | |
| 1570 | `ifdef LIB |
| 1571 | assign out = ~(in0 & in1); |
| 1572 | `endif |
| 1573 | |
| 1574 | endmodule |
| 1575 | module cl_u1_nand2_16x ( |
| 1576 | in0, |
| 1577 | in1, |
| 1578 | out |
| 1579 | ); |
| 1580 | input in0; |
| 1581 | input in1; |
| 1582 | output out; |
| 1583 | |
| 1584 | `ifdef LIB |
| 1585 | assign out = ~(in0 & in1); |
| 1586 | `endif |
| 1587 | |
| 1588 | endmodule |
| 1589 | module cl_u1_nand2_1x ( |
| 1590 | in0, |
| 1591 | in1, |
| 1592 | out |
| 1593 | ); |
| 1594 | input in0; |
| 1595 | input in1; |
| 1596 | output out; |
| 1597 | |
| 1598 | `ifdef LIB |
| 1599 | assign out = ~(in0 & in1); |
| 1600 | `endif |
| 1601 | |
| 1602 | endmodule |
| 1603 | module cl_u1_nand2_20x ( |
| 1604 | in0, |
| 1605 | in1, |
| 1606 | out |
| 1607 | ); |
| 1608 | input in0; |
| 1609 | input in1; |
| 1610 | output out; |
| 1611 | |
| 1612 | `ifdef LIB |
| 1613 | assign out = ~(in0 & in1); |
| 1614 | `endif |
| 1615 | |
| 1616 | endmodule |
| 1617 | module cl_u1_nand2_24x ( |
| 1618 | in0, |
| 1619 | in1, |
| 1620 | out |
| 1621 | ); |
| 1622 | input in0; |
| 1623 | input in1; |
| 1624 | output out; |
| 1625 | |
| 1626 | `ifdef LIB |
| 1627 | assign out = ~(in0 & in1); |
| 1628 | `endif |
| 1629 | |
| 1630 | endmodule |
| 1631 | module cl_u1_nand2_28x ( |
| 1632 | in0, |
| 1633 | in1, |
| 1634 | out |
| 1635 | ); |
| 1636 | input in0; |
| 1637 | input in1; |
| 1638 | output out; |
| 1639 | |
| 1640 | `ifdef LIB |
| 1641 | assign out = ~(in0 & in1); |
| 1642 | `endif |
| 1643 | |
| 1644 | endmodule |
| 1645 | module cl_u1_nand2_2x ( |
| 1646 | in0, |
| 1647 | in1, |
| 1648 | out |
| 1649 | ); |
| 1650 | input in0; |
| 1651 | input in1; |
| 1652 | output out; |
| 1653 | |
| 1654 | `ifdef LIB |
| 1655 | assign out = ~(in0 & in1); |
| 1656 | `endif |
| 1657 | |
| 1658 | endmodule |
| 1659 | module cl_u1_nand2_32x ( |
| 1660 | in0, |
| 1661 | in1, |
| 1662 | out |
| 1663 | ); |
| 1664 | input in0; |
| 1665 | input in1; |
| 1666 | output out; |
| 1667 | |
| 1668 | `ifdef LIB |
| 1669 | assign out = ~(in0 & in1); |
| 1670 | `endif |
| 1671 | |
| 1672 | endmodule |
| 1673 | module cl_u1_nand2_4x ( |
| 1674 | in0, |
| 1675 | in1, |
| 1676 | out |
| 1677 | ); |
| 1678 | input in0; |
| 1679 | input in1; |
| 1680 | output out; |
| 1681 | |
| 1682 | `ifdef LIB |
| 1683 | assign out = ~(in0 & in1); |
| 1684 | `endif |
| 1685 | |
| 1686 | endmodule |
| 1687 | module cl_u1_nand2_6x ( |
| 1688 | in0, |
| 1689 | in1, |
| 1690 | out |
| 1691 | ); |
| 1692 | input in0; |
| 1693 | input in1; |
| 1694 | output out; |
| 1695 | |
| 1696 | `ifdef LIB |
| 1697 | assign out = ~(in0 & in1); |
| 1698 | `endif |
| 1699 | |
| 1700 | endmodule |
| 1701 | module cl_u1_nand2_8x ( |
| 1702 | in0, |
| 1703 | in1, |
| 1704 | out |
| 1705 | ); |
| 1706 | input in0; |
| 1707 | input in1; |
| 1708 | output out; |
| 1709 | |
| 1710 | `ifdef LIB |
| 1711 | assign out = ~(in0 & in1); |
| 1712 | `endif |
| 1713 | |
| 1714 | endmodule |
| 1715 | module cl_u1_nand3_12x ( |
| 1716 | in0, |
| 1717 | in1, |
| 1718 | in2, |
| 1719 | out |
| 1720 | ); |
| 1721 | input in0; |
| 1722 | input in1; |
| 1723 | input in2; |
| 1724 | output out; |
| 1725 | |
| 1726 | `ifdef LIB |
| 1727 | assign out = ~(in0 & in1 & in2); |
| 1728 | `endif |
| 1729 | |
| 1730 | endmodule |
| 1731 | module cl_u1_nand3_16x ( |
| 1732 | in0, |
| 1733 | in1, |
| 1734 | in2, |
| 1735 | out |
| 1736 | ); |
| 1737 | input in0; |
| 1738 | input in1; |
| 1739 | input in2; |
| 1740 | output out; |
| 1741 | |
| 1742 | `ifdef LIB |
| 1743 | assign out = ~(in0 & in1 & in2); |
| 1744 | `endif |
| 1745 | |
| 1746 | endmodule |
| 1747 | module cl_u1_nand3_1x ( |
| 1748 | in0, |
| 1749 | in1, |
| 1750 | in2, |
| 1751 | out |
| 1752 | ); |
| 1753 | input in0; |
| 1754 | input in1; |
| 1755 | input in2; |
| 1756 | output out; |
| 1757 | |
| 1758 | `ifdef LIB |
| 1759 | assign out = ~(in0 & in1 & in2); |
| 1760 | `endif |
| 1761 | |
| 1762 | endmodule |
| 1763 | module cl_u1_nand3_20x ( |
| 1764 | in0, |
| 1765 | in1, |
| 1766 | in2, |
| 1767 | out |
| 1768 | ); |
| 1769 | input in0; |
| 1770 | input in1; |
| 1771 | input in2; |
| 1772 | output out; |
| 1773 | |
| 1774 | `ifdef LIB |
| 1775 | assign out = ~(in0 & in1 & in2); |
| 1776 | `endif |
| 1777 | |
| 1778 | endmodule |
| 1779 | module cl_u1_nand3_24x ( |
| 1780 | in0, |
| 1781 | in1, |
| 1782 | in2, |
| 1783 | out |
| 1784 | ); |
| 1785 | input in0; |
| 1786 | input in1; |
| 1787 | input in2; |
| 1788 | output out; |
| 1789 | |
| 1790 | `ifdef LIB |
| 1791 | assign out = ~(in0 & in1 & in2); |
| 1792 | `endif |
| 1793 | |
| 1794 | endmodule |
| 1795 | |
| 1796 | module cl_u1_nand3_2x ( |
| 1797 | in0, |
| 1798 | in1, |
| 1799 | in2, |
| 1800 | out |
| 1801 | ); |
| 1802 | input in0; |
| 1803 | input in1; |
| 1804 | input in2; |
| 1805 | output out; |
| 1806 | |
| 1807 | `ifdef LIB |
| 1808 | assign out = ~(in0 & in1 & in2); |
| 1809 | `endif |
| 1810 | |
| 1811 | endmodule |
| 1812 | |
| 1813 | module cl_u1_nand3_4x ( |
| 1814 | in0, |
| 1815 | in1, |
| 1816 | in2, |
| 1817 | out |
| 1818 | ); |
| 1819 | input in0; |
| 1820 | input in1; |
| 1821 | input in2; |
| 1822 | output out; |
| 1823 | |
| 1824 | `ifdef LIB |
| 1825 | assign out = ~(in0 & in1 & in2); |
| 1826 | `endif |
| 1827 | |
| 1828 | endmodule |
| 1829 | module cl_u1_nand3_6x ( |
| 1830 | in0, |
| 1831 | in1, |
| 1832 | in2, |
| 1833 | out |
| 1834 | ); |
| 1835 | input in0; |
| 1836 | input in1; |
| 1837 | input in2; |
| 1838 | output out; |
| 1839 | |
| 1840 | `ifdef LIB |
| 1841 | assign out = ~(in0 & in1 & in2); |
| 1842 | `endif |
| 1843 | |
| 1844 | endmodule |
| 1845 | module cl_u1_nand3_8x ( |
| 1846 | in0, |
| 1847 | in1, |
| 1848 | in2, |
| 1849 | out |
| 1850 | ); |
| 1851 | input in0; |
| 1852 | input in1; |
| 1853 | input in2; |
| 1854 | output out; |
| 1855 | |
| 1856 | `ifdef LIB |
| 1857 | assign out = ~(in0 & in1 & in2); |
| 1858 | `endif |
| 1859 | |
| 1860 | endmodule |
| 1861 | module cl_u1_nand4_12x ( |
| 1862 | in0, |
| 1863 | in1, |
| 1864 | in2, |
| 1865 | in3, |
| 1866 | out |
| 1867 | ); |
| 1868 | input in0; |
| 1869 | input in1; |
| 1870 | input in2; |
| 1871 | input in3; |
| 1872 | output out; |
| 1873 | |
| 1874 | `ifdef LIB |
| 1875 | assign out = ~(in0 & in1 & in2 & in3); |
| 1876 | `endif |
| 1877 | |
| 1878 | endmodule |
| 1879 | module cl_u1_nand4_16x ( |
| 1880 | in0, |
| 1881 | in1, |
| 1882 | in2, |
| 1883 | in3, |
| 1884 | out |
| 1885 | ); |
| 1886 | input in0; |
| 1887 | input in1; |
| 1888 | input in2; |
| 1889 | input in3; |
| 1890 | output out; |
| 1891 | |
| 1892 | `ifdef LIB |
| 1893 | assign out = ~(in0 & in1 & in2 & in3); |
| 1894 | `endif |
| 1895 | |
| 1896 | endmodule |
| 1897 | module cl_u1_nand4_1x ( |
| 1898 | in0, |
| 1899 | in1, |
| 1900 | in2, |
| 1901 | in3, |
| 1902 | out |
| 1903 | ); |
| 1904 | input in0; |
| 1905 | input in1; |
| 1906 | input in2; |
| 1907 | input in3; |
| 1908 | output out; |
| 1909 | |
| 1910 | `ifdef LIB |
| 1911 | assign out = ~(in0 & in1 & in2 & in3); |
| 1912 | `endif |
| 1913 | |
| 1914 | endmodule |
| 1915 | |
| 1916 | |
| 1917 | module cl_u1_nand4_2x ( |
| 1918 | in0, |
| 1919 | in1, |
| 1920 | in2, |
| 1921 | in3, |
| 1922 | out |
| 1923 | ); |
| 1924 | input in0; |
| 1925 | input in1; |
| 1926 | input in2; |
| 1927 | input in3; |
| 1928 | output out; |
| 1929 | |
| 1930 | `ifdef LIB |
| 1931 | assign out = ~(in0 & in1 & in2 & in3); |
| 1932 | `endif |
| 1933 | |
| 1934 | endmodule |
| 1935 | |
| 1936 | module cl_u1_nand4_4x ( |
| 1937 | in0, |
| 1938 | in1, |
| 1939 | in2, |
| 1940 | in3, |
| 1941 | out |
| 1942 | ); |
| 1943 | input in0; |
| 1944 | input in1; |
| 1945 | input in2; |
| 1946 | input in3; |
| 1947 | output out; |
| 1948 | |
| 1949 | `ifdef LIB |
| 1950 | assign out = ~(in0 & in1 & in2 & in3); |
| 1951 | `endif |
| 1952 | |
| 1953 | endmodule |
| 1954 | module cl_u1_nand4_6x ( |
| 1955 | in0, |
| 1956 | in1, |
| 1957 | in2, |
| 1958 | in3, |
| 1959 | out |
| 1960 | ); |
| 1961 | input in0; |
| 1962 | input in1; |
| 1963 | input in2; |
| 1964 | input in3; |
| 1965 | output out; |
| 1966 | |
| 1967 | `ifdef LIB |
| 1968 | assign out = ~(in0 & in1 & in2 & in3); |
| 1969 | `endif |
| 1970 | |
| 1971 | endmodule |
| 1972 | module cl_u1_nand4_8x ( |
| 1973 | in0, |
| 1974 | in1, |
| 1975 | in2, |
| 1976 | in3, |
| 1977 | out |
| 1978 | ); |
| 1979 | input in0; |
| 1980 | input in1; |
| 1981 | input in2; |
| 1982 | input in3; |
| 1983 | output out; |
| 1984 | |
| 1985 | `ifdef LIB |
| 1986 | assign out = ~(in0 & in1 & in2 & in3); |
| 1987 | `endif |
| 1988 | |
| 1989 | endmodule |
| 1990 | module cl_u1_nor2_12x ( |
| 1991 | in0, |
| 1992 | in1, |
| 1993 | out |
| 1994 | ); |
| 1995 | input in0; |
| 1996 | input in1; |
| 1997 | output out; |
| 1998 | |
| 1999 | `ifdef LIB |
| 2000 | assign out = ~(in0 | in1); |
| 2001 | `endif |
| 2002 | |
| 2003 | endmodule |
| 2004 | module cl_u1_nor2_16x ( |
| 2005 | in0, |
| 2006 | in1, |
| 2007 | out |
| 2008 | ); |
| 2009 | input in0; |
| 2010 | input in1; |
| 2011 | output out; |
| 2012 | |
| 2013 | `ifdef LIB |
| 2014 | assign out = ~(in0 | in1); |
| 2015 | `endif |
| 2016 | |
| 2017 | endmodule |
| 2018 | module cl_u1_nor2_1x ( |
| 2019 | in0, |
| 2020 | in1, |
| 2021 | out |
| 2022 | ); |
| 2023 | input in0; |
| 2024 | input in1; |
| 2025 | output out; |
| 2026 | |
| 2027 | `ifdef LIB |
| 2028 | assign out = ~(in0 | in1); |
| 2029 | `endif |
| 2030 | |
| 2031 | endmodule |
| 2032 | module cl_u1_nor2_2x ( |
| 2033 | in0, |
| 2034 | in1, |
| 2035 | out |
| 2036 | ); |
| 2037 | input in0; |
| 2038 | input in1; |
| 2039 | output out; |
| 2040 | |
| 2041 | `ifdef LIB |
| 2042 | assign out = ~(in0 | in1); |
| 2043 | `endif |
| 2044 | |
| 2045 | endmodule |
| 2046 | module cl_u1_nor2_4x ( |
| 2047 | in0, |
| 2048 | in1, |
| 2049 | out |
| 2050 | ); |
| 2051 | input in0; |
| 2052 | input in1; |
| 2053 | output out; |
| 2054 | |
| 2055 | `ifdef LIB |
| 2056 | assign out = ~(in0 | in1); |
| 2057 | `endif |
| 2058 | |
| 2059 | endmodule |
| 2060 | module cl_u1_nor2_6x ( |
| 2061 | in0, |
| 2062 | in1, |
| 2063 | out |
| 2064 | ); |
| 2065 | input in0; |
| 2066 | input in1; |
| 2067 | output out; |
| 2068 | |
| 2069 | `ifdef LIB |
| 2070 | assign out = ~(in0 | in1); |
| 2071 | `endif |
| 2072 | |
| 2073 | endmodule |
| 2074 | module cl_u1_nor2_8x ( |
| 2075 | in0, |
| 2076 | in1, |
| 2077 | out |
| 2078 | ); |
| 2079 | input in0; |
| 2080 | input in1; |
| 2081 | output out; |
| 2082 | |
| 2083 | `ifdef LIB |
| 2084 | assign out = ~(in0 | in1); |
| 2085 | `endif |
| 2086 | |
| 2087 | endmodule |
| 2088 | module cl_u1_nor3_1x ( |
| 2089 | in0, |
| 2090 | in1, |
| 2091 | in2, |
| 2092 | out |
| 2093 | ); |
| 2094 | input in0; |
| 2095 | input in1; |
| 2096 | input in2; |
| 2097 | output out; |
| 2098 | |
| 2099 | `ifdef LIB |
| 2100 | assign out = ~(in0 | in1 | in2); |
| 2101 | `endif |
| 2102 | |
| 2103 | endmodule |
| 2104 | module cl_u1_nor3_2x ( |
| 2105 | in0, |
| 2106 | in1, |
| 2107 | in2, |
| 2108 | out |
| 2109 | ); |
| 2110 | input in0; |
| 2111 | input in1; |
| 2112 | input in2; |
| 2113 | output out; |
| 2114 | |
| 2115 | `ifdef LIB |
| 2116 | assign out = ~(in0 | in1 | in2); |
| 2117 | `endif |
| 2118 | |
| 2119 | endmodule |
| 2120 | module cl_u1_nor3_4x ( |
| 2121 | in0, |
| 2122 | in1, |
| 2123 | in2, |
| 2124 | out |
| 2125 | ); |
| 2126 | input in0; |
| 2127 | input in1; |
| 2128 | input in2; |
| 2129 | output out; |
| 2130 | |
| 2131 | `ifdef LIB |
| 2132 | assign out = ~(in0 | in1 | in2); |
| 2133 | `endif |
| 2134 | |
| 2135 | endmodule |
| 2136 | // -------------------------------------------------- |
| 2137 | // File: cl_u1_oai12_12x.behV |
| 2138 | // Auto generated verilog module by HnBCellAuto |
| 2139 | // |
| 2140 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 2141 | // By: balmiki |
| 2142 | // -------------------------------------------------- |
| 2143 | // |
| 2144 | module cl_u1_oai12_12x ( |
| 2145 | out, |
| 2146 | in10, |
| 2147 | in00, |
| 2148 | in01 ); |
| 2149 | |
| 2150 | output out; |
| 2151 | input in10; |
| 2152 | input in00; |
| 2153 | input in01; |
| 2154 | |
| 2155 | `ifdef LIB |
| 2156 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 2157 | `endif |
| 2158 | |
| 2159 | endmodule |
| 2160 | // -------------------------------------------------- |
| 2161 | // File: cl_u1_oai12_16x.behV |
| 2162 | // Auto generated verilog module by HnBCellAuto |
| 2163 | // |
| 2164 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 2165 | // By: balmiki |
| 2166 | // -------------------------------------------------- |
| 2167 | // |
| 2168 | module cl_u1_oai12_16x ( |
| 2169 | out, |
| 2170 | in10, |
| 2171 | in00, |
| 2172 | in01 ); |
| 2173 | |
| 2174 | output out; |
| 2175 | input in10; |
| 2176 | input in00; |
| 2177 | input in01; |
| 2178 | |
| 2179 | `ifdef LIB |
| 2180 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 2181 | `endif |
| 2182 | |
| 2183 | endmodule |
| 2184 | // -------------------------------------------------- |
| 2185 | // File: cl_u1_oai12_1x.behV |
| 2186 | // Auto generated verilog module by HnBCellAuto |
| 2187 | // |
| 2188 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 2189 | // By: balmiki |
| 2190 | // -------------------------------------------------- |
| 2191 | // |
| 2192 | module cl_u1_oai12_1x ( |
| 2193 | out, |
| 2194 | in10, |
| 2195 | in00, |
| 2196 | in01 ); |
| 2197 | |
| 2198 | output out; |
| 2199 | input in10; |
| 2200 | input in00; |
| 2201 | input in01; |
| 2202 | |
| 2203 | `ifdef LIB |
| 2204 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 2205 | `endif |
| 2206 | |
| 2207 | endmodule |
| 2208 | // -------------------------------------------------- |
| 2209 | // File: cl_u1_oai12_2x.behV |
| 2210 | // Auto generated verilog module by HnBCellAuto |
| 2211 | // |
| 2212 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 2213 | // By: balmiki |
| 2214 | // -------------------------------------------------- |
| 2215 | // |
| 2216 | module cl_u1_oai12_2x ( |
| 2217 | out, |
| 2218 | in10, |
| 2219 | in00, |
| 2220 | in01 ); |
| 2221 | |
| 2222 | output out; |
| 2223 | input in10; |
| 2224 | input in00; |
| 2225 | input in01; |
| 2226 | |
| 2227 | `ifdef LIB |
| 2228 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 2229 | `endif |
| 2230 | |
| 2231 | endmodule |
| 2232 | // -------------------------------------------------- |
| 2233 | // File: cl_u1_oai12_4x.behV |
| 2234 | // Auto generated verilog module by HnBCellAuto |
| 2235 | // |
| 2236 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 2237 | // By: balmiki |
| 2238 | // -------------------------------------------------- |
| 2239 | // |
| 2240 | module cl_u1_oai12_4x ( |
| 2241 | out, |
| 2242 | in10, |
| 2243 | in00, |
| 2244 | in01 ); |
| 2245 | |
| 2246 | output out; |
| 2247 | input in10; |
| 2248 | input in00; |
| 2249 | input in01; |
| 2250 | |
| 2251 | `ifdef LIB |
| 2252 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 2253 | `endif |
| 2254 | |
| 2255 | endmodule |
| 2256 | // -------------------------------------------------- |
| 2257 | // File: cl_u1_oai12_8x.behV |
| 2258 | // Auto generated verilog module by HnBCellAuto |
| 2259 | // |
| 2260 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 2261 | // By: balmiki |
| 2262 | // -------------------------------------------------- |
| 2263 | // |
| 2264 | module cl_u1_oai12_8x ( |
| 2265 | out, |
| 2266 | in10, |
| 2267 | in00, |
| 2268 | in01 ); |
| 2269 | |
| 2270 | output out; |
| 2271 | input in10; |
| 2272 | input in00; |
| 2273 | input in01; |
| 2274 | |
| 2275 | `ifdef LIB |
| 2276 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 2277 | `endif |
| 2278 | |
| 2279 | endmodule |
| 2280 | // -------------------------------------------------- |
| 2281 | // File: cl_u1_oai21_12x.behV |
| 2282 | // Auto generated verilog module by HnBCellAuto |
| 2283 | // |
| 2284 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT |
| 2285 | // By: balmiki |
| 2286 | // -------------------------------------------------- |
| 2287 | // |
| 2288 | module cl_u1_oai21_12x ( |
| 2289 | out, |
| 2290 | in10, |
| 2291 | in11, |
| 2292 | in00 ); |
| 2293 | |
| 2294 | output out; |
| 2295 | input in10; |
| 2296 | input in11; |
| 2297 | input in00; |
| 2298 | |
| 2299 | `ifdef LIB |
| 2300 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 2301 | `endif |
| 2302 | |
| 2303 | endmodule |
| 2304 | // -------------------------------------------------- |
| 2305 | // File: cl_u1_oai21_16x.behV |
| 2306 | // Auto generated verilog module by HnBCellAuto |
| 2307 | // |
| 2308 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT |
| 2309 | // By: balmiki |
| 2310 | // -------------------------------------------------- |
| 2311 | // |
| 2312 | module cl_u1_oai21_16x ( |
| 2313 | out, |
| 2314 | in10, |
| 2315 | in11, |
| 2316 | in00 ); |
| 2317 | |
| 2318 | output out; |
| 2319 | input in10; |
| 2320 | input in11; |
| 2321 | input in00; |
| 2322 | |
| 2323 | `ifdef LIB |
| 2324 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 2325 | `endif |
| 2326 | |
| 2327 | endmodule |
| 2328 | // -------------------------------------------------- |
| 2329 | // File: cl_u1_oai21_1x.behV |
| 2330 | // Auto generated verilog module by HnBCellAuto |
| 2331 | // |
| 2332 | // Created: Friday Mar 15,2002 at 02:53:58 PM PST |
| 2333 | // By: balmiki |
| 2334 | // -------------------------------------------------- |
| 2335 | // |
| 2336 | module cl_u1_oai21_1x ( |
| 2337 | out, |
| 2338 | in10, |
| 2339 | in11, |
| 2340 | in00 ); |
| 2341 | |
| 2342 | output out; |
| 2343 | input in10; |
| 2344 | input in11; |
| 2345 | input in00; |
| 2346 | |
| 2347 | `ifdef LIB |
| 2348 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 2349 | `endif |
| 2350 | |
| 2351 | endmodule |
| 2352 | // -------------------------------------------------- |
| 2353 | // File: cl_u1_oai21_2x.behV |
| 2354 | // Auto generated verilog module by HnBCellAuto |
| 2355 | // |
| 2356 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT |
| 2357 | // By: balmiki |
| 2358 | // -------------------------------------------------- |
| 2359 | // |
| 2360 | module cl_u1_oai21_2x ( |
| 2361 | out, |
| 2362 | in10, |
| 2363 | in11, |
| 2364 | in00 ); |
| 2365 | |
| 2366 | output out; |
| 2367 | input in10; |
| 2368 | input in11; |
| 2369 | input in00; |
| 2370 | |
| 2371 | `ifdef LIB |
| 2372 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 2373 | `endif |
| 2374 | |
| 2375 | endmodule |
| 2376 | // -------------------------------------------------- |
| 2377 | // File: cl_u1_oai21_4x.behV |
| 2378 | // Auto generated verilog module by HnBCellAuto |
| 2379 | // |
| 2380 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT |
| 2381 | // By: balmiki |
| 2382 | // -------------------------------------------------- |
| 2383 | // |
| 2384 | module cl_u1_oai21_4x ( |
| 2385 | out, |
| 2386 | in10, |
| 2387 | in11, |
| 2388 | in00 ); |
| 2389 | |
| 2390 | output out; |
| 2391 | input in10; |
| 2392 | input in11; |
| 2393 | input in00; |
| 2394 | |
| 2395 | `ifdef LIB |
| 2396 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 2397 | `endif |
| 2398 | |
| 2399 | endmodule |
| 2400 | // -------------------------------------------------- |
| 2401 | // File: cl_u1_oai21_8x.behV |
| 2402 | // Auto generated verilog module by HnBCellAuto |
| 2403 | // |
| 2404 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT |
| 2405 | // By: balmiki |
| 2406 | // -------------------------------------------------- |
| 2407 | // |
| 2408 | module cl_u1_oai21_8x ( |
| 2409 | out, |
| 2410 | in10, |
| 2411 | in11, |
| 2412 | in00 ); |
| 2413 | |
| 2414 | output out; |
| 2415 | input in10; |
| 2416 | input in11; |
| 2417 | input in00; |
| 2418 | |
| 2419 | `ifdef LIB |
| 2420 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 2421 | `endif |
| 2422 | |
| 2423 | endmodule |
| 2424 | // -------------------------------------------------- |
| 2425 | // File: cl_u1_oai22_12x.behV |
| 2426 | // Auto generated verilog module by HnBCellAuto |
| 2427 | // |
| 2428 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT |
| 2429 | // By: balmiki |
| 2430 | // -------------------------------------------------- |
| 2431 | // |
| 2432 | module cl_u1_oai22_12x ( |
| 2433 | out, |
| 2434 | in10, |
| 2435 | in11, |
| 2436 | in00, |
| 2437 | in01 ); |
| 2438 | |
| 2439 | output out; |
| 2440 | input in10; |
| 2441 | input in11; |
| 2442 | input in00; |
| 2443 | input in01; |
| 2444 | |
| 2445 | `ifdef LIB |
| 2446 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 2447 | `endif |
| 2448 | |
| 2449 | endmodule |
| 2450 | // -------------------------------------------------- |
| 2451 | // File: cl_u1_oai22_16x.behV |
| 2452 | // Auto generated verilog module by HnBCellAuto |
| 2453 | // |
| 2454 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT |
| 2455 | // By: balmiki |
| 2456 | // -------------------------------------------------- |
| 2457 | // |
| 2458 | module cl_u1_oai22_16x ( |
| 2459 | out, |
| 2460 | in10, |
| 2461 | in11, |
| 2462 | in00, |
| 2463 | in01 ); |
| 2464 | |
| 2465 | output out; |
| 2466 | input in10; |
| 2467 | input in11; |
| 2468 | input in00; |
| 2469 | input in01; |
| 2470 | |
| 2471 | `ifdef LIB |
| 2472 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 2473 | `endif |
| 2474 | |
| 2475 | endmodule |
| 2476 | // -------------------------------------------------- |
| 2477 | // File: cl_u1_oai22_1x.behV |
| 2478 | // Auto generated verilog module by HnBCellAuto |
| 2479 | // |
| 2480 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT |
| 2481 | // By: balmiki |
| 2482 | // -------------------------------------------------- |
| 2483 | // |
| 2484 | module cl_u1_oai22_1x ( |
| 2485 | out, |
| 2486 | in10, |
| 2487 | in11, |
| 2488 | in00, |
| 2489 | in01 ); |
| 2490 | |
| 2491 | output out; |
| 2492 | input in10; |
| 2493 | input in11; |
| 2494 | input in00; |
| 2495 | input in01; |
| 2496 | |
| 2497 | `ifdef LIB |
| 2498 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 2499 | `endif |
| 2500 | |
| 2501 | endmodule |
| 2502 | // -------------------------------------------------- |
| 2503 | // File: cl_u1_oai22_2x.behV |
| 2504 | // Auto generated verilog module by HnBCellAuto |
| 2505 | // |
| 2506 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT |
| 2507 | // By: balmiki |
| 2508 | // -------------------------------------------------- |
| 2509 | // |
| 2510 | module cl_u1_oai22_2x ( |
| 2511 | out, |
| 2512 | in10, |
| 2513 | in11, |
| 2514 | in00, |
| 2515 | in01 ); |
| 2516 | |
| 2517 | output out; |
| 2518 | input in10; |
| 2519 | input in11; |
| 2520 | input in00; |
| 2521 | input in01; |
| 2522 | |
| 2523 | `ifdef LIB |
| 2524 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 2525 | `endif |
| 2526 | |
| 2527 | endmodule |
| 2528 | // -------------------------------------------------- |
| 2529 | // File: cl_u1_oai22_4x.behV |
| 2530 | // Auto generated verilog module by HnBCellAuto |
| 2531 | // |
| 2532 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT |
| 2533 | // By: balmiki |
| 2534 | // -------------------------------------------------- |
| 2535 | // |
| 2536 | module cl_u1_oai22_4x ( |
| 2537 | out, |
| 2538 | in10, |
| 2539 | in11, |
| 2540 | in00, |
| 2541 | in01 ); |
| 2542 | |
| 2543 | output out; |
| 2544 | input in10; |
| 2545 | input in11; |
| 2546 | input in00; |
| 2547 | input in01; |
| 2548 | |
| 2549 | `ifdef LIB |
| 2550 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 2551 | `endif |
| 2552 | |
| 2553 | endmodule |
| 2554 | // -------------------------------------------------- |
| 2555 | // File: cl_u1_oai22_8x.behV |
| 2556 | // Auto generated verilog module by HnBCellAuto |
| 2557 | // |
| 2558 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT |
| 2559 | // By: balmiki |
| 2560 | // -------------------------------------------------- |
| 2561 | // |
| 2562 | module cl_u1_oai22_8x ( |
| 2563 | out, |
| 2564 | in10, |
| 2565 | in11, |
| 2566 | in00, |
| 2567 | in01 ); |
| 2568 | |
| 2569 | output out; |
| 2570 | input in10; |
| 2571 | input in11; |
| 2572 | input in00; |
| 2573 | input in01; |
| 2574 | |
| 2575 | `ifdef LIB |
| 2576 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 2577 | `endif |
| 2578 | |
| 2579 | endmodule |
| 2580 | module cl_u1_xnor2_16x ( |
| 2581 | in0, |
| 2582 | in1, |
| 2583 | out |
| 2584 | ); |
| 2585 | input in0; |
| 2586 | input in1; |
| 2587 | output out; |
| 2588 | |
| 2589 | `ifdef LIB |
| 2590 | assign out = ~(in0 ^ in1); |
| 2591 | `endif |
| 2592 | |
| 2593 | endmodule |
| 2594 | |
| 2595 | module cl_u1_xnor2_1x ( |
| 2596 | in0, |
| 2597 | in1, |
| 2598 | out |
| 2599 | ); |
| 2600 | input in0; |
| 2601 | input in1; |
| 2602 | output out; |
| 2603 | |
| 2604 | `ifdef LIB |
| 2605 | assign out = ~(in0 ^ in1); |
| 2606 | `endif |
| 2607 | |
| 2608 | endmodule |
| 2609 | module cl_u1_xnor2_2x ( |
| 2610 | in0, |
| 2611 | in1, |
| 2612 | out |
| 2613 | ); |
| 2614 | input in0; |
| 2615 | input in1; |
| 2616 | output out; |
| 2617 | |
| 2618 | `ifdef LIB |
| 2619 | assign out = ~(in0 ^ in1); |
| 2620 | `endif |
| 2621 | |
| 2622 | endmodule |
| 2623 | module cl_u1_xnor2_4x ( |
| 2624 | in0, |
| 2625 | in1, |
| 2626 | out |
| 2627 | ); |
| 2628 | input in0; |
| 2629 | input in1; |
| 2630 | output out; |
| 2631 | |
| 2632 | `ifdef LIB |
| 2633 | assign out = ~(in0 ^ in1); |
| 2634 | `endif |
| 2635 | |
| 2636 | endmodule |
| 2637 | module cl_u1_xnor2_6x ( |
| 2638 | in0, |
| 2639 | in1, |
| 2640 | out |
| 2641 | ); |
| 2642 | input in0; |
| 2643 | input in1; |
| 2644 | output out; |
| 2645 | |
| 2646 | `ifdef LIB |
| 2647 | assign out = ~(in0 ^ in1); |
| 2648 | `endif |
| 2649 | |
| 2650 | endmodule |
| 2651 | module cl_u1_xnor2_8x ( |
| 2652 | in0, |
| 2653 | in1, |
| 2654 | out |
| 2655 | ); |
| 2656 | input in0; |
| 2657 | input in1; |
| 2658 | output out; |
| 2659 | |
| 2660 | `ifdef LIB |
| 2661 | assign out = ~(in0 ^ in1); |
| 2662 | `endif |
| 2663 | |
| 2664 | endmodule |
| 2665 | |
| 2666 | module cl_u1_xnor3_16x ( |
| 2667 | in0, |
| 2668 | in1, |
| 2669 | in2, |
| 2670 | out |
| 2671 | ); |
| 2672 | input in0; |
| 2673 | input in1; |
| 2674 | input in2; |
| 2675 | output out; |
| 2676 | |
| 2677 | `ifdef LIB |
| 2678 | assign out = ~(in0 ^ in1 ^ in2); |
| 2679 | `endif |
| 2680 | |
| 2681 | |
| 2682 | |
| 2683 | endmodule |
| 2684 | module cl_u1_xnor3_1x ( |
| 2685 | in0, |
| 2686 | in1, |
| 2687 | in2, |
| 2688 | out |
| 2689 | ); |
| 2690 | input in0; |
| 2691 | input in1; |
| 2692 | input in2; |
| 2693 | output out; |
| 2694 | |
| 2695 | `ifdef LIB |
| 2696 | assign out = ~(in0 ^ in1 ^ in2); |
| 2697 | `endif |
| 2698 | |
| 2699 | |
| 2700 | |
| 2701 | endmodule |
| 2702 | module cl_u1_xnor3_2x ( |
| 2703 | in0, |
| 2704 | in1, |
| 2705 | in2, |
| 2706 | out |
| 2707 | ); |
| 2708 | input in0; |
| 2709 | input in1; |
| 2710 | input in2; |
| 2711 | output out; |
| 2712 | |
| 2713 | `ifdef LIB |
| 2714 | assign out = ~(in0 ^ in1 ^ in2); |
| 2715 | `endif |
| 2716 | |
| 2717 | |
| 2718 | |
| 2719 | endmodule |
| 2720 | module cl_u1_xnor3_4x ( |
| 2721 | in0, |
| 2722 | in1, |
| 2723 | in2, |
| 2724 | out |
| 2725 | ); |
| 2726 | input in0; |
| 2727 | input in1; |
| 2728 | input in2; |
| 2729 | output out; |
| 2730 | |
| 2731 | `ifdef LIB |
| 2732 | assign out = ~(in0 ^ in1 ^ in2); |
| 2733 | `endif |
| 2734 | |
| 2735 | |
| 2736 | |
| 2737 | endmodule |
| 2738 | module cl_u1_xnor3_6x ( |
| 2739 | in0, |
| 2740 | in1, |
| 2741 | in2, |
| 2742 | out |
| 2743 | ); |
| 2744 | input in0; |
| 2745 | input in1; |
| 2746 | input in2; |
| 2747 | output out; |
| 2748 | |
| 2749 | `ifdef LIB |
| 2750 | assign out = ~(in0 ^ in1 ^ in2); |
| 2751 | `endif |
| 2752 | |
| 2753 | |
| 2754 | |
| 2755 | endmodule |
| 2756 | module cl_u1_xnor3_8x ( |
| 2757 | in0, |
| 2758 | in1, |
| 2759 | in2, |
| 2760 | out |
| 2761 | ); |
| 2762 | input in0; |
| 2763 | input in1; |
| 2764 | input in2; |
| 2765 | output out; |
| 2766 | |
| 2767 | `ifdef LIB |
| 2768 | assign out = ~(in0 ^ in1 ^ in2); |
| 2769 | `endif |
| 2770 | |
| 2771 | |
| 2772 | |
| 2773 | endmodule |
| 2774 | module cl_u1_xor2_16x ( |
| 2775 | in0, |
| 2776 | in1, |
| 2777 | out |
| 2778 | ); |
| 2779 | input in0; |
| 2780 | input in1; |
| 2781 | output out; |
| 2782 | |
| 2783 | `ifdef LIB |
| 2784 | assign out = in0 ^ in1; |
| 2785 | `endif |
| 2786 | |
| 2787 | endmodule |
| 2788 | |
| 2789 | module cl_u1_xor2_1x ( |
| 2790 | in0, |
| 2791 | in1, |
| 2792 | out |
| 2793 | ); |
| 2794 | input in0; |
| 2795 | input in1; |
| 2796 | output out; |
| 2797 | |
| 2798 | `ifdef LIB |
| 2799 | assign out = in0 ^ in1; |
| 2800 | `endif |
| 2801 | |
| 2802 | endmodule |
| 2803 | module cl_u1_xor2_2x ( |
| 2804 | in0, |
| 2805 | in1, |
| 2806 | out |
| 2807 | ); |
| 2808 | input in0; |
| 2809 | input in1; |
| 2810 | output out; |
| 2811 | |
| 2812 | `ifdef LIB |
| 2813 | assign out = in0 ^ in1; |
| 2814 | `endif |
| 2815 | |
| 2816 | endmodule |
| 2817 | module cl_u1_xor2_4x ( |
| 2818 | in0, |
| 2819 | in1, |
| 2820 | out |
| 2821 | ); |
| 2822 | input in0; |
| 2823 | input in1; |
| 2824 | output out; |
| 2825 | |
| 2826 | `ifdef LIB |
| 2827 | assign out = in0 ^ in1; |
| 2828 | `endif |
| 2829 | |
| 2830 | endmodule |
| 2831 | module cl_u1_xor2_6x ( |
| 2832 | in0, |
| 2833 | in1, |
| 2834 | out |
| 2835 | ); |
| 2836 | input in0; |
| 2837 | input in1; |
| 2838 | output out; |
| 2839 | |
| 2840 | `ifdef LIB |
| 2841 | assign out = in0 ^ in1; |
| 2842 | `endif |
| 2843 | |
| 2844 | endmodule |
| 2845 | module cl_u1_xor2_8x ( |
| 2846 | in0, |
| 2847 | in1, |
| 2848 | out |
| 2849 | ); |
| 2850 | input in0; |
| 2851 | input in1; |
| 2852 | output out; |
| 2853 | |
| 2854 | `ifdef LIB |
| 2855 | assign out = in0 ^ in1; |
| 2856 | `endif |
| 2857 | |
| 2858 | endmodule |
| 2859 | module cl_u1_xor3_16x ( |
| 2860 | in0, |
| 2861 | in1, |
| 2862 | in2, |
| 2863 | out |
| 2864 | ); |
| 2865 | input in0; |
| 2866 | input in1; |
| 2867 | input in2; |
| 2868 | output out; |
| 2869 | |
| 2870 | `ifdef LIB |
| 2871 | assign out = in0 ^ in1 ^ in2; |
| 2872 | `endif |
| 2873 | |
| 2874 | |
| 2875 | endmodule |
| 2876 | |
| 2877 | module cl_u1_xor3_1x ( |
| 2878 | in0, |
| 2879 | in1, |
| 2880 | in2, |
| 2881 | out |
| 2882 | ); |
| 2883 | input in0; |
| 2884 | input in1; |
| 2885 | input in2; |
| 2886 | output out; |
| 2887 | |
| 2888 | `ifdef LIB |
| 2889 | assign out = in0 ^ in1 ^ in2; |
| 2890 | `endif |
| 2891 | |
| 2892 | |
| 2893 | endmodule |
| 2894 | module cl_u1_xor3_2x ( |
| 2895 | in0, |
| 2896 | in1, |
| 2897 | in2, |
| 2898 | out |
| 2899 | ); |
| 2900 | input in0; |
| 2901 | input in1; |
| 2902 | input in2; |
| 2903 | output out; |
| 2904 | |
| 2905 | `ifdef LIB |
| 2906 | assign out = in0 ^ in1 ^ in2; |
| 2907 | `endif |
| 2908 | |
| 2909 | |
| 2910 | endmodule |
| 2911 | module cl_u1_xor3_4x ( |
| 2912 | in0, |
| 2913 | in1, |
| 2914 | in2, |
| 2915 | out |
| 2916 | ); |
| 2917 | input in0; |
| 2918 | input in1; |
| 2919 | input in2; |
| 2920 | output out; |
| 2921 | |
| 2922 | `ifdef LIB |
| 2923 | assign out = in0 ^ in1 ^ in2; |
| 2924 | `endif |
| 2925 | |
| 2926 | |
| 2927 | endmodule |
| 2928 | module cl_u1_xor3_6x ( |
| 2929 | in0, |
| 2930 | in1, |
| 2931 | in2, |
| 2932 | out |
| 2933 | ); |
| 2934 | input in0; |
| 2935 | input in1; |
| 2936 | input in2; |
| 2937 | output out; |
| 2938 | |
| 2939 | `ifdef LIB |
| 2940 | assign out = in0 ^ in1 ^ in2; |
| 2941 | `endif |
| 2942 | |
| 2943 | |
| 2944 | endmodule |
| 2945 | module cl_u1_xor3_8x ( |
| 2946 | in0, |
| 2947 | in1, |
| 2948 | in2, |
| 2949 | out |
| 2950 | ); |
| 2951 | input in0; |
| 2952 | input in1; |
| 2953 | input in2; |
| 2954 | output out; |
| 2955 | |
| 2956 | `ifdef LIB |
| 2957 | assign out = in0 ^ in1 ^ in2; |
| 2958 | `endif |
| 2959 | |
| 2960 | |
| 2961 | endmodule |
| 2962 | |
| 2963 | module cl_u1_clkchp_4x ( |
| 2964 | tck, |
| 2965 | aclk, |
| 2966 | bclk |
| 2967 | ); |
| 2968 | input tck; |
| 2969 | output aclk; |
| 2970 | output bclk; |
| 2971 | |
| 2972 | |
| 2973 | `ifdef LIB |
| 2974 | reg chop_aclk, chop_bclk; |
| 2975 | |
| 2976 | always @(posedge tck) begin |
| 2977 | chop_aclk = 1'b1; |
| 2978 | #5 chop_aclk = 1'b0; |
| 2979 | end |
| 2980 | always @(negedge tck) begin |
| 2981 | chop_bclk = 1'b1; |
| 2982 | #5 chop_bclk = 1'b0; |
| 2983 | end |
| 2984 | |
| 2985 | assign aclk = chop_aclk; |
| 2986 | assign bclk = chop_bclk; |
| 2987 | `endif |
| 2988 | |
| 2989 | endmodule |
| 2990 | |
| 2991 | module cl_u1_muxprotect_2x ( |
| 2992 | d0, |
| 2993 | d1, |
| 2994 | d2, |
| 2995 | d3, |
| 2996 | scan_en, |
| 2997 | e0, |
| 2998 | e1, |
| 2999 | e2, |
| 3000 | e3 |
| 3001 | ); |
| 3002 | input d0; |
| 3003 | input d1; |
| 3004 | input d2; |
| 3005 | input d3; |
| 3006 | input scan_en; |
| 3007 | output e0; |
| 3008 | output e1; |
| 3009 | output e2; |
| 3010 | output e3; |
| 3011 | |
| 3012 | `ifdef LIB |
| 3013 | assign e0 = scan_en | d0; |
| 3014 | assign e1= ~scan_en & d1; |
| 3015 | assign e2= ~scan_en & d2; |
| 3016 | assign e3= ~scan_en & d3; |
| 3017 | `endif |
| 3018 | |
| 3019 | endmodule |
| 3020 | |