| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: cl_u1lvt.behV |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module cl_u1lvt_aoi12_12x ( |
| 36 | out, |
| 37 | in10, |
| 38 | in00, |
| 39 | in01 ); |
| 40 | |
| 41 | output out; |
| 42 | input in10; |
| 43 | input in00; |
| 44 | input in01; |
| 45 | |
| 46 | `ifdef LIB |
| 47 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 48 | `endif |
| 49 | |
| 50 | endmodule |
| 51 | // -------------------------------------------------- |
| 52 | // File: cl_u1lvt_aoi12_16x.behV |
| 53 | // Auto generated verilog module by HnBCellAuto |
| 54 | // |
| 55 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST |
| 56 | // By: balmiki |
| 57 | // -------------------------------------------------- |
| 58 | // |
| 59 | module cl_u1lvt_aoi12_16x ( |
| 60 | out, |
| 61 | in10, |
| 62 | in00, |
| 63 | in01 ); |
| 64 | |
| 65 | output out; |
| 66 | input in10; |
| 67 | input in00; |
| 68 | input in01; |
| 69 | |
| 70 | `ifdef LIB |
| 71 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 72 | `endif |
| 73 | |
| 74 | endmodule |
| 75 | // -------------------------------------------------- |
| 76 | // File: cl_u1lvt_aoi12_1x.behV |
| 77 | // Auto generated verilog module by HnBCellAuto |
| 78 | // |
| 79 | // Created: Thursday Dec 6,2001 at 02:09:00 PM PST |
| 80 | // By: balmiki |
| 81 | // -------------------------------------------------- |
| 82 | // |
| 83 | module cl_u1lvt_aoi12_1x ( |
| 84 | out, |
| 85 | in10, |
| 86 | in00, |
| 87 | in01 ); |
| 88 | |
| 89 | output out; |
| 90 | input in10; |
| 91 | input in00; |
| 92 | input in01; |
| 93 | |
| 94 | `ifdef LIB |
| 95 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 96 | `endif |
| 97 | |
| 98 | endmodule |
| 99 | // -------------------------------------------------- |
| 100 | // File: cl_u1lvt_aoi12_2x.behV |
| 101 | // Auto generated verilog module by HnBCellAuto |
| 102 | // |
| 103 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST |
| 104 | // By: balmiki |
| 105 | // -------------------------------------------------- |
| 106 | // |
| 107 | module cl_u1lvt_aoi12_2x ( |
| 108 | out, |
| 109 | in10, |
| 110 | in00, |
| 111 | in01 ); |
| 112 | |
| 113 | output out; |
| 114 | input in10; |
| 115 | input in00; |
| 116 | input in01; |
| 117 | |
| 118 | `ifdef LIB |
| 119 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 120 | `endif |
| 121 | |
| 122 | endmodule |
| 123 | // -------------------------------------------------- |
| 124 | // File: cl_u1lvt_aoi12_4x.behV |
| 125 | // Auto generated verilog module by HnBCellAuto |
| 126 | // |
| 127 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST |
| 128 | // By: balmiki |
| 129 | // -------------------------------------------------- |
| 130 | // |
| 131 | module cl_u1lvt_aoi12_4x ( |
| 132 | out, |
| 133 | in10, |
| 134 | in00, |
| 135 | in01 ); |
| 136 | |
| 137 | output out; |
| 138 | input in10; |
| 139 | input in00; |
| 140 | input in01; |
| 141 | |
| 142 | `ifdef LIB |
| 143 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 144 | `endif |
| 145 | |
| 146 | endmodule |
| 147 | // -------------------------------------------------- |
| 148 | // File: cl_u1lvt_aoi12_8x.behV |
| 149 | // Auto generated verilog module by HnBCellAuto |
| 150 | // |
| 151 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST |
| 152 | // By: balmiki |
| 153 | // -------------------------------------------------- |
| 154 | // |
| 155 | module cl_u1lvt_aoi12_8x ( |
| 156 | out, |
| 157 | in10, |
| 158 | in00, |
| 159 | in01 ); |
| 160 | |
| 161 | output out; |
| 162 | input in10; |
| 163 | input in00; |
| 164 | input in01; |
| 165 | |
| 166 | `ifdef LIB |
| 167 | assign out = ~(( in10 ) | ( in00 & in01 )); |
| 168 | `endif |
| 169 | |
| 170 | endmodule |
| 171 | // -------------------------------------------------- |
| 172 | // File: cl_u1lvt_aoi21_12x.behV |
| 173 | // Auto generated verilog module by HnBCellAuto |
| 174 | // |
| 175 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 176 | // By: balmiki |
| 177 | // -------------------------------------------------- |
| 178 | // |
| 179 | module cl_u1lvt_aoi21_12x ( |
| 180 | out, |
| 181 | in10, |
| 182 | in11, |
| 183 | in00 ); |
| 184 | |
| 185 | output out; |
| 186 | input in10; |
| 187 | input in11; |
| 188 | input in00; |
| 189 | |
| 190 | `ifdef LIB |
| 191 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 192 | `endif |
| 193 | |
| 194 | endmodule |
| 195 | // -------------------------------------------------- |
| 196 | // File: cl_u1lvt_aoi21_16x.behV |
| 197 | // Auto generated verilog module by HnBCellAuto |
| 198 | // |
| 199 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 200 | // By: balmiki |
| 201 | // -------------------------------------------------- |
| 202 | // |
| 203 | module cl_u1lvt_aoi21_16x ( |
| 204 | out, |
| 205 | in10, |
| 206 | in11, |
| 207 | in00 ); |
| 208 | |
| 209 | output out; |
| 210 | input in10; |
| 211 | input in11; |
| 212 | input in00; |
| 213 | |
| 214 | `ifdef LIB |
| 215 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 216 | `endif |
| 217 | |
| 218 | endmodule |
| 219 | // -------------------------------------------------- |
| 220 | // File: cl_u1lvt_aoi21_1x.behV |
| 221 | // Auto generated verilog module by HnBCellAuto |
| 222 | // |
| 223 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 224 | // By: balmiki |
| 225 | // -------------------------------------------------- |
| 226 | // |
| 227 | module cl_u1lvt_aoi21_1x ( |
| 228 | out, |
| 229 | in10, |
| 230 | in11, |
| 231 | in00 ); |
| 232 | |
| 233 | output out; |
| 234 | input in10; |
| 235 | input in11; |
| 236 | input in00; |
| 237 | |
| 238 | `ifdef LIB |
| 239 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 240 | `endif |
| 241 | |
| 242 | endmodule |
| 243 | // -------------------------------------------------- |
| 244 | // File: cl_u1lvt_aoi21_2x.behV |
| 245 | // Auto generated verilog module by HnBCellAuto |
| 246 | // |
| 247 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 248 | // By: balmiki |
| 249 | // -------------------------------------------------- |
| 250 | // |
| 251 | module cl_u1lvt_aoi21_2x ( |
| 252 | out, |
| 253 | in10, |
| 254 | in11, |
| 255 | in00 ); |
| 256 | |
| 257 | output out; |
| 258 | input in10; |
| 259 | input in11; |
| 260 | input in00; |
| 261 | |
| 262 | `ifdef LIB |
| 263 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 264 | `endif |
| 265 | |
| 266 | endmodule |
| 267 | // -------------------------------------------------- |
| 268 | // File: cl_u1lvt_aoi21_4x.behV |
| 269 | // Auto generated verilog module by HnBCellAuto |
| 270 | // |
| 271 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 272 | // By: balmiki |
| 273 | // -------------------------------------------------- |
| 274 | // |
| 275 | module cl_u1lvt_aoi21_4x ( |
| 276 | out, |
| 277 | in10, |
| 278 | in11, |
| 279 | in00 ); |
| 280 | |
| 281 | output out; |
| 282 | input in10; |
| 283 | input in11; |
| 284 | input in00; |
| 285 | |
| 286 | `ifdef LIB |
| 287 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 288 | `endif |
| 289 | |
| 290 | endmodule |
| 291 | // -------------------------------------------------- |
| 292 | // File: cl_u1lvt_aoi21_8x.behV |
| 293 | // Auto generated verilog module by HnBCellAuto |
| 294 | // |
| 295 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT |
| 296 | // By: balmiki |
| 297 | // -------------------------------------------------- |
| 298 | // |
| 299 | module cl_u1lvt_aoi21_8x ( |
| 300 | out, |
| 301 | in10, |
| 302 | in11, |
| 303 | in00 ); |
| 304 | |
| 305 | output out; |
| 306 | input in10; |
| 307 | input in11; |
| 308 | input in00; |
| 309 | |
| 310 | `ifdef LIB |
| 311 | assign out = ~(( in10 & in11 ) | ( in00 )); |
| 312 | `endif |
| 313 | |
| 314 | endmodule |
| 315 | // -------------------------------------------------- |
| 316 | // File: cl_u1lvt_aoi22_12x.behV |
| 317 | // Auto generated verilog module by HnBCellAuto |
| 318 | // |
| 319 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT |
| 320 | // By: balmiki |
| 321 | // -------------------------------------------------- |
| 322 | // |
| 323 | module cl_u1lvt_aoi22_12x ( |
| 324 | out, |
| 325 | in10, |
| 326 | in11, |
| 327 | in00, |
| 328 | in01 ); |
| 329 | |
| 330 | output out; |
| 331 | input in10; |
| 332 | input in11; |
| 333 | input in00; |
| 334 | input in01; |
| 335 | |
| 336 | `ifdef LIB |
| 337 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); |
| 338 | `endif |
| 339 | |
| 340 | endmodule |
| 341 | // -------------------------------------------------- |
| 342 | // File: cl_u1lvt_aoi22_1x.behV |
| 343 | // Auto generated verilog module by HnBCellAuto |
| 344 | // |
| 345 | // Created: Wednesday May 29,2002 at 04:04:32 PM PDT |
| 346 | // By: balmiki |
| 347 | // -------------------------------------------------- |
| 348 | // |
| 349 | module cl_u1lvt_aoi22_1x ( |
| 350 | out, |
| 351 | in10, |
| 352 | in11, |
| 353 | in00, |
| 354 | in01 ); |
| 355 | |
| 356 | output out; |
| 357 | input in10; |
| 358 | input in11; |
| 359 | input in00; |
| 360 | input in01; |
| 361 | |
| 362 | `ifdef LIB |
| 363 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); |
| 364 | `endif |
| 365 | |
| 366 | endmodule |
| 367 | // -------------------------------------------------- |
| 368 | // File: cl_u1lvt_aoi22_2x.behV |
| 369 | // Auto generated verilog module by HnBCellAuto |
| 370 | // |
| 371 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT |
| 372 | // By: balmiki |
| 373 | // -------------------------------------------------- |
| 374 | // |
| 375 | module cl_u1lvt_aoi22_2x ( |
| 376 | out, |
| 377 | in10, |
| 378 | in11, |
| 379 | in00, |
| 380 | in01 ); |
| 381 | |
| 382 | output out; |
| 383 | input in10; |
| 384 | input in11; |
| 385 | input in00; |
| 386 | input in01; |
| 387 | |
| 388 | `ifdef LIB |
| 389 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); |
| 390 | `endif |
| 391 | |
| 392 | endmodule |
| 393 | // -------------------------------------------------- |
| 394 | // File: cl_u1lvt_aoi22_4x.behV |
| 395 | // Auto generated verilog module by HnBCellAuto |
| 396 | // |
| 397 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT |
| 398 | // By: balmiki |
| 399 | // -------------------------------------------------- |
| 400 | // |
| 401 | module cl_u1lvt_aoi22_4x ( |
| 402 | out, |
| 403 | in10, |
| 404 | in11, |
| 405 | in00, |
| 406 | in01 ); |
| 407 | |
| 408 | output out; |
| 409 | input in10; |
| 410 | input in11; |
| 411 | input in00; |
| 412 | input in01; |
| 413 | |
| 414 | `ifdef LIB |
| 415 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); |
| 416 | `endif |
| 417 | |
| 418 | endmodule |
| 419 | // -------------------------------------------------- |
| 420 | // File: cl_u1lvt_aoi22_8x.behV |
| 421 | // Auto generated verilog module by HnBCellAuto |
| 422 | // |
| 423 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT |
| 424 | // By: balmiki |
| 425 | // -------------------------------------------------- |
| 426 | // |
| 427 | module cl_u1lvt_aoi22_8x ( |
| 428 | out, |
| 429 | in10, |
| 430 | in11, |
| 431 | in00, |
| 432 | in01 ); |
| 433 | |
| 434 | output out; |
| 435 | input in10; |
| 436 | input in11; |
| 437 | input in00; |
| 438 | input in01; |
| 439 | |
| 440 | `ifdef LIB |
| 441 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); |
| 442 | `endif |
| 443 | |
| 444 | endmodule |
| 445 | // -------------------------------------------------- |
| 446 | // File: cl_u1lvt_aoi33_1x.behV |
| 447 | // Auto generated verilog module by HnBCellAuto |
| 448 | // |
| 449 | // Created: Thursday Dec 6,2001 at 02:09:02 PM PST |
| 450 | // By: balmiki |
| 451 | // -------------------------------------------------- |
| 452 | // |
| 453 | module cl_u1lvt_aoi33_1x ( |
| 454 | out, |
| 455 | in10, |
| 456 | in11, |
| 457 | in12, |
| 458 | in00, |
| 459 | in01, |
| 460 | in02 ); |
| 461 | |
| 462 | output out; |
| 463 | input in10; |
| 464 | input in11; |
| 465 | input in12; |
| 466 | input in00; |
| 467 | input in01; |
| 468 | input in02; |
| 469 | |
| 470 | `ifdef LIB |
| 471 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); |
| 472 | `endif |
| 473 | |
| 474 | endmodule |
| 475 | // -------------------------------------------------- |
| 476 | // File: cl_u1lvt_aoi33_2x.behV |
| 477 | // Auto generated verilog module by HnBCellAuto |
| 478 | // |
| 479 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT |
| 480 | // By: balmiki |
| 481 | // -------------------------------------------------- |
| 482 | // |
| 483 | module cl_u1lvt_aoi33_2x ( |
| 484 | out, |
| 485 | in10, |
| 486 | in11, |
| 487 | in12, |
| 488 | in00, |
| 489 | in01, |
| 490 | in02 ); |
| 491 | |
| 492 | output out; |
| 493 | input in10; |
| 494 | input in11; |
| 495 | input in12; |
| 496 | input in00; |
| 497 | input in01; |
| 498 | input in02; |
| 499 | |
| 500 | `ifdef LIB |
| 501 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); |
| 502 | `endif |
| 503 | |
| 504 | endmodule |
| 505 | // -------------------------------------------------- |
| 506 | // File: cl_u1lvt_aoi33_4x.behV |
| 507 | // Auto generated verilog module by HnBCellAuto |
| 508 | // |
| 509 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT |
| 510 | // By: balmiki |
| 511 | // -------------------------------------------------- |
| 512 | // |
| 513 | module cl_u1lvt_aoi33_4x ( |
| 514 | out, |
| 515 | in10, |
| 516 | in11, |
| 517 | in12, |
| 518 | in00, |
| 519 | in01, |
| 520 | in02 ); |
| 521 | |
| 522 | output out; |
| 523 | input in10; |
| 524 | input in11; |
| 525 | input in12; |
| 526 | input in00; |
| 527 | input in01; |
| 528 | input in02; |
| 529 | |
| 530 | `ifdef LIB |
| 531 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); |
| 532 | `endif |
| 533 | |
| 534 | endmodule |
| 535 | // -------------------------------------------------- |
| 536 | // File: cl_u1lvt_aoi33_8x.behV |
| 537 | // Auto generated verilog module by HnBCellAuto |
| 538 | // |
| 539 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT |
| 540 | // By: balmiki |
| 541 | // -------------------------------------------------- |
| 542 | // |
| 543 | module cl_u1lvt_aoi33_8x ( |
| 544 | out, |
| 545 | in10, |
| 546 | in11, |
| 547 | in12, |
| 548 | in00, |
| 549 | in01, |
| 550 | in02 ); |
| 551 | |
| 552 | output out; |
| 553 | input in10; |
| 554 | input in11; |
| 555 | input in12; |
| 556 | input in00; |
| 557 | input in01; |
| 558 | input in02; |
| 559 | |
| 560 | `ifdef LIB |
| 561 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); |
| 562 | `endif |
| 563 | |
| 564 | endmodule |
| 565 | module cl_u1lvt_buf_12x ( |
| 566 | in, |
| 567 | out |
| 568 | ); |
| 569 | input in; |
| 570 | output out; |
| 571 | |
| 572 | `ifdef LIB |
| 573 | assign out = in; |
| 574 | `endif |
| 575 | |
| 576 | endmodule |
| 577 | module cl_u1lvt_buf_16x ( |
| 578 | in, |
| 579 | out |
| 580 | ); |
| 581 | input in; |
| 582 | output out; |
| 583 | |
| 584 | `ifdef LIB |
| 585 | assign out = in; |
| 586 | `endif |
| 587 | |
| 588 | endmodule |
| 589 | module cl_u1lvt_buf_1x ( |
| 590 | in, |
| 591 | out |
| 592 | ); |
| 593 | input in; |
| 594 | output out; |
| 595 | |
| 596 | `ifdef LIB |
| 597 | assign out = in; |
| 598 | `endif |
| 599 | |
| 600 | endmodule |
| 601 | module cl_u1lvt_buf_20x ( |
| 602 | in, |
| 603 | out |
| 604 | ); |
| 605 | input in; |
| 606 | output out; |
| 607 | |
| 608 | `ifdef LIB |
| 609 | assign out = in; |
| 610 | `endif |
| 611 | |
| 612 | endmodule |
| 613 | module cl_u1lvt_buf_24x ( |
| 614 | in, |
| 615 | out |
| 616 | ); |
| 617 | input in; |
| 618 | output out; |
| 619 | |
| 620 | `ifdef LIB |
| 621 | assign out = in; |
| 622 | `endif |
| 623 | |
| 624 | endmodule |
| 625 | module cl_u1lvt_buf_28x ( |
| 626 | in, |
| 627 | out |
| 628 | ); |
| 629 | input in; |
| 630 | output out; |
| 631 | |
| 632 | `ifdef LIB |
| 633 | assign out = in; |
| 634 | `endif |
| 635 | |
| 636 | endmodule |
| 637 | module cl_u1lvt_buf_2x ( |
| 638 | in, |
| 639 | out |
| 640 | ); |
| 641 | input in; |
| 642 | output out; |
| 643 | |
| 644 | `ifdef LIB |
| 645 | assign out = in; |
| 646 | `endif |
| 647 | |
| 648 | endmodule |
| 649 | module cl_u1lvt_buf_32x ( |
| 650 | in, |
| 651 | out |
| 652 | ); |
| 653 | input in; |
| 654 | output out; |
| 655 | |
| 656 | `ifdef LIB |
| 657 | assign out = in; |
| 658 | `endif |
| 659 | |
| 660 | endmodule |
| 661 | module cl_u1lvt_buf_36x ( |
| 662 | in, |
| 663 | out |
| 664 | ); |
| 665 | input in; |
| 666 | output out; |
| 667 | |
| 668 | `ifdef LIB |
| 669 | assign out = in; |
| 670 | `endif |
| 671 | |
| 672 | endmodule |
| 673 | module cl_u1lvt_buf_40x ( |
| 674 | in, |
| 675 | out |
| 676 | ); |
| 677 | input in; |
| 678 | output out; |
| 679 | |
| 680 | `ifdef LIB |
| 681 | assign out = in; |
| 682 | `endif |
| 683 | |
| 684 | endmodule |
| 685 | module cl_u1lvt_buf_44x ( |
| 686 | in, |
| 687 | out |
| 688 | ); |
| 689 | input in; |
| 690 | output out; |
| 691 | |
| 692 | `ifdef LIB |
| 693 | assign out = in; |
| 694 | `endif |
| 695 | |
| 696 | endmodule |
| 697 | module cl_u1lvt_buf_48x ( |
| 698 | in, |
| 699 | out |
| 700 | ); |
| 701 | input in; |
| 702 | output out; |
| 703 | |
| 704 | `ifdef LIB |
| 705 | assign out = in; |
| 706 | `endif |
| 707 | |
| 708 | endmodule |
| 709 | module cl_u1lvt_buf_4x ( |
| 710 | in, |
| 711 | out |
| 712 | ); |
| 713 | input in; |
| 714 | output out; |
| 715 | |
| 716 | `ifdef LIB |
| 717 | assign out = in; |
| 718 | `endif |
| 719 | |
| 720 | endmodule |
| 721 | module cl_u1lvt_buf_56x ( |
| 722 | in, |
| 723 | out |
| 724 | ); |
| 725 | input in; |
| 726 | output out; |
| 727 | |
| 728 | `ifdef LIB |
| 729 | assign out = in; |
| 730 | `endif |
| 731 | |
| 732 | endmodule |
| 733 | module cl_u1lvt_buf_64x ( |
| 734 | in, |
| 735 | out |
| 736 | ); |
| 737 | input in; |
| 738 | output out; |
| 739 | |
| 740 | `ifdef LIB |
| 741 | assign out = in; |
| 742 | `endif |
| 743 | |
| 744 | endmodule |
| 745 | module cl_u1lvt_buf_6x ( |
| 746 | in, |
| 747 | out |
| 748 | ); |
| 749 | input in; |
| 750 | output out; |
| 751 | |
| 752 | `ifdef LIB |
| 753 | assign out = in; |
| 754 | `endif |
| 755 | |
| 756 | endmodule |
| 757 | module cl_u1lvt_buf_8x ( |
| 758 | in, |
| 759 | out |
| 760 | ); |
| 761 | input in; |
| 762 | output out; |
| 763 | |
| 764 | `ifdef LIB |
| 765 | assign out = in; |
| 766 | `endif |
| 767 | |
| 768 | endmodule |
| 769 | module cl_u1lvt_inv_12x ( |
| 770 | in, |
| 771 | out |
| 772 | ); |
| 773 | input in; |
| 774 | output out; |
| 775 | |
| 776 | `ifdef LIB |
| 777 | assign out = ~in; |
| 778 | `endif |
| 779 | |
| 780 | endmodule |
| 781 | module cl_u1lvt_inv_16x ( |
| 782 | in, |
| 783 | out |
| 784 | ); |
| 785 | input in; |
| 786 | output out; |
| 787 | |
| 788 | `ifdef LIB |
| 789 | assign out = ~in; |
| 790 | `endif |
| 791 | |
| 792 | endmodule |
| 793 | module cl_u1lvt_inv_1x ( |
| 794 | in, |
| 795 | out |
| 796 | ); |
| 797 | input in; |
| 798 | output out; |
| 799 | |
| 800 | `ifdef LIB |
| 801 | assign out = ~in; |
| 802 | `endif |
| 803 | |
| 804 | endmodule |
| 805 | module cl_u1lvt_inv_20x ( |
| 806 | in, |
| 807 | out |
| 808 | ); |
| 809 | input in; |
| 810 | output out; |
| 811 | |
| 812 | `ifdef LIB |
| 813 | assign out = ~in; |
| 814 | `endif |
| 815 | |
| 816 | endmodule |
| 817 | module cl_u1lvt_inv_24x ( |
| 818 | in, |
| 819 | out |
| 820 | ); |
| 821 | input in; |
| 822 | output out; |
| 823 | |
| 824 | `ifdef LIB |
| 825 | assign out = ~in; |
| 826 | `endif |
| 827 | |
| 828 | endmodule |
| 829 | module cl_u1lvt_inv_28x ( |
| 830 | in, |
| 831 | out |
| 832 | ); |
| 833 | input in; |
| 834 | output out; |
| 835 | |
| 836 | `ifdef LIB |
| 837 | assign out = ~in; |
| 838 | `endif |
| 839 | |
| 840 | endmodule |
| 841 | module cl_u1lvt_inv_2x ( |
| 842 | in, |
| 843 | out |
| 844 | ); |
| 845 | input in; |
| 846 | output out; |
| 847 | |
| 848 | `ifdef LIB |
| 849 | assign out = ~in; |
| 850 | `endif |
| 851 | |
| 852 | endmodule |
| 853 | module cl_u1lvt_inv_32x ( |
| 854 | in, |
| 855 | out |
| 856 | ); |
| 857 | input in; |
| 858 | output out; |
| 859 | |
| 860 | `ifdef LIB |
| 861 | assign out = ~in; |
| 862 | `endif |
| 863 | |
| 864 | endmodule |
| 865 | module cl_u1lvt_inv_36x ( |
| 866 | in, |
| 867 | out |
| 868 | ); |
| 869 | input in; |
| 870 | output out; |
| 871 | |
| 872 | `ifdef LIB |
| 873 | assign out = ~in; |
| 874 | `endif |
| 875 | |
| 876 | endmodule |
| 877 | module cl_u1lvt_inv_40x ( |
| 878 | in, |
| 879 | out |
| 880 | ); |
| 881 | input in; |
| 882 | output out; |
| 883 | |
| 884 | `ifdef LIB |
| 885 | assign out = ~in; |
| 886 | `endif |
| 887 | |
| 888 | endmodule |
| 889 | module cl_u1lvt_inv_44x ( |
| 890 | in, |
| 891 | out |
| 892 | ); |
| 893 | input in; |
| 894 | output out; |
| 895 | |
| 896 | `ifdef LIB |
| 897 | assign out = ~in; |
| 898 | `endif |
| 899 | |
| 900 | endmodule |
| 901 | module cl_u1lvt_inv_48x ( |
| 902 | in, |
| 903 | out |
| 904 | ); |
| 905 | input in; |
| 906 | output out; |
| 907 | |
| 908 | `ifdef LIB |
| 909 | assign out = ~in; |
| 910 | `endif |
| 911 | |
| 912 | endmodule |
| 913 | module cl_u1lvt_inv_4x ( |
| 914 | in, |
| 915 | out |
| 916 | ); |
| 917 | input in; |
| 918 | output out; |
| 919 | |
| 920 | `ifdef LIB |
| 921 | assign out = ~in; |
| 922 | `endif |
| 923 | |
| 924 | endmodule |
| 925 | module cl_u1lvt_inv_56x ( |
| 926 | in, |
| 927 | out |
| 928 | ); |
| 929 | input in; |
| 930 | output out; |
| 931 | |
| 932 | `ifdef LIB |
| 933 | assign out = ~in; |
| 934 | `endif |
| 935 | |
| 936 | endmodule |
| 937 | module cl_u1lvt_inv_64x ( |
| 938 | in, |
| 939 | out |
| 940 | ); |
| 941 | input in; |
| 942 | output out; |
| 943 | |
| 944 | `ifdef LIB |
| 945 | assign out = ~in; |
| 946 | `endif |
| 947 | |
| 948 | endmodule |
| 949 | module cl_u1lvt_inv_6x ( |
| 950 | in, |
| 951 | out |
| 952 | ); |
| 953 | input in; |
| 954 | output out; |
| 955 | |
| 956 | `ifdef LIB |
| 957 | assign out = ~in; |
| 958 | `endif |
| 959 | |
| 960 | endmodule |
| 961 | module cl_u1lvt_inv_8x ( |
| 962 | in, |
| 963 | out |
| 964 | ); |
| 965 | input in; |
| 966 | output out; |
| 967 | |
| 968 | `ifdef LIB |
| 969 | assign out = ~in; |
| 970 | `endif |
| 971 | |
| 972 | endmodule |
| 973 | module cl_u1lvt_nand2_12x ( |
| 974 | in0, |
| 975 | in1, |
| 976 | out |
| 977 | ); |
| 978 | input in0; |
| 979 | input in1; |
| 980 | output out; |
| 981 | |
| 982 | `ifdef LIB |
| 983 | assign out = ~(in0 & in1); |
| 984 | `endif |
| 985 | |
| 986 | endmodule |
| 987 | module cl_u1lvt_nand2_16x ( |
| 988 | in0, |
| 989 | in1, |
| 990 | out |
| 991 | ); |
| 992 | input in0; |
| 993 | input in1; |
| 994 | output out; |
| 995 | |
| 996 | `ifdef LIB |
| 997 | assign out = ~(in0 & in1); |
| 998 | `endif |
| 999 | |
| 1000 | endmodule |
| 1001 | module cl_u1lvt_nand2_1x ( |
| 1002 | in0, |
| 1003 | in1, |
| 1004 | out |
| 1005 | ); |
| 1006 | input in0; |
| 1007 | input in1; |
| 1008 | output out; |
| 1009 | |
| 1010 | `ifdef LIB |
| 1011 | assign out = ~(in0 & in1); |
| 1012 | `endif |
| 1013 | |
| 1014 | endmodule |
| 1015 | module cl_u1lvt_nand2_20x ( |
| 1016 | in0, |
| 1017 | in1, |
| 1018 | out |
| 1019 | ); |
| 1020 | input in0; |
| 1021 | input in1; |
| 1022 | output out; |
| 1023 | |
| 1024 | `ifdef LIB |
| 1025 | assign out = ~(in0 & in1); |
| 1026 | `endif |
| 1027 | |
| 1028 | endmodule |
| 1029 | module cl_u1lvt_nand2_24x ( |
| 1030 | in0, |
| 1031 | in1, |
| 1032 | out |
| 1033 | ); |
| 1034 | input in0; |
| 1035 | input in1; |
| 1036 | output out; |
| 1037 | |
| 1038 | `ifdef LIB |
| 1039 | assign out = ~(in0 & in1); |
| 1040 | `endif |
| 1041 | |
| 1042 | endmodule |
| 1043 | module cl_u1lvt_nand2_28x ( |
| 1044 | in0, |
| 1045 | in1, |
| 1046 | out |
| 1047 | ); |
| 1048 | input in0; |
| 1049 | input in1; |
| 1050 | output out; |
| 1051 | |
| 1052 | `ifdef LIB |
| 1053 | assign out = ~(in0 & in1); |
| 1054 | `endif |
| 1055 | |
| 1056 | endmodule |
| 1057 | module cl_u1lvt_nand2_2x ( |
| 1058 | in0, |
| 1059 | in1, |
| 1060 | out |
| 1061 | ); |
| 1062 | input in0; |
| 1063 | input in1; |
| 1064 | output out; |
| 1065 | |
| 1066 | `ifdef LIB |
| 1067 | assign out = ~(in0 & in1); |
| 1068 | `endif |
| 1069 | |
| 1070 | endmodule |
| 1071 | module cl_u1lvt_nand2_32x ( |
| 1072 | in0, |
| 1073 | in1, |
| 1074 | out |
| 1075 | ); |
| 1076 | input in0; |
| 1077 | input in1; |
| 1078 | output out; |
| 1079 | |
| 1080 | `ifdef LIB |
| 1081 | assign out = ~(in0 & in1); |
| 1082 | `endif |
| 1083 | |
| 1084 | endmodule |
| 1085 | module cl_u1lvt_nand2_4x ( |
| 1086 | in0, |
| 1087 | in1, |
| 1088 | out |
| 1089 | ); |
| 1090 | input in0; |
| 1091 | input in1; |
| 1092 | output out; |
| 1093 | |
| 1094 | `ifdef LIB |
| 1095 | assign out = ~(in0 & in1); |
| 1096 | `endif |
| 1097 | |
| 1098 | endmodule |
| 1099 | module cl_u1lvt_nand2_6x ( |
| 1100 | in0, |
| 1101 | in1, |
| 1102 | out |
| 1103 | ); |
| 1104 | input in0; |
| 1105 | input in1; |
| 1106 | output out; |
| 1107 | |
| 1108 | `ifdef LIB |
| 1109 | assign out = ~(in0 & in1); |
| 1110 | `endif |
| 1111 | |
| 1112 | endmodule |
| 1113 | module cl_u1lvt_nand2_8x ( |
| 1114 | in0, |
| 1115 | in1, |
| 1116 | out |
| 1117 | ); |
| 1118 | input in0; |
| 1119 | input in1; |
| 1120 | output out; |
| 1121 | |
| 1122 | `ifdef LIB |
| 1123 | assign out = ~(in0 & in1); |
| 1124 | `endif |
| 1125 | |
| 1126 | endmodule |
| 1127 | module cl_u1lvt_nand3_12x ( |
| 1128 | in0, |
| 1129 | in1, |
| 1130 | in2, |
| 1131 | out |
| 1132 | ); |
| 1133 | input in0; |
| 1134 | input in1; |
| 1135 | input in2; |
| 1136 | output out; |
| 1137 | |
| 1138 | `ifdef LIB |
| 1139 | assign out = ~(in0 & in1 & in2); |
| 1140 | `endif |
| 1141 | |
| 1142 | endmodule |
| 1143 | module cl_u1lvt_nand3_16x ( |
| 1144 | in0, |
| 1145 | in1, |
| 1146 | in2, |
| 1147 | out |
| 1148 | ); |
| 1149 | input in0; |
| 1150 | input in1; |
| 1151 | input in2; |
| 1152 | output out; |
| 1153 | |
| 1154 | `ifdef LIB |
| 1155 | assign out = ~(in0 & in1 & in2); |
| 1156 | `endif |
| 1157 | |
| 1158 | endmodule |
| 1159 | module cl_u1lvt_nand3_1x ( |
| 1160 | in0, |
| 1161 | in1, |
| 1162 | in2, |
| 1163 | out |
| 1164 | ); |
| 1165 | input in0; |
| 1166 | input in1; |
| 1167 | input in2; |
| 1168 | output out; |
| 1169 | |
| 1170 | `ifdef LIB |
| 1171 | assign out = ~(in0 & in1 & in2); |
| 1172 | `endif |
| 1173 | |
| 1174 | endmodule |
| 1175 | module cl_u1lvt_nand3_20x ( |
| 1176 | in0, |
| 1177 | in1, |
| 1178 | in2, |
| 1179 | out |
| 1180 | ); |
| 1181 | input in0; |
| 1182 | input in1; |
| 1183 | input in2; |
| 1184 | output out; |
| 1185 | |
| 1186 | `ifdef LIB |
| 1187 | assign out = ~(in0 & in1 & in2); |
| 1188 | `endif |
| 1189 | |
| 1190 | endmodule |
| 1191 | module cl_u1lvt_nand3_24x ( |
| 1192 | in0, |
| 1193 | in1, |
| 1194 | in2, |
| 1195 | out |
| 1196 | ); |
| 1197 | input in0; |
| 1198 | input in1; |
| 1199 | input in2; |
| 1200 | output out; |
| 1201 | |
| 1202 | `ifdef LIB |
| 1203 | assign out = ~(in0 & in1 & in2); |
| 1204 | `endif |
| 1205 | |
| 1206 | endmodule |
| 1207 | module cl_u1lvt_nand3_2x ( |
| 1208 | in0, |
| 1209 | in1, |
| 1210 | in2, |
| 1211 | out |
| 1212 | ); |
| 1213 | input in0; |
| 1214 | input in1; |
| 1215 | input in2; |
| 1216 | output out; |
| 1217 | |
| 1218 | `ifdef LIB |
| 1219 | assign out = ~(in0 & in1 & in2); |
| 1220 | `endif |
| 1221 | |
| 1222 | endmodule |
| 1223 | module cl_u1lvt_nand3_4x ( |
| 1224 | in0, |
| 1225 | in1, |
| 1226 | in2, |
| 1227 | out |
| 1228 | ); |
| 1229 | input in0; |
| 1230 | input in1; |
| 1231 | input in2; |
| 1232 | output out; |
| 1233 | |
| 1234 | `ifdef LIB |
| 1235 | assign out = ~(in0 & in1 & in2); |
| 1236 | `endif |
| 1237 | |
| 1238 | endmodule |
| 1239 | module cl_u1lvt_nand3_6x ( |
| 1240 | in0, |
| 1241 | in1, |
| 1242 | in2, |
| 1243 | out |
| 1244 | ); |
| 1245 | input in0; |
| 1246 | input in1; |
| 1247 | input in2; |
| 1248 | output out; |
| 1249 | |
| 1250 | `ifdef LIB |
| 1251 | assign out = ~(in0 & in1 & in2); |
| 1252 | `endif |
| 1253 | |
| 1254 | endmodule |
| 1255 | module cl_u1lvt_nand3_8x ( |
| 1256 | in0, |
| 1257 | in1, |
| 1258 | in2, |
| 1259 | out |
| 1260 | ); |
| 1261 | input in0; |
| 1262 | input in1; |
| 1263 | input in2; |
| 1264 | output out; |
| 1265 | |
| 1266 | `ifdef LIB |
| 1267 | assign out = ~(in0 & in1 & in2); |
| 1268 | `endif |
| 1269 | |
| 1270 | endmodule |
| 1271 | module cl_u1lvt_nand4_12x ( |
| 1272 | in0, |
| 1273 | in1, |
| 1274 | in2, |
| 1275 | in3, |
| 1276 | out |
| 1277 | ); |
| 1278 | input in0; |
| 1279 | input in1; |
| 1280 | input in2; |
| 1281 | input in3; |
| 1282 | output out; |
| 1283 | |
| 1284 | `ifdef LIB |
| 1285 | assign out = ~(in0 & in1 & in2 & in3); |
| 1286 | `endif |
| 1287 | |
| 1288 | endmodule |
| 1289 | module cl_u1lvt_nand4_16x ( |
| 1290 | in0, |
| 1291 | in1, |
| 1292 | in2, |
| 1293 | in3, |
| 1294 | out |
| 1295 | ); |
| 1296 | input in0; |
| 1297 | input in1; |
| 1298 | input in2; |
| 1299 | input in3; |
| 1300 | output out; |
| 1301 | |
| 1302 | `ifdef LIB |
| 1303 | assign out = ~(in0 & in1 & in2 & in3); |
| 1304 | `endif |
| 1305 | |
| 1306 | endmodule |
| 1307 | module cl_u1lvt_nand4_1x ( |
| 1308 | in0, |
| 1309 | in1, |
| 1310 | in2, |
| 1311 | in3, |
| 1312 | out |
| 1313 | ); |
| 1314 | input in0; |
| 1315 | input in1; |
| 1316 | input in2; |
| 1317 | input in3; |
| 1318 | output out; |
| 1319 | |
| 1320 | `ifdef LIB |
| 1321 | assign out = ~(in0 & in1 & in2 & in3); |
| 1322 | `endif |
| 1323 | |
| 1324 | endmodule |
| 1325 | module cl_u1lvt_nand4_2x ( |
| 1326 | in0, |
| 1327 | in1, |
| 1328 | in2, |
| 1329 | in3, |
| 1330 | out |
| 1331 | ); |
| 1332 | input in0; |
| 1333 | input in1; |
| 1334 | input in2; |
| 1335 | input in3; |
| 1336 | output out; |
| 1337 | |
| 1338 | `ifdef LIB |
| 1339 | assign out = ~(in0 & in1 & in2 & in3); |
| 1340 | `endif |
| 1341 | |
| 1342 | endmodule |
| 1343 | module cl_u1lvt_nand4_4x ( |
| 1344 | in0, |
| 1345 | in1, |
| 1346 | in2, |
| 1347 | in3, |
| 1348 | out |
| 1349 | ); |
| 1350 | input in0; |
| 1351 | input in1; |
| 1352 | input in2; |
| 1353 | input in3; |
| 1354 | output out; |
| 1355 | |
| 1356 | `ifdef LIB |
| 1357 | assign out = ~(in0 & in1 & in2 & in3); |
| 1358 | `endif |
| 1359 | |
| 1360 | endmodule |
| 1361 | module cl_u1lvt_nand4_6x ( |
| 1362 | in0, |
| 1363 | in1, |
| 1364 | in2, |
| 1365 | in3, |
| 1366 | out |
| 1367 | ); |
| 1368 | input in0; |
| 1369 | input in1; |
| 1370 | input in2; |
| 1371 | input in3; |
| 1372 | output out; |
| 1373 | |
| 1374 | `ifdef LIB |
| 1375 | assign out = ~(in0 & in1 & in2 & in3); |
| 1376 | `endif |
| 1377 | |
| 1378 | endmodule |
| 1379 | module cl_u1lvt_nand4_8x ( |
| 1380 | in0, |
| 1381 | in1, |
| 1382 | in2, |
| 1383 | in3, |
| 1384 | out |
| 1385 | ); |
| 1386 | input in0; |
| 1387 | input in1; |
| 1388 | input in2; |
| 1389 | input in3; |
| 1390 | output out; |
| 1391 | |
| 1392 | `ifdef LIB |
| 1393 | assign out = ~(in0 & in1 & in2 & in3); |
| 1394 | `endif |
| 1395 | |
| 1396 | endmodule |
| 1397 | module cl_u1lvt_nor2_12x ( |
| 1398 | in0, |
| 1399 | in1, |
| 1400 | out |
| 1401 | ); |
| 1402 | input in0; |
| 1403 | input in1; |
| 1404 | output out; |
| 1405 | |
| 1406 | `ifdef LIB |
| 1407 | assign out = ~(in0 | in1); |
| 1408 | `endif |
| 1409 | |
| 1410 | endmodule |
| 1411 | module cl_u1lvt_nor2_16x ( |
| 1412 | in0, |
| 1413 | in1, |
| 1414 | out |
| 1415 | ); |
| 1416 | input in0; |
| 1417 | input in1; |
| 1418 | output out; |
| 1419 | |
| 1420 | `ifdef LIB |
| 1421 | assign out = ~(in0 | in1); |
| 1422 | `endif |
| 1423 | |
| 1424 | endmodule |
| 1425 | module cl_u1lvt_nor2_1x ( |
| 1426 | in0, |
| 1427 | in1, |
| 1428 | out |
| 1429 | ); |
| 1430 | input in0; |
| 1431 | input in1; |
| 1432 | output out; |
| 1433 | |
| 1434 | `ifdef LIB |
| 1435 | assign out = ~(in0 | in1); |
| 1436 | `endif |
| 1437 | |
| 1438 | endmodule |
| 1439 | module cl_u1lvt_nor2_2x ( |
| 1440 | in0, |
| 1441 | in1, |
| 1442 | out |
| 1443 | ); |
| 1444 | input in0; |
| 1445 | input in1; |
| 1446 | output out; |
| 1447 | |
| 1448 | `ifdef LIB |
| 1449 | assign out = ~(in0 | in1); |
| 1450 | `endif |
| 1451 | |
| 1452 | endmodule |
| 1453 | module cl_u1lvt_nor2_4x ( |
| 1454 | in0, |
| 1455 | in1, |
| 1456 | out |
| 1457 | ); |
| 1458 | input in0; |
| 1459 | input in1; |
| 1460 | output out; |
| 1461 | |
| 1462 | `ifdef LIB |
| 1463 | assign out = ~(in0 | in1); |
| 1464 | `endif |
| 1465 | |
| 1466 | endmodule |
| 1467 | module cl_u1lvt_nor2_6x ( |
| 1468 | in0, |
| 1469 | in1, |
| 1470 | out |
| 1471 | ); |
| 1472 | input in0; |
| 1473 | input in1; |
| 1474 | output out; |
| 1475 | |
| 1476 | `ifdef LIB |
| 1477 | assign out = ~(in0 | in1); |
| 1478 | `endif |
| 1479 | |
| 1480 | endmodule |
| 1481 | module cl_u1lvt_nor2_8x ( |
| 1482 | in0, |
| 1483 | in1, |
| 1484 | out |
| 1485 | ); |
| 1486 | input in0; |
| 1487 | input in1; |
| 1488 | output out; |
| 1489 | |
| 1490 | `ifdef LIB |
| 1491 | assign out = ~(in0 | in1); |
| 1492 | `endif |
| 1493 | |
| 1494 | endmodule |
| 1495 | module cl_u1lvt_nor3_1x ( |
| 1496 | in0, |
| 1497 | in1, |
| 1498 | in2, |
| 1499 | out |
| 1500 | ); |
| 1501 | input in0; |
| 1502 | input in1; |
| 1503 | input in2; |
| 1504 | output out; |
| 1505 | |
| 1506 | `ifdef LIB |
| 1507 | assign out = ~(in0 | in1 | in2); |
| 1508 | `endif |
| 1509 | |
| 1510 | endmodule |
| 1511 | module cl_u1lvt_nor3_2x ( |
| 1512 | in0, |
| 1513 | in1, |
| 1514 | in2, |
| 1515 | out |
| 1516 | ); |
| 1517 | input in0; |
| 1518 | input in1; |
| 1519 | input in2; |
| 1520 | output out; |
| 1521 | |
| 1522 | `ifdef LIB |
| 1523 | assign out = ~(in0 | in1 | in2); |
| 1524 | `endif |
| 1525 | |
| 1526 | endmodule |
| 1527 | module cl_u1lvt_nor3_4x ( |
| 1528 | in0, |
| 1529 | in1, |
| 1530 | in2, |
| 1531 | out |
| 1532 | ); |
| 1533 | input in0; |
| 1534 | input in1; |
| 1535 | input in2; |
| 1536 | output out; |
| 1537 | |
| 1538 | `ifdef LIB |
| 1539 | assign out = ~(in0 | in1 | in2); |
| 1540 | `endif |
| 1541 | |
| 1542 | endmodule |
| 1543 | // -------------------------------------------------- |
| 1544 | // File: cl_u1lvt_oai12_12x.behV |
| 1545 | // Auto generated verilog module by HnBCellAuto |
| 1546 | // |
| 1547 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 1548 | // By: balmiki |
| 1549 | // -------------------------------------------------- |
| 1550 | // |
| 1551 | module cl_u1lvt_oai12_12x ( |
| 1552 | out, |
| 1553 | in10, |
| 1554 | in00, |
| 1555 | in01 ); |
| 1556 | |
| 1557 | output out; |
| 1558 | input in10; |
| 1559 | input in00; |
| 1560 | input in01; |
| 1561 | |
| 1562 | `ifdef LIB |
| 1563 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 1564 | `endif |
| 1565 | |
| 1566 | endmodule |
| 1567 | // -------------------------------------------------- |
| 1568 | // File: cl_u1lvt_oai12_16x.behV |
| 1569 | // Auto generated verilog module by HnBCellAuto |
| 1570 | // |
| 1571 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 1572 | // By: balmiki |
| 1573 | // -------------------------------------------------- |
| 1574 | // |
| 1575 | module cl_u1lvt_oai12_16x ( |
| 1576 | out, |
| 1577 | in10, |
| 1578 | in00, |
| 1579 | in01 ); |
| 1580 | |
| 1581 | output out; |
| 1582 | input in10; |
| 1583 | input in00; |
| 1584 | input in01; |
| 1585 | |
| 1586 | `ifdef LIB |
| 1587 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 1588 | `endif |
| 1589 | |
| 1590 | endmodule |
| 1591 | // -------------------------------------------------- |
| 1592 | // File: cl_u1lvt_oai12_1x.behV |
| 1593 | // Auto generated verilog module by HnBCellAuto |
| 1594 | // |
| 1595 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 1596 | // By: balmiki |
| 1597 | // -------------------------------------------------- |
| 1598 | // |
| 1599 | module cl_u1lvt_oai12_1x ( |
| 1600 | out, |
| 1601 | in10, |
| 1602 | in00, |
| 1603 | in01 ); |
| 1604 | |
| 1605 | output out; |
| 1606 | input in10; |
| 1607 | input in00; |
| 1608 | input in01; |
| 1609 | |
| 1610 | `ifdef LIB |
| 1611 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 1612 | `endif |
| 1613 | |
| 1614 | endmodule |
| 1615 | // -------------------------------------------------- |
| 1616 | // File: cl_u1lvt_oai12_2x.behV |
| 1617 | // Auto generated verilog module by HnBCellAuto |
| 1618 | // |
| 1619 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 1620 | // By: balmiki |
| 1621 | // -------------------------------------------------- |
| 1622 | // |
| 1623 | module cl_u1lvt_oai12_2x ( |
| 1624 | out, |
| 1625 | in10, |
| 1626 | in00, |
| 1627 | in01 ); |
| 1628 | |
| 1629 | output out; |
| 1630 | input in10; |
| 1631 | input in00; |
| 1632 | input in01; |
| 1633 | |
| 1634 | `ifdef LIB |
| 1635 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 1636 | `endif |
| 1637 | |
| 1638 | endmodule |
| 1639 | // -------------------------------------------------- |
| 1640 | // File: cl_u1lvt_oai12_4x.behV |
| 1641 | // Auto generated verilog module by HnBCellAuto |
| 1642 | // |
| 1643 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 1644 | // By: balmiki |
| 1645 | // -------------------------------------------------- |
| 1646 | // |
| 1647 | module cl_u1lvt_oai12_4x ( |
| 1648 | out, |
| 1649 | in10, |
| 1650 | in00, |
| 1651 | in01 ); |
| 1652 | |
| 1653 | output out; |
| 1654 | input in10; |
| 1655 | input in00; |
| 1656 | input in01; |
| 1657 | |
| 1658 | `ifdef LIB |
| 1659 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 1660 | `endif |
| 1661 | |
| 1662 | endmodule |
| 1663 | // -------------------------------------------------- |
| 1664 | // File: cl_u1lvt_oai12_8x.behV |
| 1665 | // Auto generated verilog module by HnBCellAuto |
| 1666 | // |
| 1667 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT |
| 1668 | // By: balmiki |
| 1669 | // -------------------------------------------------- |
| 1670 | // |
| 1671 | module cl_u1lvt_oai12_8x ( |
| 1672 | out, |
| 1673 | in10, |
| 1674 | in00, |
| 1675 | in01 ); |
| 1676 | |
| 1677 | output out; |
| 1678 | input in10; |
| 1679 | input in00; |
| 1680 | input in01; |
| 1681 | |
| 1682 | `ifdef LIB |
| 1683 | assign out = ~(( in10 ) & ( in00 | in01 )); |
| 1684 | `endif |
| 1685 | |
| 1686 | endmodule |
| 1687 | // -------------------------------------------------- |
| 1688 | // File: cl_u1lvt_oai21_12x.behV |
| 1689 | // Auto generated verilog module by HnBCellAuto |
| 1690 | // |
| 1691 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT |
| 1692 | // By: balmiki |
| 1693 | // -------------------------------------------------- |
| 1694 | // |
| 1695 | module cl_u1lvt_oai21_12x ( |
| 1696 | out, |
| 1697 | in10, |
| 1698 | in11, |
| 1699 | in00 ); |
| 1700 | |
| 1701 | output out; |
| 1702 | input in10; |
| 1703 | input in11; |
| 1704 | input in00; |
| 1705 | |
| 1706 | `ifdef LIB |
| 1707 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 1708 | `endif |
| 1709 | |
| 1710 | endmodule |
| 1711 | // -------------------------------------------------- |
| 1712 | // File: cl_u1lvt_oai21_16x.behV |
| 1713 | // Auto generated verilog module by HnBCellAuto |
| 1714 | // |
| 1715 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT |
| 1716 | // By: balmiki |
| 1717 | // -------------------------------------------------- |
| 1718 | // |
| 1719 | module cl_u1lvt_oai21_16x ( |
| 1720 | out, |
| 1721 | in10, |
| 1722 | in11, |
| 1723 | in00 ); |
| 1724 | |
| 1725 | output out; |
| 1726 | input in10; |
| 1727 | input in11; |
| 1728 | input in00; |
| 1729 | |
| 1730 | `ifdef LIB |
| 1731 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 1732 | `endif |
| 1733 | |
| 1734 | endmodule |
| 1735 | // -------------------------------------------------- |
| 1736 | // File: cl_u1lvt_oai21_1x.behV |
| 1737 | // Auto generated verilog module by HnBCellAuto |
| 1738 | // |
| 1739 | // Created: Friday Mar 15,2002 at 02:53:58 PM PST |
| 1740 | // By: balmiki |
| 1741 | // -------------------------------------------------- |
| 1742 | // |
| 1743 | module cl_u1lvt_oai21_1x ( |
| 1744 | out, |
| 1745 | in10, |
| 1746 | in11, |
| 1747 | in00 ); |
| 1748 | |
| 1749 | output out; |
| 1750 | input in10; |
| 1751 | input in11; |
| 1752 | input in00; |
| 1753 | |
| 1754 | `ifdef LIB |
| 1755 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 1756 | `endif |
| 1757 | |
| 1758 | endmodule |
| 1759 | // -------------------------------------------------- |
| 1760 | // File: cl_u1lvt_oai21_2x.behV |
| 1761 | // Auto generated verilog module by HnBCellAuto |
| 1762 | // |
| 1763 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT |
| 1764 | // By: balmiki |
| 1765 | // -------------------------------------------------- |
| 1766 | // |
| 1767 | module cl_u1lvt_oai21_2x ( |
| 1768 | out, |
| 1769 | in10, |
| 1770 | in11, |
| 1771 | in00 ); |
| 1772 | |
| 1773 | output out; |
| 1774 | input in10; |
| 1775 | input in11; |
| 1776 | input in00; |
| 1777 | |
| 1778 | `ifdef LIB |
| 1779 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 1780 | `endif |
| 1781 | |
| 1782 | endmodule |
| 1783 | // -------------------------------------------------- |
| 1784 | // File: cl_u1lvt_oai21_4x.behV |
| 1785 | // Auto generated verilog module by HnBCellAuto |
| 1786 | // |
| 1787 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT |
| 1788 | // By: balmiki |
| 1789 | // -------------------------------------------------- |
| 1790 | // |
| 1791 | module cl_u1lvt_oai21_4x ( |
| 1792 | out, |
| 1793 | in10, |
| 1794 | in11, |
| 1795 | in00 ); |
| 1796 | |
| 1797 | output out; |
| 1798 | input in10; |
| 1799 | input in11; |
| 1800 | input in00; |
| 1801 | |
| 1802 | `ifdef LIB |
| 1803 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 1804 | `endif |
| 1805 | |
| 1806 | endmodule |
| 1807 | // -------------------------------------------------- |
| 1808 | // File: cl_u1lvt_oai21_8x.behV |
| 1809 | // Auto generated verilog module by HnBCellAuto |
| 1810 | // |
| 1811 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT |
| 1812 | // By: balmiki |
| 1813 | // -------------------------------------------------- |
| 1814 | // |
| 1815 | module cl_u1lvt_oai21_8x ( |
| 1816 | out, |
| 1817 | in10, |
| 1818 | in11, |
| 1819 | in00 ); |
| 1820 | |
| 1821 | output out; |
| 1822 | input in10; |
| 1823 | input in11; |
| 1824 | input in00; |
| 1825 | |
| 1826 | `ifdef LIB |
| 1827 | assign out = ~(( in10 | in11 ) & ( in00 )); |
| 1828 | `endif |
| 1829 | |
| 1830 | endmodule |
| 1831 | // -------------------------------------------------- |
| 1832 | // File: cl_u1lvt_oai22_12x.behV |
| 1833 | // Auto generated verilog module by HnBCellAuto |
| 1834 | // |
| 1835 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT |
| 1836 | // By: balmiki |
| 1837 | // -------------------------------------------------- |
| 1838 | // |
| 1839 | module cl_u1lvt_oai22_12x ( |
| 1840 | out, |
| 1841 | in10, |
| 1842 | in11, |
| 1843 | in00, |
| 1844 | in01 ); |
| 1845 | |
| 1846 | output out; |
| 1847 | input in10; |
| 1848 | input in11; |
| 1849 | input in00; |
| 1850 | input in01; |
| 1851 | |
| 1852 | `ifdef LIB |
| 1853 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 1854 | `endif |
| 1855 | |
| 1856 | endmodule |
| 1857 | // -------------------------------------------------- |
| 1858 | // File: cl_u1lvt_oai22_16x.behV |
| 1859 | // Auto generated verilog module by HnBCellAuto |
| 1860 | // |
| 1861 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT |
| 1862 | // By: balmiki |
| 1863 | // -------------------------------------------------- |
| 1864 | // |
| 1865 | module cl_u1lvt_oai22_16x ( |
| 1866 | out, |
| 1867 | in10, |
| 1868 | in11, |
| 1869 | in00, |
| 1870 | in01 ); |
| 1871 | |
| 1872 | output out; |
| 1873 | input in10; |
| 1874 | input in11; |
| 1875 | input in00; |
| 1876 | input in01; |
| 1877 | |
| 1878 | `ifdef LIB |
| 1879 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 1880 | `endif |
| 1881 | |
| 1882 | endmodule |
| 1883 | // -------------------------------------------------- |
| 1884 | // File: cl_u1lvt_oai22_1x.behV |
| 1885 | // Auto generated verilog module by HnBCellAuto |
| 1886 | // |
| 1887 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT |
| 1888 | // By: balmiki |
| 1889 | // -------------------------------------------------- |
| 1890 | // |
| 1891 | module cl_u1lvt_oai22_1x ( |
| 1892 | out, |
| 1893 | in10, |
| 1894 | in11, |
| 1895 | in00, |
| 1896 | in01 ); |
| 1897 | |
| 1898 | output out; |
| 1899 | input in10; |
| 1900 | input in11; |
| 1901 | input in00; |
| 1902 | input in01; |
| 1903 | |
| 1904 | `ifdef LIB |
| 1905 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 1906 | `endif |
| 1907 | |
| 1908 | endmodule |
| 1909 | // -------------------------------------------------- |
| 1910 | // File: cl_u1lvt_oai22_2x.behV |
| 1911 | // Auto generated verilog module by HnBCellAuto |
| 1912 | // |
| 1913 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT |
| 1914 | // By: balmiki |
| 1915 | // -------------------------------------------------- |
| 1916 | // |
| 1917 | module cl_u1lvt_oai22_2x ( |
| 1918 | out, |
| 1919 | in10, |
| 1920 | in11, |
| 1921 | in00, |
| 1922 | in01 ); |
| 1923 | |
| 1924 | output out; |
| 1925 | input in10; |
| 1926 | input in11; |
| 1927 | input in00; |
| 1928 | input in01; |
| 1929 | |
| 1930 | `ifdef LIB |
| 1931 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 1932 | `endif |
| 1933 | |
| 1934 | endmodule |
| 1935 | // -------------------------------------------------- |
| 1936 | // File: cl_u1lvt_oai22_4x.behV |
| 1937 | // Auto generated verilog module by HnBCellAuto |
| 1938 | // |
| 1939 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT |
| 1940 | // By: balmiki |
| 1941 | // -------------------------------------------------- |
| 1942 | // |
| 1943 | module cl_u1lvt_oai22_4x ( |
| 1944 | out, |
| 1945 | in10, |
| 1946 | in11, |
| 1947 | in00, |
| 1948 | in01 ); |
| 1949 | |
| 1950 | output out; |
| 1951 | input in10; |
| 1952 | input in11; |
| 1953 | input in00; |
| 1954 | input in01; |
| 1955 | |
| 1956 | `ifdef LIB |
| 1957 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 1958 | `endif |
| 1959 | |
| 1960 | endmodule |
| 1961 | // -------------------------------------------------- |
| 1962 | // File: cl_u1lvt_oai22_8x.behV |
| 1963 | // Auto generated verilog module by HnBCellAuto |
| 1964 | // |
| 1965 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT |
| 1966 | // By: balmiki |
| 1967 | // -------------------------------------------------- |
| 1968 | // |
| 1969 | module cl_u1lvt_oai22_8x ( |
| 1970 | out, |
| 1971 | in10, |
| 1972 | in11, |
| 1973 | in00, |
| 1974 | in01 ); |
| 1975 | |
| 1976 | output out; |
| 1977 | input in10; |
| 1978 | input in11; |
| 1979 | input in00; |
| 1980 | input in01; |
| 1981 | |
| 1982 | `ifdef LIB |
| 1983 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); |
| 1984 | `endif |
| 1985 | |
| 1986 | endmodule |
| 1987 | module cl_u1lvt_rep_dcp_32x ( |
| 1988 | in, |
| 1989 | out |
| 1990 | ); |
| 1991 | input in; |
| 1992 | output out; |
| 1993 | |
| 1994 | `ifdef LIB |
| 1995 | assign out = in; |
| 1996 | `endif |
| 1997 | |
| 1998 | endmodule |
| 1999 | module cl_u1lvt_rep_dcp_48x ( |
| 2000 | in, |
| 2001 | out |
| 2002 | ); |
| 2003 | input in; |
| 2004 | output out; |
| 2005 | |
| 2006 | `ifdef LIB |
| 2007 | assign out = in; |
| 2008 | `endif |
| 2009 | |
| 2010 | endmodule |
| 2011 | module cl_u1lvt_rep_8x ( |
| 2012 | in, |
| 2013 | out |
| 2014 | ); |
| 2015 | input in; |
| 2016 | output out; |
| 2017 | |
| 2018 | `ifdef LIB |
| 2019 | assign out = in; |
| 2020 | `endif |
| 2021 | |
| 2022 | endmodule |
| 2023 | module cl_u1lvt_rep_16x ( |
| 2024 | in, |
| 2025 | out |
| 2026 | ); |
| 2027 | input in; |
| 2028 | output out; |
| 2029 | |
| 2030 | `ifdef LIB |
| 2031 | assign out = in; |
| 2032 | `endif |
| 2033 | |
| 2034 | endmodule |
| 2035 | module cl_u1lvt_rep_24x ( |
| 2036 | in, |
| 2037 | out |
| 2038 | ); |
| 2039 | input in; |
| 2040 | output out; |
| 2041 | |
| 2042 | `ifdef LIB |
| 2043 | assign out = in; |
| 2044 | `endif |
| 2045 | |
| 2046 | endmodule |
| 2047 | module cl_u1lvt_rep_32x ( |
| 2048 | in, |
| 2049 | out |
| 2050 | ); |
| 2051 | input in; |
| 2052 | output out; |
| 2053 | |
| 2054 | `ifdef LIB |
| 2055 | assign out = in; |
| 2056 | `endif |
| 2057 | |
| 2058 | endmodule |
| 2059 | module cl_u1lvt_rep_40x ( |
| 2060 | in, |
| 2061 | out |
| 2062 | ); |
| 2063 | input in; |
| 2064 | output out; |
| 2065 | |
| 2066 | `ifdef LIB |
| 2067 | assign out = in; |
| 2068 | `endif |
| 2069 | |
| 2070 | endmodule |
| 2071 | module cl_u1lvt_rep_48x ( |
| 2072 | in, |
| 2073 | out |
| 2074 | ); |
| 2075 | input in; |
| 2076 | output out; |
| 2077 | |
| 2078 | `ifdef LIB |
| 2079 | assign out = in; |
| 2080 | `endif |
| 2081 | |
| 2082 | endmodule |
| 2083 | module cl_u1lvt_xnor2_16x ( |
| 2084 | in0, |
| 2085 | in1, |
| 2086 | out |
| 2087 | ); |
| 2088 | input in0; |
| 2089 | input in1; |
| 2090 | output out; |
| 2091 | |
| 2092 | `ifdef LIB |
| 2093 | assign out = ~(in0 ^ in1); |
| 2094 | `endif |
| 2095 | |
| 2096 | endmodule |
| 2097 | module cl_u1lvt_xnor2_1x ( |
| 2098 | in0, |
| 2099 | in1, |
| 2100 | out |
| 2101 | ); |
| 2102 | input in0; |
| 2103 | input in1; |
| 2104 | output out; |
| 2105 | |
| 2106 | `ifdef LIB |
| 2107 | assign out = ~(in0 ^ in1); |
| 2108 | `endif |
| 2109 | |
| 2110 | endmodule |
| 2111 | module cl_u1lvt_xnor2_2x ( |
| 2112 | in0, |
| 2113 | in1, |
| 2114 | out |
| 2115 | ); |
| 2116 | input in0; |
| 2117 | input in1; |
| 2118 | output out; |
| 2119 | |
| 2120 | `ifdef LIB |
| 2121 | assign out = ~(in0 ^ in1); |
| 2122 | `endif |
| 2123 | |
| 2124 | endmodule |
| 2125 | module cl_u1lvt_xnor2_4x ( |
| 2126 | in0, |
| 2127 | in1, |
| 2128 | out |
| 2129 | ); |
| 2130 | input in0; |
| 2131 | input in1; |
| 2132 | output out; |
| 2133 | |
| 2134 | `ifdef LIB |
| 2135 | assign out = ~(in0 ^ in1); |
| 2136 | `endif |
| 2137 | |
| 2138 | endmodule |
| 2139 | module cl_u1lvt_xnor2_6x ( |
| 2140 | in0, |
| 2141 | in1, |
| 2142 | out |
| 2143 | ); |
| 2144 | input in0; |
| 2145 | input in1; |
| 2146 | output out; |
| 2147 | |
| 2148 | `ifdef LIB |
| 2149 | assign out = ~(in0 ^ in1); |
| 2150 | `endif |
| 2151 | |
| 2152 | endmodule |
| 2153 | module cl_u1lvt_xnor2_8x ( |
| 2154 | in0, |
| 2155 | in1, |
| 2156 | out |
| 2157 | ); |
| 2158 | input in0; |
| 2159 | input in1; |
| 2160 | output out; |
| 2161 | |
| 2162 | `ifdef LIB |
| 2163 | assign out = ~(in0 ^ in1); |
| 2164 | `endif |
| 2165 | |
| 2166 | endmodule |
| 2167 | module cl_u1lvt_xnor3_16x ( |
| 2168 | in0, |
| 2169 | in1, |
| 2170 | in2, |
| 2171 | out |
| 2172 | ); |
| 2173 | input in0; |
| 2174 | input in1; |
| 2175 | input in2; |
| 2176 | output out; |
| 2177 | |
| 2178 | `ifdef LIB |
| 2179 | assign out = ~(in0 ^ in1 ^ in2); |
| 2180 | `endif |
| 2181 | |
| 2182 | |
| 2183 | |
| 2184 | endmodule |
| 2185 | module cl_u1lvt_xnor3_1x ( |
| 2186 | in0, |
| 2187 | in1, |
| 2188 | in2, |
| 2189 | out |
| 2190 | ); |
| 2191 | input in0; |
| 2192 | input in1; |
| 2193 | input in2; |
| 2194 | output out; |
| 2195 | |
| 2196 | `ifdef LIB |
| 2197 | assign out = ~(in0 ^ in1 ^ in2); |
| 2198 | `endif |
| 2199 | |
| 2200 | |
| 2201 | |
| 2202 | endmodule |
| 2203 | module cl_u1lvt_xnor3_2x ( |
| 2204 | in0, |
| 2205 | in1, |
| 2206 | in2, |
| 2207 | out |
| 2208 | ); |
| 2209 | input in0; |
| 2210 | input in1; |
| 2211 | input in2; |
| 2212 | output out; |
| 2213 | |
| 2214 | `ifdef LIB |
| 2215 | assign out = ~(in0 ^ in1 ^ in2); |
| 2216 | `endif |
| 2217 | |
| 2218 | |
| 2219 | |
| 2220 | endmodule |
| 2221 | module cl_u1lvt_xnor3_4x ( |
| 2222 | in0, |
| 2223 | in1, |
| 2224 | in2, |
| 2225 | out |
| 2226 | ); |
| 2227 | input in0; |
| 2228 | input in1; |
| 2229 | input in2; |
| 2230 | output out; |
| 2231 | |
| 2232 | `ifdef LIB |
| 2233 | assign out = ~(in0 ^ in1 ^ in2); |
| 2234 | `endif |
| 2235 | |
| 2236 | |
| 2237 | |
| 2238 | endmodule |
| 2239 | module cl_u1lvt_xnor3_6x ( |
| 2240 | in0, |
| 2241 | in1, |
| 2242 | in2, |
| 2243 | out |
| 2244 | ); |
| 2245 | input in0; |
| 2246 | input in1; |
| 2247 | input in2; |
| 2248 | output out; |
| 2249 | |
| 2250 | `ifdef LIB |
| 2251 | assign out = ~(in0 ^ in1 ^ in2); |
| 2252 | `endif |
| 2253 | |
| 2254 | |
| 2255 | |
| 2256 | endmodule |
| 2257 | module cl_u1lvt_xnor3_8x ( |
| 2258 | in0, |
| 2259 | in1, |
| 2260 | in2, |
| 2261 | out |
| 2262 | ); |
| 2263 | input in0; |
| 2264 | input in1; |
| 2265 | input in2; |
| 2266 | output out; |
| 2267 | |
| 2268 | `ifdef LIB |
| 2269 | assign out = ~(in0 ^ in1 ^ in2); |
| 2270 | `endif |
| 2271 | |
| 2272 | |
| 2273 | |
| 2274 | endmodule |
| 2275 | module cl_u1lvt_xor2_16x ( |
| 2276 | in0, |
| 2277 | in1, |
| 2278 | out |
| 2279 | ); |
| 2280 | input in0; |
| 2281 | input in1; |
| 2282 | output out; |
| 2283 | |
| 2284 | `ifdef LIB |
| 2285 | assign out = in0 ^ in1; |
| 2286 | `endif |
| 2287 | |
| 2288 | endmodule |
| 2289 | module cl_u1lvt_xor2_1x ( |
| 2290 | in0, |
| 2291 | in1, |
| 2292 | out |
| 2293 | ); |
| 2294 | input in0; |
| 2295 | input in1; |
| 2296 | output out; |
| 2297 | |
| 2298 | `ifdef LIB |
| 2299 | assign out = in0 ^ in1; |
| 2300 | `endif |
| 2301 | |
| 2302 | endmodule |
| 2303 | module cl_u1lvt_xor2_2x ( |
| 2304 | in0, |
| 2305 | in1, |
| 2306 | out |
| 2307 | ); |
| 2308 | input in0; |
| 2309 | input in1; |
| 2310 | output out; |
| 2311 | |
| 2312 | `ifdef LIB |
| 2313 | assign out = in0 ^ in1; |
| 2314 | `endif |
| 2315 | |
| 2316 | endmodule |
| 2317 | module cl_u1lvt_xor2_4x ( |
| 2318 | in0, |
| 2319 | in1, |
| 2320 | out |
| 2321 | ); |
| 2322 | input in0; |
| 2323 | input in1; |
| 2324 | output out; |
| 2325 | |
| 2326 | `ifdef LIB |
| 2327 | assign out = in0 ^ in1; |
| 2328 | `endif |
| 2329 | |
| 2330 | endmodule |
| 2331 | module cl_u1lvt_xor2_6x ( |
| 2332 | in0, |
| 2333 | in1, |
| 2334 | out |
| 2335 | ); |
| 2336 | input in0; |
| 2337 | input in1; |
| 2338 | output out; |
| 2339 | |
| 2340 | `ifdef LIB |
| 2341 | assign out = in0 ^ in1; |
| 2342 | `endif |
| 2343 | |
| 2344 | endmodule |
| 2345 | module cl_u1lvt_xor2_8x ( |
| 2346 | in0, |
| 2347 | in1, |
| 2348 | out |
| 2349 | ); |
| 2350 | input in0; |
| 2351 | input in1; |
| 2352 | output out; |
| 2353 | |
| 2354 | `ifdef LIB |
| 2355 | assign out = in0 ^ in1; |
| 2356 | `endif |
| 2357 | |
| 2358 | endmodule |
| 2359 | module cl_u1lvt_xor3_16x ( |
| 2360 | in0, |
| 2361 | in1, |
| 2362 | in2, |
| 2363 | out |
| 2364 | ); |
| 2365 | input in0; |
| 2366 | input in1; |
| 2367 | input in2; |
| 2368 | output out; |
| 2369 | |
| 2370 | `ifdef LIB |
| 2371 | assign out = in0 ^ in1 ^ in2; |
| 2372 | `endif |
| 2373 | |
| 2374 | |
| 2375 | endmodule |
| 2376 | module cl_u1lvt_xor3_1x ( |
| 2377 | in0, |
| 2378 | in1, |
| 2379 | in2, |
| 2380 | out |
| 2381 | ); |
| 2382 | input in0; |
| 2383 | input in1; |
| 2384 | input in2; |
| 2385 | output out; |
| 2386 | |
| 2387 | `ifdef LIB |
| 2388 | assign out = in0 ^ in1 ^ in2; |
| 2389 | `endif |
| 2390 | |
| 2391 | |
| 2392 | endmodule |
| 2393 | module cl_u1lvt_xor3_2x ( |
| 2394 | in0, |
| 2395 | in1, |
| 2396 | in2, |
| 2397 | out |
| 2398 | ); |
| 2399 | input in0; |
| 2400 | input in1; |
| 2401 | input in2; |
| 2402 | output out; |
| 2403 | |
| 2404 | `ifdef LIB |
| 2405 | assign out = in0 ^ in1 ^ in2; |
| 2406 | `endif |
| 2407 | |
| 2408 | |
| 2409 | endmodule |
| 2410 | module cl_u1lvt_xor3_4x ( |
| 2411 | in0, |
| 2412 | in1, |
| 2413 | in2, |
| 2414 | out |
| 2415 | ); |
| 2416 | input in0; |
| 2417 | input in1; |
| 2418 | input in2; |
| 2419 | output out; |
| 2420 | |
| 2421 | `ifdef LIB |
| 2422 | assign out = in0 ^ in1 ^ in2; |
| 2423 | `endif |
| 2424 | |
| 2425 | |
| 2426 | endmodule |
| 2427 | module cl_u1lvt_xor3_6x ( |
| 2428 | in0, |
| 2429 | in1, |
| 2430 | in2, |
| 2431 | out |
| 2432 | ); |
| 2433 | input in0; |
| 2434 | input in1; |
| 2435 | input in2; |
| 2436 | output out; |
| 2437 | |
| 2438 | `ifdef LIB |
| 2439 | assign out = in0 ^ in1 ^ in2; |
| 2440 | `endif |
| 2441 | |
| 2442 | |
| 2443 | endmodule |
| 2444 | module cl_u1lvt_xor3_8x ( |
| 2445 | in0, |
| 2446 | in1, |
| 2447 | in2, |
| 2448 | out |
| 2449 | ); |
| 2450 | input in0; |
| 2451 | input in1; |
| 2452 | input in2; |
| 2453 | output out; |
| 2454 | |
| 2455 | `ifdef LIB |
| 2456 | assign out = in0 ^ in1 ^ in2; |
| 2457 | `endif |
| 2458 | |
| 2459 | |
| 2460 | endmodule |