| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: clkgen_ccx_cmp.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `ifndef FPGA |
| 36 | module clkgen_ccx_cmp ( |
| 37 | array_wr_inhibit, |
| 38 | tcu_atpg_mode, |
| 39 | tcu_wr_inhibit, |
| 40 | l2clk, |
| 41 | aclk, |
| 42 | bclk, |
| 43 | scan_out, |
| 44 | pce_ov, |
| 45 | aclk_wmr, |
| 46 | wmr_protect, |
| 47 | wmr_, |
| 48 | por_, |
| 49 | cmp_slow_sync_en, |
| 50 | slow_cmp_sync_en, |
| 51 | tcu_clk_stop_left, |
| 52 | tcu_clk_stop_right, |
| 53 | tcu_pce_ov, |
| 54 | rst_wmr_protect, |
| 55 | rst_wmr_, |
| 56 | rst_por_, |
| 57 | ccu_cmp_slow_sync_en, |
| 58 | ccu_slow_cmp_sync_en, |
| 59 | tcu_div_bypass_left, |
| 60 | tcu_div_bypass_right, |
| 61 | ccu_div_ph, |
| 62 | cluster_div_en, |
| 63 | gclk_left, |
| 64 | gclk_right, |
| 65 | cluster_arst_l_left, |
| 66 | cluster_arst_l_right, |
| 67 | clk_ext, |
| 68 | ccu_serdes_dtm, |
| 69 | tcu_aclk, |
| 70 | tcu_bclk, |
| 71 | scan_en, |
| 72 | scan_in |
| 73 | ); |
| 74 | |
| 75 | |
| 76 | // ************************** |
| 77 | // port declaration |
| 78 | // ************************** |
| 79 | |
| 80 | // clock & test out |
| 81 | output l2clk; // assume we do not need aclk, bclk outputs |
| 82 | output aclk; // buffered version of aclk |
| 83 | output bclk; // buffered version of bclk |
| 84 | output scan_out; // unused as of today - feb 10, 05 |
| 85 | output aclk_wmr; |
| 86 | |
| 87 | // pipelined out |
| 88 | output pce_ov; // pce override to l1 header |
| 89 | output wmr_protect; // warm reset protect |
| 90 | output wmr_; // warm reset (active low) |
| 91 | output por_; // power-on-reset |
| 92 | output cmp_slow_sync_en; // cmp->slow clk sync pulse |
| 93 | output slow_cmp_sync_en; // slow->cmp clk sync pulse |
| 94 | |
| 95 | // ctrl in (for pipelining) |
| 96 | output array_wr_inhibit; |
| 97 | input tcu_atpg_mode; |
| 98 | input tcu_wr_inhibit; |
| 99 | input tcu_clk_stop_left; |
| 100 | input tcu_clk_stop_right; |
| 101 | input tcu_pce_ov; |
| 102 | input rst_wmr_protect; |
| 103 | input rst_wmr_; |
| 104 | input rst_por_; |
| 105 | input ccu_cmp_slow_sync_en; |
| 106 | input ccu_slow_cmp_sync_en; |
| 107 | |
| 108 | // ctrl in (for clock gen) |
| 109 | // input tcu_div_bypass; // bypasses clk divider to mux in ext clk |
| 110 | input tcu_div_bypass_left; |
| 111 | input tcu_div_bypass_right; |
| 112 | input ccu_div_ph; // phase signal from ccu (div/4 or div/2) |
| 113 | input cluster_div_en; // if enabled, l2clk is divided down |
| 114 | input cluster_arst_l_left; |
| 115 | input cluster_arst_l_right; |
| 116 | |
| 117 | // clock & test in |
| 118 | input gclk_left; // global clk - this is either cmp or dr |
| 119 | input gclk_right; // global clk - this is either cmp or dr |
| 120 | input ccu_serdes_dtm; |
| 121 | input clk_ext; // external clk muxed in for ioclk bypass |
| 122 | input scan_en; // unused as of today - feb 10, 05 |
| 123 | input scan_in; // unused as of today - feb 10, 05 |
| 124 | input tcu_aclk; |
| 125 | input tcu_bclk; |
| 126 | |
| 127 | |
| 128 | // ************************** |
| 129 | // wire declaration |
| 130 | // ************************** |
| 131 | wire array_wr_inhibit; |
| 132 | wire tcu_atpg_mode; |
| 133 | wire tcu_wr_inhibit; |
| 134 | wire l2clk; |
| 135 | wire aclk; |
| 136 | wire bclk; |
| 137 | wire scan_out; |
| 138 | wire aclk_wmr; |
| 139 | wire pce_ov; |
| 140 | wire wmr_protect; |
| 141 | wire wmr_; |
| 142 | wire por_; |
| 143 | wire cmp_slow_sync_en; |
| 144 | wire slow_cmp_sync_en; |
| 145 | wire tcu_clk_stop_left; |
| 146 | wire tcu_clk_stop_right; |
| 147 | wire tcu_pce_ov; |
| 148 | wire rst_wmr_protect; |
| 149 | wire rst_wmr_; |
| 150 | wire rst_por_; |
| 151 | wire ccu_cmp_slow_sync_en; |
| 152 | wire ccu_slow_cmp_sync_en; |
| 153 | wire tcu_div_bypass_right; |
| 154 | wire tcu_div_bypass_left; |
| 155 | wire ccu_div_ph; |
| 156 | wire cluster_div_en; |
| 157 | wire gclk_left; |
| 158 | wire gclk_right; |
| 159 | wire cluster_arst_l_left; |
| 160 | wire cluster_arst_l_right; |
| 161 | wire clk_ext; |
| 162 | wire ccu_serdes_dtm; |
| 163 | wire scan_en; |
| 164 | wire scan_in; |
| 165 | wire tcu_aclk; |
| 166 | wire tcu_bclk; |
| 167 | |
| 168 | wire cclk_left; |
| 169 | wire cclk_right; |
| 170 | |
| 171 | wire scan_tmp; |
| 172 | |
| 173 | |
| 174 | // ************************** |
| 175 | // instantiations |
| 176 | // ************************** |
| 177 | |
| 178 | // needs a few edits to cluster header def - mahmud.hassan |
| 179 | // modified custom cell name for avoiding |
| 180 | // collision with sparc core and other clusters - mhassan |
| 181 | n2_clk_clstr_hdr_cust xcluster_header_right ( |
| 182 | .gclk (gclk_right), |
| 183 | .l2clk (l2clk), |
| 184 | .cluster_arst_l (cluster_arst_l_right), |
| 185 | .ccu_div_ph (ccu_div_ph), |
| 186 | .cluster_div_en (cluster_div_en), |
| 187 | .tcu_div_bypass (tcu_div_bypass_right), |
| 188 | // .clk_ext (clk_ext), |
| 189 | // .ccu_serdes_dtm (ccu_serdes_dtm), |
| 190 | .scan_in (scan_in), |
| 191 | .scan_en (scan_en), // temporary |
| 192 | .tcu_aclk (tcu_aclk), |
| 193 | .tcu_bclk (tcu_bclk), |
| 194 | .ccu_cmp_slow_sync_en (ccu_cmp_slow_sync_en), |
| 195 | .ccu_slow_cmp_sync_en (ccu_slow_cmp_sync_en), |
| 196 | .tcu_pce_ov (tcu_pce_ov), |
| 197 | .tcu_clk_stop (tcu_clk_stop_right), |
| 198 | .rst_por_ (rst_por_), |
| 199 | .rst_wmr_ (rst_wmr_), |
| 200 | .rst_wmr_protect (rst_wmr_protect), |
| 201 | .aclk_wmr (aclk_wmr), |
| 202 | .aclk (aclk), |
| 203 | .bclk (bclk), |
| 204 | .cmp_slow_sync_en (cmp_slow_sync_en), |
| 205 | .slow_cmp_sync_en (slow_cmp_sync_en), |
| 206 | .pce_ov (pce_ov), |
| 207 | .por_ (por_), |
| 208 | .wmr_ (wmr_), |
| 209 | .wmr_protect (wmr_protect), |
| 210 | .scan_out (scan_out), |
| 211 | .array_wr_inhibit (array_wr_inhibit), |
| 212 | .tcu_atpg_mode (tcu_atpg_mode), |
| 213 | .tcu_wr_inhibit (tcu_wr_inhibit), |
| 214 | .cclk (cclk_right) |
| 215 | ); |
| 216 | |
| 217 | |
| 218 | n2_clk_clstr_hdr_cust xcluster_header_left ( |
| 219 | .gclk (gclk_left), |
| 220 | .l2clk (l2clk), |
| 221 | .cluster_arst_l (cluster_arst_l_left), |
| 222 | .ccu_div_ph (ccu_div_ph), |
| 223 | .cluster_div_en (cluster_div_en), |
| 224 | .tcu_div_bypass (tcu_div_bypass_left), |
| 225 | // .clk_ext (1'b0), |
| 226 | // .ccu_serdes_dtm (1'b0), |
| 227 | .scan_in (1'b0), |
| 228 | .scan_en (1'b0), |
| 229 | .tcu_aclk (1'b0), |
| 230 | .tcu_bclk (1'b0), |
| 231 | .ccu_cmp_slow_sync_en (1'b0), |
| 232 | .ccu_slow_cmp_sync_en (1'b0), |
| 233 | .tcu_pce_ov (1'b1), |
| 234 | .tcu_clk_stop (tcu_clk_stop_left), |
| 235 | .rst_por_ (1'b0), |
| 236 | .rst_wmr_ (1'b0), |
| 237 | .rst_wmr_protect (1'b0), |
| 238 | .aclk_wmr (), |
| 239 | .aclk (), |
| 240 | .bclk (), |
| 241 | .cmp_slow_sync_en (), |
| 242 | .slow_cmp_sync_en (), |
| 243 | .pce_ov (), |
| 244 | .por_ (), |
| 245 | .wmr_ (), |
| 246 | .wmr_protect (), |
| 247 | .scan_out (), |
| 248 | .array_wr_inhibit (), |
| 249 | .tcu_atpg_mode (tcu_atpg_mode), |
| 250 | .tcu_wr_inhibit (1'b0), |
| 251 | .cclk (cclk_left) |
| 252 | ); |
| 253 | |
| 254 | // cclk -> l2clk on bottom |
| 255 | n2_clk_ccx_cmp_cust xbottom ( |
| 256 | .l2clk (l2clk), |
| 257 | .cclk_right (cclk_right), |
| 258 | .cclk_left (cclk_left) |
| 259 | ); |
| 260 | |
| 261 | |
| 262 | // cclk -> l2clk on top |
| 263 | n2_clk_ccx_cmp_cust xtop ( |
| 264 | .l2clk (l2clk), |
| 265 | .cclk_right (cclk_right), |
| 266 | .cclk_left (cclk_left) |
| 267 | ); |
| 268 | |
| 269 | |
| 270 | |
| 271 | endmodule |
| 272 | |
| 273 | |
| 274 | `endif // `ifndef FPGA |
| 275 | |
| 276 | `ifdef FPGA |
| 277 | module clkgen_ccx_cmp(array_wr_inhibit, tcu_atpg_mode, tcu_wr_inhibit, l2clk, |
| 278 | aclk, bclk, scan_out, pce_ov, aclk_wmr, wmr_protect, wmr_, por_, |
| 279 | cmp_slow_sync_en, slow_cmp_sync_en, tcu_clk_stop_left, |
| 280 | tcu_clk_stop_right, tcu_pce_ov, rst_wmr_protect, rst_wmr_, rst_por_, |
| 281 | ccu_cmp_slow_sync_en, ccu_slow_cmp_sync_en, tcu_div_bypass_left, |
| 282 | tcu_div_bypass_right, ccu_div_ph, cluster_div_en, gclk_left, gclk_right, |
| 283 | cluster_arst_l_left, cluster_arst_l_right, clk_ext, ccu_serdes_dtm, |
| 284 | tcu_aclk, tcu_bclk, scan_en, scan_in); |
| 285 | |
| 286 | output l2clk; |
| 287 | output aclk; |
| 288 | output bclk; |
| 289 | output scan_out; |
| 290 | output aclk_wmr; |
| 291 | output pce_ov; |
| 292 | output wmr_protect; |
| 293 | output wmr_; |
| 294 | output por_; |
| 295 | output cmp_slow_sync_en; |
| 296 | output slow_cmp_sync_en; |
| 297 | output array_wr_inhibit; |
| 298 | input tcu_atpg_mode; |
| 299 | input tcu_wr_inhibit; |
| 300 | input tcu_clk_stop_left; |
| 301 | input tcu_clk_stop_right; |
| 302 | input tcu_pce_ov; |
| 303 | input rst_wmr_protect; |
| 304 | input rst_wmr_; |
| 305 | input rst_por_; |
| 306 | input ccu_cmp_slow_sync_en; |
| 307 | input ccu_slow_cmp_sync_en; |
| 308 | input tcu_div_bypass_left; |
| 309 | input tcu_div_bypass_right; |
| 310 | input ccu_div_ph; |
| 311 | input cluster_div_en; |
| 312 | input cluster_arst_l_left; |
| 313 | input cluster_arst_l_right; |
| 314 | input gclk_left; |
| 315 | input gclk_right; |
| 316 | input ccu_serdes_dtm; |
| 317 | input clk_ext; |
| 318 | input scan_en; |
| 319 | input scan_in; |
| 320 | input tcu_aclk; |
| 321 | input tcu_bclk; |
| 322 | |
| 323 | wire cclk_left; |
| 324 | wire cclk_right; |
| 325 | wire scan_tmp; |
| 326 | |
| 327 | n2_clk_clstr_hdr_cust xcluster_header_right( |
| 328 | .gclk (gclk_right), |
| 329 | .l2clk (l2clk), |
| 330 | .cluster_arst_l (cluster_arst_l_right), |
| 331 | .ccu_div_ph (ccu_div_ph), |
| 332 | .cluster_div_en (cluster_div_en), |
| 333 | .tcu_div_bypass (tcu_div_bypass_right), |
| 334 | .scan_in (scan_in), |
| 335 | .scan_en (scan_en), |
| 336 | .tcu_aclk (tcu_aclk), |
| 337 | .tcu_bclk (tcu_bclk), |
| 338 | .ccu_cmp_slow_sync_en (ccu_cmp_slow_sync_en), |
| 339 | .ccu_slow_cmp_sync_en (ccu_slow_cmp_sync_en), |
| 340 | .tcu_pce_ov (tcu_pce_ov), |
| 341 | .tcu_clk_stop (tcu_clk_stop_right), |
| 342 | .rst_por_ (rst_por_), |
| 343 | .rst_wmr_ (rst_wmr_), |
| 344 | .rst_wmr_protect (rst_wmr_protect), |
| 345 | .aclk_wmr (aclk_wmr), |
| 346 | .aclk (aclk), |
| 347 | .bclk (bclk), |
| 348 | .cmp_slow_sync_en (cmp_slow_sync_en), |
| 349 | .slow_cmp_sync_en (slow_cmp_sync_en), |
| 350 | .pce_ov (pce_ov), |
| 351 | .por_ (por_), |
| 352 | .wmr_ (wmr_), |
| 353 | .wmr_protect (wmr_protect), |
| 354 | .scan_out (scan_out), |
| 355 | .array_wr_inhibit (array_wr_inhibit), |
| 356 | .tcu_atpg_mode (tcu_atpg_mode), |
| 357 | .tcu_wr_inhibit (tcu_wr_inhibit), |
| 358 | .cclk (cclk_right)); |
| 359 | n2_clk_clstr_hdr_cust xcluster_header_left( |
| 360 | .gclk (gclk_left), |
| 361 | .l2clk (l2clk), |
| 362 | .cluster_arst_l (cluster_arst_l_left), |
| 363 | .ccu_div_ph (ccu_div_ph), |
| 364 | .cluster_div_en (cluster_div_en), |
| 365 | .tcu_div_bypass (tcu_div_bypass_left), |
| 366 | .scan_in (1'b0), |
| 367 | .scan_en (1'b0), |
| 368 | .tcu_aclk (1'b0), |
| 369 | .tcu_bclk (1'b0), |
| 370 | .ccu_cmp_slow_sync_en (1'b0), |
| 371 | .ccu_slow_cmp_sync_en (1'b0), |
| 372 | .tcu_pce_ov (1'b1), |
| 373 | .tcu_clk_stop (tcu_clk_stop_left), |
| 374 | .rst_por_ (1'b0), |
| 375 | .rst_wmr_ (1'b0), |
| 376 | .rst_wmr_protect (1'b0), |
| 377 | .tcu_atpg_mode (tcu_atpg_mode), |
| 378 | .tcu_wr_inhibit (1'b0), |
| 379 | .cclk (cclk_left)); |
| 380 | n2_clk_ccx_cmp_cust xbottom( |
| 381 | .l2clk (l2clk), |
| 382 | .cclk_right (cclk_right), |
| 383 | .cclk_left (cclk_left)); |
| 384 | n2_clk_ccx_cmp_cust xtop( |
| 385 | .l2clk (l2clk), |
| 386 | .cclk_right (cclk_right), |
| 387 | .cclk_left (cclk_left)); |
| 388 | |
| 389 | |
| 390 | endmodule |
| 391 | |
| 392 | `endif // `ifdef FPGA |
| 393 | |