| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: n2_peu_dp_256x138s_cust_array.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module n2_peu_dp_256x138s_cust_array ( |
| 36 | |
| 37 | wr_addr_array, |
| 38 | wr_en_array, |
| 39 | din_array, |
| 40 | |
| 41 | clk, |
| 42 | rd_addr_array, |
| 43 | rd_en_array, |
| 44 | dout_array |
| 45 | |
| 46 | ); |
| 47 | |
| 48 | |
| 49 | input [7:0] wr_addr_array; // write port address in |
| 50 | input wr_en_array; // write port enable |
| 51 | input [137:0] din_array; // data in |
| 52 | |
| 53 | input clk; // clk |
| 54 | input [7:0] rd_addr_array; // read port address in |
| 55 | input rd_en_array; // read port enable |
| 56 | output [137:0] dout_array; // data out |
| 57 | |
| 58 | |
| 59 | // ---------------------------------------------------------------------------- |
| 60 | // Zero In Checkers |
| 61 | // ---------------------------------------------------------------------------- |
| 62 | // checker to verify on accesses's that no bits are x |
| 63 | // 0in kndr -var rd_addr_array |
| 64 | // 0in kndr -var wr_addr_array |
| 65 | // 0in kndr -var rd_en_array |
| 66 | // 0in kndr -var wr_en_array |
| 67 | |
| 68 | |
| 69 | reg [137:0] array_ram [0:255]; |
| 70 | reg [137:0] dout_array; |
| 71 | |
| 72 | // Initialize the array |
| 73 | `ifndef NOINITMEM |
| 74 | integer i; |
| 75 | |
| 76 | initial begin |
| 77 | for (i=0; i<256; i=i+1) begin |
| 78 | array_ram[i] = 138'b0; |
| 79 | end |
| 80 | end |
| 81 | `endif |
| 82 | |
| 83 | // ---------------------------------------------------------------------------- |
| 84 | // Read the array |
| 85 | // ---------------------------------------------------------------------------- |
| 86 | always @(clk or rd_en_array or rd_addr_array or wr_en_array or wr_addr_array ) begin |
| 87 | if (clk) begin |
| 88 | if (rd_en_array) begin |
| 89 | if (wr_en_array & (rd_addr_array == wr_addr_array)) // 0in < fire -severity 1 -message "Detected rd/wr collision in PEU RBUF RAM, dout driven as X's" -group mbist_mode |
| 90 | dout_array[137:0] <= {138{1'bx}} ; |
| 91 | else |
| 92 | dout_array[137:0] <= array_ram[rd_addr_array[7:0]]; |
| 93 | end |
| 94 | else begin |
| 95 | dout_array[137:0] <= 138'b0 ; |
| 96 | end |
| 97 | end |
| 98 | end |
| 99 | |
| 100 | |
| 101 | |
| 102 | // ---------------------------------------------------------------------------- |
| 103 | // Write the array, note: it is written when the clock is low |
| 104 | // ---------------------------------------------------------------------------- |
| 105 | always @(clk or wr_en_array or wr_addr_array or din_array ) begin |
| 106 | if (~clk) begin |
| 107 | if(wr_en_array ) begin |
| 108 | array_ram[wr_addr_array[7:0]] <= din_array[137:0]; |
| 109 | end |
| 110 | end |
| 111 | end |
| 112 | |
| 113 | |
| 114 | endmodule // n2_peu_dp_256x138s_cust_array |
| 115 | |
| 116 | |